1 /* Simulator for the FT32 processor
3 Copyright (C) 2008-2022 Free Software Foundation, Inc.
6 This file is part of simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 /* This must come before any other includes. */
30 #include "sim/callback.h"
31 #include "libiberty.h"
35 #include "sim-options.h"
36 #include "sim-signal.h"
38 #include "opcode/ft32.h"
41 * FT32 is a Harvard architecture: RAM and code occupy
42 * different address spaces.
44 * sim and gdb model FT32 memory by adding 0x800000 to RAM
45 * addresses. This means that sim/gdb can treat all addresses
48 * The address space looks like:
50 * 00000 start of code memory
51 * 3ffff end of code memory
56 #define RAM_BIAS 0x800000 /* Bias added to RAM addresses. */
59 ft32_extract_unsigned_integer (const unsigned char *addr, int len)
63 unsigned char *startaddr = (unsigned char *) addr;
64 unsigned char *endaddr = startaddr + len;
66 /* Start at the most significant end of the integer, and work towards
67 the least significant. */
70 for (p = endaddr; p > startaddr;)
71 retval = (retval << 8) | * -- p;
77 ft32_store_unsigned_integer (unsigned char *addr, int len, unsigned long val)
80 unsigned char *startaddr = (unsigned char *)addr;
81 unsigned char *endaddr = startaddr + len;
83 for (p = startaddr; p < endaddr; p++)
91 * Align EA according to its size DW.
92 * The FT32 ignores the low bit of a 16-bit addresss,
93 * and the low two bits of a 32-bit address.
95 static uint32_t ft32_align (uint32_t dw, uint32_t ea)
111 /* Read an item from memory address EA, sized DW. */
113 ft32_read_item (SIM_DESC sd, int dw, uint32_t ea)
115 sim_cpu *cpu = STATE_CPU (sd, 0);
116 address_word cia = CPU_PC_GET (cpu);
120 ea = ft32_align (dw, ea);
124 return sim_core_read_aligned_1 (cpu, cia, read_map, ea);
126 return sim_core_read_aligned_2 (cpu, cia, read_map, ea);
128 return sim_core_read_aligned_4 (cpu, cia, read_map, ea);
134 /* Write item V to memory address EA, sized DW. */
136 ft32_write_item (SIM_DESC sd, int dw, uint32_t ea, uint32_t v)
138 sim_cpu *cpu = STATE_CPU (sd, 0);
139 address_word cia = CPU_PC_GET (cpu);
142 ea = ft32_align (dw, ea);
146 sim_core_write_aligned_1 (cpu, cia, write_map, ea, v);
149 sim_core_write_aligned_2 (cpu, cia, write_map, ea, v);
152 sim_core_write_aligned_4 (cpu, cia, write_map, ea, v);
160 sim_engine_halt (sd, cpu, NULL, insnpc, sim_signalled, SIM_SIGILL)
162 static uint32_t cpu_mem_read (SIM_DESC sd, uint32_t dw, uint32_t ea)
164 sim_cpu *cpu = STATE_CPU (sd, 0);
165 uint32_t insnpc = cpu->state.pc;
172 /* Simulate some IO devices */
178 /* Read the simulator cycle timer. */
179 return cpu->state.cycles / 100;
181 sim_io_eprintf (sd, "Illegal IO read address %08x, pc %#x\n",
186 return ft32_read_item (sd, dw, RAM_BIAS + ea);
189 static void cpu_mem_write (SIM_DESC sd, uint32_t dw, uint32_t ea, uint32_t d)
191 sim_cpu *cpu = STATE_CPU (sd, 0);
195 /* Simulate some IO devices */
203 /* Unlock the PM write port */
204 cpu->state.pm_unlock = (d == 0x1337f7d1);
207 /* Set the PM write address register */
208 cpu->state.pm_addr = d;
211 if (cpu->state.pm_unlock)
214 ft32_write_item (sd, dw, cpu->state.pm_addr, d);
215 cpu->state.pm_addr += 4;
220 sim_engine_halt (sd, cpu, NULL, cpu->state.pc, sim_exited, cpu->state.regs[0]);
223 sim_io_printf (sd, "Debug write %08x\n", d);
226 sim_io_eprintf (sd, "Unknown IO write %08x to to %08x\n", d, ea);
230 ft32_write_item (sd, dw, RAM_BIAS + ea, d);
233 #define GET_BYTE(ea) cpu_mem_read (sd, 0, (ea))
234 #define PUT_BYTE(ea, d) cpu_mem_write (sd, 0, (ea), (d))
236 /* LSBS (n) is a mask of the least significant N bits. */
237 #define LSBS(n) ((1U << (n)) - 1)
239 static void ft32_push (SIM_DESC sd, uint32_t v)
241 sim_cpu *cpu = STATE_CPU (sd, 0);
242 cpu->state.regs[FT32_HARD_SP] -= 4;
243 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
244 cpu_mem_write (sd, 2, cpu->state.regs[FT32_HARD_SP], v);
247 static uint32_t ft32_pop (SIM_DESC sd)
249 sim_cpu *cpu = STATE_CPU (sd, 0);
250 uint32_t r = cpu_mem_read (sd, 2, cpu->state.regs[FT32_HARD_SP]);
251 cpu->state.regs[FT32_HARD_SP] += 4;
252 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
256 /* Extract the low SIZ bits of N as an unsigned number. */
257 static int nunsigned (int siz, int n)
259 return n & LSBS (siz);
262 /* Extract the low SIZ bits of N as a signed number. */
263 static int nsigned (int siz, int n)
265 int shift = (sizeof (int) * 8) - siz;
266 return (n << shift) >> shift;
269 /* Signed division N / D, matching hw behavior for (MIN_INT, -1). */
270 static uint32_t ft32sdiv (uint32_t n, uint32_t d)
272 if (n == 0x80000000UL && d == 0xffffffffUL)
275 return (uint32_t)((int)n / (int)d);
278 /* Signed modulus N % D, matching hw behavior for (MIN_INT, -1). */
279 static uint32_t ft32smod (uint32_t n, uint32_t d)
281 if (n == 0x80000000UL && d == 0xffffffffUL)
284 return (uint32_t)((int)n % (int)d);
287 /* Circular rotate right N by B bits. */
288 static uint32_t ror (uint32_t n, uint32_t b)
291 return (n >> b) | (n << (32 - b));
294 /* Implement the BINS machine instruction.
295 See FT32 Programmer's Reference for details. */
296 static uint32_t bins (uint32_t d, uint32_t f, uint32_t len, uint32_t pos)
298 uint32_t bitmask = LSBS (len) << pos;
299 return (d & ~bitmask) | ((f << pos) & bitmask);
302 /* Implement the FLIP machine instruction.
303 See FT32 Programmer's Reference for details. */
304 static uint32_t flip (uint32_t x, uint32_t b)
307 x = (x & 0x55555555) << 1 | (x & 0xAAAAAAAA) >> 1;
309 x = (x & 0x33333333) << 2 | (x & 0xCCCCCCCC) >> 2;
311 x = (x & 0x0F0F0F0F) << 4 | (x & 0xF0F0F0F0) >> 4;
313 x = (x & 0x00FF00FF) << 8 | (x & 0xFF00FF00) >> 8;
315 x = (x & 0x0000FFFF) << 16 | (x & 0xFFFF0000) >> 16;
320 step_once (SIM_DESC sd)
322 sim_cpu *cpu = STATE_CPU (sd, 0);
323 address_word cia = CPU_PC_GET (cpu);
349 inst = ft32_read_item (sd, 2, cpu->state.pc);
350 cpu->state.cycles += 1;
352 if ((STATE_ARCHITECTURE (sd)->mach == bfd_mach_ft32b)
353 && ft32_decode_shortcode (cpu->state.pc, inst, sc))
355 if ((cpu->state.pc & 3) == 0)
364 /* Handle "call 8" (which is FT32's "break" equivalent) here. */
365 if (inst == 0x00340002)
367 sim_engine_halt (sd, cpu, NULL,
369 sim_stopped, SIM_SIGTRAP);
373 dw = (inst >> FT32_FLD_DW_BIT) & LSBS (FT32_FLD_DW_SIZ);
374 cb = (inst >> FT32_FLD_CB_BIT) & LSBS (FT32_FLD_CB_SIZ);
375 r_d = (inst >> FT32_FLD_R_D_BIT) & LSBS (FT32_FLD_R_D_SIZ);
376 cr = (inst >> FT32_FLD_CR_BIT) & LSBS (FT32_FLD_CR_SIZ);
377 cv = (inst >> FT32_FLD_CV_BIT) & LSBS (FT32_FLD_CV_SIZ);
378 bt = (inst >> FT32_FLD_BT_BIT) & LSBS (FT32_FLD_BT_SIZ);
379 r_1 = (inst >> FT32_FLD_R_1_BIT) & LSBS (FT32_FLD_R_1_SIZ);
380 rimm = (inst >> FT32_FLD_RIMM_BIT) & LSBS (FT32_FLD_RIMM_SIZ);
381 r_2 = (inst >> FT32_FLD_R_2_BIT) & LSBS (FT32_FLD_R_2_SIZ);
382 k20 = nsigned (20, (inst >> FT32_FLD_K20_BIT) & LSBS (FT32_FLD_K20_SIZ));
383 pa = (inst >> FT32_FLD_PA_BIT) & LSBS (FT32_FLD_PA_SIZ);
384 aa = (inst >> FT32_FLD_AA_BIT) & LSBS (FT32_FLD_AA_SIZ);
385 k16 = (inst >> FT32_FLD_K16_BIT) & LSBS (FT32_FLD_K16_SIZ);
386 k15 = (inst >> FT32_FLD_K15_BIT) & LSBS (FT32_FLD_K15_SIZ);
391 al = (inst >> FT32_FLD_AL_BIT) & LSBS (FT32_FLD_AL_SIZ);
393 r_1v = cpu->state.regs[r_1];
394 rimmv = (rimm & 0x400) ? nsigned (10, rimm) : cpu->state.regs[rimm & 0x1f];
396 bit_pos = rimmv & 31;
397 bit_len = 0xf & (rimmv >> 5);
401 upper = (inst >> 27);
403 insnpc = cpu->state.pc;
404 cpu->state.pc += isize;
410 int take = (cr == 3) || ((1 & (cpu->state.regs[28 + cr] >> cb)) == cv);
413 cpu->state.cycles += 1;
415 ft32_push (sd, cpu->state.pc); /* this is a call. */
416 if (upper == FT32_PAT_TOC)
417 cpu->state.pc = pa << 2;
419 cpu->state.pc = cpu->state.regs[r_2];
420 if (cpu->state.pc == 0x8)
432 case 0x0: result = r_1v + rimmv; break;
433 case 0x1: result = ror (r_1v, rimmv); break;
434 case 0x2: result = r_1v - rimmv; break;
435 case 0x3: result = (r_1v << 10) | (1023 & rimmv); break;
436 case 0x4: result = r_1v & rimmv; break;
437 case 0x5: result = r_1v | rimmv; break;
438 case 0x6: result = r_1v ^ rimmv; break;
439 case 0x7: result = ~(r_1v ^ rimmv); break;
440 case 0x8: result = r_1v << rimmv; break;
441 case 0x9: result = r_1v >> rimmv; break;
442 case 0xa: result = (int32_t)r_1v >> rimmv; break;
443 case 0xb: result = bins (r_1v, rimmv >> 10, bit_len, bit_pos); break;
444 case 0xc: result = nsigned (bit_len, r_1v >> bit_pos); break;
445 case 0xd: result = nunsigned (bit_len, r_1v >> bit_pos); break;
446 case 0xe: result = flip (r_1v, rimmv); break;
448 sim_io_eprintf (sd, "Unhandled alu %#x\n", al);
451 if (upper == FT32_PAT_ALUOP)
452 cpu->state.regs[r_d] = result;
472 case 0: dwsiz = 7; dwmask = 0xffU; break;
473 case 1: dwsiz = 15; dwmask = 0xffffU; break;
474 case 2: dwsiz = 31; dwmask = 0xffffffffU; break;
477 zero = (0 == (result & dwmask));
478 sign = 1 & (result >> dwsiz);
479 ahi = 1 & (r_1v >> dwsiz);
480 bhi = 1 & (rimmv >> dwsiz);
481 overflow = (sign != ahi) & (ahi == !bhi);
487 case 0x0: carry = 1 & ((ra + rb) >> bit); break;
488 case 0x2: carry = 1 & ((ra - rb) >> bit); break;
489 default: carry = 0; break;
491 above = (!carry & !zero);
492 greater = (sign == overflow) & !zero;
493 greatereq = (sign == overflow);
495 cpu->state.regs[r_d] = (
508 cpu->state.regs[r_d] = k20;
512 cpu->state.regs[r_d] = ft32_read_item (sd, dw, pa << 2);
513 cpu->state.cycles += 1;
517 cpu->state.regs[r_d] = ft32_read_item (sd, dw, cpu->state.regs[r_1] + k15);
518 cpu->state.cycles += 1;
522 cpu_mem_write (sd, dw, aa, cpu->state.regs[r_d]);
526 cpu_mem_write (sd, dw, cpu->state.regs[r_d] + k15, cpu->state.regs[r_1]);
530 cpu->state.regs[r_d] = cpu_mem_read (sd, dw, aa);
531 cpu->state.cycles += 1;
535 cpu->state.regs[r_d] = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k15);
536 cpu->state.cycles += 1;
542 tmp = cpu_mem_read (sd, dw, aa);
543 cpu_mem_write (sd, dw, aa, cpu->state.regs[r_d]);
544 cpu->state.regs[r_d] = tmp;
545 cpu->state.cycles += 1;
552 tmp = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k15);
553 cpu_mem_write (sd, dw, cpu->state.regs[r_1] + k15, cpu->state.regs[r_d]);
554 cpu->state.regs[r_d] = tmp;
555 cpu->state.cycles += 1;
560 ft32_push (sd, r_1v);
564 ft32_push (sd, cpu->state.regs[r_d]);
565 cpu->state.regs[r_d] = cpu->state.regs[FT32_HARD_SP];
566 cpu->state.regs[FT32_HARD_SP] -= k16;
567 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
570 case FT32_PAT_UNLINK:
571 cpu->state.regs[FT32_HARD_SP] = cpu->state.regs[r_d];
572 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
573 cpu->state.regs[r_d] = ft32_pop (sd);
577 cpu->state.cycles += 1;
578 cpu->state.regs[r_d] = ft32_pop (sd);
581 case FT32_PAT_RETURN:
582 cpu->state.pc = ft32_pop (sd);
589 cpu->state.regs[r_d] = r_1v / rimmv;
592 cpu->state.regs[r_d] = r_1v % rimmv;
595 cpu->state.regs[r_d] = ft32sdiv (r_1v, rimmv);
598 cpu->state.regs[r_d] = ft32smod (r_1v, rimmv);
603 /* strcmp instruction. */
607 while ((GET_BYTE (a + i) != 0) &&
608 (GET_BYTE (a + i) == GET_BYTE (b + i)))
610 cpu->state.regs[r_d] = GET_BYTE (a + i) - GET_BYTE (b + i);
616 /* memcpy instruction. */
618 uint32_t dst = cpu->state.regs[r_d];
620 for (i = 0; i < (rimmv & 0x7fff); i++)
621 PUT_BYTE (dst + i, GET_BYTE (src + i));
626 /* strlen instruction. */
629 for (i = 0; GET_BYTE (src + i) != 0; i++)
631 cpu->state.regs[r_d] = i;
636 /* memset instruction. */
637 uint32_t dst = cpu->state.regs[r_d];
639 for (i = 0; i < (rimmv & 0x7fff); i++)
640 PUT_BYTE (dst + i, r_1v);
644 cpu->state.regs[r_d] = r_1v * rimmv;
647 cpu->state.regs[r_d] = ((uint64_t)r_1v * (uint64_t)rimmv) >> 32;
651 /* stpcpy instruction. */
653 uint32_t dst = cpu->state.regs[r_d];
655 for (i = 0; GET_BYTE (src + i) != 0; i++)
656 PUT_BYTE (dst + i, GET_BYTE (src + i));
657 PUT_BYTE (dst + i, 0);
658 cpu->state.regs[r_d] = dst + i;
663 /* streamout instruction. */
665 uint32_t src = cpu->state.regs[r_1];
666 for (i = 0; i < rimmv; i += (1 << dw))
670 cpu->state.regs[r_d],
671 cpu_mem_read (sd, dw, src));
677 sim_io_eprintf (sd, "Unhandled ffu %#x at %08x\n", al, insnpc);
683 sim_io_eprintf (sd, "Unhandled pattern %d at %08x\n", upper, insnpc);
693 sim_engine_run (SIM_DESC sd,
694 int next_cpu_nr, /* ignore */
695 int nr_cpus, /* ignore */
696 int siggnal) /* ignore */
700 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
702 cpu = STATE_CPU (sd, 0);
707 if (sim_events_tick (sd))
708 sim_events_process (sd);
713 ft32_lookup_register (SIM_CPU *cpu, int nr)
715 /* Handle the register number translation here.
716 * Sim registers are 0-31.
717 * Other tools (gcc, gdb) use:
724 if ((nr < 0) || (nr > 32))
726 sim_io_eprintf (CPU_STATE (cpu), "unknown register %i\n", nr);
733 return &cpu->state.regs[FT32_HARD_FP];
735 return &cpu->state.regs[FT32_HARD_SP];
737 return &cpu->state.regs[FT32_HARD_CC];
739 return &cpu->state.pc;
741 return &cpu->state.regs[nr - 2];
746 ft32_reg_store (SIM_CPU *cpu,
751 if (0 <= rn && rn <= 32)
754 *ft32_lookup_register (cpu, rn) = ft32_extract_unsigned_integer (memory, 4);
763 ft32_reg_fetch (SIM_CPU *cpu,
768 if (0 <= rn && rn <= 32)
771 ft32_store_unsigned_integer (memory, 4, *ft32_lookup_register (cpu, rn));
780 ft32_pc_get (SIM_CPU *cpu)
782 return cpu->state.pc;
786 ft32_pc_set (SIM_CPU *cpu, sim_cia newpc)
788 cpu->state.pc = newpc;
791 /* Cover function of sim_state_free to free the cpu buffers as well. */
794 free_state (SIM_DESC sd)
796 if (STATE_MODULES (sd) != NULL)
797 sim_module_uninstall (sd);
798 sim_cpu_free_all (sd);
803 sim_open (SIM_OPEN_KIND kind,
810 SIM_DESC sd = sim_state_alloc (kind, cb);
812 /* Set default options before parsing user options. */
813 current_alignment = STRICT_ALIGNMENT;
814 current_target_byte_order = BFD_ENDIAN_LITTLE;
816 /* The cpu data is kept in a separately allocated chunk of memory. */
817 if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
823 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
829 /* The parser will print an error message for us, so we silently return. */
830 if (sim_parse_args (sd, argv) != SIM_RC_OK)
836 /* Allocate external memory if none specified by user.
837 Use address 4 here in case the user wanted address 0 unmapped. */
838 if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
840 sim_do_command (sd, "memory region 0x00000000,0x40000");
841 sim_do_command (sd, "memory region 0x800000,0x10000");
844 /* Check for/establish the reference program image. */
845 if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK)
851 /* Configure/verify the target byte order and other runtime
852 configuration options. */
853 if (sim_config (sd) != SIM_RC_OK)
859 if (sim_post_argv_init (sd) != SIM_RC_OK)
865 /* CPU specific initialization. */
866 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
868 SIM_CPU *cpu = STATE_CPU (sd, i);
870 CPU_REG_FETCH (cpu) = ft32_reg_fetch;
871 CPU_REG_STORE (cpu) = ft32_reg_store;
872 CPU_PC_FETCH (cpu) = ft32_pc_get;
873 CPU_PC_STORE (cpu) = ft32_pc_set;
880 sim_create_inferior (SIM_DESC sd,
886 sim_cpu *cpu = STATE_CPU (sd, 0);
887 host_callback *cb = STATE_CALLBACK (sd);
891 addr = bfd_get_start_address (abfd);
895 /* Standalone mode (i.e. `run`) will take care of the argv for us in
896 sim_open() -> sim_parse_args(). But in debug mode (i.e. 'target sim'
897 with `gdb`), we need to handle it because the user can change the
898 argv on the fly via gdb's 'run'. */
899 if (STATE_PROG_ARGV (sd) != argv)
901 freeargv (STATE_PROG_ARGV (sd));
902 STATE_PROG_ARGV (sd) = dupargv (argv);
905 if (STATE_PROG_ENVP (sd) != env)
907 freeargv (STATE_PROG_ENVP (sd));
908 STATE_PROG_ENVP (sd) = dupargv (env);
911 cb->argv = STATE_PROG_ARGV (sd);
912 cb->envp = STATE_PROG_ENVP (sd);
914 cpu->state.regs[FT32_HARD_SP] = addr;
915 cpu->state.num_i = 0;
916 cpu->state.cycles = 0;
917 cpu->state.next_tick_cycle = 100000;