gprofng/common/core_pcbe.c

   1 /* Copyright (C) 2021 Free Software Foundation, Inc.
   2    Contributed by Oracle.
   3
   4    This file is part of GNU Binutils.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21 /*
  22  * Performance Counter Back-End for Intel Family 6
  23  *   Models 15(06_0FH) 23(06_17H)                       (Core 2)
  24  *   Models 28(06_1CH)                                  (Atom)
  25  *   Models 37(06_25H) 44(06_2CH)                       (Westmere)
  26  *   Models 26(06_1AH) 30(06_1EH) 31(06_1FH) 46(06_2EH) (Nehalem)
  27  *   Models 42(06_2AH) 45(06_2DH)                       (Sandy Bridge)
  28  *   Models 58(06_3AH) 62(06_3EH)                       (Ivy Bridge)
  29  *   Models 60(06_3CH) 63(06_3FH) 69(06_45H) 70(06_46H) (Haswell)
  30  *   Models 61(06_3DH) 71(06_47H) 79(06_4FH) 86(06_??H) (Broadwell) (79 not listed in Intel SDM as of June 2015)
  31  *   Models 78(06_4EH) 85(06_55H) 94(06_5EH)            (Skylake) (Note Skylake and later: versionID==4)
  32  * To add another model number:
  33  *   - add appropriate table data in the form
  34  *       #define EVENTS_FAM6_MODXX
  35  *   - add appropriate table definitions in the form
  36  *       const struct events_table_t events_fam6_modXX[] =
  37  *   - set events_table to the appropriate table
  38  *     using the "switch ( cpuid_getmodel(CPU) )" statement
  39  *     in core_pcbe_init()
  40  *   - check the date in core_pcbe_cpuref()
  41  * Table data can be derived from:
  42  *   - the Intel SDM
  43  *       also https://download.01.org/perfmon/
  44  *   - libcpc source code in usr/src/uts/intel/pcbe/
  45  *   - libpfm4
  46  * but there are typically inconsistencies among these
  47  * sources of data.  So, judgment is required.
  48  * Other things to do to add a new processor:
  49  *   x file hwc_cpus.h
  50  *     add a cpuver enumerator
  51  *     add lookup entry
  52  *   x file hwctable.c
  53  *     add a table (aliases, etc.)
  54  *     add a cputabs entry, including default metrics
  55  *     look for other places where the most-recently-added CPU is mentioned
  56  *   x file cpu_frequency.h
  57  *     function get_max_turbo_freq()
  58  *     go to "switch (model)", and add turbo boosts
  59  */
  60
  61 #include <sys/types.h>
  62 #include "hwcdrv.h"
  63
  64 static uint64_t num_gpc;    /* number of general purpose counters (e.g. 2-4) */
  65 static uint64_t num_ffc;    /* number fixed function counters (e.g. 3) */
  66 static uint_t total_pmc;    /* num_gpc + num_ffc */
  67
  68 /*
  69  * Only the lower 32-bits can be written to in the general-purpose
  70  * counters.  The higher bits are extended from bit 31; all ones if
  71  * bit 31 is one and all zeros otherwise.
  72  *
  73  * The fixed-function counters do not have this restriction.
  74  */
  75
  76 static const char *ffc_names[] = {
  77 /*
  78  * While modern Intel processors have fixed-function counters (FFCs),
  79  * on Linux we access HWCs through the perf_event_open() kernel interface,
  80  * which does not allow us direct access to the FFCs.
  81  * Rather, the Linux kernel manages registers opaquely.
  82  * At best, it allows us extra HW events by off-loading
  83  * HWCs to FFCs as available.  Often, however, the FFCs
  84  * are commandeered by other activities like the NMI watchdog.
  85  * We will omit any explicit reference to them.
  86  * https://lists.eecs.utk.edu/pipermail/perfapi-devel/2015-February/006895.html
  87  * See also bug 21315497.
  88  */
  89 #if 0
  90         "instr_retired.any",
  91         "cpu_clk_unhalted.core",
  92         "cpu_clk_unhalted.ref",
  93 #endif
  94         NULL
  95 };
  96
  97 #define IMPL_NAME_LEN   100
  98 static char core_impl_name[IMPL_NAME_LEN];
  99
 100 /*
 101  * Most events require only an event code and a umask.
 102  * Some also require attributes, cmasks, or MSR programming.
 103  * Until Sandy Bridge, the number of these other events
 104  * was small and libcpc just ignored them.
 105  * With Sandy Bridge, libcpc added for support for these
 106  * additional events.
 107  *
 108  * We use an expanded events_table_t here -- patterned
 109  * after snb_pcbe_events_table_t in libcpc's
 110  * usr/src/uts/intel/pcbe/snb_pcbe.h -- for all processors.
 111  *
 112  * Correspondingly, we also define ATTR_* macros, but we
 113  * define them to set bits as they will appear
 114  * in bits 16-23 of the final eventsel.  Definitions of those
 115  * bits can be found in "struct ia32_perfevtsel" in libcpc's
 116  * usr/src/uts/intel/pcbe/intel_pcbe_utils.h .
 117  *
 118  * For now, I don't know how to handle msr_offset.
 119  * So, let's not include events that call for it.
 120  *
 121  * For now, don't do anything with ATTR_PEBS other than
 122  * to note it in tables (starting with Haswell).
 123  *
 124  * Solaris tables also have ATTR_PEBS_ONLY.  We cannot
 125  * use these counters from "collect -h" and so do not
 126  * include them.
 127  */
 128 #define ATTR_NONE               0
 129 #define ATTR_EDGE               (1 << 2) /* bit 18 - offset 16 */
 130 #define ATTR_ANY                (1 << 5) /* bit 21 - offset 16 */
 131 #define ATTR_INV                (1 << 7) /* bit 23 - offset 16 */
 132 #define ATTR_PEBS               ATTR_NONE // PEBS not supported
 133 #define ATTR_TSX                ATTR_NONE // TSX MSRs not supported
 134 #undef ATTR_PEBS_ONLY           // PEBS-only event, not supported
 135 #undef ATTR_PEBS_ONLY_LD_LAT    // not supported
 136
 137 struct events_table_t
 138 {
 139   uint32_t eventselect;
 140   uint32_t unitmask;
 141   uint64_t supported_counters;
 142   const char *name;
 143   uint8_t cmask;
 144   uint8_t attrs;
 145   uint16_t msr_offset;
 146 };
 147
 148 /* Used to describe which counters support an event */
 149 #define C(x)    (1 << (x))
 150 #define C0      C(0)
 151 #define C1      C(1)
 152 #define C2      C(2)
 153 #define C3      C(3)
 154 #define C_ALL   0xFFFFFFFFFFFFFFFF
 155 #define CDEAD   0 /* Counter that is broken  */
 156
 157 /* note that regular events use the original spelling like "inst_retired.any_p" */
 158 #define ARCH_EVENTS /* NOTE: Order specified in PRM must be maintained! */ \
 159 { 0x3C, 0x00, C_ALL, "unhalted-core-cycles"         , 0x0, ATTR_NONE, 0x0 }, \
 160 { 0x3C, 0x01, C_ALL, "unhalted-reference-cycles"    , 0x0, ATTR_NONE, 0x0 }, \
 161 { 0xC0, 0x00, C_ALL, "instruction-retired"          , 0x0, ATTR_NONE, 0x0 }, \
 162 { 0x2E, 0x4F, C_ALL, "llc-reference"    , 0x0, ATTR_NONE, 0x0 }, \
 163 { 0x2E, 0x41, C_ALL, "llc-misses"       , 0x0, ATTR_NONE, 0x0 }, \
 164 { 0xC4, 0x00, C_ALL, "branch-instruction-retired"   , 0x0, ATTR_NONE, 0x0 }, \
 165 { 0xC5, 0x00, C_ALL, "branch-misses-retired"        , 0x0, ATTR_NONE, 0x0 }, \
 166 /* end of #define */
 167
 168 /*
 169  * FAM6/MOD15:
 170  *  Xeon 3000, 3200, 5100, 5300, 7300
 171  *  Core 2 Quad, Extreme, and Duo
 172  *  Pentium dual-core processors
 173  * FAM6/MOD23:
 174  *  Xeon 5200, 5400 series, Intel
 175  *  Core 2 Quad Q9650.
 176  */
 177 #define EVENTS_FAM6_MOD23                                               \
 178 { 0x03, 0x00, C0|C1, "load_block"                           , 0x0, ATTR_NONE, 0x0 }, \
 179 { 0x03, 0x02, C0|C1, "load_block.sta"                       , 0x0, ATTR_NONE, 0x0 }, \
 180 { 0x03, 0x04, C0|C1, "load_block.std"                       , 0x0, ATTR_NONE, 0x0 }, \
 181 { 0x03, 0x08, C0|C1, "load_block.overlap_store"             , 0x0, ATTR_NONE, 0x0 }, \
 182 { 0x03, 0x10, C0|C1, "load_block.until_retire"              , 0x0, ATTR_NONE, 0x0 }, \
 183 { 0x03, 0x20, C0|C1, "load_block.l1d"                       , 0x0, ATTR_NONE, 0x0 }, \
 184 { 0x04, 0x00, C0|C1, "store_block"                          , 0x0, ATTR_NONE, 0x0 }, \
 185 { 0x04, 0x01, C0|C1, "store_block.drain_cycles" /*spell-diff*/    , 0x0, ATTR_NONE, 0x0 }, \
 186 { 0x04, 0x02, C0|C1, "store_block.order"                    , 0x0, ATTR_NONE, 0x0 }, \
 187 { 0x04, 0x08, C0|C1, "store_block.snoop"                    , 0x0, ATTR_NONE, 0x0 }, \
 188 { 0x05, 0x00, C0|C1, "misalign_mem_ref"                     , 0x0, ATTR_NONE, 0x0 }, \
 189 { 0x06, 0x00, C0|C1, "segment_reg_loads"                    , 0x0, ATTR_NONE, 0x0 }, \
 190 { 0x07, 0x00, C0|C1, "sse_pre_exec"                         , 0x0, ATTR_NONE, 0x0 }, \
 191 { 0x07, 0x00, C0|C1, "sse_pre_exec.nta"                     , 0x0, ATTR_NONE, 0x0 }, \
 192 { 0x07, 0x01, C0|C1, "sse_pre_exec.l1"                      , 0x0, ATTR_NONE, 0x0 }, \
 193 { 0x07, 0x02, C0|C1, "sse_pre_exec.l2"                      , 0x0, ATTR_NONE, 0x0 }, \
 194 { 0x07, 0x03, C0|C1, "sse_pre_exec.stores"                  , 0x0, ATTR_NONE, 0x0 }, \
 195 { 0x08, 0x00, C0|C1, "dtlb_misses"                          , 0x0, ATTR_NONE, 0x0 }, \
 196 { 0x08, 0x01, C0|C1, "dtlb_misses.any"                      , 0x0, ATTR_NONE, 0x0 }, \
 197 { 0x08, 0x02, C0|C1, "dtlb_misses.miss_ld"                  , 0x0, ATTR_NONE, 0x0 }, \
 198 { 0x08, 0x04, C0|C1, "dtlb_misses.l0_miss_ld"               , 0x0, ATTR_NONE, 0x0 }, \
 199 { 0x08, 0x08, C0|C1, "dtlb_misses.miss_st"                  , 0x0, ATTR_NONE, 0x0 }, \
 200 { 0x09, 0x00, C0|C1, "memory_disambiguation"                , 0x0, ATTR_NONE, 0x0 }, \
 201 { 0x09, 0x01, C0|C1, "memory_disambiguation.reset"          , 0x0, ATTR_NONE, 0x0 }, \
 202 { 0x09, 0x02, C0|C1, "memory_disambiguation.success"        , 0x0, ATTR_NONE, 0x0 }, \
 203 { 0x0c, 0x00, C0|C1, "page_walks"                           , 0x0, ATTR_NONE, 0x0 }, \
 204 { 0x0c, 0x01, C0|C1, "page_walks.count"                     , 0x0, ATTR_NONE, 0x0 }, \
 205 { 0x0c, 0x02, C0|C1, "page_walks.cycles"                    , 0x0, ATTR_NONE, 0x0 }, \
 206 { 0x10, 0x00, C0   , "fp_comp_ops_exe"                      , 0x0, ATTR_NONE, 0x0 }, \
 207 { 0x11, 0x00,    C1, "fp_assist"                            , 0x0, ATTR_NONE, 0x0 }, \
 208 { 0x12, 0x00,    C1, "mul"                                  , 0x0, ATTR_NONE, 0x0 }, \
 209 { 0x13, 0x00,    C1, "div"                                  , 0x0, ATTR_NONE, 0x0 }, \
 210 { 0x14, 0x00, C0   , "cycles_div_busy"                      , 0x0, ATTR_NONE, 0x0 }, \
 211 { 0x18, 0x00, C0   , "idle_during_div"                      , 0x0, ATTR_NONE, 0x0 }, \
 212 { 0x19, 0x00,    C1, "delayed_bypass"                       , 0x0, ATTR_NONE, 0x0 }, \
 213 { 0x19, 0x00,    C1, "delayed_bypass.fp"                    , 0x0, ATTR_NONE, 0x0 }, \
 214 { 0x19, 0x01,    C1, "delayed_bypass.simd"                  , 0x0, ATTR_NONE, 0x0 }, \
 215 { 0x19, 0x02,    C1, "delayed_bypass.load"                  , 0x0, ATTR_NONE, 0x0 }, \
 216 { 0x21, 0x00, C0|C1, "l2_ads"                               , 0x0, ATTR_NONE, 0x0 }, \
 217 { 0x23, 0x00, C0|C1, "l2_dbus_busy_rd"                      , 0x0, ATTR_NONE, 0x0 }, \
 218 { 0x24, 0x00, C0|C1, "l2_lines_in"                          , 0x0, ATTR_NONE, 0x0 }, \
 219 { 0x25, 0x00, C0|C1, "l2_m_lines_in"                        , 0x0, ATTR_NONE, 0x0 }, \
 220 { 0x26, 0x00, C0|C1, "l2_lines_out"                         , 0x0, ATTR_NONE, 0x0 }, \
 221 { 0x27, 0x00, C0|C1, "l2_m_lines_out"                       , 0x0, ATTR_NONE, 0x0 }, \
 222 { 0x28, 0x00, C0|C1, "l2_ifetch"                            , 0x0, ATTR_NONE, 0x0 }, \
 223 { 0x29, 0x00, C0|C1, "l2_ld"                                , 0x0, ATTR_NONE, 0x0 }, \
 224 { 0x2a, 0x00, C0|C1, "l2_st"                                , 0x0, ATTR_NONE, 0x0 }, \
 225 { 0x2b, 0x00, C0|C1, "l2_lock"                              , 0x0, ATTR_NONE, 0x0 }, \
 226 { 0x2e, 0x00, C0|C1, "l2_rqsts"                             , 0x0, ATTR_NONE, 0x0 }, \
 227 { 0x2e, 0x41, C0|C1, "l2_rqsts.self.demand.i_state"         , 0x0, ATTR_NONE, 0x0 }, \
 228 { 0x2e, 0x4f, C0|C1, "l2_rqsts.self.demand.mesi"            , 0x0, ATTR_NONE, 0x0 }, \
 229 { 0x30, 0x00, C0|C1, "l2_reject_busq"                       , 0x0, ATTR_NONE, 0x0 }, \
 230 { 0x32, 0x00, C0|C1, "l2_no_req"                            , 0x0, ATTR_NONE, 0x0 }, \
 231 { 0x3a, 0x00, C0|C1, "eist_trans"                           , 0x0, ATTR_NONE, 0x0 }, \
 232 { 0x3b, 0xc0, C0|C1, "thermal_trip" /*non-zero umask*/      , 0x0, ATTR_NONE, 0x0 }, \
 233 { 0x3c, 0x00, C0|C1, "cpu_clk_unhalted"                     , 0x0, ATTR_NONE, 0x0 }, \
 234 { 0x3c, 0x00, C0|C1, "cpu_clk_unhalted.core_p"              , 0x0, ATTR_NONE, 0x0 }, \
 235 { 0x3c, 0x01, C0|C1, "cpu_clk_unhalted.bus"                 , 0x0, ATTR_NONE, 0x0 }, \
 236 { 0x3c, 0x02, C0|C1, "cpu_clk_unhalted.no_other"            , 0x0, ATTR_NONE, 0x0 }, \
 237 { 0x40, 0x00, C0|C1, "l1d_cache_ld"                         , 0x0, ATTR_NONE, 0x0 }, \
 238 { 0x41, 0x00, C0|C1, "l1d_cache_st"                         , 0x0, ATTR_NONE, 0x0 }, \
 239 { 0x42, 0x00, C0|C1, "l1d_cache_lock"                       , 0x0, ATTR_NONE, 0x0 }, \
 240 { 0x42, 0x10, C0|C1, "l1d_cache_lock.duration" /*spelling*/ , 0x0, ATTR_NONE, 0x0 }, \
 241 { 0x43, 0x00, C0|C1, "l1d_all"                              , 0x0, ATTR_NONE, 0x0 }, \
 242 { 0x43, 0x00, C0|C1, "l1d_all_ref"                          , 0x0, ATTR_NONE, 0x0 }, \
 243 { 0x43, 0x01, C0|C1, "l1d_all.ref" /*spelling*/             , 0x0, ATTR_NONE, 0x0 }, \
 244 { 0x43, 0x02, C0|C1, "l1d_all.cache_ref" /*spelling*/       , 0x0, ATTR_NONE, 0x0 }, \
 245 { 0x45, 0x0f, C0|C1, "l1d_repl" /*non-zero umask*/          , 0x0, ATTR_NONE, 0x0 }, \
 246 { 0x46, 0x00, C0|C1, "l1d_m_repl"                           , 0x0, ATTR_NONE, 0x0 }, \
 247 { 0x47, 0x00, C0|C1, "l1d_m_evict"                          , 0x0, ATTR_NONE, 0x0 }, \
 248 { 0x48, 0x00, C0|C1, "l1d_pend_miss"                        , 0x0, ATTR_NONE, 0x0 }, \
 249 { 0x49, 0x00, C0|C1, "l1d_split"                            , 0x0, ATTR_NONE, 0x0 }, \
 250 { 0x49, 0x01, C0|C1, "l1d_split.loads"                      , 0x0, ATTR_NONE, 0x0 }, \
 251 { 0x49, 0x02, C0|C1, "l1d_split.stores"                     , 0x0, ATTR_NONE, 0x0 }, \
 252 { 0x4b, 0x00, C0|C1, "sse_pre_miss"                         , 0x0, ATTR_NONE, 0x0 }, \
 253 { 0x4b, 0x00, C0|C1, "sse_pre_miss.nta"                     , 0x0, ATTR_NONE, 0x0 }, \
 254 { 0x4b, 0x01, C0|C1, "sse_pre_miss.l1"                      , 0x0, ATTR_NONE, 0x0 }, \
 255 { 0x4b, 0x02, C0|C1, "sse_pre_miss.l2"                      , 0x0, ATTR_NONE, 0x0 }, \
 256 { 0x4c, 0x00, C0|C1, "load_hit_pre"                         , 0x0, ATTR_NONE, 0x0 }, \
 257 { 0x4e, 0x00, C0|C1, "l1d_prefetch"                         , 0x0, ATTR_NONE, 0x0 }, \
 258 { 0x4e, 0x10, C0|C1, "l1d_prefetch.requests"                , 0x0, ATTR_NONE, 0x0 }, \
 259 { 0x60, 0x00, C0|C1, "bus_request_outstanding"              , 0x0, ATTR_NONE, 0x0 }, \
 260 { 0x61, 0x00, C0|C1, "bus_bnr_drv"                          , 0x0, ATTR_NONE, 0x0 }, \
 261 { 0x62, 0x00, C0|C1, "bus_drdy_clocks"                      , 0x0, ATTR_NONE, 0x0 }, \
 262 { 0x63, 0x00, C0|C1, "bus_lock_clocks"                      , 0x0, ATTR_NONE, 0x0 }, \
 263 { 0x64, 0x00, C0|C1, "bus_data_rcv"                         , 0x0, ATTR_NONE, 0x0 }, \
 264 { 0x65, 0x00, C0|C1, "bus_trans_brd"                        , 0x0, ATTR_NONE, 0x0 }, \
 265 { 0x66, 0x00, C0|C1, "bus_trans_rfo"                        , 0x0, ATTR_NONE, 0x0 }, \
 266 { 0x67, 0x00, C0|C1, "bus_trans_wb"                         , 0x0, ATTR_NONE, 0x0 }, \
 267 { 0x68, 0x00, C0|C1, "bus_trans_ifetch"                     , 0x0, ATTR_NONE, 0x0 }, \
 268 { 0x69, 0x00, C0|C1, "bus_trans_inval"                      , 0x0, ATTR_NONE, 0x0 }, \
 269 { 0x6a, 0x00, C0|C1, "bus_trans_pwr"                        , 0x0, ATTR_NONE, 0x0 }, \
 270 { 0x6b, 0x00, C0|C1, "bus_trans_p"                          , 0x0, ATTR_NONE, 0x0 }, \
 271 { 0x6c, 0x00, C0|C1, "bus_trans_io"                         , 0x0, ATTR_NONE, 0x0 }, \
 272 { 0x6d, 0x00, C0|C1, "bus_trans_def"                        , 0x0, ATTR_NONE, 0x0 }, \
 273 { 0x6e, 0x00, C0|C1, "bus_trans_burst"                      , 0x0, ATTR_NONE, 0x0 }, \
 274 { 0x6f, 0x00, C0|C1, "bus_trans_mem"                        , 0x0, ATTR_NONE, 0x0 }, \
 275 { 0x70, 0x00, C0|C1, "bus_trans_any"                        , 0x0, ATTR_NONE, 0x0 }, \
 276 { 0x77, 0x00, C0|C1, "ext_snoop"                            , 0x0, ATTR_NONE, 0x0 }, \
 277 { 0x78, 0x00, C0|C1, "cmp_snoop"                            , 0x0, ATTR_NONE, 0x0 }, \
 278 { 0x7a, 0x00, C0|C1, "bus_hit_drv"                          , 0x0, ATTR_NONE, 0x0 }, \
 279 { 0x7b, 0x00, C0|C1, "bus_hitm_drv"                         , 0x0, ATTR_NONE, 0x0 }, \
 280 { 0x7d, 0x00, C0|C1, "busq_empty"                           , 0x0, ATTR_NONE, 0x0 }, \
 281 { 0x7e, 0x00, C0|C1, "snoop_stall_drv"                      , 0x0, ATTR_NONE, 0x0 }, \
 282 { 0x7f, 0x00, C0|C1, "bus_io_wait"                          , 0x0, ATTR_NONE, 0x0 }, \
 283 { 0x80, 0x00, C0|C1, "l1i_reads"                            , 0x0, ATTR_NONE, 0x0 }, \
 284 { 0x81, 0x00, C0|C1, "l1i_misses"                           , 0x0, ATTR_NONE, 0x0 }, \
 285 { 0x82, 0x00, C0|C1, "itlb"                                 , 0x0, ATTR_NONE, 0x0 }, \
 286 { 0x82, 0x02, C0|C1, "itlb.small_miss"                      , 0x0, ATTR_NONE, 0x0 }, \
 287 { 0x82, 0x10, C0|C1, "itlb.large_miss"                      , 0x0, ATTR_NONE, 0x0 }, \
 288 { 0x82, 0x12, C0|C1, "itlb.misses"                          , 0x0, ATTR_NONE, 0x0 }, \
 289 { 0x82, 0x40, C0|C1, "itlb.flush"                           , 0x0, ATTR_NONE, 0x0 }, \
 290 { 0x83, 0x00, C0|C1, "inst_queue"                           , 0x0, ATTR_NONE, 0x0 }, \
 291 { 0x83, 0x02, C0|C1, "inst_queue.full"                      , 0x0, ATTR_NONE, 0x0 }, \
 292 { 0x86, 0x00, C0|C1, "cycles_l1i_mem_stalled"               , 0x0, ATTR_NONE, 0x0 }, \
 293 { 0x87, 0x00, C0|C1, "ild_stall"                            , 0x0, ATTR_NONE, 0x0 }, \
 294 { 0x88, 0x00, C0|C1, "br_inst_exec"                         , 0x0, ATTR_NONE, 0x0 }, \
 295 { 0x89, 0x00, C0|C1, "br_missp_exec"                        , 0x0, ATTR_NONE, 0x0 }, \
 296 { 0x8a, 0x00, C0|C1, "br_bac_missp_exec"                    , 0x0, ATTR_NONE, 0x0 }, \
 297 { 0x8b, 0x00, C0|C1, "br_cnd_exec"                          , 0x0, ATTR_NONE, 0x0 }, \
 298 { 0x8c, 0x00, C0|C1, "br_cnd_missp_exec"                    , 0x0, ATTR_NONE, 0x0 }, \
 299 { 0x8d, 0x00, C0|C1, "br_ind_exec"                          , 0x0, ATTR_NONE, 0x0 }, \
 300 { 0x8e, 0x00, C0|C1, "br_ind_missp_exec"                    , 0x0, ATTR_NONE, 0x0 }, \
 301 { 0x8f, 0x00, C0|C1, "br_ret_exec"                          , 0x0, ATTR_NONE, 0x0 }, \
 302 { 0x90, 0x00, C0|C1, "br_ret_missp_exec"                    , 0x0, ATTR_NONE, 0x0 }, \
 303 { 0x91, 0x00, C0|C1, "br_ret_bac_missp_exec"                , 0x0, ATTR_NONE, 0x0 }, \
 304 { 0x92, 0x00, C0|C1, "br_call_exec"                         , 0x0, ATTR_NONE, 0x0 }, \
 305 { 0x93, 0x00, C0|C1, "br_call_missp_exec"                   , 0x0, ATTR_NONE, 0x0 }, \
 306 { 0x94, 0x00, C0|C1, "br_ind_call_exec"                     , 0x0, ATTR_NONE, 0x0 }, \
 307 { 0x97, 0x00, C0|C1, "br_tkn_bubble_1"                      , 0x0, ATTR_NONE, 0x0 }, \
 308 { 0x98, 0x00, C0|C1, "br_tkn_bubble_2"                      , 0x0, ATTR_NONE, 0x0 }, \
 309 { 0xa0, 0x00, C0|C1, "rs_uops_dispatched"                   , 0x0, ATTR_NONE, 0x0 }, \
 310 { 0xa1, 0x00, C0   , "rs_uops_dispatched_port"              , 0x0, ATTR_NONE, 0x0 }, \
 311 { 0xa1, 0x01, C0   , "rs_uops_dispatched_port.0" /*spelling*/     , 0x0, ATTR_NONE, 0x0 }, \
 312 { 0xa1, 0x02, C0   , "rs_uops_dispatched_port.1" /*spelling*/     , 0x0, ATTR_NONE, 0x0 }, \
 313 { 0xa1, 0x04, C0   , "rs_uops_dispatched_port.2" /*spelling*/     , 0x0, ATTR_NONE, 0x0 }, \
 314 { 0xa1, 0x08, C0   , "rs_uops_dispatched_port.3" /*spelling*/     , 0x0, ATTR_NONE, 0x0 }, \
 315 { 0xa1, 0x10, C0   , "rs_uops_dispatched_port.4" /*spelling*/     , 0x0, ATTR_NONE, 0x0 }, \
 316 { 0xa1, 0x20, C0   , "rs_uops_dispatched_port.5" /*spelling*/     , 0x0, ATTR_NONE, 0x0 }, \
 317 { 0xaa, 0x00, C0|C1, "macro_insts"                          , 0x0, ATTR_NONE, 0x0 }, \
 318 { 0xaa, 0x01, C0|C1, "macro_insts.decoded"                  , 0x0, ATTR_NONE, 0x0 }, \
 319 { 0xaa, 0x08, C0|C1, "macro_insts.cisc_decoded"             , 0x0, ATTR_NONE, 0x0 }, \
 320 { 0xab, 0x00, C0|C1, "esp"                                  , 0x0, ATTR_NONE, 0x0 }, \
 321 { 0xab, 0x01, C0|C1, "esp.synch"                            , 0x0, ATTR_NONE, 0x0 }, \
 322 { 0xab, 0x02, C0|C1, "esp.additions"                        , 0x0, ATTR_NONE, 0x0 }, \
 323 { 0xb0, 0x00, C0|C1, "simd_uops_exec"                       , 0x0, ATTR_NONE, 0x0 }, \
 324 { 0xb1, 0x00, C0|C1, "simd_sat_uop_exec"                    , 0x0, ATTR_NONE, 0x0 }, \
 325 { 0xb3, 0x00, C0|C1, "simd_uop_type_exec"                   , 0x0, ATTR_NONE, 0x0 }, \
 326 { 0xb3, 0x01, C0|C1, "simd_uop_type_exec.mul"               , 0x0, ATTR_NONE, 0x0 }, \
 327 { 0xb3, 0x02, C0|C1, "simd_uop_type_exec.shift"             , 0x0, ATTR_NONE, 0x0 }, \
 328 { 0xb3, 0x04, C0|C1, "simd_uop_type_exec.pack"              , 0x0, ATTR_NONE, 0x0 }, \
 329 { 0xb3, 0x08, C0|C1, "simd_uop_type_exec.unpack"            , 0x0, ATTR_NONE, 0x0 }, \
 330 { 0xb3, 0x10, C0|C1, "simd_uop_type_exec.logical"           , 0x0, ATTR_NONE, 0x0 }, \
 331 { 0xb3, 0x20, C0|C1, "simd_uop_type_exec.arithmetic"        , 0x0, ATTR_NONE, 0x0 }, \
 332 { 0xc0, 0x00, C0|C1, "inst_retired"                         , 0x0, ATTR_NONE, 0x0 }, \
 333 { 0xc0, 0x00, C0|C1, "inst_retired.any_p"                   , 0x0, ATTR_NONE, 0x0 }, \
 334 { 0xc0, 0x01, C0|C1, "inst_retired.loads"                   , 0x0, ATTR_NONE, 0x0 }, \
 335 { 0xc0, 0x02, C0|C1, "inst_retired.stores"                  , 0x0, ATTR_NONE, 0x0 }, \
 336 { 0xc0, 0x04, C0|C1, "inst_retired.other"                   , 0x0, ATTR_NONE, 0x0 }, \
 337 { 0xc0, 0x08, C0|C1, "inst_retired.vm_h"                    , 0x0, ATTR_NONE, 0x0 }, \
 338 { 0xc1, 0x00, C0|C1, "x87_ops_retired"                      , 0x0, ATTR_NONE, 0x0 }, \
 339 { 0xc1, 0x01, C0|C1, "x87_ops_retired.fxch"                 , 0x0, ATTR_NONE, 0x0 }, \
 340 { 0xc1, 0xfe, C0|C1, "x87_ops_retired.any"                  , 0x0, ATTR_NONE, 0x0 }, \
 341 { 0xc2, 0x00, C0|C1, "uops_retired"                         , 0x0, ATTR_NONE, 0x0 }, \
 342 { 0xc2, 0x01, C0|C1, "uops_retired.ld_ind_br"               , 0x0, ATTR_NONE, 0x0 }, \
 343 { 0xc2, 0x02, C0|C1, "uops_retired.std_sta"                 , 0x0, ATTR_NONE, 0x0 }, \
 344 { 0xc2, 0x04, C0|C1, "uops_retired.macro_fusion"            , 0x0, ATTR_NONE, 0x0 }, \
 345 { 0xc2, 0x07, C0|C1, "uops_retired.fused"                   , 0x0, ATTR_NONE, 0x0 }, \
 346 { 0xc2, 0x08, C0|C1, "uops_retired.non_fused"               , 0x0, ATTR_NONE, 0x0 }, \
 347 { 0xc2, 0x0f, C0|C1, "uops_retired.any"                     , 0x0, ATTR_NONE, 0x0 }, \
 348 { 0xc3, 0x00, C0|C1, "machine_nukes"                        , 0x0, ATTR_NONE, 0x0 }, \
 349 { 0xc3, 0x01, C0|C1, "machine_nukes.smc"                    , 0x0, ATTR_NONE, 0x0 }, \
 350 { 0xc3, 0x04, C0|C1, "machine_nukes.mem_order"              , 0x0, ATTR_NONE, 0x0 }, \
 351 { 0xc4, 0x00, C0|C1, "br_inst_retired"                      , 0x0, ATTR_NONE, 0x0 }, \
 352 { 0xc4, 0x00, C0|C1, "br_inst_retired.any"                  , 0x0, ATTR_NONE, 0x0 }, \
 353 { 0xc4, 0x01, C0|C1, "br_inst_retired.pred_not_taken"       , 0x0, ATTR_NONE, 0x0 }, \
 354 { 0xc4, 0x02, C0|C1, "br_inst_retired.mispred_not_taken"    , 0x0, ATTR_NONE, 0x0 }, \
 355 { 0xc4, 0x04, C0|C1, "br_inst_retired.pred_taken"           , 0x0, ATTR_NONE, 0x0 }, \
 356 { 0xc4, 0x08, C0|C1, "br_inst_retired.mispred_taken"        , 0x0, ATTR_NONE, 0x0 }, \
 357 { 0xc4, 0x0c, C0|C1, "br_inst_retired.taken"                , 0x0, ATTR_NONE, 0x0 }, \
 358 { 0xc5, 0x00, C0|C1, "br_inst_retired_mispred"              , 0x0, ATTR_NONE, 0x0 }, \
 359 { 0xc5, 0x00, C0|C1, "br_inst_retired.mispred" /*alt-spelling*/   , 0x0, ATTR_NONE, 0x0 }, \
 360 { 0xc6, 0x00, C0|C1, "cycles_int"                           , 0x0, ATTR_NONE, 0x0 }, \
 361 { 0xc6, 0x01, C0|C1, "cycles_int.masked" /*spelling*/       , 0x0, ATTR_NONE, 0x0 }, \
 362 { 0xc6, 0x02, C0|C1, "cycles_int.pending_and_masked" /*spelling*/ , 0x0, ATTR_NONE, 0x0 }, \
 363 { 0xc7, 0x00, C0|C1, "simd_inst_retired"                    , 0x0, ATTR_NONE, 0x0 }, \
 364 { 0xc7, 0x01, C0|C1, "simd_inst_retired.packed_single"      , 0x0, ATTR_NONE, 0x0 }, \
 365 { 0xc7, 0x02, C0|C1, "simd_inst_retired.scalar_single"      , 0x0, ATTR_NONE, 0x0 }, \
 366 { 0xc7, 0x04, C0|C1, "simd_inst_retired.packed_double"      , 0x0, ATTR_NONE, 0x0 }, \
 367 { 0xc7, 0x08, C0|C1, "simd_inst_retired.scalar_double"      , 0x0, ATTR_NONE, 0x0 }, \
 368 { 0xc7, 0x10, C0|C1, "simd_inst_retired.vector"             , 0x0, ATTR_NONE, 0x0 }, \
 369 { 0xc7, 0x1f, C0|C1, "simd_inst_retired.any"                , 0x0, ATTR_NONE, 0x0 }, \
 370 { 0xc8, 0x00, C0|C1, "hw_int_rcv"                           , 0x0, ATTR_NONE, 0x0 }, \
 371 { 0xc9, 0x00, C0|C1, "itlb_miss_retired"                    , 0x0, ATTR_NONE, 0x0 }, \
 372 { 0xca, 0x00, C0|C1, "simd_comp_inst_retired"               , 0x0, ATTR_NONE, 0x0 }, \
 373 { 0xca, 0x01, C0|C1, "simd_comp_inst_retired.packed_single" , 0x0, ATTR_NONE, 0x0 }, \
 374 { 0xca, 0x02, C0|C1, "simd_comp_inst_retired.scalar_single" , 0x0, ATTR_NONE, 0x0 }, \
 375 { 0xca, 0x04, C0|C1, "simd_comp_inst_retired.packed_double" , 0x0, ATTR_NONE, 0x0 }, \
 376 { 0xca, 0x08, C0|C1, "simd_comp_inst_retired.scalar_double" , 0x0, ATTR_NONE, 0x0 }, \
 377 { 0xcb, 0x00, C0   , "mem_load_retired"                     , 0x0, ATTR_NONE, 0x0 }, \
 378 { 0xcb, 0x01, C0   , "mem_load_retired.l1d_miss"            , 0x0, ATTR_NONE, 0x0 }, \
 379 { 0xcb, 0x02, C0   , "mem_load_retired.l1d_line_miss"       , 0x0, ATTR_NONE, 0x0 }, \
 380 { 0xcb, 0x04, C0   , "mem_load_retired.l2_miss"             , 0x0, ATTR_NONE, 0x0 }, \
 381 { 0xcb, 0x08, C0   , "mem_load_retired.l2_line_miss"        , 0x0, ATTR_NONE, 0x0 }, \
 382 { 0xcb, 0x10, C0   , "mem_load_retired.dtlb_miss"           , 0x0, ATTR_NONE, 0x0 }, \
 383 { 0xcc, 0x00, C0|C1, "fp_mmx_trans"                         , 0x0, ATTR_NONE, 0x0 }, \
 384 { 0xcc, 0x01, C0|C1, "fp_mmx_trans.to_mmx" /*spelling*/     , 0x0, ATTR_NONE, 0x0 }, \
 385 { 0xcc, 0x02, C0|C1, "fp_mmx_trans.to_fp" /*spelling*/      , 0x0, ATTR_NONE, 0x0 }, \
 386 { 0xcd, 0x00, C0|C1, "simd_assist"                          , 0x0, ATTR_NONE, 0x0 }, \
 387 { 0xce, 0x00, C0|C1, "simd_instr_retired"                   , 0x0, ATTR_NONE, 0x0 }, \
 388 { 0xcf, 0x00, C0|C1, "simd_sat_instr_retired"               , 0x0, ATTR_NONE, 0x0 }, \
 389 { 0xd2, 0x00, C0|C1, "rat_stalls"                           , 0x0, ATTR_NONE, 0x0 }, \
 390 { 0xd2, 0x01, C0|C1, "rat_stalls.rob_read_port"             , 0x0, ATTR_NONE, 0x0 }, \
 391 { 0xd2, 0x02, C0|C1, "rat_stalls.partial_cycles"            , 0x0, ATTR_NONE, 0x0 }, \
 392 { 0xd2, 0x04, C0|C1, "rat_stalls.flags"                     , 0x0, ATTR_NONE, 0x0 }, \
 393 { 0xd2, 0x08, C0|C1, "rat_stalls.fpsw"                      , 0x0, ATTR_NONE, 0x0 }, \
 394 { 0xd2, 0x0f, C0|C1, "rat_stalls.any"                       , 0x0, ATTR_NONE, 0x0 }, \
 395 { 0xd2, 0x10, C0|C1, "rat_stalls.other_serialization_stalls", 0x0, ATTR_NONE, 0x0 }, \
 396 { 0xd4, 0x00, C0|C1, "seg_rename_stalls"                    , 0x0, ATTR_NONE, 0x0 }, \
 397 { 0xd4, 0x01, C0|C1, "seg_rename_stalls.es"                 , 0x0, ATTR_NONE, 0x0 }, \
 398 { 0xd4, 0x02, C0|C1, "seg_rename_stalls.ds"                 , 0x0, ATTR_NONE, 0x0 }, \
 399 { 0xd4, 0x04, C0|C1, "seg_rename_stalls.fs"                 , 0x0, ATTR_NONE, 0x0 }, \
 400 { 0xd4, 0x08, C0|C1, "seg_rename_stalls.gs"                 , 0x0, ATTR_NONE, 0x0 }, \
 401 { 0xd4, 0x0f, C0|C1, "seg_rename_stalls.any"                , 0x0, ATTR_NONE, 0x0 }, \
 402 { 0xd5, 0x00, C0|C1, "seg_reg_renames"                      , 0x0, ATTR_NONE, 0x0 }, \
 403 { 0xd5, 0x01, C0|C1, "seg_reg_renames.es"                   , 0x0, ATTR_NONE, 0x0 }, \
 404 { 0xd5, 0x02, C0|C1, "seg_reg_renames.ds"                   , 0x0, ATTR_NONE, 0x0 }, \
 405 { 0xd5, 0x04, C0|C1, "seg_reg_renames.fs"                   , 0x0, ATTR_NONE, 0x0 }, \
 406 { 0xd5, 0x08, C0|C1, "seg_reg_renames.gs"                   , 0x0, ATTR_NONE, 0x0 }, \
 407 { 0xd5, 0x0f, C0|C1, "seg_reg_renames.any"                  , 0x0, ATTR_NONE, 0x0 }, \
 408 { 0xdc, 0x00, C0|C1, "resource_stalls"                      , 0x0, ATTR_NONE, 0x0 }, \
 409 { 0xdc, 0x01, C0|C1, "resource_stalls.rob_full"             , 0x0, ATTR_NONE, 0x0 }, \
 410 { 0xdc, 0x02, C0|C1, "resource_stalls.rs_full"              , 0x0, ATTR_NONE, 0x0 }, \
 411 { 0xdc, 0x04, C0|C1, "resource_stalls.ld_st"                , 0x0, ATTR_NONE, 0x0 }, \
 412 { 0xdc, 0x08, C0|C1, "resource_stalls.fpcw"                 , 0x0, ATTR_NONE, 0x0 }, \
 413 { 0xdc, 0x10, C0|C1, "resource_stalls.br_miss_clear"        , 0x0, ATTR_NONE, 0x0 }, \
 414 { 0xdc, 0x1f, C0|C1, "resource_stalls.any"                  , 0x0, ATTR_NONE, 0x0 }, \
 415 { 0xe0, 0x00, C0|C1, "br_inst_decoded"                      , 0x0, ATTR_NONE, 0x0 }, \
 416 { 0xe4, 0x00, C0|C1, "bogus_br"                             , 0x0, ATTR_NONE, 0x0 }, \
 417 { 0xe6, 0x00, C0|C1, "baclears"                             , 0x0, ATTR_NONE, 0x0 }, \
 418 { 0xf0, 0x00, C0|C1, "pref_rqsts_up"                        , 0x0, ATTR_NONE, 0x0 }, \
 419 { 0xf8, 0x00, C0|C1, "pref_rqsts_dn"                        , 0x0, ATTR_NONE, 0x0 }, \
 420 /* end of #define */
 421
 422 /* FAM6 MOD28: Intel Atom processor */
 423 #define EVENTS_FAM6_MOD28                                               \
 424 { 0x02, 0x81, C0|C1, "store_forwards.good"                  , 0x0, ATTR_NONE, 0x0 }, \
 425 { 0x06, 0x00, C0|C1, "segment_reg_loads.any"                , 0x0, ATTR_NONE, 0x0 }, \
 426 { 0x07, 0x01, C0|C1, "prefetch.prefetcht0"                  , 0x0, ATTR_NONE, 0x0 }, \
 427 { 0x07, 0x06, C0|C1, "prefetch.sw_l2"                       , 0x0, ATTR_NONE, 0x0 }, \
 428 { 0x07, 0x08, C0|C1, "prefetch.prefetchnta"                 , 0x0, ATTR_NONE, 0x0 }, \
 429 { 0x08, 0x05, C0|C1, "data_tlb_misses.dtlb_miss_ld"         , 0x0, ATTR_NONE, 0x0 }, \
 430 { 0x08, 0x06, C0|C1, "data_tlb_misses.dtlb_miss_st"         , 0x0, ATTR_NONE, 0x0 }, \
 431 { 0x08, 0x07, C0|C1, "data_tlb_misses.dtlb_miss"            , 0x0, ATTR_NONE, 0x0 }, \
 432 { 0x08, 0x09, C0|C1, "data_tlb_misses.l0_dtlb_miss_ld"      , 0x0, ATTR_NONE, 0x0 }, \
 433 { 0x0c, 0x03, C0|C1, "page_walks.cycles"                    , 0x0, ATTR_NONE, 0x0 }, \
 434 { 0x10, 0x01, C0|C1, "x87_comp_ops_exe.any.s"               , 0x0, ATTR_NONE, 0x0 }, \
 435 { 0x10, 0x81, C0|C1, "x87_comp_ops_exe.any.ar"              , 0x0, ATTR_NONE, 0x0 }, \
 436 { 0x11, 0x01, C0|C1, "fp_assist"                            , 0x0, ATTR_NONE, 0x0 }, \
 437 { 0x11, 0x81, C0|C1, "fp_assist.ar"                         , 0x0, ATTR_NONE, 0x0 }, \
 438 { 0x12, 0x01, C0|C1, "mul.s"                                , 0x0, ATTR_NONE, 0x0 }, \
 439 { 0x12, 0x81, C0|C1, "mul.ar"                               , 0x0, ATTR_NONE, 0x0 }, \
 440 { 0x13, 0x01, C0|C1, "div.s"                                , 0x0, ATTR_NONE, 0x0 }, \
 441 { 0x13, 0x81, C0|C1, "div.ar"                               , 0x0, ATTR_NONE, 0x0 }, \
 442 { 0x14, 0x01, C0|C1, "cycles_div_busy"                      , 0x0, ATTR_NONE, 0x0 }, \
 443 { 0x21, 0x00, C0|C1, "l2_ads"                               , 0x0, ATTR_NONE, 0x0 }, \
 444 { 0x22, 0x00, C0|C1, "l2_dbus_busy"                         , 0x0, ATTR_NONE, 0x0 }, \
 445 { 0x24, 0x00, C0|C1, "l2_lines_in"                          , 0x0, ATTR_NONE, 0x0 }, \
 446 { 0x25, 0x00, C0|C1, "l2_m_lines_in"                        , 0x0, ATTR_NONE, 0x0 }, \
 447 { 0x26, 0x00, C0|C1, "l2_lines_out"                         , 0x0, ATTR_NONE, 0x0 }, \
 448 { 0x27, 0x00, C0|C1, "l2_m_lines_out"                       , 0x0, ATTR_NONE, 0x0 }, \
 449 { 0x28, 0x00, C0|C1, "l2_ifetch"                            , 0x0, ATTR_NONE, 0x0 }, \
 450 { 0x29, 0x00, C0|C1, "l2_ld"                                , 0x0, ATTR_NONE, 0x0 }, \
 451 { 0x2a, 0x00, C0|C1, "l2_st"                                , 0x0, ATTR_NONE, 0x0 }, \
 452 { 0x2b, 0x00, C0|C1, "l2_lock"                              , 0x0, ATTR_NONE, 0x0 }, \
 453 { 0x2e, 0x00, C0|C1, "l2_rqsts"                             , 0x0, ATTR_NONE, 0x0 }, \
 454 { 0x2e, 0x41, C0|C1, "l2_rqsts.self.demand.i_state"         , 0x0, ATTR_NONE, 0x0 }, \
 455 { 0x2e, 0x4f, C0|C1, "l2_rqsts.self.demand.mesi"            , 0x0, ATTR_NONE, 0x0 }, \
 456 { 0x30, 0x00, C0|C1, "l2_reject_busq"                       , 0x0, ATTR_NONE, 0x0 }, \
 457 { 0x32, 0x00, C0|C1, "l2_no_req"                            , 0x0, ATTR_NONE, 0x0 }, \
 458 { 0x3a, 0x00, C0|C1, "eist_trans"                           , 0x0, ATTR_NONE, 0x0 }, \
 459 { 0x3b, 0xc0, C0|C1, "thermal_trip"                         , 0x0, ATTR_NONE, 0x0 }, \
 460 { 0x3c, 0x00, C0|C1, "cpu_clk_unhalted.core_p"              , 0x0, ATTR_NONE, 0x0 }, \
 461 { 0x3c, 0x01, C0|C1, "cpu_clk_unhalted.bus"                 , 0x0, ATTR_NONE, 0x0 }, \
 462 { 0x3c, 0x02, C0|C1, "cpu_clk_unhalted.no_other"            , 0x0, ATTR_NONE, 0x0 }, \
 463 { 0x40, 0x21, C0|C1, "l1d_cache.ld"                         , 0x0, ATTR_NONE, 0x0 }, \
 464 { 0x40, 0x22, C0|C1, "l1d_cache.st"                         , 0x0, ATTR_NONE, 0x0 }, \
 465 { 0x60, 0x00, C0|C1, "bus_request_outstanding"              , 0x0, ATTR_NONE, 0x0 }, \
 466 { 0x61, 0x00, C0|C1, "bus_bnr_drv"                          , 0x0, ATTR_NONE, 0x0 }, \
 467 { 0x62, 0x00, C0|C1, "bus_drdy_clocks"                      , 0x0, ATTR_NONE, 0x0 }, \
 468 { 0x63, 0x00, C0|C1, "bus_lock_clocks"                      , 0x0, ATTR_NONE, 0x0 }, \
 469 { 0x64, 0x00, C0|C1, "bus_data_rcv"                         , 0x0, ATTR_NONE, 0x0 }, \
 470 { 0x65, 0x00, C0|C1, "bus_trans_brd"                        , 0x0, ATTR_NONE, 0x0 }, \
 471 { 0x66, 0x00, C0|C1, "bus_trans_rfo"                        , 0x0, ATTR_NONE, 0x0 }, \
 472 { 0x67, 0x00, C0|C1, "bus_trans_wb"                         , 0x0, ATTR_NONE, 0x0 }, \
 473 { 0x68, 0x00, C0|C1, "bus_trans_ifetch"                     , 0x0, ATTR_NONE, 0x0 }, \
 474 { 0x69, 0x00, C0|C1, "bus_trans_inval"                      , 0x0, ATTR_NONE, 0x0 }, \
 475 { 0x6a, 0x00, C0|C1, "bus_trans_pwr"                        , 0x0, ATTR_NONE, 0x0 }, \
 476 { 0x6b, 0x00, C0|C1, "bus_trans_p"                          , 0x0, ATTR_NONE, 0x0 }, \
 477 { 0x6c, 0x00, C0|C1, "bus_trans_io"                         , 0x0, ATTR_NONE, 0x0 }, \
 478 { 0x6d, 0x00, C0|C1, "bus_trans_def"                        , 0x0, ATTR_NONE, 0x0 }, \
 479 { 0x6e, 0x00, C0|C1, "bus_trans_burst"                      , 0x0, ATTR_NONE, 0x0 }, \
 480 { 0x6f, 0x00, C0|C1, "bus_trans_mem"                        , 0x0, ATTR_NONE, 0x0 }, \
 481 { 0x70, 0x00, C0|C1, "bus_trans_any"                        , 0x0, ATTR_NONE, 0x0 }, \
 482 { 0x77, 0x00, C0|C1, "ext_snoop"                            , 0x0, ATTR_NONE, 0x0 }, \
 483 { 0x7a, 0x00, C0|C1, "bus_hit_drv"                          , 0x0, ATTR_NONE, 0x0 }, \
 484 { 0x7b, 0x00, C0|C1, "bus_hitm_drv"                         , 0x0, ATTR_NONE, 0x0 }, \
 485 { 0x7d, 0x00, C0|C1, "busq_empty"                           , 0x0, ATTR_NONE, 0x0 }, \
 486 { 0x7e, 0x00, C0|C1, "snoop_stall_drv"                      , 0x0, ATTR_NONE, 0x0 }, \
 487 { 0x7f, 0x00, C0|C1, "bus_io_wait"                          , 0x0, ATTR_NONE, 0x0 }, \
 488 { 0x80, 0x02, C0|C1, "icache.misses"                        , 0x0, ATTR_NONE, 0x0 }, \
 489 { 0x80, 0x03, C0|C1, "icache.accesses"                      , 0x0, ATTR_NONE, 0x0 }, \
 490 { 0x82, 0x02, C0|C1, "itlb.misses"                          , 0x0, ATTR_NONE, 0x0 }, \
 491 { 0x82, 0x04, C0|C1, "itlb.flush"                           , 0x0, ATTR_NONE, 0x0 }, \
 492 { 0xaa, 0x02, C0|C1, "macro_insts.cisc_decoded"             , 0x0, ATTR_NONE, 0x0 }, \
 493 { 0xaa, 0x03, C0|C1, "macro_insts.all_decoded"              , 0x0, ATTR_NONE, 0x0 }, \
 494 { 0xb0, 0x00, C0|C1, "simd_uops_exec.s"                     , 0x0, ATTR_NONE, 0x0 }, \
 495 { 0xb0, 0x80, C0|C1, "simd_uops_exec.ar"                    , 0x0, ATTR_NONE, 0x0 }, \
 496 { 0xb1, 0x00, C0|C1, "simd_sat_uop_exec.s"                  , 0x0, ATTR_NONE, 0x0 }, \
 497 { 0xb1, 0x80, C0|C1, "simd_sat_uop_exec.ar"                 , 0x0, ATTR_NONE, 0x0 }, \
 498 { 0xb3, 0x01, C0|C1, "simd_uop_type_exec.mul.s"             , 0x0, ATTR_NONE, 0x0 }, \
 499 { 0xb3, 0x02, C0|C1, "simd_uop_type_exec.shift.s"           , 0x0, ATTR_NONE, 0x0 }, \
 500 { 0xb3, 0x04, C0|C1, "simd_uop_type_exec.pack.s"            , 0x0, ATTR_NONE, 0x0 }, \
 501 { 0xb3, 0x08, C0|C1, "simd_uop_type_exec.unpack.s"          , 0x0, ATTR_NONE, 0x0 }, \
 502 { 0xb3, 0x10, C0|C1, "simd_uop_type_exec.logical.s"         , 0x0, ATTR_NONE, 0x0 }, \
 503 { 0xb3, 0x20, C0|C1, "simd_uop_type_exec.arithmetic.s"      , 0x0, ATTR_NONE, 0x0 }, \
 504 { 0xb3, 0x81, C0|C1, "simd_uop_type_exec.mul.ar"            , 0x0, ATTR_NONE, 0x0 }, \
 505 { 0xb3, 0x82, C0|C1, "simd_uop_type_exec.shift.ar"          , 0x0, ATTR_NONE, 0x0 }, \
 506 { 0xb3, 0x84, C0|C1, "simd_uop_type_exec.pack.ar"           , 0x0, ATTR_NONE, 0x0 }, \
 507 { 0xb3, 0x88, C0|C1, "simd_uop_type_exec.unpack.ar"         , 0x0, ATTR_NONE, 0x0 }, \
 508 { 0xb3, 0x90, C0|C1, "simd_uop_type_exec.logical.ar"        , 0x0, ATTR_NONE, 0x0 }, \
 509 { 0xb3, 0xa0, C0|C1, "simd_uop_type_exec.arithmetic.ar"     , 0x0, ATTR_NONE, 0x0 }, \
 510 { 0xc0, 0x00, C0|C1, "inst_retired.any_p"                   , 0x0, ATTR_NONE, 0x0 }, \
 511 { 0xc2, 0x10, C0|C1, "uops_retired.any"                     , 0x0, ATTR_NONE, 0x0 }, \
 512 { 0xc3, 0x01, C0|C1, "machine_clears.smc"                   , 0x0, ATTR_NONE, 0x0 }, \
 513 { 0xc4, 0x00, C0|C1, "br_inst_retired.any"                  , 0x0, ATTR_NONE, 0x0 }, \
 514 { 0xc4, 0x01, C0|C1, "br_inst_retired.pred_not_taken"       , 0x0, ATTR_NONE, 0x0 }, \
 515 { 0xc4, 0x02, C0|C1, "br_inst_retired.mispred_not_taken"    , 0x0, ATTR_NONE, 0x0 }, \
 516 { 0xc4, 0x04, C0|C1, "br_inst_retired.pred_taken"           , 0x0, ATTR_NONE, 0x0 }, \
 517 { 0xc4, 0x08, C0|C1, "br_inst_retired.mispred_taken"        , 0x0, ATTR_NONE, 0x0 }, \
 518 { 0xc4, 0x0a, C0|C1, "br_inst_retired.mispred"              , 0x0, ATTR_NONE, 0x0 }, \
 519 { 0xc4, 0x0c, C0|C1, "br_inst_retired.taken"                , 0x0, ATTR_NONE, 0x0 }, \
 520 { 0xc4, 0x0f, C0|C1, "br_inst_retired.any1"                 , 0x0, ATTR_NONE, 0x0 }, \
 521 { 0xc5, 0x00, C0|C1, "br_inst_retired.mispred"              , 0x0, ATTR_NONE, 0x0 }, \
 522 { 0xc6, 0x01, C0|C1, "cycles_int_masked.cycles_int_masked"  , 0x0, ATTR_NONE, 0x0 }, \
 523 { 0xc6, 0x02, C0|C1, "cycles_int_masked.cycles_int_pending_and_masked" , 0x0, ATTR_NONE, 0x0 }, \
 524 { 0xc7, 0x01, C0|C1, "simd_inst_retired.packed_single"      , 0x0, ATTR_NONE, 0x0 }, \
 525 { 0xc7, 0x02, C0|C1, "simd_inst_retired.scalar_single"      , 0x0, ATTR_NONE, 0x0 }, \
 526 { 0xc7, 0x04, C0|C1, "simd_inst_retired.packed_double"      , 0x0, ATTR_NONE, 0x0 }, \
 527 { 0xc7, 0x08, C0|C1, "simd_inst_retired.scalar_double"      , 0x0, ATTR_NONE, 0x0 }, \
 528 { 0xc7, 0x10, C0|C1, "simd_inst_retired.vector"             , 0x0, ATTR_NONE, 0x0 }, \
 529 { 0xc7, 0x1f, C0|C1, "simd_inst_retired.any"                , 0x0, ATTR_NONE, 0x0 }, \
 530 { 0xc8, 0x00, C0|C1, "hw_int_rcv"                           , 0x0, ATTR_NONE, 0x0 }, \
 531 { 0xca, 0x01, C0|C1, "simd_comp_inst_retired.packed_single" , 0x0, ATTR_NONE, 0x0 }, \
 532 { 0xca, 0x02, C0|C1, "simd_comp_inst_retired.scalar_single" , 0x0, ATTR_NONE, 0x0 }, \
 533 { 0xca, 0x04, C0|C1, "simd_comp_inst_retired.packed_double" , 0x0, ATTR_NONE, 0x0 }, \
 534 { 0xca, 0x08, C0|C1, "simd_comp_inst_retired.scalar_double" , 0x0, ATTR_NONE, 0x0 }, \
 535 { 0xcb, 0x01, C0|C1, "mem_load_retired.l2_hit"              , 0x0, ATTR_NONE, 0x0 }, \
 536 { 0xcb, 0x02, C0|C1, "mem_load_retired.l2_miss"             , 0x0, ATTR_NONE, 0x0 }, \
 537 { 0xcb, 0x04, C0|C1, "mem_load_retired.dtlb_miss"           , 0x0, ATTR_NONE, 0x0 }, \
 538 { 0xcd, 0x00, C0|C1, "simd_assist"                          , 0x0, ATTR_NONE, 0x0 }, \
 539 { 0xce, 0x00, C0|C1, "simd_instr_retired"                   , 0x0, ATTR_NONE, 0x0 }, \
 540 { 0xcf, 0x00, C0|C1, "simd_sat_instr_retired"               , 0x0, ATTR_NONE, 0x0 }, \
 541 { 0xe0, 0x01, C0|C1, "br_inst_decoded"                      , 0x0, ATTR_NONE, 0x0 }, \
 542 { 0xe4, 0x01, C0|C1, "bogus_br"                             , 0x0, ATTR_NONE, 0x0 }, \
 543 { 0xe6, 0x01, C0|C1, "baclears.any"                         , 0x0, ATTR_NONE, 0x0 }, \
 544 /* end of #define */
 545
 546 /* Intel Core i7 (Nehalem) Processor */
 547 /*
 548  * The Nehalem tables are basically from Bug 16457009
 549  *   libcpc counter names should be based on public Intel documentation -- Nehalem
 550  * and those tables are basically from the
 551  * Intel SDM, January 2013, Section 19.5, Table 19-11.
 552  * We omit the Table 19-12 uncore events.
 553  *
 554  * Note that the table below includes some events from
 555  * the Intel SDM that require cmask or attr settings.
 556  * These events are not in libcpc, which did not include
 557  * events requiring cmask or attr until Sandy Bridge.
 558  */
 559
 560 #define EVENTS_FAM6_MOD26                                               \
 561 { 0x04, 0x07, C0|C1|C2|C3, "sb_drain.any"                         , 0x0, ATTR_NONE, 0x0 }, \
 562 { 0x06, 0x04, C0|C1|C2|C3, "store_blocks.at_ret"                  , 0x0, ATTR_NONE, 0x0 }, \
 563 { 0x06, 0x08, C0|C1|C2|C3, "store_blocks.l1d_block"               , 0x0, ATTR_NONE, 0x0 }, \
 564 { 0x07, 0x01, C0|C1|C2|C3, "partial_address_alias"                , 0x0, ATTR_NONE, 0x0 }, \
 565 { 0x08, 0x01, C0|C1|C2|C3, "dtlb_load_misses.any"                 , 0x0, ATTR_NONE, 0x0 }, \
 566 { 0x08, 0x02, C0|C1|C2|C3, "dtlb_load_misses.walk_completed"      , 0x0, ATTR_NONE, 0x0 }, \
 567 { 0x08, 0x10, C0|C1|C2|C3, "dtlb_load_misses.stlb_hit"            , 0x0, ATTR_NONE, 0x0 }, \
 568 { 0x08, 0x20, C0|C1|C2|C3, "dtlb_load_misses.pde_miss"            , 0x0, ATTR_NONE, 0x0 }, \
 569 { 0x08, 0x80, C0|C1|C2|C3, "dtlb_load_misses.large_walk_completed", 0x0, ATTR_NONE, 0x0 }, \
 570 { 0x0B, 0x01, C0|C1|C2|C3, "mem_inst_retired.loads"               , 0x0, ATTR_NONE, 0x0 }, \
 571 { 0x0B, 0x02, C0|C1|C2|C3, "mem_inst_retired.stores"              , 0x0, ATTR_NONE, 0x0 }, \
 572 { 0x0B, 0x10, C0|C1|C2|C3, "mem_inst_retired.latency_above_threshold"   , 0x0, ATTR_NONE, 0x0 }, \
 573 { 0x0C, 0x01, C0|C1|C2|C3, "mem_store_retired.dtlb_miss"          , 0x0, ATTR_NONE, 0x0 }, \
 574 { 0x0E, 0x01, C0|C1|C2|C3, "uops_issued.any"                      , 0x0, ATTR_NONE, 0x0 }, \
 575 { 0x0E, 0x01, C0|C1|C2|C3, "uops_issued.stalled_cycles"           , 0x1, ATTR_INV , 0x0 }, \
 576 { 0x0E, 0x02, C0|C1|C2|C3, "uops_issued.fused"                    , 0x0, ATTR_NONE, 0x0 }, \
 577 { 0x0F, 0x02, C0|C1|C2|C3, "mem_uncore_retired.other_core_l2_hitm", 0x0, ATTR_NONE, 0x0 }, \
 578 { 0x0F, 0x08, C0|C1|C2|C3, "mem_uncore_retired.remote_cache_local_home_hit", 0x0, ATTR_NONE, 0x0 }, \
 579 { 0x0F, 0x10, C0|C1|C2|C3, "mem_uncore_retired.remote_dram"       , 0x0, ATTR_NONE, 0x0 }, \
 580 { 0x0F, 0x20, C0|C1|C2|C3, "mem_uncore_retired.local_dram"        , 0x0, ATTR_NONE, 0x0 }, \
 581 { 0x10, 0x01, C0|C1|C2|C3, "fp_comp_ops_exe.x87"                  , 0x0, ATTR_NONE, 0x0 }, \
 582 { 0x10, 0x02, C0|C1|C2|C3, "fp_comp_ops_exe.mmx"                  , 0x0, ATTR_NONE, 0x0 }, \
 583 { 0x10, 0x04, C0|C1|C2|C3, "fp_comp_ops_exe.sse_fp"               , 0x0, ATTR_NONE, 0x0 }, \
 584 { 0x10, 0x08, C0|C1|C2|C3, "fp_comp_ops_exe.sse2_integer"         , 0x0, ATTR_NONE, 0x0 }, \
 585 { 0x10, 0x10, C0|C1|C2|C3, "fp_comp_ops_exe.sse_fp_packed"        , 0x0, ATTR_NONE, 0x0 }, \
 586 { 0x10, 0x20, C0|C1|C2|C3, "fp_comp_ops_exe.sse_fp_scalar"        , 0x0, ATTR_NONE, 0x0 }, \
 587 { 0x10, 0x40, C0|C1|C2|C3, "fp_comp_ops_exe.sse_single_precision" , 0x0, ATTR_NONE, 0x0 }, \
 588 { 0x10, 0x80, C0|C1|C2|C3, "fp_comp_ops_exe.sse_double_precision" , 0x0, ATTR_NONE, 0x0 }, \
 589 { 0x12, 0x01, C0|C1|C2|C3, "simd_int_128.packed_mpy"              , 0x0, ATTR_NONE, 0x0 }, \
 590 { 0x12, 0x02, C0|C1|C2|C3, "simd_int_128.packed_shift"            , 0x0, ATTR_NONE, 0x0 }, \
 591 { 0x12, 0x04, C0|C1|C2|C3, "simd_int_128.pack"                    , 0x0, ATTR_NONE, 0x0 }, \
 592 { 0x12, 0x08, C0|C1|C2|C3, "simd_int_128.unpack"                  , 0x0, ATTR_NONE, 0x0 }, \
 593 { 0x12, 0x10, C0|C1|C2|C3, "simd_int_128.packed_logical"          , 0x0, ATTR_NONE, 0x0 }, \
 594 { 0x12, 0x20, C0|C1|C2|C3, "simd_int_128.packed_arith"            , 0x0, ATTR_NONE, 0x0 }, \
 595 { 0x12, 0x40, C0|C1|C2|C3, "simd_int_128.shuffle_move"            , 0x0, ATTR_NONE, 0x0 }, \
 596 { 0x13, 0x01, C0|C1|C2|C3, "load_dispatch.rs"                     , 0x0, ATTR_NONE, 0x0 }, \
 597 { 0x13, 0x02, C0|C1|C2|C3, "load_dispatch.rs_delayed"             , 0x0, ATTR_NONE, 0x0 }, \
 598 { 0x13, 0x04, C0|C1|C2|C3, "load_dispatch.mob"                    , 0x0, ATTR_NONE, 0x0 }, \
 599 { 0x13, 0x07, C0|C1|C2|C3, "load_dispatch.any"                    , 0x0, ATTR_NONE, 0x0 }, \
 600 { 0x14, 0x01, C0|C1|C2|C3, "arith.cycles_div_busy"                , 0x0, ATTR_NONE, 0x0 }, \
 601 { 0x14, 0x01, C0|C1|C2|C3, "arith.fpu_div"                        , 0x1, ATTR_EDGE | ATTR_INV, 0x0 }, \
 602 { 0x14, 0x02, C0|C1|C2|C3, "arith.mul"                            , 0x0, ATTR_NONE, 0x0 }, \
 603 { 0x17, 0x01, C0|C1|C2|C3, "inst_queue_writes"                    , 0x0, ATTR_NONE, 0x0 }, \
 604 { 0x18, 0x01, C0|C1|C2|C3, "inst_decoded.dec0"                    , 0x0, ATTR_NONE, 0x0 }, \
 605 { 0x19, 0x01, C0|C1|C2|C3, "two_uop_insts_decoded"                , 0x0, ATTR_NONE, 0x0 }, \
 606 { 0x1E, 0x01, C0|C1|C2|C3, "inst_queue_write_cycles"              , 0x0, ATTR_NONE, 0x0 }, \
 607 { 0x20, 0x01, C0|C1|C2|C3, "lsd_overflow"                         , 0x0, ATTR_NONE, 0x0 }, \
 608 { 0x24, 0x01, C0|C1|C2|C3, "l2_rqsts.ld_hit"                      , 0x0, ATTR_NONE, 0x0 }, \
 609 { 0x24, 0x02, C0|C1|C2|C3, "l2_rqsts.ld_miss"                     , 0x0, ATTR_NONE, 0x0 }, \
 610 { 0x24, 0x03, C0|C1|C2|C3, "l2_rqsts.loads"                       , 0x0, ATTR_NONE, 0x0 }, \
 611 { 0x24, 0x04, C0|C1|C2|C3, "l2_rqsts.rfo_hit"                     , 0x0, ATTR_NONE, 0x0 }, \
 612 { 0x24, 0x08, C0|C1|C2|C3, "l2_rqsts.rfo_miss"                    , 0x0, ATTR_NONE, 0x0 }, \
 613 { 0x24, 0x0C, C0|C1|C2|C3, "l2_rqsts.rfos"                        , 0x0, ATTR_NONE, 0x0 }, \
 614 { 0x24, 0x10, C0|C1|C2|C3, "l2_rqsts.ifetch_hit"                  , 0x0, ATTR_NONE, 0x0 }, \
 615 { 0x24, 0x20, C0|C1|C2|C3, "l2_rqsts.ifetch_miss"                 , 0x0, ATTR_NONE, 0x0 }, \
 616 { 0x24, 0x30, C0|C1|C2|C3, "l2_rqsts.ifetches"                    , 0x0, ATTR_NONE, 0x0 }, \
 617 { 0x24, 0x40, C0|C1|C2|C3, "l2_rqsts.prefetch_hit"                , 0x0, ATTR_NONE, 0x0 }, \
 618 { 0x24, 0x80, C0|C1|C2|C3, "l2_rqsts.prefetch_miss"               , 0x0, ATTR_NONE, 0x0 }, \
 619 { 0x24, 0xAA, C0|C1|C2|C3, "l2_rqsts.miss"                        , 0x0, ATTR_NONE, 0x0 }, \
 620 { 0x24, 0xC0, C0|C1|C2|C3, "l2_rqsts.prefetches"                  , 0x0, ATTR_NONE, 0x0 }, \
 621 { 0x24, 0xFF, C0|C1|C2|C3, "l2_rqsts.references"                  , 0x0, ATTR_NONE, 0x0 }, \
 622 { 0x26, 0x01, C0|C1|C2|C3, "l2_data_rqsts.demand.i_state"         , 0x0, ATTR_NONE, 0x0 }, \
 623 { 0x26, 0x02, C0|C1|C2|C3, "l2_data_rqsts.demand.s_state"         , 0x0, ATTR_NONE, 0x0 }, \
 624 { 0x26, 0x04, C0|C1|C2|C3, "l2_data_rqsts.demand.e_state"         , 0x0, ATTR_NONE, 0x0 }, \
 625 { 0x26, 0x08, C0|C1|C2|C3, "l2_data_rqsts.demand.m_state"         , 0x0, ATTR_NONE, 0x0 }, \
 626 { 0x26, 0x0F, C0|C1|C2|C3, "l2_data_rqsts.demand.mesi"            , 0x0, ATTR_NONE, 0x0 }, \
 627 { 0x26, 0x10, C0|C1|C2|C3, "l2_data_rqsts.prefetch.i_state"       , 0x0, ATTR_NONE, 0x0 }, \
 628 { 0x26, 0x20, C0|C1|C2|C3, "l2_data_rqsts.prefetch.s_state"       , 0x0, ATTR_NONE, 0x0 }, \
 629 { 0x26, 0x40, C0|C1|C2|C3, "l2_data_rqsts.prefetch.e_state"       , 0x0, ATTR_NONE, 0x0 }, \
 630 { 0x26, 0x80, C0|C1|C2|C3, "l2_data_rqsts.prefetch.m_state"       , 0x0, ATTR_NONE, 0x0 }, \
 631 { 0x26, 0xF0, C0|C1|C2|C3, "l2_data_rqsts.prefetch.mesi"          , 0x0, ATTR_NONE, 0x0 }, \
 632 { 0x26, 0xFF, C0|C1|C2|C3, "l2_data_rqsts.any"                    , 0x0, ATTR_NONE, 0x0 }, \
 633 { 0x27, 0x01, C0|C1|C2|C3, "l2_write.rfo.i_state"                 , 0x0, ATTR_NONE, 0x0 }, \
 634 { 0x27, 0x02, C0|C1|C2|C3, "l2_write.rfo.s_state"                 , 0x0, ATTR_NONE, 0x0 }, \
 635 { 0x27, 0x08, C0|C1|C2|C3, "l2_write.rfo.m_state"                 , 0x0, ATTR_NONE, 0x0 }, \
 636 { 0x27, 0x0E, C0|C1|C2|C3, "l2_write.rfo.hit"                     , 0x0, ATTR_NONE, 0x0 }, \
 637 { 0x27, 0x0F, C0|C1|C2|C3, "l2_write.rfo.mesi"                    , 0x0, ATTR_NONE, 0x0 }, \
 638 { 0x27, 0x10, C0|C1|C2|C3, "l2_write.lock.i_state"                , 0x0, ATTR_NONE, 0x0 }, \
 639 { 0x27, 0x20, C0|C1|C2|C3, "l2_write.lock.s_state"                , 0x0, ATTR_NONE, 0x0 }, \
 640 { 0x27, 0x40, C0|C1|C2|C3, "l2_write.lock.e_state"                , 0x0, ATTR_NONE, 0x0 }, \
 641 { 0x27, 0x80, C0|C1|C2|C3, "l2_write.lock.m_state"                , 0x0, ATTR_NONE, 0x0 }, \
 642 { 0x27, 0xE0, C0|C1|C2|C3, "l2_write.lock.hit"                    , 0x0, ATTR_NONE, 0x0 }, \
 643 { 0x27, 0xF0, C0|C1|C2|C3, "l2_write.lock.mesi"                   , 0x0, ATTR_NONE, 0x0 }, \
 644 { 0x28, 0x01, C0|C1|C2|C3, "l1d_wb_l2.i_state"                    , 0x0, ATTR_NONE, 0x0 }, \
 645 { 0x28, 0x02, C0|C1|C2|C3, "l1d_wb_l2.s_state"                    , 0x0, ATTR_NONE, 0x0 }, \
 646 { 0x28, 0x04, C0|C1|C2|C3, "l1d_wb_l2.e_state"                    , 0x0, ATTR_NONE, 0x0 }, \
 647 { 0x28, 0x08, C0|C1|C2|C3, "l1d_wb_l2.m_state"                    , 0x0, ATTR_NONE, 0x0 }, \
 648 { 0x28, 0x0F, C0|C1|C2|C3, "l1d_wb_l2.mesi"                       , 0x0, ATTR_NONE, 0x0 }, \
 649 { 0x2E, 0x41, C0|C1|C2|C3, "l3_lat_cache.miss"                    , 0x0, ATTR_NONE, 0x0 }, \
 650 { 0x2E, 0x4F, C0|C1|C2|C3, "l3_lat_cache.reference"               , 0x0, ATTR_NONE, 0x0 }, \
 651 { 0x3C, 0x00, C0|C1|C2|C3, "cpu_clk_unhalted.thread_p"            , 0x0, ATTR_NONE, 0x0 }, \
 652 { 0x3C, 0x01, C0|C1|C2|C3, "cpu_clk_unhalted.ref_p"               , 0x0, ATTR_NONE, 0x0 }, \
 653 { 0x40, 0x01, C0|C1      , "l1d_cache_ld.i_state"                 , 0x0, ATTR_NONE, 0x0 }, \
 654 { 0x40, 0x02, C0|C1      , "l1d_cache_ld.s_state"                 , 0x0, ATTR_NONE, 0x0 }, \
 655 { 0x40, 0x04, C0|C1      , "l1d_cache_ld.e_state"                 , 0x0, ATTR_NONE, 0x0 }, \
 656 { 0x40, 0x08, C0|C1      , "l1d_cache_ld.m_state"                 , 0x0, ATTR_NONE, 0x0 }, \
 657 { 0x40, 0x0F, C0|C1      , "l1d_cache_ld.mesi"                    , 0x0, ATTR_NONE, 0x0 }, \
 658 { 0x41, 0x02, C0|C1      , "l1d_cache_st.s_state"                 , 0x0, ATTR_NONE, 0x0 }, \
 659 { 0x41, 0x04, C0|C1      , "l1d_cache_st.e_state"                 , 0x0, ATTR_NONE, 0x0 }, \
 660 { 0x41, 0x08, C0|C1      , "l1d_cache_st.m_state"                 , 0x0, ATTR_NONE, 0x0 }, \
 661 { 0x42, 0x01, C0|C1      , "l1d_cache_lock.hit"                   , 0x0, ATTR_NONE, 0x0 }, \
 662 { 0x42, 0x02, C0|C1      , "l1d_cache_lock.s_state"               , 0x0, ATTR_NONE, 0x0 }, \
 663 { 0x42, 0x04, C0|C1      , "l1d_cache_lock.e_state"               , 0x0, ATTR_NONE, 0x0 }, \
 664 { 0x42, 0x08, C0|C1      , "l1d_cache_lock.m_state"               , 0x0, ATTR_NONE, 0x0 }, \
 665 { 0x43, 0x01, C0|C1      , "l1d_all_ref.any"                      , 0x0, ATTR_NONE, 0x0 }, \
 666 { 0x43, 0x02, C0|C1      , "l1d_all_ref.cacheable"                , 0x0, ATTR_NONE, 0x0 }, \
 667 { 0x49, 0x01, C0|C1|C2|C3, "dtlb_misses.any"                      , 0x0, ATTR_NONE, 0x0 }, \
 668 { 0x49, 0x02, C0|C1|C2|C3, "dtlb_misses.walk_completed"           , 0x0, ATTR_NONE, 0x0 }, \
 669 { 0x49, 0x10, C0|C1|C2|C3, "dtlb_misses.stlb_hit"                 , 0x0, ATTR_NONE, 0x0 }, \
 670 { 0x49, 0x20, C0|C1|C2|C3, "dtlb_misses.pde_miss"                 , 0x0, ATTR_NONE, 0x0 }, \
 671 { 0x49, 0x80, C0|C1|C2|C3, "dtlb_misses.large_walk_completed"     , 0x0, ATTR_NONE, 0x0 }, \
 672 { 0x4C, 0x01, C0|C1|C2|C3, "load_hit_pre"                         , 0x0, ATTR_NONE, 0x0 }, \
 673 { 0x4E, 0x01, C0|C1|C2|C3, "l1d_prefetch.requests"                , 0x0, ATTR_NONE, 0x0 }, \
 674 { 0x4E, 0x02, C0|C1|C2|C3, "l1d_prefetch.miss"                    , 0x0, ATTR_NONE, 0x0 }, \
 675 { 0x4E, 0x04, C0|C1|C2|C3, "l1d_prefetch.triggers"                , 0x0, ATTR_NONE, 0x0 }, \
 676 { 0x51, 0x01, C0|C1      , "l1d.repl"                             , 0x0, ATTR_NONE, 0x0 }, \
 677 { 0x51, 0x02, C0|C1      , "l1d.m_repl"                           , 0x0, ATTR_NONE, 0x0 }, \
 678 { 0x51, 0x04, C0|C1      , "l1d.m_evict"                          , 0x0, ATTR_NONE, 0x0 }, \
 679 { 0x51, 0x08, C0|C1      , "l1d.m_snoop_evict"                    , 0x0, ATTR_NONE, 0x0 }, \
 680 { 0x52, 0x01, C0|C1|C2|C3, "l1d_cache_prefetch_lock_fb_hit"       , 0x0, ATTR_NONE, 0x0 }, \
 681 { 0x53, 0x01, C0|C1|C2|C3, "l1d_cache_lock_fb_hit"                , 0x0, ATTR_NONE, 0x0 }, \
 682 { 0x63, 0x01, C0|C1      , "cache_lock_cycles.l1d_l2"             , 0x0, ATTR_NONE, 0x0 }, \
 683 { 0x63, 0x02, C0|C1      , "cache_lock_cycles.l1d"                , 0x0, ATTR_NONE, 0x0 }, \
 684 { 0x6C, 0x01, C0|C1|C2|C3, "io_transactions"                      , 0x0, ATTR_NONE, 0x0 }, \
 685 { 0x80, 0x01, C0|C1|C2|C3, "l1i.hits"                             , 0x0, ATTR_NONE, 0x0 }, \
 686 { 0x80, 0x02, C0|C1|C2|C3, "l1i.misses"                           , 0x0, ATTR_NONE, 0x0 }, \
 687 { 0x80, 0x03, C0|C1|C2|C3, "l1i.reads"                            , 0x0, ATTR_NONE, 0x0 }, \
 688 { 0x80, 0x04, C0|C1|C2|C3, "l1i.cycles_stalled"                   , 0x0, ATTR_NONE, 0x0 }, \
 689 { 0x82, 0x01, C0|C1|C2|C3, "large_itlb.hit"                       , 0x0, ATTR_NONE, 0x0 }, \
 690 { 0x85, 0x01, C0|C1|C2|C3, "itlb_misses.any"                      , 0x0, ATTR_NONE, 0x0 }, \
 691 { 0x85, 0x02, C0|C1|C2|C3, "itlb_misses.walk_completed"           , 0x0, ATTR_NONE, 0x0 }, \
 692 { 0x87, 0x01, C0|C1|C2|C3, "ild_stall.lcp"                        , 0x0, ATTR_NONE, 0x0 }, \
 693 { 0x87, 0x02, C0|C1|C2|C3, "ild_stall.mru"                        , 0x0, ATTR_NONE, 0x0 }, \
 694 { 0x87, 0x04, C0|C1|C2|C3, "ild_stall.iq_full"                    , 0x0, ATTR_NONE, 0x0 }, \
 695 { 0x87, 0x08, C0|C1|C2|C3, "ild_stall.regen"                      , 0x0, ATTR_NONE, 0x0 }, \
 696 { 0x87, 0x0F, C0|C1|C2|C3, "ild_stall.any"                        , 0x0, ATTR_NONE, 0x0 }, \
 697 { 0x88, 0x01, C0|C1|C2|C3, "br_inst_exec.cond"                    , 0x0, ATTR_NONE, 0x0 }, \
 698 { 0x88, 0x02, C0|C1|C2|C3, "br_inst_exec.direct"                  , 0x0, ATTR_NONE, 0x0 }, \
 699 { 0x88, 0x04, C0|C1|C2|C3, "br_inst_exec.indirect_non_call"       , 0x0, ATTR_NONE, 0x0 }, \
 700 { 0x88, 0x07, C0|C1|C2|C3, "br_inst_exec.non_calls"               , 0x0, ATTR_NONE, 0x0 }, \
 701 { 0x88, 0x08, C0|C1|C2|C3, "br_inst_exec.return_near"             , 0x0, ATTR_NONE, 0x0 }, \
 702 { 0x88, 0x10, C0|C1|C2|C3, "br_inst_exec.direct_near_call"        , 0x0, ATTR_NONE, 0x0 }, \
 703 { 0x88, 0x20, C0|C1|C2|C3, "br_inst_exec.indirect_near_call"      , 0x0, ATTR_NONE, 0x0 }, \
 704 { 0x88, 0x30, C0|C1|C2|C3, "br_inst_exec.near_calls"              , 0x0, ATTR_NONE, 0x0 }, \
 705 { 0x88, 0x40, C0|C1|C2|C3, "br_inst_exec.taken"                   , 0x0, ATTR_NONE, 0x0 }, \
 706 { 0x88, 0x7F, C0|C1|C2|C3, "br_inst_exec.any"                     , 0x0, ATTR_NONE, 0x0 }, \
 707 { 0x89, 0x01, C0|C1|C2|C3, "br_misp_exec.cond"                    , 0x0, ATTR_NONE, 0x0 }, \
 708 { 0x89, 0x02, C0|C1|C2|C3, "br_misp_exec.direct"                  , 0x0, ATTR_NONE, 0x0 }, \
 709 { 0x89, 0x04, C0|C1|C2|C3, "br_misp_exec.indirect_non_call"       , 0x0, ATTR_NONE, 0x0 }, \
 710 { 0x89, 0x07, C0|C1|C2|C3, "br_misp_exec.non_calls"               , 0x0, ATTR_NONE, 0x0 }, \
 711 { 0x89, 0x08, C0|C1|C2|C3, "br_misp_exec.return_near"             , 0x0, ATTR_NONE, 0x0 }, \
 712 { 0x89, 0x10, C0|C1|C2|C3, "br_misp_exec.direct_near_call"        , 0x0, ATTR_NONE, 0x0 }, \
 713 { 0x89, 0x20, C0|C1|C2|C3, "br_misp_exec.indirect_near_call"      , 0x0, ATTR_NONE, 0x0 }, \
 714 { 0x89, 0x30, C0|C1|C2|C3, "br_misp_exec.near_calls"              , 0x0, ATTR_NONE, 0x0 }, \
 715 { 0x89, 0x40, C0|C1|C2|C3, "br_misp_exec.taken"                   , 0x0, ATTR_NONE, 0x0 }, \
 716 { 0x89, 0x7F, C0|C1|C2|C3, "br_misp_exec.any"                     , 0x0, ATTR_NONE, 0x0 }, \
 717 { 0xA2, 0x01, C0|C1|C2|C3, "resource_stalls.any"                  , 0x0, ATTR_NONE, 0x0 }, \
 718 { 0xA2, 0x02, C0|C1|C2|C3, "resource_stalls.load"                 , 0x0, ATTR_NONE, 0x0 }, \
 719 { 0xA2, 0x04, C0|C1|C2|C3, "resource_stalls.rs_full"              , 0x0, ATTR_NONE, 0x0 }, \
 720 { 0xA2, 0x08, C0|C1|C2|C3, "resource_stalls.store"                , 0x0, ATTR_NONE, 0x0 }, \
 721 { 0xA2, 0x10, C0|C1|C2|C3, "resource_stalls.rob_full"             , 0x0, ATTR_NONE, 0x0 }, \
 722 { 0xA2, 0x20, C0|C1|C2|C3, "resource_stalls.fpcw"                 , 0x0, ATTR_NONE, 0x0 }, \
 723 { 0xA2, 0x40, C0|C1|C2|C3, "resource_stalls.mxcsr"                , 0x0, ATTR_NONE, 0x0 }, \
 724 { 0xA2, 0x80, C0|C1|C2|C3, "resource_stalls.other"                , 0x0, ATTR_NONE, 0x0 }, \
 725 { 0xA6, 0x01, C0|C1|C2|C3, "macro_insts.fusions_decoded"          , 0x0, ATTR_NONE, 0x0 }, \
 726 { 0xA7, 0x01, C0|C1|C2|C3, "baclear_force_iq"                     , 0x0, ATTR_NONE, 0x0 }, \
 727 { 0xA8, 0x01, C0|C1|C2|C3, "lsd.uops"                             , 0x0, ATTR_NONE, 0x0 }, \
 728 { 0xA8, 0x01, C0|C1|C2|C3, "lsd.cycles"                           , 0x1, ATTR_INV , 0x0 }, \
 729 { 0xAE, 0x01, C0|C1|C2|C3, "itlb_flush"                           , 0x0, ATTR_NONE, 0x0 }, \
 730 { 0xB0, 0x40, C0|C1|C2|C3, "offcore_requests.l1d_writeback"       , 0x0, ATTR_NONE, 0x0 }, \
 731 { 0xB1, 0x01, C0|C1|C2|C3, "uops_executed.port0"                  , 0x0, ATTR_NONE, 0x0 }, \
 732 { 0xB1, 0x02, C0|C1|C2|C3, "uops_executed.port1"                  , 0x0, ATTR_NONE, 0x0 }, \
 733 { 0xB1, 0x04, C0|C1|C2|C3, "uops_executed.port2_core"             , 0x0, ATTR_NONE, 0x0 }, \
 734 { 0xB1, 0x08, C0|C1|C2|C3, "uops_executed.port3_core"             , 0x0, ATTR_NONE, 0x0 }, \
 735 { 0xB1, 0x10, C0|C1|C2|C3, "uops_executed.port4_core"             , 0x0, ATTR_NONE, 0x0 }, \
 736 { 0xB1, 0x1F, C0|C1|C2|C3, "uops_executed.core_active_cycles_no_port5"  , 0x0, ATTR_NONE, 0x0 }, \
 737 { 0xB1, 0x20, C0|C1|C2|C3, "uops_executed.port5"                  , 0x0, ATTR_NONE, 0x0 }, \
 738 { 0xB1, 0x3F, C0|C1|C2|C3, "uops_executed.core_active_cycles"     , 0x0, ATTR_NONE, 0x0 }, \
 739 { 0xB1, 0x40, C0|C1|C2|C3, "uops_executed.port015"                , 0x0, ATTR_NONE, 0x0 }, \
 740 { 0xB1, 0x40, C0|C1|C2|C3, "uops_executed.port015_stall_cycles"   , 0x1, ATTR_INV , 0x0 }, \
 741 { 0xB1, 0x80, C0|C1|C2|C3, "uops_executed.port234"                , 0x0, ATTR_NONE, 0x0 }, \
 742 { 0xB2, 0x01, C0|C1|C2|C3, "offcore_requests_sq_full"             , 0x0, ATTR_NONE, 0x0 }, \
 743 /* { 0xB7, 0x01, C0|C1|C2|C3, "off_core_response_0"                  , 0x0, ATTR_NONE, 0x1A6 }, ignore events that require msr_offset */ \
 744 { 0xB8, 0x01, C0|C1|C2|C3, "snoop_response.hit"                   , 0x0, ATTR_NONE, 0x0 }, \
 745 { 0xB8, 0x02, C0|C1|C2|C3, "snoop_response.hite"                  , 0x0, ATTR_NONE, 0x0 }, \
 746 { 0xB8, 0x04, C0|C1|C2|C3, "snoop_response.hitm"                  , 0x0, ATTR_NONE, 0x0 }, \
 747 /* { 0xBB, 0x01, C0|C1|C2|C3, "off_core_response_1"                  , 0x0, ATTR_NONE, 0x1A7 }, ignore events that require msr_offset */ \
 748 { 0xC0, 0x00, C0|C1|C2|C3, "inst_retired.any_p"                   , 0x0, ATTR_NONE, 0x0 }, \
 749 { 0xC0, 0x02, C0|C1|C2|C3, "inst_retired.x87"                     , 0x0, ATTR_NONE, 0x0 }, \
 750 { 0xC0, 0x04, C0|C1|C2|C3, "inst_retired.mmx"                     , 0x0, ATTR_NONE, 0x0 }, \
 751 { 0xC2, 0x01, C0|C1|C2|C3, "uops_retired.any"                     , 0x0, ATTR_NONE, 0x0 }, \
 752 { 0xC2, 0x01, C0|C1|C2|C3, "uops_retired.active_cycles"           , 0x1, ATTR_NONE, 0x0 }, \
 753 { 0xC2, 0x01, C0|C1|C2|C3, "uops_retired.stall_cycles"            , 0x1, ATTR_INV , 0x0 }, \
 754 { 0xC2, 0x02, C0|C1|C2|C3, "uops_retired.retire_slots"            , 0x0, ATTR_NONE, 0x0 }, \
 755 { 0xC2, 0x04, C0|C1|C2|C3, "uops_retired.macro_fused"             , 0x0, ATTR_NONE, 0x0 }, \
 756 { 0xC3, 0x01, C0|C1|C2|C3, "machine_clears.cycles"                , 0x0, ATTR_NONE, 0x0 }, \
 757 { 0xC3, 0x02, C0|C1|C2|C3, "machine_clears.mem_order"             , 0x0, ATTR_NONE, 0x0 }, \
 758 { 0xC3, 0x04, C0|C1|C2|C3, "machine_clears.smc"                   , 0x0, ATTR_NONE, 0x0 }, \
 759 { 0xC4, 0x00, C0|C1|C2|C3, "br_inst_retired.all_branches"         , 0x0, ATTR_NONE, 0x0 }, \
 760 { 0xC4, 0x01, C0|C1|C2|C3, "br_inst_retired.conditional"          , 0x0, ATTR_NONE, 0x0 }, \
 761 { 0xC4, 0x02, C0|C1|C2|C3, "br_inst_retired.near_call"            , 0x0, ATTR_NONE, 0x0 }, \
 762 { 0xC5, 0x00, C0|C1|C2|C3, "br_misp_retired.all_branches"         , 0x0, ATTR_NONE, 0x0 }, \
 763 { 0xC5, 0x02, C0|C1|C2|C3, "br_misp_retired.near_call"            , 0x0, ATTR_NONE, 0x0 }, \
 764 { 0xC7, 0x01, C0|C1|C2|C3, "ssex_uops_retired.packed_single"      , 0x0, ATTR_NONE, 0x0 }, \
 765 { 0xC7, 0x02, C0|C1|C2|C3, "ssex_uops_retired.scalar_single"      , 0x0, ATTR_NONE, 0x0 }, \
 766 { 0xC7, 0x04, C0|C1|C2|C3, "ssex_uops_retired.packed_double"      , 0x0, ATTR_NONE, 0x0 }, \
 767 { 0xC7, 0x08, C0|C1|C2|C3, "ssex_uops_retired.scalar_double"      , 0x0, ATTR_NONE, 0x0 }, \
 768 { 0xC7, 0x10, C0|C1|C2|C3, "ssex_uops_retired.vector_integer"     , 0x0, ATTR_NONE, 0x0 }, \
 769 { 0xC8, 0x20, C0|C1|C2|C3, "itlb_miss_retired"                    , 0x0, ATTR_NONE, 0x0 }, \
 770 { 0xCB, 0x01, C0|C1|C2|C3, "mem_load_retired.l1d_hit"             , 0x0, ATTR_NONE, 0x0 }, \
 771 { 0xCB, 0x02, C0|C1|C2|C3, "mem_load_retired.l2_hit"              , 0x0, ATTR_NONE, 0x0 }, \
 772 { 0xCB, 0x04, C0|C1|C2|C3, "mem_load_retired.llc_unshared_hit"    , 0x0, ATTR_NONE, 0x0 }, \
 773 { 0xCB, 0x08, C0|C1|C2|C3, "mem_load_retired.other_core_l2_hit_hitm"    , 0x0, ATTR_NONE, 0x0 }, \
 774 { 0xCB, 0x10, C0|C1|C2|C3, "mem_load_retired.llc_miss"            , 0x0, ATTR_NONE, 0x0 }, \
 775 { 0xCB, 0x40, C0|C1|C2|C3, "mem_load_retired.hit_lfb"             , 0x0, ATTR_NONE, 0x0 }, \
 776 { 0xCB, 0x80, C0|C1|C2|C3, "mem_load_retired.dtlb_miss"           , 0x0, ATTR_NONE, 0x0 }, \
 777 { 0xCC, 0x01, C0|C1|C2|C3, "fp_mmx_trans.to_fp"                   , 0x0, ATTR_NONE, 0x0 }, \
 778 { 0xCC, 0x02, C0|C1|C2|C3, "fp_mmx_trans.to_mmx"                  , 0x0, ATTR_NONE, 0x0 }, \
 779 { 0xCC, 0x03, C0|C1|C2|C3, "fp_mmx_trans.any"                     , 0x0, ATTR_NONE, 0x0 }, \
 780 { 0xD0, 0x01, C0|C1|C2|C3, "macro_insts.decoded"                  , 0x0, ATTR_NONE, 0x0 }, \
 781 { 0xD1, 0x02, C0|C1|C2|C3, "uops_decoded.ms"                      , 0x0, ATTR_NONE, 0x0 }, \
 782 { 0xD1, 0x04, C0|C1|C2|C3, "uops_decoded.esp_folding"             , 0x0, ATTR_NONE, 0x0 }, \
 783 { 0xD1, 0x08, C0|C1|C2|C3, "uops_decoded.esp_sync"                , 0x0, ATTR_NONE, 0x0 }, \
 784 { 0xD2, 0x01, C0|C1|C2|C3, "rat_stalls.flags"                     , 0x0, ATTR_NONE, 0x0 }, \
 785 { 0xD2, 0x02, C0|C1|C2|C3, "rat_stalls.registers"                 , 0x0, ATTR_NONE, 0x0 }, \
 786 { 0xD2, 0x04, C0|C1|C2|C3, "rat_stalls.rob_read_port"             , 0x0, ATTR_NONE, 0x0 }, \
 787 { 0xD2, 0x08, C0|C1|C2|C3, "rat_stalls.scoreboard"                , 0x0, ATTR_NONE, 0x0 }, \
 788 { 0xD2, 0x0F, C0|C1|C2|C3, "rat_stalls.any"                       , 0x0, ATTR_NONE, 0x0 }, \
 789 { 0xD4, 0x01, C0|C1|C2|C3, "seg_rename_stalls"                    , 0x0, ATTR_NONE, 0x0 }, \
 790 { 0xD5, 0x01, C0|C1|C2|C3, "es_reg_renames"                       , 0x0, ATTR_NONE, 0x0 }, \
 791 { 0xDB, 0x01, C0|C1|C2|C3, "uop_unfusion"                         , 0x0, ATTR_NONE, 0x0 }, \
 792 { 0xE0, 0x01, C0|C1|C2|C3, "br_inst_decoded"                      , 0x0, ATTR_NONE, 0x0 }, \
 793 { 0xE5, 0x01, C0|C1|C2|C3, "bpu_missed_call_ret"                  , 0x0, ATTR_NONE, 0x0 }, \
 794 { 0xE6, 0x01, C0|C1|C2|C3, "baclear.clear"                        , 0x0, ATTR_NONE, 0x0 }, \
 795 { 0xE6, 0x02, C0|C1|C2|C3, "baclear.bad_target"                   , 0x0, ATTR_NONE, 0x0 }, \
 796 { 0xE8, 0x01, C0|C1|C2|C3, "bpu_clears.early"                     , 0x0, ATTR_NONE, 0x0 }, \
 797 { 0xE8, 0x02, C0|C1|C2|C3, "bpu_clears.late"                      , 0x0, ATTR_NONE, 0x0 }, \
 798 { 0xF0, 0x01, C0|C1|C2|C3, "l2_transactions.load"                 , 0x0, ATTR_NONE, 0x0 }, \
 799 { 0xF0, 0x02, C0|C1|C2|C3, "l2_transactions.rfo"                  , 0x0, ATTR_NONE, 0x0 }, \
 800 { 0xF0, 0x04, C0|C1|C2|C3, "l2_transactions.ifetch"               , 0x0, ATTR_NONE, 0x0 }, \
 801 { 0xF0, 0x08, C0|C1|C2|C3, "l2_transactions.prefetch"             , 0x0, ATTR_NONE, 0x0 }, \
 802 { 0xF0, 0x10, C0|C1|C2|C3, "l2_transactions.l1d_wb"               , 0x0, ATTR_NONE, 0x0 }, \
 803 { 0xF0, 0x20, C0|C1|C2|C3, "l2_transactions.fill"                 , 0x0, ATTR_NONE, 0x0 }, \
 804 { 0xF0, 0x40, C0|C1|C2|C3, "l2_transactions.wb"                   , 0x0, ATTR_NONE, 0x0 }, \
 805 { 0xF0, 0x80, C0|C1|C2|C3, "l2_transactions.any"                  , 0x0, ATTR_NONE, 0x0 }, \
 806 { 0xF1, 0x02, C0|C1|C2|C3, "l2_lines_in.s_state"                  , 0x0, ATTR_NONE, 0x0 }, \
 807 { 0xF1, 0x04, C0|C1|C2|C3, "l2_lines_in.e_state"                  , 0x0, ATTR_NONE, 0x0 }, \
 808 { 0xF1, 0x07, C0|C1|C2|C3, "l2_lines_in.any"                      , 0x0, ATTR_NONE, 0x0 }, \
 809 { 0xF2, 0x01, C0|C1|C2|C3, "l2_lines_out.demand_clean"            , 0x0, ATTR_NONE, 0x0 }, \
 810 { 0xF2, 0x02, C0|C1|C2|C3, "l2_lines_out.demand_dirty"            , 0x0, ATTR_NONE, 0x0 }, \
 811 { 0xF2, 0x04, C0|C1|C2|C3, "l2_lines_out.prefetch_clean"          , 0x0, ATTR_NONE, 0x0 }, \
 812 { 0xF2, 0x08, C0|C1|C2|C3, "l2_lines_out.prefetch_dirty"          , 0x0, ATTR_NONE, 0x0 }, \
 813 { 0xF2, 0x0F, C0|C1|C2|C3, "l2_lines_out.any"                     , 0x0, ATTR_NONE, 0x0 }, \
 814 { 0xF4, 0x10, C0|C1|C2|C3, "sq_misc.split_lock"                   , 0x0, ATTR_NONE, 0x0 }, \
 815 { 0xF6, 0x01, C0|C1|C2|C3, "sq_full_stall_cycles"                 , 0x0, ATTR_NONE, 0x0 }, \
 816 { 0xF7, 0x01, C0|C1|C2|C3, "fp_assist.all"                        , 0x0, ATTR_NONE, 0x0 }, \
 817 { 0xF7, 0x02, C0|C1|C2|C3, "fp_assist.output"                     , 0x0, ATTR_NONE, 0x0 }, \
 818 { 0xF7, 0x04, C0|C1|C2|C3, "fp_assist.input"                      , 0x0, ATTR_NONE, 0x0 }, \
 819 { 0xFD, 0x01, C0|C1|C2|C3, "simd_int_64.packed_mpy"               , 0x0, ATTR_NONE, 0x0 }, \
 820 { 0xFD, 0x02, C0|C1|C2|C3, "simd_int_64.packed_shift"             , 0x0, ATTR_NONE, 0x0 }, \
 821 { 0xFD, 0x04, C0|C1|C2|C3, "simd_int_64.pack"                     , 0x0, ATTR_NONE, 0x0 }, \
 822 { 0xFD, 0x08, C0|C1|C2|C3, "simd_int_64.unpack"                   , 0x0, ATTR_NONE, 0x0 }, \
 823 { 0xFD, 0x10, C0|C1|C2|C3, "simd_int_64.packed_logical"           , 0x0, ATTR_NONE, 0x0 }, \
 824 { 0xFD, 0x20, C0|C1|C2|C3, "simd_int_64.packed_arith"             , 0x0, ATTR_NONE, 0x0 }, \
 825 { 0xFD, 0x40, C0|C1|C2|C3, "simd_int_64.shuffle_move"             , 0x0, ATTR_NONE, 0x0 }, \
 826 /* end of #define */
 827
 828 #define   EVENTS_FAM6_MOD46_ONLY                  \
 829 { 0x0F, 0x01, C0|C1|C2|C3, "mem_uncore_retired.l3_data_miss_unknown"    , 0x0, ATTR_NONE, 0x0 }, \
 830 { 0x0F, 0x80, C0|C1|C2|C3, "mem_uncore_retired.uncacheable"       , 0x0, ATTR_NONE, 0x0 }, \
 831 /* end of #define */
 832
 833 /* Intel Westmere Processor */
 834 /*
 835  * The Westmere tables are basically from Bug 16173963
 836  *   libcpc counter names should be based on public Intel documentation -- Westmere
 837  * and those tables are basically from the
 838  * Intel SDM, January 2013, Section 19.6, Table 19-13.
 839  * We omit the Table 19-14 uncore events.
 840  *
 841  * Note that the table below includes some events from
 842  * the Intel SDM that require cmask or attr settings.
 843  * These events are not in libcpc, which did not include
 844  * events requiring cmask or attr until Sandy Bridge.
 845  */
 846
 847 #define EVENTS_FAM6_MOD37                                               \
 848 { 0x03, 0x02, C0|C1|C2|C3, "load_block.overlap_store"             , 0x0, ATTR_NONE, 0x0 }, \
 849 { 0x04, 0x07, C0|C1|C2|C3, "sb_drain.any"                         , 0x0, ATTR_NONE, 0x0 }, \
 850 { 0x05, 0x02, C0|C1|C2|C3, "misalign_mem_ref.store"               , 0x0, ATTR_NONE, 0x0 }, \
 851 { 0x06, 0x04, C0|C1|C2|C3, "store_blocks.at_ret"                  , 0x0, ATTR_NONE, 0x0 }, \
 852 { 0x06, 0x08, C0|C1|C2|C3, "store_blocks.l1d_block"               , 0x0, ATTR_NONE, 0x0 }, \
 853 { 0x07, 0x01, C0|C1|C2|C3, "partial_address_alias"                , 0x0, ATTR_NONE, 0x0 }, \
 854 { 0x08, 0x01, C0|C1|C2|C3, "dtlb_load_misses.any"                 , 0x0, ATTR_NONE, 0x0 }, \
 855 { 0x08, 0x02, C0|C1|C2|C3, "dtlb_load_misses.walk_completed"      , 0x0, ATTR_NONE, 0x0 }, \
 856 { 0x08, 0x04, C0|C1|C2|C3, "dtlb_load_misses.walk_cycles"         , 0x0, ATTR_NONE, 0x0 }, \
 857 { 0x08, 0x10, C0|C1|C2|C3, "dtlb_load_misses.stlb_hit"            , 0x0, ATTR_NONE, 0x0 }, \
 858 { 0x08, 0x20, C0|C1|C2|C3, "dtlb_load_misses.pde_miss"            , 0x0, ATTR_NONE, 0x0 }, \
 859 { 0x0B, 0x01, C0|C1|C2|C3, "mem_inst_retired.loads"               , 0x0, ATTR_NONE, 0x0 }, \
 860 { 0x0B, 0x02, C0|C1|C2|C3, "mem_inst_retired.stores"              , 0x0, ATTR_NONE, 0x0 }, \
 861 { 0x0B, 0x10, C0|C1|C2|C3, "mem_inst_retired.latency_above_threshold"   , 0x0, ATTR_NONE, 0x0 }, \
 862 { 0x0C, 0x01, C0|C1|C2|C3, "mem_store_retired.dtlb_miss"          , 0x0, ATTR_NONE, 0x0 }, \
 863 { 0x0E, 0x01, C0|C1|C2|C3, "uops_issued.any"                      , 0x0, ATTR_NONE, 0x0 }, \
 864 { 0x0E, 0x02, C0|C1|C2|C3, "uops_issued.fused"                    , 0x0, ATTR_NONE, 0x0 }, \
 865 { 0x0F, 0x01, C0|C1|C2|C3, "mem_uncore_retired.unknown_source"    , 0x0, ATTR_NONE, 0x0 }, \
 866 { 0x0F, 0x80, C0|C1|C2|C3, "mem_uncore_retired.uncacheable"       , 0x0, ATTR_NONE, 0x0 }, \
 867 { 0x10, 0x01, C0|C1|C2|C3, "fp_comp_ops_exe.x87"                  , 0x0, ATTR_NONE, 0x0 }, \
 868 { 0x10, 0x02, C0|C1|C2|C3, "fp_comp_ops_exe.mmx"                  , 0x0, ATTR_NONE, 0x0 }, \
 869 { 0x10, 0x04, C0|C1|C2|C3, "fp_comp_ops_exe.sse_fp"               , 0x0, ATTR_NONE, 0x0 }, \
 870 { 0x10, 0x08, C0|C1|C2|C3, "fp_comp_ops_exe.sse2_integer"         , 0x0, ATTR_NONE, 0x0 }, \
 871 { 0x10, 0x10, C0|C1|C2|C3, "fp_comp_ops_exe.sse_fp_packed"        , 0x0, ATTR_NONE, 0x0 }, \
 872 { 0x10, 0x20, C0|C1|C2|C3, "fp_comp_ops_exe.sse_fp_scalar"        , 0x0, ATTR_NONE, 0x0 }, \
 873 { 0x10, 0x40, C0|C1|C2|C3, "fp_comp_ops_exe.sse_single_precision" , 0x0, ATTR_NONE, 0x0 }, \
 874 { 0x10, 0x80, C0|C1|C2|C3, "fp_comp_ops_exe.sse_double_precision" , 0x0, ATTR_NONE, 0x0 }, \
 875 { 0x12, 0x01, C0|C1|C2|C3, "simd_int_128.packed_mpy"              , 0x0, ATTR_NONE, 0x0 }, \
 876 { 0x12, 0x02, C0|C1|C2|C3, "simd_int_128.packed_shift"            , 0x0, ATTR_NONE, 0x0 }, \
 877 { 0x12, 0x04, C0|C1|C2|C3, "simd_int_128.pack"                    , 0x0, ATTR_NONE, 0x0 }, \
 878 { 0x12, 0x08, C0|C1|C2|C3, "simd_int_128.unpack"                  , 0x0, ATTR_NONE, 0x0 }, \
 879 { 0x12, 0x10, C0|C1|C2|C3, "simd_int_128.packed_logical"          , 0x0, ATTR_NONE, 0x0 }, \
 880 { 0x12, 0x20, C0|C1|C2|C3, "simd_int_128.packed_arith"            , 0x0, ATTR_NONE, 0x0 }, \
 881 { 0x12, 0x40, C0|C1|C2|C3, "simd_int_128.shuffle_move"            , 0x0, ATTR_NONE, 0x0 }, \
 882 { 0x13, 0x01, C0|C1|C2|C3, "load_dispatch.rs"                     , 0x0, ATTR_NONE, 0x0 }, \
 883 { 0x13, 0x02, C0|C1|C2|C3, "load_dispatch.rs_delayed"             , 0x0, ATTR_NONE, 0x0 }, \
 884 { 0x13, 0x04, C0|C1|C2|C3, "load_dispatch.mob"                    , 0x0, ATTR_NONE, 0x0 }, \
 885 { 0x13, 0x07, C0|C1|C2|C3, "load_dispatch.any"                    , 0x0, ATTR_NONE, 0x0 }, \
 886 { 0x14, 0x01, C0|C1|C2|C3, "arith.cycles_div_busy"                , 0x0, ATTR_NONE, 0x0 }, \
 887 { 0x14, 0x02, C0|C1|C2|C3, "arith.mul"                            , 0x0, ATTR_NONE, 0x0 }, \
 888 { 0x17, 0x01, C0|C1|C2|C3, "inst_queue_writes"                    , 0x0, ATTR_NONE, 0x0 }, \
 889 { 0x18, 0x01, C0|C1|C2|C3, "inst_decoded.dec0"                    , 0x0, ATTR_NONE, 0x0 }, \
 890 { 0x19, 0x01, C0|C1|C2|C3, "two_uop_insts_decoded"                , 0x0, ATTR_NONE, 0x0 }, \
 891 { 0x1E, 0x01, C0|C1|C2|C3, "inst_queue_write_cycles"              , 0x0, ATTR_NONE, 0x0 }, \
 892 { 0x20, 0x01, C0|C1|C2|C3, "lsd_overflow"                         , 0x0, ATTR_NONE, 0x0 }, \
 893 { 0x24, 0x01, C0|C1|C2|C3, "l2_rqsts.ld_hit"                      , 0x0, ATTR_NONE, 0x0 }, \
 894 { 0x24, 0x02, C0|C1|C2|C3, "l2_rqsts.ld_miss"                     , 0x0, ATTR_NONE, 0x0 }, \
 895 { 0x24, 0x03, C0|C1|C2|C3, "l2_rqsts.loads"                       , 0x0, ATTR_NONE, 0x0 }, \
 896 { 0x24, 0x04, C0|C1|C2|C3, "l2_rqsts.rfo_hit"                     , 0x0, ATTR_NONE, 0x0 }, \
 897 { 0x24, 0x08, C0|C1|C2|C3, "l2_rqsts.rfo_miss"                    , 0x0, ATTR_NONE, 0x0 }, \
 898 { 0x24, 0x0C, C0|C1|C2|C3, "l2_rqsts.rfos"                        , 0x0, ATTR_NONE, 0x0 }, \
 899 { 0x24, 0x10, C0|C1|C2|C3, "l2_rqsts.ifetch_hit"                  , 0x0, ATTR_NONE, 0x0 }, \
 900 { 0x24, 0x20, C0|C1|C2|C3, "l2_rqsts.ifetch_miss"                 , 0x0, ATTR_NONE, 0x0 }, \
 901 { 0x24, 0x30, C0|C1|C2|C3, "l2_rqsts.ifetches"                    , 0x0, ATTR_NONE, 0x0 }, \
 902 { 0x24, 0x40, C0|C1|C2|C3, "l2_rqsts.prefetch_hit"                , 0x0, ATTR_NONE, 0x0 }, \
 903 { 0x24, 0x80, C0|C1|C2|C3, "l2_rqsts.prefetch_miss"               , 0x0, ATTR_NONE, 0x0 }, \
 904 { 0x24, 0xAA, C0|C1|C2|C3, "l2_rqsts.miss"                        , 0x0, ATTR_NONE, 0x0 }, \
 905 { 0x24, 0xC0, C0|C1|C2|C3, "l2_rqsts.prefetches"                  , 0x0, ATTR_NONE, 0x0 }, \
 906 { 0x24, 0xFF, C0|C1|C2|C3, "l2_rqsts.references"                  , 0x0, ATTR_NONE, 0x0 }, \
 907 { 0x26, 0x01, C0|C1|C2|C3, "l2_data_rqsts.demand.i_state"         , 0x0, ATTR_NONE, 0x0 }, \
 908 { 0x26, 0x02, C0|C1|C2|C3, "l2_data_rqsts.demand.s_state"         , 0x0, ATTR_NONE, 0x0 }, \
 909 { 0x26, 0x04, C0|C1|C2|C3, "l2_data_rqsts.demand.e_state"         , 0x0, ATTR_NONE, 0x0 }, \
 910 { 0x26, 0x08, C0|C1|C2|C3, "l2_data_rqsts.demand.m_state"         , 0x0, ATTR_NONE, 0x0 }, \
 911 { 0x26, 0x0F, C0|C1|C2|C3, "l2_data_rqsts.demand.mesi"            , 0x0, ATTR_NONE, 0x0 }, \
 912 { 0x26, 0x10, C0|C1|C2|C3, "l2_data_rqsts.prefetch.i_state"       , 0x0, ATTR_NONE, 0x0 }, \
 913 { 0x26, 0x20, C0|C1|C2|C3, "l2_data_rqsts.prefetch.s_state"       , 0x0, ATTR_NONE, 0x0 }, \
 914 { 0x26, 0x40, C0|C1|C2|C3, "l2_data_rqsts.prefetch.e_state"       , 0x0, ATTR_NONE, 0x0 }, \
 915 { 0x26, 0x80, C0|C1|C2|C3, "l2_data_rqsts.prefetch.m_state"       , 0x0, ATTR_NONE, 0x0 }, \
 916 { 0x26, 0xF0, C0|C1|C2|C3, "l2_data_rqsts.prefetch.mesi"          , 0x0, ATTR_NONE, 0x0 }, \
 917 { 0x26, 0xFF, C0|C1|C2|C3, "l2_data_rqsts.any"                    , 0x0, ATTR_NONE, 0x0 }, \
 918 { 0x27, 0x01, C0|C1|C2|C3, "l2_write.rfo.i_state"                 , 0x0, ATTR_NONE, 0x0 }, \
 919 { 0x27, 0x02, C0|C1|C2|C3, "l2_write.rfo.s_state"                 , 0x0, ATTR_NONE, 0x0 }, \
 920 { 0x27, 0x08, C0|C1|C2|C3, "l2_write.rfo.m_state"                 , 0x0, ATTR_NONE, 0x0 }, \
 921 { 0x27, 0x0E, C0|C1|C2|C3, "l2_write.rfo.hit"                     , 0x0, ATTR_NONE, 0x0 }, \
 922 { 0x27, 0x0F, C0|C1|C2|C3, "l2_write.rfo.mesi"                    , 0x0, ATTR_NONE, 0x0 }, \
 923 { 0x27, 0x10, C0|C1|C2|C3, "l2_write.lock.i_state"                , 0x0, ATTR_NONE, 0x0 }, \
 924 { 0x27, 0x20, C0|C1|C2|C3, "l2_write.lock.s_state"                , 0x0, ATTR_NONE, 0x0 }, \
 925 { 0x27, 0x40, C0|C1|C2|C3, "l2_write.lock.e_state"                , 0x0, ATTR_NONE, 0x0 }, \
 926 { 0x27, 0x80, C0|C1|C2|C3, "l2_write.lock.m_state"                , 0x0, ATTR_NONE, 0x0 }, \
 927 { 0x27, 0xE0, C0|C1|C2|C3, "l2_write.lock.hit"                    , 0x0, ATTR_NONE, 0x0 }, \
 928 { 0x27, 0xF0, C0|C1|C2|C3, "l2_write.lock.mesi"                   , 0x0, ATTR_NONE, 0x0 }, \
 929 { 0x28, 0x01, C0|C1|C2|C3, "l1d_wb_l2.i_state"                    , 0x0, ATTR_NONE, 0x0 }, \
 930 { 0x28, 0x02, C0|C1|C2|C3, "l1d_wb_l2.s_state"                    , 0x0, ATTR_NONE, 0x0 }, \
 931 { 0x28, 0x04, C0|C1|C2|C3, "l1d_wb_l2.e_state"                    , 0x0, ATTR_NONE, 0x0 }, \
 932 { 0x28, 0x08, C0|C1|C2|C3, "l1d_wb_l2.m_state"                    , 0x0, ATTR_NONE, 0x0 }, \
 933 { 0x28, 0x0F, C0|C1|C2|C3, "l1d_wb_l2.mesi"                       , 0x0, ATTR_NONE, 0x0 }, \
 934 { 0x2E, 0x41, C0|C1|C2|C3, "l3_lat_cache.miss"                    , 0x0, ATTR_NONE, 0x0 }, \
 935 { 0x2E, 0x4F, C0|C1|C2|C3, "l3_lat_cache.reference"               , 0x0, ATTR_NONE, 0x0 }, \
 936 { 0x3C, 0x00, C0|C1|C2|C3, "cpu_clk_unhalted.thread_p"            , 0x0, ATTR_NONE, 0x0 }, \
 937 { 0x3C, 0x01, C0|C1|C2|C3, "cpu_clk_unhalted.ref_p"               , 0x0, ATTR_NONE, 0x0 }, \
 938 { 0x49, 0x01, C0|C1|C2|C3, "dtlb_misses.any"                      , 0x0, ATTR_NONE, 0x0 }, \
 939 { 0x49, 0x02, C0|C1|C2|C3, "dtlb_misses.walk_completed"           , 0x0, ATTR_NONE, 0x0 }, \
 940 { 0x49, 0x04, C0|C1|C2|C3, "dtlb_misses.walk_cycles"              , 0x0, ATTR_NONE, 0x0 }, \
 941 { 0x49, 0x10, C0|C1|C2|C3, "dtlb_misses.stlb_hit"                 , 0x0, ATTR_NONE, 0x0 }, \
 942 { 0x49, 0x20, C0|C1|C2|C3, "dtlb_misses.pde_miss"                 , 0x0, ATTR_NONE, 0x0 }, \
 943 { 0x49, 0x80, C0|C1|C2|C3, "dtlb_misses.large_walk_completed"     , 0x0, ATTR_NONE, 0x0 }, \
 944 { 0x4C, 0x01, C0|C1      , "load_hit_pre"                         , 0x0, ATTR_NONE, 0x0 }, \
 945 { 0x4E, 0x01, C0|C1      , "l1d_prefetch.requests"                , 0x0, ATTR_NONE, 0x0 }, \
 946 { 0x4E, 0x02, C0|C1      , "l1d_prefetch.miss"                    , 0x0, ATTR_NONE, 0x0 }, \
 947 { 0x4E, 0x04, C0|C1      , "l1d_prefetch.triggers"                , 0x0, ATTR_NONE, 0x0 }, \
 948 { 0x4F, 0x10, C0|C1|C2|C3, "ept.walk_cycles"                      , 0x0, ATTR_NONE, 0x0 }, \
 949 { 0x51, 0x01, C0|C1      , "l1d.repl"                             , 0x0, ATTR_NONE, 0x0 }, \
 950 { 0x51, 0x02, C0|C1      , "l1d.m_repl"                           , 0x0, ATTR_NONE, 0x0 }, \
 951 { 0x51, 0x04, C0|C1      , "l1d.m_evict"                          , 0x0, ATTR_NONE, 0x0 }, \
 952 { 0x51, 0x08, C0|C1      , "l1d.m_snoop_evict"                    , 0x0, ATTR_NONE, 0x0 }, \
 953 { 0x52, 0x01, C0|C1|C2|C3, "l1d_cache_prefetch_lock_fb_hit"       , 0x0, ATTR_NONE, 0x0 }, \
 954 { 0x60, 0x01, C0         , "offcore_requests_outstanding.demand.read_data", 0x0, ATTR_NONE, 0x0 }, \
 955 { 0x60, 0x02, C0         , "offcore_requests_outstanding.demand.read_code", 0x0, ATTR_NONE, 0x0 }, \
 956 { 0x60, 0x04, C0         , "offcore_requests_outstanding.demand.rfo"    , 0x0, ATTR_NONE, 0x0 }, \
 957 { 0x60, 0x08, C0         , "offcore_requests_outstanding.any_read", 0x0, ATTR_NONE, 0x0 }, \
 958 { 0x63, 0x01, C0|C1      , "cache_lock_cycles.l1d_l2"             , 0x0, ATTR_NONE, 0x0 }, \
 959 { 0x63, 0x02, C0|C1      , "cache_lock_cycles.l1d"                , 0x0, ATTR_NONE, 0x0 }, \
 960 { 0x6C, 0x01, C0|C1|C2|C3, "io_transactions"                      , 0x0, ATTR_NONE, 0x0 }, \
 961 { 0x80, 0x01, C0|C1|C2|C3, "l1i.hits"                             , 0x0, ATTR_NONE, 0x0 }, \
 962 { 0x80, 0x02, C0|C1|C2|C3, "l1i.misses"                           , 0x0, ATTR_NONE, 0x0 }, \
 963 { 0x80, 0x03, C0|C1|C2|C3, "l1i.reads"                            , 0x0, ATTR_NONE, 0x0 }, \
 964 { 0x80, 0x04, C0|C1|C2|C3, "l1i.cycles_stalled"                   , 0x0, ATTR_NONE, 0x0 }, \
 965 { 0x82, 0x01, C0|C1|C2|C3, "large_itlb.hit"                       , 0x0, ATTR_NONE, 0x0 }, \
 966 { 0x85, 0x01, C0|C1|C2|C3, "itlb_misses.any"                      , 0x0, ATTR_NONE, 0x0 }, \
 967 { 0x85, 0x02, C0|C1|C2|C3, "itlb_misses.walk_completed"           , 0x0, ATTR_NONE, 0x0 }, \
 968 { 0x85, 0x04, C0|C1|C2|C3, "itlb_misses.walk_cycles"              , 0x0, ATTR_NONE, 0x0 }, \
 969 { 0x85, 0x10, C0|C1|C2|C3, "itlb_misses.stlb_hit"                 , 0x0, ATTR_NONE, 0x0 }, \
 970 { 0x85, 0x80, C0|C1|C2|C3, "itlb_misses.large_walk_completed"     , 0x0, ATTR_NONE, 0x0 }, \
 971 { 0x87, 0x01, C0|C1|C2|C3, "ild_stall.lcp"                        , 0x0, ATTR_NONE, 0x0 }, \
 972 { 0x87, 0x02, C0|C1|C2|C3, "ild_stall.mru"                        , 0x0, ATTR_NONE, 0x0 }, \
 973 { 0x87, 0x04, C0|C1|C2|C3, "ild_stall.iq_full"                    , 0x0, ATTR_NONE, 0x0 }, \
 974 { 0x87, 0x08, C0|C1|C2|C3, "ild_stall.regen"                      , 0x0, ATTR_NONE, 0x0 }, \
 975 { 0x87, 0x0F, C0|C1|C2|C3, "ild_stall.any"                        , 0x0, ATTR_NONE, 0x0 }, \
 976 { 0x88, 0x01, C0|C1|C2|C3, "br_inst_exec.cond"                    , 0x0, ATTR_NONE, 0x0 }, \
 977 { 0x88, 0x02, C0|C1|C2|C3, "br_inst_exec.direct"                  , 0x0, ATTR_NONE, 0x0 }, \
 978 { 0x88, 0x04, C0|C1|C2|C3, "br_inst_exec.indirect_non_call"       , 0x0, ATTR_NONE, 0x0 }, \
 979 { 0x88, 0x07, C0|C1|C2|C3, "br_inst_exec.non_calls"               , 0x0, ATTR_NONE, 0x0 }, \
 980 { 0x88, 0x08, C0|C1|C2|C3, "br_inst_exec.return_near"             , 0x0, ATTR_NONE, 0x0 }, \
 981 { 0x88, 0x10, C0|C1|C2|C3, "br_inst_exec.direct_near_call"        , 0x0, ATTR_NONE, 0x0 }, \
 982 { 0x88, 0x20, C0|C1|C2|C3, "br_inst_exec.indirect_near_call"      , 0x0, ATTR_NONE, 0x0 }, \
 983 { 0x88, 0x30, C0|C1|C2|C3, "br_inst_exec.near_calls"              , 0x0, ATTR_NONE, 0x0 }, \
 984 { 0x88, 0x40, C0|C1|C2|C3, "br_inst_exec.taken"                   , 0x0, ATTR_NONE, 0x0 }, \
 985 { 0x88, 0x7F, C0|C1|C2|C3, "br_inst_exec.any"                     , 0x0, ATTR_NONE, 0x0 }, \
 986 { 0x89, 0x01, C0|C1|C2|C3, "br_misp_exec.cond"                    , 0x0, ATTR_NONE, 0x0 }, \
 987 { 0x89, 0x02, C0|C1|C2|C3, "br_misp_exec.direct"                  , 0x0, ATTR_NONE, 0x0 }, \
 988 { 0x89, 0x04, C0|C1|C2|C3, "br_misp_exec.indirect_non_call"       , 0x0, ATTR_NONE, 0x0 }, \
 989 { 0x89, 0x07, C0|C1|C2|C3, "br_misp_exec.non_calls"               , 0x0, ATTR_NONE, 0x0 }, \
 990 { 0x89, 0x08, C0|C1|C2|C3, "br_misp_exec.return_near"             , 0x0, ATTR_NONE, 0x0 }, \
 991 { 0x89, 0x10, C0|C1|C2|C3, "br_misp_exec.direct_near_call"        , 0x0, ATTR_NONE, 0x0 }, \
 992 { 0x89, 0x20, C0|C1|C2|C3, "br_misp_exec.indirect_near_call"      , 0x0, ATTR_NONE, 0x0 }, \
 993 { 0x89, 0x30, C0|C1|C2|C3, "br_misp_exec.near_calls"              , 0x0, ATTR_NONE, 0x0 }, \
 994 { 0x89, 0x40, C0|C1|C2|C3, "br_misp_exec.taken"                   , 0x0, ATTR_NONE, 0x0 }, \
 995 { 0x89, 0x7F, C0|C1|C2|C3, "br_misp_exec.any"                     , 0x0, ATTR_NONE, 0x0 }, \
 996 { 0xA2, 0x01, C0|C1|C2|C3, "resource_stalls.any"                  , 0x0, ATTR_NONE, 0x0 }, \
 997 { 0xA2, 0x02, C0|C1|C2|C3, "resource_stalls.load"                 , 0x0, ATTR_NONE, 0x0 }, \
 998 { 0xA2, 0x04, C0|C1|C2|C3, "resource_stalls.rs_full"              , 0x0, ATTR_NONE, 0x0 }, \
 999 { 0xA2, 0x08, C0|C1|C2|C3, "resource_stalls.store"                , 0x0, ATTR_NONE, 0x0 }, \
1000 { 0xA2, 0x10, C0|C1|C2|C3, "resource_stalls.rob_full"             , 0x0, ATTR_NONE, 0x0 }, \
1001 { 0xA2, 0x20, C0|C1|C2|C3, "resource_stalls.fpcw"                 , 0x0, ATTR_NONE, 0x0 }, \
1002 { 0xA2, 0x40, C0|C1|C2|C3, "resource_stalls.mxcsr"                , 0x0, ATTR_NONE, 0x0 }, \
1003 { 0xA2, 0x80, C0|C1|C2|C3, "resource_stalls.other"                , 0x0, ATTR_NONE, 0x0 }, \
1004 { 0xA6, 0x01, C0|C1|C2|C3, "macro_insts.fusions_decoded"          , 0x0, ATTR_NONE, 0x0 }, \
1005 { 0xA7, 0x01, C0|C1|C2|C3, "baclear_force_iq"                     , 0x0, ATTR_NONE, 0x0 }, \
1006 { 0xA8, 0x01, C0|C1|C2|C3, "lsd.uops"                             , 0x0, ATTR_NONE, 0x0 }, \
1007 { 0xAE, 0x01, C0|C1|C2|C3, "itlb_flush"                           , 0x0, ATTR_NONE, 0x0 }, \
1008 { 0xB0, 0x01, C0|C1|C2|C3, "offcore_requests.demand.read_data"    , 0x0, ATTR_NONE, 0x0 }, \
1009 { 0xB0, 0x02, C0|C1|C2|C3, "offcore_requests.demand.read_code"    , 0x0, ATTR_NONE, 0x0 }, \
1010 { 0xB0, 0x04, C0|C1|C2|C3, "offcore_requests.demand.rfo"          , 0x0, ATTR_NONE, 0x0 }, \
1011 { 0xB0, 0x08, C0|C1|C2|C3, "offcore_requests.any.read"            , 0x0, ATTR_NONE, 0x0 }, \
1012 { 0xB0, 0x10, C0|C1|C2|C3, "offcore_requests.any.rfo"             , 0x0, ATTR_NONE, 0x0 }, \
1013 { 0xB0, 0x40, C0|C1|C2|C3, "offcore_requests.l1d_writeback"       , 0x0, ATTR_NONE, 0x0 }, \
1014 { 0xB0, 0x80, C0|C1|C2|C3, "offcore_requests.any"                 , 0x0, ATTR_NONE, 0x0 }, \
1015 { 0xB1, 0x01, C0|C1|C2|C3, "uops_executed.port0"                  , 0x0, ATTR_NONE, 0x0 }, \
1016 { 0xB1, 0x02, C0|C1|C2|C3, "uops_executed.port1"                  , 0x0, ATTR_NONE, 0x0 }, \
1017 { 0xB1, 0x04, C0|C1|C2|C3, "uops_executed.port2_core"             , 0x0, ATTR_NONE, 0x0 }, \
1018 { 0xB1, 0x08, C0|C1|C2|C3, "uops_executed.port3_core"             , 0x0, ATTR_NONE, 0x0 }, \
1019 { 0xB1, 0x10, C0|C1|C2|C3, "uops_executed.port4_core"             , 0x0, ATTR_NONE, 0x0 }, \
1020 { 0xB1, 0x1F, C0|C1|C2|C3, "uops_executed.core_active_cycles_no_port5"  , 0x0, ATTR_NONE, 0x0 }, \
1021 { 0xB1, 0x20, C0|C1|C2|C3, "uops_executed.port5"                  , 0x0, ATTR_NONE, 0x0 }, \
1022 { 0xB1, 0x3F, C0|C1|C2|C3, "uops_executed.core_active_cycles"     , 0x0, ATTR_NONE, 0x0 }, \
1023 { 0xB1, 0x40, C0|C1|C2|C3, "uops_executed.port015"                , 0x0, ATTR_NONE, 0x0 }, \
1024 { 0xB1, 0x80, C0|C1|C2|C3, "uops_executed.port234"                , 0x0, ATTR_NONE, 0x0 }, \
1025 { 0xB2, 0x01, C0|C1|C2|C3, "offcore_requests_sq_full"             , 0x0, ATTR_NONE, 0x0 }, \
1026 { 0xB3, 0x01, C0,          "snoopq_requests_outstanding.data"     , 0x0, ATTR_NONE, 0x0 }, \
1027 { 0xB3, 0x02, C0,          "snoopq_requests_outstanding.invalidate"     , 0x0, ATTR_NONE, 0x0 }, \
1028 { 0xB3, 0x04, C0,          "snoopq_requests_outstanding.code"     , 0x0, ATTR_NONE, 0x0 }, \
1029 { 0xB4, 0x01, C0|C1|C2|C3, "snoopq_requests.code"                 , 0x0, ATTR_NONE, 0x0 }, \
1030 { 0xB4, 0x02, C0|C1|C2|C3, "snoopq_requests.data"                 , 0x0, ATTR_NONE, 0x0 }, \
1031 { 0xB4, 0x04, C0|C1|C2|C3, "snoopq_requests.invalidate"           , 0x0, ATTR_NONE, 0x0 }, \
1032 /* { 0xB7, 0x01, C0|C1|C2|C3, "off_core_response_0"                  , 0x0, ATTR_NONE, 0x1A6 }, ignore events that require msr_offset */ \
1033 { 0xB8, 0x01, C0|C1|C2|C3, "snoop_response.hit"                   , 0x0, ATTR_NONE, 0x0 }, \
1034 { 0xB8, 0x02, C0|C1|C2|C3, "snoop_response.hite"                  , 0x0, ATTR_NONE, 0x0 }, \
1035 { 0xB8, 0x04, C0|C1|C2|C3, "snoop_response.hitm"                  , 0x0, ATTR_NONE, 0x0 }, \
1036 /* { 0xBB, 0x01, C0|C1|C2|C3, "off_core_response_1"                  , 0x0, ATTR_NONE, 0x1A7 }, ignore events that require msr_offset */ \
1037 { 0xC0, 0x00, C0|C1|C2|C3, "inst_retired.any_p"                   , 0x0, ATTR_NONE, 0x0 }, \
1038 { 0xC0, 0x02, C0|C1|C2|C3, "inst_retired.x87"                     , 0x0, ATTR_NONE, 0x0 }, \
1039 { 0xC0, 0x04, C0|C1|C2|C3, "inst_retired.mmx"                     , 0x0, ATTR_NONE, 0x0 }, \
1040 { 0xC2, 0x01, C0|C1|C2|C3, "uops_retired.any"                     , 0x0, ATTR_NONE, 0x0 }, \
1041 { 0xC2, 0x02, C0|C1|C2|C3, "uops_retired.retire_slots"            , 0x0, ATTR_NONE, 0x0 }, \
1042 { 0xC2, 0x04, C0|C1|C2|C3, "uops_retired.macro_fused"             , 0x0, ATTR_NONE, 0x0 }, \
1043 { 0xC3, 0x01, C0|C1|C2|C3, "machine_clears.cycles"                , 0x0, ATTR_NONE, 0x0 }, \
1044 { 0xC3, 0x02, C0|C1|C2|C3, "machine_clears.mem_order"             , 0x0, ATTR_NONE, 0x0 }, \
1045 { 0xC3, 0x04, C0|C1|C2|C3, "machine_clears.smc"                   , 0x0, ATTR_NONE, 0x0 }, \
1046 { 0xC4, 0x00, C0|C1|C2|C3, "br_inst_retired.all_branches"         , 0x0, ATTR_NONE, 0x0 }, \
1047 { 0xC4, 0x01, C0|C1|C2|C3, "br_inst_retired.conditional"          , 0x0, ATTR_NONE, 0x0 }, \
1048 { 0xC4, 0x02, C0|C1|C2|C3, "br_inst_retired.near_call"            , 0x0, ATTR_NONE, 0x0 }, \
1049 { 0xC5, 0x00, C0|C1|C2|C3, "br_misp_retired.all_branches"         , 0x0, ATTR_NONE, 0x0 }, \
1050 { 0xC5, 0x01, C0|C1|C2|C3, "br_misp_retired.conditional"          , 0x0, ATTR_NONE, 0x0 }, \
1051 { 0xC5, 0x02, C0|C1|C2|C3, "br_misp_retired.near_call"            , 0x0, ATTR_NONE, 0x0 }, \
1052 { 0xC5, 0x04, C0|C1|C2|C3, "br_misp_retired.all_branches"         , 0x0, ATTR_NONE, 0x0 }, \
1053 { 0xC7, 0x01, C0|C1|C2|C3, "ssex_uops_retired.packed_single"      , 0x0, ATTR_NONE, 0x0 }, \
1054 { 0xC7, 0x02, C0|C1|C2|C3, "ssex_uops_retired.scalar_single"      , 0x0, ATTR_NONE, 0x0 }, \
1055 { 0xC7, 0x04, C0|C1|C2|C3, "ssex_uops_retired.packed_double"      , 0x0, ATTR_NONE, 0x0 }, \
1056 { 0xC7, 0x08, C0|C1|C2|C3, "ssex_uops_retired.scalar_double"      , 0x0, ATTR_NONE, 0x0 }, \
1057 { 0xC7, 0x10, C0|C1|C2|C3, "ssex_uops_retired.vector_integer"     , 0x0, ATTR_NONE, 0x0 }, \
1058 { 0xC8, 0x20, C0|C1|C2|C3, "itlb_miss_retired"                    , 0x0, ATTR_NONE, 0x0 }, \
1059 { 0xCB, 0x01, C0|C1|C2|C3, "mem_load_retired.l1d_hit"             , 0x0, ATTR_NONE, 0x0 }, \
1060 { 0xCB, 0x02, C0|C1|C2|C3, "mem_load_retired.l2_hit"              , 0x0, ATTR_NONE, 0x0 }, \
1061 { 0xCB, 0x04, C0|C1|C2|C3, "mem_load_retired.llc_unshared_hit"    , 0x0, ATTR_NONE, 0x0 }, \
1062 { 0xCB, 0x08, C0|C1|C2|C3, "mem_load_retired.other_core_l2_hit_hitm"    , 0x0, ATTR_NONE, 0x0 }, \
1063 { 0xCB, 0x10, C0|C1|C2|C3, "mem_load_retired.llc_miss"            , 0x0, ATTR_NONE, 0x0 }, \
1064 { 0xCB, 0x40, C0|C1|C2|C3, "mem_load_retired.hit_lfb"             , 0x0, ATTR_NONE, 0x0 }, \
1065 { 0xCB, 0x80, C0|C1|C2|C3, "mem_load_retired.dtlb_miss"           , 0x0, ATTR_NONE, 0x0 }, \
1066 { 0xCC, 0x01, C0|C1|C2|C3, "fp_mmx_trans.to_fp"                   , 0x0, ATTR_NONE, 0x0 }, \
1067 { 0xCC, 0x02, C0|C1|C2|C3, "fp_mmx_trans.to_mmx"                  , 0x0, ATTR_NONE, 0x0 }, \
1068 { 0xCC, 0x03, C0|C1|C2|C3, "fp_mmx_trans.any"                     , 0x0, ATTR_NONE, 0x0 }, \
1069 { 0xD0, 0x01, C0|C1|C2|C3, "macro_insts.decoded"                  , 0x0, ATTR_NONE, 0x0 }, \
1070 { 0xD1, 0x01, C0|C1|C2|C3, "uops_decoded.stall_cycles"            , 0x1, ATTR_INV , 0x0 }, \
1071 { 0xD1, 0x02, C0|C1|C2|C3, "uops_decoded.ms"                      , 0x0, ATTR_NONE, 0x0 }, \
1072 { 0xD1, 0x04, C0|C1|C2|C3, "uops_decoded.esp_folding"             , 0x0, ATTR_NONE, 0x0 }, \
1073 { 0xD1, 0x08, C0|C1|C2|C3, "uops_decoded.esp_sync"                , 0x0, ATTR_NONE, 0x0 }, \
1074 { 0xD2, 0x01, C0|C1|C2|C3, "rat_stalls.flags"                     , 0x0, ATTR_NONE, 0x0 }, \
1075 { 0xD2, 0x02, C0|C1|C2|C3, "rat_stalls.registers"                 , 0x0, ATTR_NONE, 0x0 }, \
1076 { 0xD2, 0x04, C0|C1|C2|C3, "rat_stalls.rob_read_port"             , 0x0, ATTR_NONE, 0x0 }, \
1077 { 0xD2, 0x08, C0|C1|C2|C3, "rat_stalls.scoreboard"                , 0x0, ATTR_NONE, 0x0 }, \
1078 { 0xD2, 0x0F, C0|C1|C2|C3, "rat_stalls.any"                       , 0x0, ATTR_NONE, 0x0 }, \
1079 { 0xD4, 0x01, C0|C1|C2|C3, "seg_rename_stalls"                    , 0x0, ATTR_NONE, 0x0 }, \
1080 { 0xD5, 0x01, C0|C1|C2|C3, "es_reg_renames"                       , 0x0, ATTR_NONE, 0x0 }, \
1081 { 0xDB, 0x01, C0|C1|C2|C3, "uop_unfusion"                         , 0x0, ATTR_NONE, 0x0 }, \
1082 { 0xE0, 0x01, C0|C1|C2|C3, "br_inst_decoded"                      , 0x0, ATTR_NONE, 0x0 }, \
1083 { 0xE5, 0x01, C0|C1|C2|C3, "bpu_missed_call_ret"                  , 0x0, ATTR_NONE, 0x0 }, \
1084 { 0xE6, 0x01, C0|C1|C2|C3, "baclear.clear"                        , 0x0, ATTR_NONE, 0x0 }, \
1085 { 0xE6, 0x02, C0|C1|C2|C3, "baclear.bad_target"                   , 0x0, ATTR_NONE, 0x0 }, \
1086 { 0xE8, 0x02, C0|C1|C2|C3, "bpu_clears.late"                      , 0x0, ATTR_NONE, 0x0 }, \
1087 { 0xEC, 0x01, C0|C1|C2|C3, "thread_active"                        , 0x0, ATTR_NONE, 0x0 }, \
1088 { 0xF0, 0x01, C0|C1|C2|C3, "l2_transactions.load"                 , 0x0, ATTR_NONE, 0x0 }, \
1089 { 0xF0, 0x02, C0|C1|C2|C3, "l2_transactions.rfo"                  , 0x0, ATTR_NONE, 0x0 }, \
1090 { 0xF0, 0x04, C0|C1|C2|C3, "l2_transactions.ifetch"               , 0x0, ATTR_NONE, 0x0 }, \
1091 { 0xF0, 0x08, C0|C1|C2|C3, "l2_transactions.prefetch"             , 0x0, ATTR_NONE, 0x0 }, \
1092 { 0xF0, 0x10, C0|C1|C2|C3, "l2_transactions.l1d_wb"               , 0x0, ATTR_NONE, 0x0 }, \
1093 { 0xF0, 0x20, C0|C1|C2|C3, "l2_transactions.fill"                 , 0x0, ATTR_NONE, 0x0 }, \
1094 { 0xF0, 0x40, C0|C1|C2|C3, "l2_transactions.wb"                   , 0x0, ATTR_NONE, 0x0 }, \
1095 { 0xF0, 0x80, C0|C1|C2|C3, "l2_transactions.any"                  , 0x0, ATTR_NONE, 0x0 }, \
1096 { 0xF1, 0x02, C0|C1|C2|C3, "l2_lines_in.s_state"                  , 0x0, ATTR_NONE, 0x0 }, \
1097 { 0xF1, 0x04, C0|C1|C2|C3, "l2_lines_in.e_state"                  , 0x0, ATTR_NONE, 0x0 }, \
1098 { 0xF1, 0x07, C0|C1|C2|C3, "l2_lines_in.any"                      , 0x0, ATTR_NONE, 0x0 }, \
1099 { 0xF2, 0x01, C0|C1|C2|C3, "l2_lines_out.demand_clean"            , 0x0, ATTR_NONE, 0x0 }, \
1100 { 0xF2, 0x02, C0|C1|C2|C3, "l2_lines_out.demand_dirty"            , 0x0, ATTR_NONE, 0x0 }, \
1101 { 0xF2, 0x04, C0|C1|C2|C3, "l2_lines_out.prefetch_clean"          , 0x0, ATTR_NONE, 0x0 }, \
1102 { 0xF2, 0x08, C0|C1|C2|C3, "l2_lines_out.prefetch_dirty"          , 0x0, ATTR_NONE, 0x0 }, \
1103 { 0xF2, 0x0F, C0|C1|C2|C3, "l2_lines_out.any"                     , 0x0, ATTR_NONE, 0x0 }, \
1104 { 0xF4, 0x04, C0|C1|C2|C3, "sq_misc.lru_hints"                    , 0x0, ATTR_NONE, 0x0 }, \
1105 { 0xF4, 0x10, C0|C1|C2|C3, "sq_misc.split_lock"                   , 0x0, ATTR_NONE, 0x0 }, \
1106 { 0xF6, 0x01, C0|C1|C2|C3, "sq_full_stall_cycles"                 , 0x0, ATTR_NONE, 0x0 }, \
1107 { 0xF7, 0x01, C0|C1|C2|C3, "fp_assist.all"                        , 0x0, ATTR_NONE, 0x0 }, \
1108 { 0xF7, 0x02, C0|C1|C2|C3, "fp_assist.output"                     , 0x0, ATTR_NONE, 0x0 }, \
1109 { 0xF7, 0x04, C0|C1|C2|C3, "fp_assist.input"                      , 0x0, ATTR_NONE, 0x0 }, \
1110 { 0xFD, 0x01, C0|C1|C2|C3, "simd_int_64.packed_mpy"               , 0x0, ATTR_NONE, 0x0 }, \
1111 { 0xFD, 0x02, C0|C1|C2|C3, "simd_int_64.packed_shift"             , 0x0, ATTR_NONE, 0x0 }, \
1112 { 0xFD, 0x04, C0|C1|C2|C3, "simd_int_64.pack"                     , 0x0, ATTR_NONE, 0x0 }, \
1113 { 0xFD, 0x08, C0|C1|C2|C3, "simd_int_64.unpack"                   , 0x0, ATTR_NONE, 0x0 }, \
1114 { 0xFD, 0x10, C0|C1|C2|C3, "simd_int_64.packed_logical"           , 0x0, ATTR_NONE, 0x0 }, \
1115 { 0xFD, 0x20, C0|C1|C2|C3, "simd_int_64.packed_arith"             , 0x0, ATTR_NONE, 0x0 }, \
1116 { 0xFD, 0x40, C0|C1|C2|C3, "simd_int_64.shuffle_move"             , 0x0, ATTR_NONE, 0x0 }, \
1117 /* end of #define */
1118
1119 /*
1120  * This special omission of the following events from Model 47
1121  * is due to usr/src/uts/intel/pcbe/wm_pcbe.h .  There seems
1122  * to be no substantiation for this treatment in the Intel SDM.
1123  */
1124 #define       EVENTS_FAM6_MOD37_ALSO                                    \
1125 { 0x0F, 0x02, C0|C1|C2|C3, "mem_uncore_retired.other_core_l2_hit" , 0x0, ATTR_NONE, 0x0 }, \
1126 { 0x0F, 0x04, C0|C1|C2|C3, "mem_uncore_retired.remote_hitm"       , 0x0, ATTR_NONE, 0x0 }, \
1127 { 0x0F, 0x08, C0|C1|C2|C3, "mem_uncore_retired.local_dram_remote_cache_hit", 0x0, ATTR_NONE, 0x0 },\
1128 { 0x0F, 0x10, C0|C1|C2|C3, "mem_uncore_retired.remote_dram"       , 0x0, ATTR_NONE, 0x0 }, \
1129 { 0x0F, 0x20, C0|C1|C2|C3, "mem_uncore_retired.other_llc_miss"    , 0x0, ATTR_NONE, 0x0 }, \
1130 /* end of #define */
1131
1132 /* Intel Sandy Bridge Processor */
1133 /*
1134  * The Sandy Bridge tables are basically from Bug 16457080
1135  *   libcpc counter names should be based on public Intel documentation -- Sandy Bridge
1136  * and those tables are basically from the
1137  * Intel SDM, January 2013, Section 19.4, Table 19-7.
1138  * Additionally, there are
1139  *   Table 19-8.  Model 42 only.
1140  *   Table 19-9.  Model 45 only.
1141  * We omit the Table 19-10 uncore events.
1142  */
1143
1144 #define EVENTS_FAM6_MOD42                                               \
1145 { 0x03, 0x01, C_ALL, "ld_blocks.data_unknown"                            , 0x0, ATTR_NONE, 0x0 }, \
1146 { 0x03, 0x02, C_ALL, "ld_blocks.store_forward"                           , 0x0, ATTR_NONE, 0x0 }, \
1147 { 0x03, 0x08, C_ALL, "ld_blocks.no_sr"                                   , 0x0, ATTR_NONE, 0x0 }, \
1148 { 0x03, 0x10, C_ALL, "ld_blocks.all_block"                               , 0x0, ATTR_NONE, 0x0 }, \
1149 { 0x05, 0x01, C_ALL, "misalign_mem_ref.loads"                            , 0x0, ATTR_NONE, 0x0 }, \
1150 { 0x05, 0x02, C_ALL, "misalign_mem_ref.stores"                           , 0x0, ATTR_NONE, 0x0 }, \
1151 { 0x07, 0x01, C_ALL, "ld_blocks_partial.address_alias"                   , 0x0, ATTR_NONE, 0x0 }, \
1152 { 0x07, 0x08, C_ALL, "ld_blocks_partial.all_sta_block"                   , 0x0, ATTR_NONE, 0x0 }, \
1153 { 0x08, 0x01, C_ALL, "dtlb_load_misses.miss_causes_a_walk"               , 0x0, ATTR_NONE, 0x0 }, \
1154 { 0x08, 0x02, C_ALL, "dtlb_load_misses.walk_completed"                   , 0x0, ATTR_NONE, 0x0 }, \
1155 { 0x08, 0x04, C_ALL, "dtlb_load_misses.walk_duration"                    , 0x0, ATTR_NONE, 0x0 }, \
1156 { 0x08, 0x10, C_ALL, "dtlb_load_misses.stlb_hit"                         , 0x0, ATTR_NONE, 0x0 }, \
1157 { 0x0D, 0x03, C_ALL, "int_misc.recovery_cycles"                          , 0x1, ATTR_NONE, 0x0 }, \
1158 { 0x0D, 0x03, C_ALL, "int_misc.recovery_stalls_count"                    , 0x1, ATTR_EDGE, 0x0 }, \
1159 { 0x0D, 0x40, C_ALL, "int_misc.rat_stall_cycles"                         , 0x0, ATTR_NONE, 0x0 }, \
1160 { 0x0E, 0x01, C_ALL, "uops_issued.any"                                   , 0x0, ATTR_NONE, 0x0 }, \
1161 { 0x0E, 0x01, C_ALL, "uops_issued.stall_cycles"                          , 0x1, ATTR_INV , 0x0 }, \
1162 { 0x0E, 0x01, C_ALL, "uops_issued.core_stall_cycles"                     , 0x1, ATTR_INV | ATTR_ANY, 0x0 }, \
1163 { 0x10, 0x01, C_ALL, "fp_comp_ops_exe.x87"                               , 0x0, ATTR_NONE, 0x0 }, \
1164 { 0x10, 0x10, C_ALL, "fp_comp_ops_exe.sse_fp_packed_double"              , 0x0, ATTR_NONE, 0x0 }, \
1165 { 0x10, 0x20, C_ALL, "fp_comp_ops_exe.sse_fp_scalar_single"              , 0x0, ATTR_NONE, 0x0 }, \
1166 { 0x10, 0x40, C_ALL, "fp_comp_ops_exe.sse_packed_single"                 , 0x0, ATTR_NONE, 0x0 }, \
1167 { 0x10, 0x80, C_ALL, "fp_comp_ops_exe.sse_scalar_double"                 , 0x0, ATTR_NONE, 0x0 }, \
1168 { 0x11, 0x01, C_ALL, "simd_fp_256.packed_single"                         , 0x0, ATTR_NONE, 0x0 }, \
1169 { 0x11, 0x02, C_ALL, "simd_fp_256.packed_double"                         , 0x0, ATTR_NONE, 0x0 }, \
1170 { 0x14, 0x01, C_ALL, "arith.fpu_div_active"                              , 0x0, ATTR_NONE, 0x0 }, \
1171 { 0x14, 0x01, C_ALL, "arith.fpu_div"                                     , 0x1, ATTR_EDGE, 0x0 }, \
1172 { 0x17, 0x01, C_ALL, "insts_written_to_iq.insts"                         , 0x0, ATTR_NONE, 0x0 }, \
1173 { 0x24, 0x01, C_ALL, "l2_rqsts.demand_data_rd_hit"                       , 0x0, ATTR_NONE, 0x0 }, \
1174 { 0x24, 0x03, C_ALL, "l2_rqsts.all_demand_data_rd"                       , 0x0, ATTR_NONE, 0x0 }, \
1175 { 0x24, 0x04, C_ALL, "l2_rqsts.rfo_hits"                                 , 0x0, ATTR_NONE, 0x0 }, \
1176 { 0x24, 0x08, C_ALL, "l2_rqsts.rfo_miss"                                 , 0x0, ATTR_NONE, 0x0 }, \
1177 { 0x24, 0x0C, C_ALL, "l2_rqsts.all_rfo"                                  , 0x0, ATTR_NONE, 0x0 }, \
1178 { 0x24, 0x10, C_ALL, "l2_rqsts.code_rd_hit"                              , 0x0, ATTR_NONE, 0x0 }, \
1179 { 0x24, 0x20, C_ALL, "l2_rqsts.code_rd_miss"                             , 0x0, ATTR_NONE, 0x0 }, \
1180 { 0x24, 0x30, C_ALL, "l2_rqsts.all_code_rd"                              , 0x0, ATTR_NONE, 0x0 }, \
1181 { 0x24, 0x40, C_ALL, "l2_rqsts.pf_hit"                                   , 0x0, ATTR_NONE, 0x0 }, \
1182 { 0x24, 0x80, C_ALL, "l2_rqsts.pf_miss"                                  , 0x0, ATTR_NONE, 0x0 }, \
1183 { 0x24, 0xC0, C_ALL, "l2_rqsts.all_pf"                                   , 0x0, ATTR_NONE, 0x0 }, \
1184 { 0x27, 0x01, C_ALL, "l2_store_lock_rqsts.miss"                          , 0x0, ATTR_NONE, 0x0 }, \
1185 { 0x27, 0x04, C_ALL, "l2_store_lock_rqsts.hit_e"                         , 0x0, ATTR_NONE, 0x0 }, \
1186 { 0x27, 0x08, C_ALL, "l2_store_lock_rqsts.hit_m"                         , 0x0, ATTR_NONE, 0x0 }, \
1187 { 0x27, 0x0F, C_ALL, "l2_store_lock_rqsts.all"                           , 0x0, ATTR_NONE, 0x0 }, \
1188 { 0x28, 0x01, C_ALL, "l2_l1d_wb_rqsts.miss"                              , 0x0, ATTR_NONE, 0x0 }, \
1189 { 0x28, 0x02, C_ALL, "l2_l1d_wb_rqsts.hit_s"                             , 0x0, ATTR_NONE, 0x0 }, \
1190 { 0x28, 0x04, C_ALL, "l2_l1d_wb_rqsts.hit_e"                             , 0x0, ATTR_NONE, 0x0 }, \
1191 { 0x28, 0x08, C_ALL, "l2_l1d_wb_rqsts.hit_m"                             , 0x0, ATTR_NONE, 0x0 }, \
1192 { 0x28, 0x0F, C_ALL, "l2_l1d_wb_rqsts.all"                               , 0x0, ATTR_NONE, 0x0 }, \
1193 { 0x2E, 0x41, C_ALL, "longest_lat_cache.miss"                            , 0x0, ATTR_NONE, 0x0 }, \
1194 { 0x2E, 0x4F, C_ALL, "longest_lat_cache.reference"                       , 0x0, ATTR_NONE, 0x0 }, \
1195 { 0x3C, 0x00, C_ALL, "cpu_clk_unhalted.thread_p"                         , 0x0, ATTR_NONE, 0x0 }, \
1196 { 0x3C, 0x01, C_ALL, "cpu_clk_thread_unhalted.ref_xclk"                  , 0x0, ATTR_NONE, 0x0 }, \
1197 { 0x48, 0x01, C2   , "l1d_pend_miss.pending"                             , 0x0, ATTR_NONE, 0x0 }, \
1198 { 0x48, 0x01, C2   , "l1d_pend_miss.pending_cycles"                      , 0x1, ATTR_NONE, 0x0 }, \
1199 { 0x48, 0x01, C2   , "l1d_pend_miss.occurrences"                         , 0x1, ATTR_EDGE, 0x0 }, \
1200 { 0x49, 0x01, C_ALL, "dtlb_store_misses.miss_causes_a_walk"              , 0x0, ATTR_NONE, 0x0 }, \
1201 { 0x49, 0x02, C_ALL, "dtlb_store_misses.walk_completed"                  , 0x0, ATTR_NONE, 0x0 }, \
1202 { 0x49, 0x04, C_ALL, "dtlb_store_misses.walk_duration"                   , 0x0, ATTR_NONE, 0x0 }, \
1203 { 0x49, 0x10, C_ALL, "dtlb_store_misses.stlb_hit"                        , 0x0, ATTR_NONE, 0x0 }, \
1204 { 0x4C, 0x01, C_ALL, "load_hit_pre.sw_pf"                                , 0x0, ATTR_NONE, 0x0 }, \
1205 { 0x4C, 0x02, C_ALL, "load_hit_pre.hw_pf"                                , 0x0, ATTR_NONE, 0x0 }, \
1206 { 0x4E, 0x02, C_ALL, "hw_pre_req.dl1_miss"                               , 0x0, ATTR_NONE, 0x0 }, \
1207 { 0x51, 0x01, C_ALL, "l1d.replacement"                                   , 0x0, ATTR_NONE, 0x0 }, \
1208 { 0x51, 0x02, C_ALL, "l1d.allocated_in_m"                                , 0x0, ATTR_NONE, 0x0 }, \
1209 { 0x51, 0x04, C_ALL, "l1d.eviction"                                      , 0x0, ATTR_NONE, 0x0 }, \
1210 { 0x51, 0x08, C_ALL, "l1d.all_m_replacement"                             , 0x0, ATTR_NONE, 0x0 }, \
1211 { 0x59, 0x20, C_ALL, "partial_rat_stalls.flags_merge_uop"                , 0x0, ATTR_NONE, 0x0 }, \
1212 { 0x59, 0x20, C_ALL, "partial_rat_stalls.flags_merge_uop_cycles"         , 0x1, ATTR_NONE, 0x0 }, \
1213 { 0x59, 0x40, C_ALL, "partial_rat_stalls.slow_lea_window"                , 0x0, ATTR_NONE, 0x0 }, \
1214 { 0x59, 0x80, C_ALL, "partial_rat_stalls.mul_single_uop"                 , 0x0, ATTR_NONE, 0x0 }, \
1215 { 0x5B, 0x0C, C0|C1|C2|C3, "resource_stalls2.all_fl_empty"               , 0x0, ATTR_NONE, 0x0 }, \
1216 { 0x5B, 0x0F, C_ALL, "resource_stalls2.all_prf_control"                  , 0x0, ATTR_NONE, 0x0 }, \
1217 { 0x5B, 0x40, C_ALL, "resource_stalls2.bob_full"                         , 0x0, ATTR_NONE, 0x0 }, \
1218 { 0x5B, 0x4F, C_ALL, "resource_stalls2.ooo_rsrc"                         , 0x0, ATTR_NONE, 0x0 }, \
1219 { 0x5C, 0x01, C_ALL, "cpl_cycles.ring0"                                  , 0x0, ATTR_NONE, 0x0 }, \
1220 { 0x5C, 0x01, C_ALL, "cpl_cycles.ring0_transition"                       , 0x0, ATTR_EDGE, 0x0 }, \
1221 { 0x5C, 0x02, C_ALL, "cpl_cycles.ring123"                                , 0x0, ATTR_NONE, 0x0 }, \
1222 { 0x5E, 0x01, C_ALL, "rs_events.empty_cycles"                            , 0x0, ATTR_NONE, 0x0 }, \
1223 { 0x60, 0x01, C_ALL, "offcore_requests_outstanding.demand_data_rd"       , 0x0, ATTR_NONE, 0x0 }, \
1224 { 0x60, 0x01, C_ALL, "offcore_requests_outstanding.demand_data_rd_cycles", 0x1, ATTR_NONE, 0x0 }, \
1225 { 0x60, 0x04, C_ALL, "offcore_requests_outstanding.demand_rfo"           , 0x0, ATTR_NONE, 0x0 }, \
1226 { 0x60, 0x04, C_ALL, "offcore_requests_outstanding.demand_rfo_cycles"    , 0x1, ATTR_NONE, 0x0 }, \
1227 { 0x60, 0x08, C_ALL, "offcore_requests_outstanding.all_data_rd"          , 0x0, ATTR_NONE, 0x0 }, \
1228 { 0x60, 0x08, C_ALL, "offcore_requests_outstanding.all_data_rd_cycles"   , 0x1, ATTR_NONE, 0x0 }, \
1229 { 0x63, 0x01, C_ALL, "lock_cycles.split_lock_uc_lock_duration"           , 0x0, ATTR_NONE, 0x0 }, \
1230 { 0x63, 0x02, C_ALL, "lock_cycles.cache_lock_duration"                   , 0x0, ATTR_NONE, 0x0 }, \
1231 { 0x79, 0x02, C_ALL, "idq.empty"                                         , 0x0, ATTR_NONE, 0x0 }, \
1232 { 0x79, 0x04, C_ALL, "idq.mite_uops"                                     , 0x0, ATTR_NONE, 0x0 }, \
1233 { 0x79, 0x04, C_ALL, "idq.mite_cycles"                                   , 0x1, ATTR_NONE, 0x0 }, \
1234 { 0x79, 0x08, C_ALL, "idq.dsb_uops"                                      , 0x0, ATTR_NONE, 0x0 }, \
1235 { 0x79, 0x08, C_ALL, "idq.dsb_cycles"                                    , 0x1, ATTR_NONE, 0x0 }, \
1236 { 0x79, 0x10, C_ALL, "idq.ms_dsb_uops"                                   , 0x0, ATTR_NONE, 0x0 }, \
1237 { 0x79, 0x10, C_ALL, "idq.ms_dsb_cycles"                                 , 0x1, ATTR_NONE, 0x0 }, \
1238 { 0x79, 0x10, C_ALL, "idq.ms_dsb_activations"                            , 0x1, ATTR_EDGE, 0x0 }, \
1239 { 0x79, 0x20, C_ALL, "idq.ms_mite_uops"                                  , 0x0, ATTR_NONE, 0x0 }, \
1240 { 0x79, 0x20, C_ALL, "idq.ms_mite_cycles"                                , 0x1, ATTR_NONE, 0x0 }, \
1241 { 0x79, 0x30, C_ALL, "idq.ms_uops"                                       , 0x0, ATTR_NONE, 0x0 }, \
1242 { 0x79, 0x30, C_ALL, "idq.ms_cycles"                                     , 0x1, ATTR_NONE, 0x0 }, \
1243 { 0x79, 0x18, C_ALL, "idq.all_dsb_uops"                                  , 0x0, ATTR_NONE, 0x0 }, \
1244 { 0x79, 0x18, C_ALL, "idq.all_dsb_cycles"                                , 0x1, ATTR_NONE, 0x0 }, \
1245 { 0x79, 0x24, C_ALL, "idq.all_mite_uops"                                 , 0x0, ATTR_NONE, 0x0 }, \
1246 { 0x79, 0x24, C_ALL, "idq.all_mite_cycles"                               , 0x1, ATTR_NONE, 0x0 }, \
1247 { 0x79, 0x3C, C_ALL, "idq.mite_all_uops"                                 , 0x0, ATTR_NONE, 0x0 }, \
1248 { 0x79, 0x3C, C_ALL, "idq.mite_all_cycles"                               , 0x1, ATTR_NONE, 0x0 }, \
1249 { 0x80, 0x02, C_ALL, "icache.misses"                                     , 0x0, ATTR_NONE, 0x0 }, \
1250 { 0x85, 0x01, C_ALL, "itlb_misses.miss_causes_a_walk"                    , 0x0, ATTR_NONE, 0x0 }, \
1251 { 0x85, 0x02, C_ALL, "itlb_misses.walk_completed"                        , 0x0, ATTR_NONE, 0x0 }, \
1252 { 0x85, 0x04, C_ALL, "itlb_misses.walk_duration"                         , 0x0, ATTR_NONE, 0x0 }, \
1253 { 0x85, 0x10, C_ALL, "itlb_misses.stlb_hit"                              , 0x0, ATTR_NONE, 0x0 }, \
1254 { 0x87, 0x01, C_ALL, "ild_stall.lcp"                                     , 0x0, ATTR_NONE, 0x0 }, \
1255 { 0x87, 0x04, C_ALL, "ild_stall.iq_full"                                 , 0x0, ATTR_NONE, 0x0 }, \
1256 { 0x88, 0x41, C_ALL, "br_inst_exec.nontaken_cond"                        , 0x0, ATTR_NONE, 0x0 }, \
1257 { 0x88, 0x81, C_ALL, "br_inst_exec.taken_cond"                           , 0x0, ATTR_NONE, 0x0 }, \
1258 { 0x88, 0x82, C_ALL, "br_inst_exec.taken_direct_jmp"                     , 0x0, ATTR_NONE, 0x0 }, \
1259 { 0x88, 0x84, C_ALL, "br_inst_exec.taken_indirect_jmp_non_call_ret"      , 0x0, ATTR_NONE, 0x0 }, \
1260 { 0x88, 0x88, C_ALL, "br_inst_exec.taken_return_near"                    , 0x0, ATTR_NONE, 0x0 }, \
1261 { 0x88, 0x90, C_ALL, "br_inst_exec.taken_direct_near_call"               , 0x0, ATTR_NONE, 0x0 }, \
1262 { 0x88, 0xA0, C_ALL, "br_inst_exec.taken_indirect_near_call"             , 0x0, ATTR_NONE, 0x0 }, \
1263 { 0x88, 0xC1, C_ALL, "br_inst_exec.all_cond"                             , 0x0, ATTR_NONE, 0x0 }, \
1264 { 0x88, 0xFF, C_ALL, "br_inst_exec.all_branches"                         , 0x0, ATTR_NONE, 0x0 }, \
1265 { 0x89, 0x41, C_ALL, "br_misp_exec.nontaken_cond"                        , 0x0, ATTR_NONE, 0x0 }, \
1266 { 0x89, 0x81, C_ALL, "br_misp_exec.taken_cond"                           , 0x0, ATTR_NONE, 0x0 }, \
1267 { 0x89, 0x84, C_ALL, "br_misp_exec.taken_indirect_jmp_non_call_ret"      , 0x0, ATTR_NONE, 0x0 }, \
1268 { 0x89, 0x88, C_ALL, "br_misp_exec.taken_return_near"                    , 0x0, ATTR_NONE, 0x0 }, \
1269 { 0x89, 0x90, C_ALL, "br_misp_exec.taken_direct_near_call"               , 0x0, ATTR_NONE, 0x0 }, \
1270 { 0x89, 0xA0, C_ALL, "br_misp_exec.taken_indirect_near_call"             , 0x0, ATTR_NONE, 0x0 }, \
1271 { 0x89, 0xC1, C_ALL, "br_misp_exec.all_cond"                             , 0x0, ATTR_NONE, 0x0 }, \
1272 { 0x89, 0xFF, C_ALL, "br_misp_exec.all_branches"                         , 0x0, ATTR_NONE, 0x0 }, \
1273 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.core"                       , 0x0, ATTR_NONE, 0x0 }, \
1274 { 0xA1, 0x01, C_ALL, "uops_dispatched_port.port_0"                       , 0x0, ATTR_NONE, 0x0 }, \
1275 { 0xA1, 0x02, C_ALL, "uops_dispatched_port.port_1"                       , 0x0, ATTR_NONE, 0x0 }, \
1276 { 0xA1, 0x04, C_ALL, "uops_dispatched_port.port_2_ld"                    , 0x0, ATTR_NONE, 0x0 }, \
1277 { 0xA1, 0x08, C_ALL, "uops_dispatched_port.port_2_sta"                   , 0x0, ATTR_NONE, 0x0 }, \
1278 { 0xA1, 0x0C, C_ALL, "uops_dispatched_port.port_2"                       , 0x0, ATTR_NONE, 0x0 }, \
1279 { 0xA1, 0x10, C_ALL, "uops_dispatched_port.port_3_ld"                    , 0x0, ATTR_NONE, 0x0 }, \
1280 { 0xA1, 0x20, C_ALL, "uops_dispatched_port.port_3_sta"                   , 0x0, ATTR_NONE, 0x0 }, \
1281 { 0xA1, 0x30, C_ALL, "uops_dispatched_port.port_3"                       , 0x0, ATTR_NONE, 0x0 }, \
1282 { 0xA1, 0x40, C_ALL, "uops_dispatched_port.port_4"                       , 0x0, ATTR_NONE, 0x0 }, \
1283 { 0xA1, 0x80, C_ALL, "uops_dispatched_port.port_5"                       , 0x0, ATTR_NONE, 0x0 }, \
1284 { 0xA2, 0x01, C_ALL, "resource_stalls.any"                               , 0x0, ATTR_NONE, 0x0 }, \
1285 { 0xA2, 0x02, C_ALL, "resource_stalls.lb"                                , 0x0, ATTR_NONE, 0x0 }, \
1286 { 0xA2, 0x04, C_ALL, "resource_stalls.rs"                                , 0x0, ATTR_NONE, 0x0 }, \
1287 { 0xA2, 0x08, C_ALL, "resource_stalls.sb"                                , 0x0, ATTR_NONE, 0x0 }, \
1288 { 0xA2, 0x10, C_ALL, "resource_stalls.rob"                               , 0x0, ATTR_NONE, 0x0 }, \
1289 { 0xA2, 0x20, C_ALL, "resource_stalls.fcsw"                              , 0x0, ATTR_NONE, 0x0 }, \
1290 { 0xA2, 0x40, C_ALL, "resource_stalls.mxcsr"                             , 0x0, ATTR_NONE, 0x0 }, \
1291 { 0xA2, 0x80, C_ALL, "resource_stalls.other"                             , 0x0, ATTR_NONE, 0x0 }, \
1292 { 0xA3, 0x02, C2   , "cycle_activity.cycles_l1d_pending"                 , 0x0, ATTR_NONE, 0x0 }, \
1293 { 0xA3, 0x01, C_ALL, "cycle_activity.cycles_l2_pending"                  , 0x0, ATTR_NONE, 0x0 }, \
1294 { 0xA3, 0x04, C0|C1|C2|C3, "cycle_activity.cycles_no_dispatch"           , 0x0, ATTR_NONE, 0x0 }, \
1295 { 0xAB, 0x01, C_ALL, "dsb2mite_switches.count"                           , 0x0, ATTR_NONE, 0x0 }, \
1296 { 0xAB, 0x02, C_ALL, "dsb2mite_switches.penalty_cycles"                  , 0x0, ATTR_NONE, 0x0 }, \
1297 { 0xAC, 0x02, C_ALL, "dsb_fill.other_cancel"                             , 0x0, ATTR_NONE, 0x0 }, \
1298 { 0xAC, 0x08, C_ALL, "dsb_fill.exceed_dsb_lines"                         , 0x0, ATTR_NONE, 0x0 }, \
1299 { 0xAC, 0x0A, C_ALL, "dsb_fill.all_cancel"                               , 0x0, ATTR_NONE, 0x0 }, \
1300 { 0xAE, 0x01, C_ALL, "itlb.itlb_flush"                                   , 0x0, ATTR_NONE, 0x0 }, \
1301 { 0xB0, 0x01, C_ALL, "offcore_requests.demand_data_rd"                   , 0x0, ATTR_NONE, 0x0 }, \
1302 { 0xB0, 0x04, C_ALL, "offcore_requests.demand_rfo"                       , 0x0, ATTR_NONE, 0x0 }, \
1303 { 0xB0, 0x08, C_ALL, "offcore_requests.all_data_rd"                      , 0x0, ATTR_NONE, 0x0 }, \
1304 { 0xB1, 0x01, C0|C1|C2|C3, "uops_dispatched.thread"                      , 0x0, ATTR_NONE, 0x0 }, \
1305 { 0xB1, 0x01, C0|C1|C2|C3, "uops_dispatched.stall_cycles"                , 0x1, ATTR_INV , 0x0 }, \
1306 { 0xB1, 0x02, C_ALL, "uops_dispatched.core"                              , 0x0, ATTR_NONE, 0x0 }, \
1307 { 0xB2, 0x01, C_ALL, "offcore_requests_buffer.sq_full"                   , 0x0, ATTR_NONE, 0x0 }, \
1308 { 0xB6, 0x01, C_ALL, "agu_bypass_cancel.count"                           , 0x0, ATTR_NONE, 0x0 }, \
1309 /* { 0xB7, 0x01, C_ALL, "off_core_response_0"                               , 0x0, ATTR_NONE, 0x1A6 }, ignore events that require msr_offset */ \
1310 /* { 0xBB, 0x01, C_ALL, "off_core_response_1"                               , 0x0, ATTR_NONE, 0x1A7 }, ignore events that require msr_offset */ \
1311 { 0xBD, 0x01, C_ALL, "tlb_flush.dtlb_thread"                             , 0x0, ATTR_NONE, 0x0 }, \
1312 { 0xBD, 0x20, C_ALL, "tlb_flush.stlb_any"                                , 0x0, ATTR_NONE, 0x0 }, \
1313 { 0xBF, 0x05, C_ALL, "l1d_blocks.bank_conflict_cycles"                   , 0x1, ATTR_NONE, 0x0 }, \
1314 { 0xC0, 0x00, C_ALL, "inst_retired.any_p"                                , 0x0, ATTR_NONE, 0x0 }, \
1315 { 0xC0, 0x01,    C1, "inst_retired.prec_dist"                            , 0x0, ATTR_NONE, 0x0 }, \
1316 { 0xC1, 0x02, C_ALL, "other_assists.itlb_miss_retired"                   , 0x0, ATTR_NONE, 0x0 }, \
1317 { 0xC1, 0x08, C_ALL, "other_assists.avx_store"                           , 0x0, ATTR_NONE, 0x0 }, \
1318 { 0xC1, 0x10, C_ALL, "other_assists.avx_to_sse"                          , 0x0, ATTR_NONE, 0x0 }, \
1319 { 0xC1, 0x20, C_ALL, "other_assists.sse_to_avx"                          , 0x0, ATTR_NONE, 0x0 }, \
1320 { 0xC2, 0x01, C_ALL, "uops_retired.all"                                  , 0x0, ATTR_NONE, 0x0 }, \
1321 { 0xC2, 0x01, C_ALL, "uops_retired.active_cycles"                        , 0x1, ATTR_NONE, 0x0 }, \
1322 { 0xC2, 0x01, C_ALL, "uops_retired.stall_cycles"                         , 0x1, ATTR_INV , 0x0 }, \
1323 { 0xC2, 0x02, C_ALL, "uops_retired.retire_slots"                         , 0x0, ATTR_NONE, 0x0 }, \
1324 { 0xC3, 0x02, C_ALL, "machine_clears.memory_ordering"                    , 0x0, ATTR_NONE, 0x0 }, \
1325 { 0xC3, 0x04, C_ALL, "machine_clears.smc"                                , 0x0, ATTR_NONE, 0x0 }, \
1326 { 0xC3, 0x20, C_ALL, "machine_clears.maskmov"                            , 0x0, ATTR_NONE, 0x0 }, \
1327 { 0xC4, 0x00, C_ALL, "br_inst_retired.all_branches"                      , 0x0, ATTR_NONE, 0x0 }, \
1328 { 0xC4, 0x01, C_ALL, "br_inst_retired.conditional"                       , 0x0, ATTR_NONE, 0x0 }, \
1329 { 0xC4, 0x02, C_ALL, "br_inst_retired.near_call"                         , 0x0, ATTR_NONE, 0x0 }, \
1330 { 0xC4, 0x04, C_ALL, "br_inst_retired.all_branches"                      , 0x0, ATTR_NONE, 0x0 }, \
1331 { 0xC4, 0x08, C_ALL, "br_inst_retired.near_return"                       , 0x0, ATTR_NONE, 0x0 }, \
1332 { 0xC4, 0x10, C_ALL, "br_inst_retired.not_taken"                         , 0x0, ATTR_NONE, 0x0 }, \
1333 { 0xC4, 0x20, C_ALL, "br_inst_retired.near_taken"                        , 0x0, ATTR_NONE, 0x0 }, \
1334 { 0xC4, 0x40, C_ALL, "br_inst_retired.far_branch"                        , 0x0, ATTR_NONE, 0x0 }, \
1335 { 0xC5, 0x00, C_ALL, "br_misp_retired.all_branches"                      , 0x0, ATTR_NONE, 0x0 }, \
1336 { 0xC5, 0x00, C_ALL, "br_misp_retired.all_branches"                      , 0x0, ATTR_NONE, 0x0 }, \
1337 { 0xC5, 0x01, C_ALL, "br_misp_retired.conditional"                       , 0x0, ATTR_NONE, 0x0 }, \
1338 { 0xC5, 0x02, C_ALL, "br_misp_retired.near_call"                         , 0x0, ATTR_NONE, 0x0 }, \
1339 { 0xC5, 0x04, C_ALL, "br_misp_retired.all_branches"                      , 0x0, ATTR_NONE, 0x0 }, \
1340 { 0xC5, 0x10, C_ALL, "br_misp_retired.not_taken"                         , 0x0, ATTR_NONE, 0x0 }, \
1341 { 0xC5, 0x20, C_ALL, "br_misp_retired.taken"                             , 0x0, ATTR_NONE, 0x0 }, \
1342 { 0xCA, 0x02, C_ALL, "fp_assist.x87_output"                              , 0x0, ATTR_NONE, 0x0 }, \
1343 { 0xCA, 0x04, C_ALL, "fp_assist.x87_input"                               , 0x0, ATTR_NONE, 0x0 }, \
1344 { 0xCA, 0x08, C_ALL, "fp_assist.simd_output"                             , 0x0, ATTR_NONE, 0x0 }, \
1345 { 0xCA, 0x10, C_ALL, "fp_assist.simd_input"                              , 0x0, ATTR_NONE, 0x0 }, \
1346 { 0xCA, 0x1E, C_ALL, "fp_assist.any"                                     , 0x0, ATTR_NONE, 0x0 }, \
1347 { 0xCC, 0x20, C_ALL, "rob_misc_events.lbr_inserts"                       , 0x0, ATTR_NONE, 0x0 }, \
1348 /* { 0xCD, 0x01, C3, "mem_trans_retired.load_latency"                    , 0x0, ATTR_NONE, 0x3F6 }, ignore events that require msr_offset */ /* See Section "MSR_PEBS_LD_LAT_THRESHOLD" */ \
1349 { 0xCD, 0x02,    C3, "mem_trans_retired.precise_store"                   , 0x0, ATTR_NONE, 0x0 }, /* See Section "Precise Store Facility" */ \
1350 { 0xD0, 0x11, C_ALL, "mem_uops_retired.stlb_miss_loads"                  , 0x0, ATTR_NONE, 0x0 }, \
1351 { 0xD0, 0x12, C_ALL, "mem_uops_retired.stlb_miss_stores"                 , 0x0, ATTR_NONE, 0x0 }, \
1352 { 0xD0, 0x21, C_ALL, "mem_uops_retired.lock_loads"                       , 0x0, ATTR_NONE, 0x0 }, \
1353 { 0xD0, 0x22, C_ALL, "mem_uops_retired.lock_stores"                      , 0x0, ATTR_NONE, 0x0 }, \
1354 { 0xD0, 0x41, C_ALL, "mem_uops_retired.split_loads"                      , 0x0, ATTR_NONE, 0x0 }, \
1355 { 0xD0, 0x42, C_ALL, "mem_uops_retired.split_stores"                     , 0x0, ATTR_NONE, 0x0 }, \
1356 { 0xD0, 0x81, C_ALL, "mem_uops_retired.all_loads"                        , 0x0, ATTR_NONE, 0x0 }, \
1357 { 0xD0, 0x82, C_ALL, "mem_uops_retired.all_stores"                       , 0x0, ATTR_NONE, 0x0 }, \
1358 { 0xD1, 0x01, C0|C1|C2|C3, "mem_load_uops_retired.l1_hit"                , 0x0, ATTR_NONE, 0x0 }, \
1359 { 0xD1, 0x02, C_ALL, "mem_load_uops_retired.l2_hit"                      , 0x0, ATTR_NONE, 0x0 }, \
1360 { 0xD1, 0x04, C_ALL, "mem_load_uops_retired.llc_hit"                     , 0x0, ATTR_NONE, 0x0 }, \
1361 { 0xD1, 0x20, C_ALL, "mem_load_uops_retired.llc_miss"                    , 0x0, ATTR_NONE, 0x0 }, \
1362 { 0xD1, 0x40, C_ALL, "mem_load_uops_retired.hit_lfb"                     , 0x0, ATTR_NONE, 0x0 }, \
1363 { 0xD2, 0x01, C_ALL, "mem_load_uops_llc_hit_retired.xsnp_miss"           , 0x0, ATTR_NONE, 0x0 }, \
1364 { 0xD2, 0x02, C_ALL, "mem_load_uops_llc_hit_retired.xsnp_hit"            , 0x0, ATTR_NONE, 0x0 }, \
1365 { 0xD2, 0x04, C_ALL, "mem_load_uops_llc_hit_retired.xsnp_hitm"           , 0x0, ATTR_NONE, 0x0 }, \
1366 { 0xD2, 0x08, C_ALL, "mem_load_uops_llc_hit_retired.xsnp_none"           , 0x0, ATTR_NONE, 0x0 }, \
1367 { 0xE6, 0x01, C_ALL, "baclears.any"                                      , 0x0, ATTR_NONE, 0x0 }, \
1368 { 0xF0, 0x01, C_ALL, "l2_trans.demand_data_rd"                           , 0x0, ATTR_NONE, 0x0 }, \
1369 { 0xF0, 0x02, C_ALL, "l2_trans.rfo"                                      , 0x0, ATTR_NONE, 0x0 }, \
1370 { 0xF0, 0x04, C_ALL, "l2_trans.code_rd"                                  , 0x0, ATTR_NONE, 0x0 }, \
1371 { 0xF0, 0x08, C_ALL, "l2_trans.all_pf"                                   , 0x0, ATTR_NONE, 0x0 }, \
1372 { 0xF0, 0x10, C_ALL, "l2_trans.l1d_wb"                                   , 0x0, ATTR_NONE, 0x0 }, \
1373 { 0xF0, 0x20, C_ALL, "l2_trans.l2_fill"                                  , 0x0, ATTR_NONE, 0x0 }, \
1374 { 0xF0, 0x40, C_ALL, "l2_trans.l2_wb"                                    , 0x0, ATTR_NONE, 0x0 }, \
1375 { 0xF0, 0x80, C_ALL, "l2_trans.all_requests"                             , 0x0, ATTR_NONE, 0x0 }, \
1376 { 0xF1, 0x01, C_ALL, "l2_lines_in.i"                                     , 0x0, ATTR_NONE, 0x0 }, \
1377 { 0xF1, 0x02, C_ALL, "l2_lines_in.s"                                     , 0x0, ATTR_NONE, 0x0 }, \
1378 { 0xF1, 0x04, C_ALL, "l2_lines_in.e"                                     , 0x0, ATTR_NONE, 0x0 }, \
1379 { 0xF1, 0x07, C_ALL, "l2_lines_in.all"                                   , 0x0, ATTR_NONE, 0x0 }, \
1380 { 0xF2, 0x01, C_ALL, "l2_lines_out.demand_clean"                         , 0x0, ATTR_NONE, 0x0 }, \
1381 { 0xF2, 0x02, C_ALL, "l2_lines_out.demand_dirty"                         , 0x0, ATTR_NONE, 0x0 }, \
1382 { 0xF2, 0x04, C_ALL, "l2_lines_out.pf_clean"                             , 0x0, ATTR_NONE, 0x0 }, \
1383 { 0xF2, 0x08, C_ALL, "l2_lines_out.pf_dirty"                             , 0x0, ATTR_NONE, 0x0 }, \
1384 { 0xF2, 0x0A, C_ALL, "l2_lines_out.dirty_all"                            , 0x0, ATTR_NONE, 0x0 }, \
1385 { 0xF4, 0x10, C_ALL, "sq_misc.split_lock"                                , 0x0, ATTR_NONE, 0x0 }, \
1386 /* end of #define */
1387
1388 #define EVENTS_FAM6_MOD42_ONLY \
1389 { 0xD4, 0x02, C0|C1|C2|C3, "mem_load_uops_misc_retired.llc_miss"         , 0x0, ATTR_NONE, 0x0 }, \
1390 /* end of #define */
1391
1392 #define EVENTS_FAM6_MOD45_ONLY \
1393 /* { 0xD3, 0x01, C_ALL, "mem_load_uops_llc_miss_retired.local_dram"   , 0x0, ATTR_NONE, 0x3C9 }, ignore events that require msr_offset */ \
1394 /* { 0xD3, 0x04, C_ALL, "mem_load_uops_llc_miss_retired.remote_dram"  , 0x0, ATTR_NONE, 0x3C9 }, ignore events that require msr_offset */ \
1395 /* end of #define */
1396
1397 /* Intel Ivy Bridge Processor */
1398 /*
1399  * The Ivy Bridge tables are basically from Bug 16457100
1400  *   libcpc counter names should be based on public Intel documentation -- Ivy Bridge
1401  * and those tables are basically from the
1402  * Intel SDM, January 2013, Section 19.3, Table 19-5.
1403  * Additionally, there is
1404  *   Table 19-6.  Model 62 only.
1405  */
1406
1407 #define EVENTS_FAM6_MOD58 \
1408 { 0x03, 0x02, C_ALL, "ld_blocks.store_forward"                           , 0x0, ATTR_NONE, 0x0 }, \
1409 { 0x05, 0x01, C_ALL, "misalign_mem_ref.loads"                            , 0x0, ATTR_NONE, 0x0 }, \
1410 { 0x05, 0x02, C_ALL, "misalign_mem_ref.stores"                           , 0x0, ATTR_NONE, 0x0 }, \
1411 { 0x07, 0x01, C_ALL, "ld_blocks_partial.address_alias"                   , 0x0, ATTR_NONE, 0x0 }, \
1412 { 0x08, 0x81, C_ALL, "dtlb_load_misses.miss_causes_a_walk"               , 0x0, ATTR_NONE, 0x0 }, \
1413 { 0x08, 0x82, C_ALL, "dtlb_load_misses.walk_completed"                   , 0x0, ATTR_NONE, 0x0 }, \
1414 { 0x08, 0x84, C_ALL, "dtlb_load_misses.walk_duration"                    , 0x0, ATTR_NONE, 0x0 }, \
1415 { 0x0E, 0x01, C_ALL, "uops_issued.any"                                   , 0x0, ATTR_NONE, 0x0 }, \
1416 { 0x0E, 0x01, C_ALL, "uops_issued.stall_cycles"                          , 0x1, ATTR_INV , 0x0 }, \
1417 { 0x0E, 0x01, C_ALL, "uops_issued.core_stall_cycles"                     , 0x1, ATTR_INV | ATTR_ANY, 0x0 }, \
1418 { 0x0E, 0x10, C_ALL, "uops_issued.flags_merge"                           , 0x0, ATTR_NONE, 0x0 }, \
1419 { 0x0E, 0x20, C_ALL, "uops_issued.slow_lea"                              , 0x0, ATTR_NONE, 0x0 }, \
1420 { 0x0E, 0x40, C_ALL, "uops_issued.sIngle_mul"                            , 0x0, ATTR_NONE, 0x0 }, \
1421 { 0x10, 0x01, C_ALL, "fp_comp_ops_exe.x87"                               , 0x0, ATTR_NONE, 0x0 }, \
1422 { 0x10, 0x10, C_ALL, "fp_comp_ops_exe.sse_fp_packed_double"              , 0x0, ATTR_NONE, 0x0 }, \
1423 { 0x10, 0x20, C_ALL, "fp_comp_ops_exe.sse_fp_scalar_single"              , 0x0, ATTR_NONE, 0x0 }, \
1424 { 0x10, 0x40, C_ALL, "fp_comp_ops_exe.sse_packed_single"                 , 0x0, ATTR_NONE, 0x0 }, \
1425 { 0x10, 0x80, C_ALL, "fp_comp_ops_exe.sse_scalar_double"                 , 0x0, ATTR_NONE, 0x0 }, \
1426 { 0x11, 0x01, C_ALL, "simd_fp_256.packed_single"                         , 0x0, ATTR_NONE, 0x0 }, \
1427 { 0x11, 0x02, C_ALL, "simd_fp_256.packed_double"                         , 0x0, ATTR_NONE, 0x0 }, \
1428 { 0x14, 0x01, C_ALL, "arith.fpu_div_active"                              , 0x0, ATTR_NONE, 0x0 }, \
1429 { 0x14, 0x01, C_ALL, "arith.fpu_div"                                     , 0x1, ATTR_EDGE, 0x0 }, \
1430 { 0x24, 0x01, C_ALL, "l2_rqsts.demand_data_rd_hit"                       , 0x0, ATTR_NONE, 0x0 }, \
1431 { 0x24, 0x03, C_ALL, "l2_rqsts.all_demand_data_rd"                       , 0x0, ATTR_NONE, 0x0 }, \
1432 { 0x24, 0x04, C_ALL, "l2_rqsts.rfo_hits"                                 , 0x0, ATTR_NONE, 0x0 }, \
1433 { 0x24, 0x08, C_ALL, "l2_rqsts.rfo_miss"                                 , 0x0, ATTR_NONE, 0x0 }, \
1434 { 0x24, 0x0C, C_ALL, "l2_rqsts.all_rfo"                                  , 0x0, ATTR_NONE, 0x0 }, \
1435 { 0x24, 0x10, C_ALL, "l2_rqsts.code_rd_hit"                              , 0x0, ATTR_NONE, 0x0 }, \
1436 { 0x24, 0x20, C_ALL, "l2_rqsts.code_rd_miss"                             , 0x0, ATTR_NONE, 0x0 }, \
1437 { 0x24, 0x30, C_ALL, "l2_rqsts.all_code_rd"                              , 0x0, ATTR_NONE, 0x0 }, \
1438 { 0x24, 0x40, C_ALL, "l2_rqsts.pf_hit"                                   , 0x0, ATTR_NONE, 0x0 }, \
1439 { 0x24, 0x80, C_ALL, "l2_rqsts.pf_miss"                                  , 0x0, ATTR_NONE, 0x0 }, \
1440 { 0x24, 0xC0, C_ALL, "l2_rqsts.all_pf"                                   , 0x0, ATTR_NONE, 0x0 }, \
1441 { 0x27, 0x01, C_ALL, "l2_store_lock_rqsts.miss"                          , 0x0, ATTR_NONE, 0x0 }, \
1442 { 0x27, 0x08, C_ALL, "l2_store_lock_rqsts.hit_m"                         , 0x0, ATTR_NONE, 0x0 }, \
1443 { 0x27, 0x0F, C_ALL, "l2_store_lock_rqsts.all"                           , 0x0, ATTR_NONE, 0x0 }, \
1444 { 0x28, 0x01, C_ALL, "l2_l1d_wb_rqsts.miss"                              , 0x0, ATTR_NONE, 0x0 }, \
1445 { 0x28, 0x04, C_ALL, "l2_l1d_wb_rqsts.hit_e"                             , 0x0, ATTR_NONE, 0x0 }, \
1446 { 0x28, 0x08, C_ALL, "l2_l1d_wb_rqsts.hit_m"                             , 0x0, ATTR_NONE, 0x0 }, \
1447 { 0x28, 0x0F, C_ALL, "l2_l1d_wb_rqsts.all"                               , 0x0, ATTR_NONE, 0x0 }, \
1448 { 0x2E, 0x41, C_ALL, "longest_lat_cache.miss"                            , 0x0, ATTR_NONE, 0x0 }, \
1449 { 0x2E, 0x4F, C_ALL, "longest_lat_cache.reference"                       , 0x0, ATTR_NONE, 0x0 }, \
1450 { 0x3C, 0x00, C_ALL, "cpu_clk_unhalted.thread_p"                         , 0x0, ATTR_NONE, 0x0 }, \
1451 { 0x3C, 0x01, C_ALL, "cpu_clk_thread_unhalted.ref_xclk"                  , 0x0, ATTR_NONE, 0x0 }, \
1452 { 0x48, 0x01, C(2), "l1d_pend_miss.pending"                              , 0x0, ATTR_NONE, 0x0 }, \
1453 { 0x48, 0x01, C(2), "l1d_pend_miss.pending_cycles"                       , 0x1, ATTR_NONE, 0x0 }, \
1454 { 0x48, 0x01, C(2), "l1d_pend_miss.occurrences"                          , 0x1, ATTR_EDGE, 0x0 }, \
1455 { 0x49, 0x01, C_ALL, "dtlb_store_misses.miss_causes_a_walk"              , 0x0, ATTR_NONE, 0x0 }, \
1456 { 0x49, 0x02, C_ALL, "dtlb_store_misses.walk_completed"                  , 0x0, ATTR_NONE, 0x0 }, \
1457 { 0x49, 0x04, C_ALL, "dtlb_store_misses.walk_duration"                   , 0x0, ATTR_NONE, 0x0 }, \
1458 { 0x49, 0x10, C_ALL, "dtlb_store_misses.stlb_hit"                        , 0x0, ATTR_NONE, 0x0 }, \
1459 { 0x4C, 0x01, C_ALL, "load_hit_pre.sw_pf"                                , 0x0, ATTR_NONE, 0x0 }, \
1460 { 0x4C, 0x02, C_ALL, "load_hit_pre.hw_pf"                                , 0x0, ATTR_NONE, 0x0 }, \
1461 { 0x51, 0x01, C_ALL, "l1d.replacement"                                   , 0x0, ATTR_NONE, 0x0 }, \
1462 { 0x58, 0x04, C_ALL, "move_elimination.int_not_eliminated"               , 0x0, ATTR_NONE, 0x0 }, \
1463 { 0x58, 0x08, C_ALL, "move_elimination.simd_not_eliminated"              , 0x0, ATTR_NONE, 0x0 }, \
1464 { 0x58, 0x01, C_ALL, "move_elimination.int_eliminated"                   , 0x0, ATTR_NONE, 0x0 }, \
1465 { 0x58, 0x02, C_ALL, "move_elimination.simd_eliminated"                  , 0x0, ATTR_NONE, 0x0 }, \
1466 { 0x5C, 0x01, C_ALL, "cpl_cycles.ring0"                                  , 0x0, ATTR_NONE, 0x0 }, \
1467 { 0x5C, 0x01, C_ALL, "cpl_cycles.ring0_trans"                            , 0x0, ATTR_EDGE, 0x0 }, \
1468 { 0x5C, 0x02, C_ALL, "cpl_cycles.ring123"                                , 0x0, ATTR_NONE, 0x0 }, \
1469 { 0x5E, 0x01, C_ALL, "rs_events.empty_cycles"                            , 0x0, ATTR_NONE, 0x0 }, \
1470 { 0x5F, 0x04, C_ALL, "dtlb_load_misses.stlb_hit"                         , 0x0, ATTR_NONE, 0x0 }, \
1471 { 0x60, 0x01, C_ALL, "offcore_requests_outstanding.demand_data_rd"       , 0x0, ATTR_NONE, 0x0 }, \
1472 { 0x60, 0x01, C_ALL, "offcore_requests_outstanding.demand_data_rd_cycles", 0x1, ATTR_NONE, 0x0 }, \
1473 { 0x60, 0x02, C_ALL, "offcore_requests_outstanding.demand_code_rd"       , 0x0, ATTR_NONE, 0x0 }, \
1474 { 0x60, 0x02, C_ALL, "offcore_requests_outstanding.demand_code_rd_cycles", 0x1, ATTR_NONE, 0x0 }, \
1475 { 0x60, 0x04, C_ALL, "offcore_requests_outstanding.demand_rfo"           , 0x0, ATTR_NONE, 0x0 }, \
1476 { 0x60, 0x04, C_ALL, "offcore_requests_outstanding.demand_rfo_cycles"    , 0x1, ATTR_NONE, 0x0 }, \
1477 { 0x60, 0x08, C_ALL, "offcore_requests_outstanding.all_data_rd"          , 0x0, ATTR_NONE, 0x0 }, \
1478 { 0x60, 0x08, C_ALL, "offcore_requests_outstanding.all_data_rd_cycles"   , 0x1, ATTR_NONE, 0x0 }, \
1479 { 0x63, 0x01, C_ALL, "lock_cycles.split_lock_uc_lock_duration"           , 0x0, ATTR_NONE, 0x0 }, \
1480 { 0x63, 0x02, C_ALL, "lock_cycles.cache_lock_duration"                   , 0x0, ATTR_NONE, 0x0 }, \
1481 { 0x79, 0x02, C_ALL, "idq.empty"                                         , 0x0, ATTR_NONE, 0x0 }, \
1482 { 0x79, 0x04, C_ALL, "idq.mite_uops"                                     , 0x0, ATTR_NONE, 0x0 }, \
1483 { 0x79, 0x04, C_ALL, "idq.mite_cycles"                                   , 0x1, ATTR_NONE, 0x0 }, \
1484 { 0x79, 0x08, C_ALL, "idq.dsb_uops"                                      , 0x0, ATTR_NONE, 0x0 }, \
1485 { 0x79, 0x08, C_ALL, "idq.dsb_cycles"                                    , 0x1, ATTR_NONE, 0x0 }, \
1486 { 0x79, 0x10, C_ALL, "idq.ms_dsb_uops"                                   , 0x0, ATTR_NONE, 0x0 }, \
1487 { 0x79, 0x10, C_ALL, "idq.ms_dsb_cycles"                                 , 0x1, ATTR_NONE, 0x0 }, \
1488 { 0x79, 0x10, C_ALL, "idq.ms_dsb_activations"                            , 0x1, ATTR_EDGE, 0x0 }, \
1489 { 0x79, 0x18, C_ALL, "idq.all_dsb_uops"                                  , 0x0, ATTR_NONE, 0x0 }, \
1490 { 0x79, 0x18, C_ALL, "idq.all_dsb_cycles"                                , 0x1, ATTR_NONE, 0x0 }, \
1491 { 0x79, 0x18, C_ALL, "idq.all_dsb_cycles_any_uops" /* synonym, from Intel SDM */   , 0x1, ATTR_NONE, 0x0 }, \
1492 { 0x79, 0x18, C_ALL, "idq.all_dsb_cycles_4_uops"                         , 0x4, ATTR_NONE, 0x0 }, \
1493 { 0x79, 0x20, C_ALL, "idq.ms_mite_cycles"                                , 0x0, ATTR_NONE, 0x0 }, \
1494 { 0x79, 0x20, C_ALL, "idq.ms_mite_cycles"                                , 0x1, ATTR_NONE, 0x0 }, \
1495 { 0x79, 0x24, C_ALL, "idq.all_mite_uops"                                 , 0x0, ATTR_NONE, 0x0 }, \
1496 { 0x79, 0x24, C_ALL, "idq.all_mite_cycles"                               , 0x1, ATTR_NONE, 0x0 }, \
1497 { 0x79, 0x24, C_ALL, "idq.all_mite_cycles_any_uops" /* synonym, from Intel SDM */  , 0x1, ATTR_NONE, 0x0 }, \
1498 { 0x79, 0x24, C_ALL, "idq.all_mite_cycles_4_uops"                        , 0x4, ATTR_NONE, 0x0 }, \
1499 { 0x79, 0x30, C_ALL, "idq.ms_uops"                                       , 0x0, ATTR_NONE, 0x0 }, \
1500 { 0x79, 0x30, C_ALL, "idq.ms_cycles"                                     , 0x1, ATTR_NONE, 0x0 }, \
1501 { 0x79, 0x3C, C_ALL, "idq.mite_all_uops"  /* weird name suggested by Intel docs */   , 0x0, ATTR_NONE, 0x0 }, \
1502 { 0x79, 0x3C, C_ALL, "idq.mite_all_cycles"                               , 0x1, ATTR_NONE, 0x0 }, \
1503 { 0x80, 0x02, C_ALL, "icache.misses"                                     , 0x0, ATTR_NONE, 0x0 }, \
1504 { 0x85, 0x01, C_ALL, "itlb_misses.miss_causes_a_walk"                    , 0x0, ATTR_NONE, 0x0 }, \
1505 { 0x85, 0x02, C_ALL, "itlb_misses.walk_completed"                        , 0x0, ATTR_NONE, 0x0 }, \
1506 { 0x85, 0x04, C_ALL, "itlb_misses.walk_duration"                         , 0x0, ATTR_NONE, 0x0 }, \
1507 { 0x85, 0x10, C_ALL, "itlb_misses.stlb_hit"                              , 0x0, ATTR_NONE, 0x0 }, \
1508 { 0x87, 0x01, C_ALL, "ild_stall.lcp"                                     , 0x0, ATTR_NONE, 0x0 }, \
1509 { 0x87, 0x04, C_ALL, "ild_stall.iq_full"                                 , 0x0, ATTR_NONE, 0x0 }, \
1510 { 0x88, 0x41, C_ALL, "br_inst_exec.nontaken_cond"                        , 0x0, ATTR_NONE, 0x0 }, \
1511 { 0x88, 0x81, C_ALL, "br_inst_exec.taken_cond"                           , 0x0, ATTR_NONE, 0x0 }, \
1512 { 0x88, 0x82, C_ALL, "br_inst_exec.taken_direct_jmp"                     , 0x0, ATTR_NONE, 0x0 }, \
1513 { 0x88, 0x84, C_ALL, "br_inst_exec.taken_indirect_jmp_non_call_ret"      , 0x0, ATTR_NONE, 0x0 }, \
1514 { 0x88, 0x88, C_ALL, "br_inst_exec.taken_return_near"                    , 0x0, ATTR_NONE, 0x0 }, \
1515 { 0x88, 0x90, C_ALL, "br_inst_exec.taken_direct_near_call"               , 0x0, ATTR_NONE, 0x0 }, \
1516 { 0x88, 0xA0, C_ALL, "br_inst_exec.taken_indirect_near_call"             , 0x0, ATTR_NONE, 0x0 }, \
1517 { 0x88, 0xFF, C_ALL, "br_inst_exec.all_branches"                         , 0x0, ATTR_NONE, 0x0 }, \
1518 { 0x89, 0x41, C_ALL, "br_misp_exec.nontaken_cond"                        , 0x0, ATTR_NONE, 0x0 }, \
1519 { 0x89, 0x81, C_ALL, "br_misp_exec.taken_cond"                           , 0x0, ATTR_NONE, 0x0 }, \
1520 { 0x89, 0x84, C_ALL, "br_misp_exec.taken_indirect_jmp_non_call_ret"      , 0x0, ATTR_NONE, 0x0 }, \
1521 { 0x89, 0x88, C_ALL, "br_misp_exec.taken_return_near"                    , 0x0, ATTR_NONE, 0x0 }, \
1522 { 0x89, 0x90, C_ALL, "br_misp_exec.taken_direct_near_call"               , 0x0, ATTR_NONE, 0x0 }, \
1523 { 0x89, 0xA0, C_ALL, "br_misp_exec.taken_indirect_near_call"             , 0x0, ATTR_NONE, 0x0 }, \
1524 { 0x89, 0xFF, C_ALL, "br_misp_exec.all_branches"                         , 0x0, ATTR_NONE, 0x0 }, \
1525 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.core"                       , 0x0, ATTR_NONE, 0x0 }, \
1526 { 0xA1, 0x01, C_ALL, "uops_dispatched_port.port_0"                       , 0x0, ATTR_NONE, 0x0 }, \
1527 { 0xA1, 0x02, C_ALL, "uops_dispatched_port.port_1"                       , 0x0, ATTR_NONE, 0x0 }, \
1528 { 0xA1, 0x04, C_ALL, "uops_dispatched_port.port_2_ld"                    , 0x0, ATTR_NONE, 0x0 }, \
1529 { 0xA1, 0x08, C_ALL, "uops_dispatched_port.port_2_sta"                   , 0x0, ATTR_NONE, 0x0 }, \
1530 { 0xA1, 0x0C, C_ALL, "uops_dispatched_port.port_2"                       , 0x0, ATTR_NONE, 0x0 }, \
1531 { 0xA1, 0x10, C_ALL, "uops_dispatched_port.port_3_ld"                    , 0x0, ATTR_NONE, 0x0 }, \
1532 { 0xA1, 0x20, C_ALL, "uops_dispatched_port.port_3_sta"                   , 0x0, ATTR_NONE, 0x0 }, \
1533 { 0xA1, 0x30, C_ALL, "uops_dispatched_port.port_3"                       , 0x0, ATTR_NONE, 0x0 }, \
1534 { 0xA1, 0x40, C_ALL, "uops_dispatched_port.port_4"                       , 0x0, ATTR_NONE, 0x0 }, \
1535 { 0xA1, 0x80, C_ALL, "uops_dispatched_port.port_5"                       , 0x0, ATTR_NONE, 0x0 }, \
1536 { 0xA2, 0x01, C_ALL, "resource_stalls.any"                               , 0x0, ATTR_NONE, 0x0 }, \
1537 { 0xA2, 0x04, C_ALL, "resource_stalls.rs"                                , 0x0, ATTR_NONE, 0x0 }, \
1538 { 0xA2, 0x08, C_ALL, "resource_stalls.sb"                                , 0x0, ATTR_NONE, 0x0 }, \
1539 { 0xA2, 0x10, C_ALL, "resource_stalls.rob"                               , 0x0, ATTR_NONE, 0x0 }, \
1540 { 0xA3, 0x01, C_ALL, "cycle_activity.cycles_l2_pending"                  , 0x0, ATTR_NONE, 0x0 }, \
1541 { 0xA3, 0x01, C_ALL, "cycle_activity.cycles_l2_pending_core"             , 0x0, ATTR_ANY , 0x0 }, \
1542 { 0xA3, 0x02, C0|C1|C2|C3, "cycle_activity.cycles_ldm_pending"           , 0x0, ATTR_NONE, 0x0 }, \
1543 { 0xA3, 0x02, C0|C1|C2|C3, "cycle_activity.cycles_ldm_pending_core"      , 0x0, ATTR_ANY , 0x0 }, \
1544 { 0xA3, 0x08, C(2), "cycle_activity.cycles_l1d_pending"                  , 0x0, ATTR_NONE, 0x0 }, \
1545 { 0xA3, 0x08, C(2), "cycle_activity.cycles_l1d_pending_core"             , 0x0, ATTR_ANY , 0x0 }, \
1546 { 0xA3, 0x04, C_ALL, "cycle_activity.cycles_no_execute"                  , 0x0, ATTR_NONE, 0x0 }, \
1547 { 0xA3, 0x04, C_ALL, "cycle_activity.cycles_no_execute_core"             , 0x0, ATTR_ANY , 0x0 }, \
1548 { 0xAB, 0x01, C_ALL, "dsb2mite_switches.count"                           , 0x0, ATTR_NONE, 0x0 }, \
1549 { 0xAB, 0x02, C_ALL, "dsb2mite_switches.penalty_cycles"                  , 0x0, ATTR_NONE, 0x0 }, \
1550 { 0xAC, 0x08, C_ALL, "dsb_fill.exceed_dsb_lines"                         , 0x0, ATTR_NONE, 0x0 }, \
1551 { 0xAE, 0x01, C_ALL, "itlb.itlb_flush"                                   , 0x0, ATTR_NONE, 0x0 }, \
1552 { 0xB0, 0x01, C_ALL, "offcore_requests.demand_data_rd"                   , 0x0, ATTR_NONE, 0x0 }, \
1553 { 0xB0, 0x02, C_ALL, "offcore_requests.demand_code_rd"                   , 0x0, ATTR_NONE, 0x0 }, \
1554 { 0xB0, 0x04, C_ALL, "offcore_requests.demand_rfo"                       , 0x0, ATTR_NONE, 0x0 }, \
1555 { 0xB0, 0x08, C_ALL, "offcore_requests.all_data_rd"                      , 0x0, ATTR_NONE, 0x0 }, \
1556 { 0xB1, 0x01, C_ALL, "uops_executed.thread"                              , 0x0, ATTR_NONE, 0x0 }, \
1557 { 0xB1, 0x01, C_ALL, "uops_executed.stall_cycles"                        , 0x1, ATTR_INV , 0x0 }, \
1558 { 0xB1, 0x02, C_ALL, "uops_executed.core"                                , 0x0, ATTR_NONE, 0x0 }, \
1559 /* { 0xB7, 0x01, C_ALL, "offcore_response_0"                             , 0x0, ATTR_NONE, 0x1A6 }, ignore events that require msr_offset */ \
1560 /* { 0xBB, 0x01, C_ALL, "offcore_response_1"                             , 0x0, ATTR_NONE, 0x1A7 }, ignore events that require msr_offset */ \
1561 { 0xBD, 0x01, C_ALL, "tlb_flush.dtlb_thread"                             , 0x0, ATTR_NONE, 0x0 }, \
1562 { 0xBD, 0x20, C_ALL, "tlb_flush.stlb_any"                                , 0x0, ATTR_NONE, 0x0 }, \
1563 { 0xC0, 0x00, C_ALL, "inst_retired.any_p"                                , 0x0, ATTR_NONE, 0x0 }, \
1564 { 0xC0, 0x01, C(1), "inst_retired.prec_dist"                             , 0x0, ATTR_NONE, 0x0 }, \
1565 { 0xC1, 0x08, C_ALL, "other_assists.avx_store"                           , 0x0, ATTR_NONE, 0x0 }, \
1566 { 0xC1, 0x10, C_ALL, "other_assists.avx_to_sse"                          , 0x0, ATTR_NONE, 0x0 }, \
1567 { 0xC1, 0x20, C_ALL, "other_assists.sse_to_avx"                          , 0x0, ATTR_NONE, 0x0 }, \
1568 { 0xC2, 0x01, C_ALL, "uops_retired.all"                                  , 0x0, ATTR_NONE, 0x0 }, \
1569 { 0xC2, 0x01, C_ALL, "uops_retired.active_cycles"                        , 0x1, ATTR_NONE, 0x0 }, \
1570 { 0xC2, 0x01, C_ALL, "uops_retired.stall_cycles"                         , 0x1, ATTR_INV , 0x0 }, \
1571 { 0xC2, 0x02, C_ALL, "uops_retired.retire_slots"                         , 0x0, ATTR_NONE, 0x0 }, \
1572 { 0xC3, 0x02, C_ALL, "machine_clears.memory_ordering"                    , 0x0, ATTR_NONE, 0x0 }, \
1573 { 0xC3, 0x04, C_ALL, "machine_clears.smc"                                , 0x0, ATTR_NONE, 0x0 }, \
1574 { 0xC3, 0x20, C_ALL, "machine_clears.maskmov"                            , 0x0, ATTR_NONE, 0x0 }, \
1575 { 0xC4, 0x00, C_ALL, "br_inst_retired.all_branches"                      , 0x0, ATTR_NONE, 0x0 }, \
1576 { 0xC4, 0x01, C_ALL, "br_inst_retired.conditional"                       , 0x0, ATTR_NONE, 0x0 }, \
1577 { 0xC4, 0x02, C_ALL, "br_inst_retired.near_call"                         , 0x0, ATTR_NONE, 0x0 }, \
1578 { 0xC4, 0x04, C_ALL, "br_inst_retired.all_branches"                      , 0x0, ATTR_NONE, 0x0 }, \
1579 { 0xC4, 0x08, C_ALL, "br_inst_retired.near_return"                       , 0x0, ATTR_NONE, 0x0 }, \
1580 { 0xC4, 0x10, C_ALL, "br_inst_retired.not_taken"                         , 0x0, ATTR_NONE, 0x0 }, \
1581 { 0xC4, 0x20, C_ALL, "br_inst_retired.near_taken"                        , 0x0, ATTR_NONE, 0x0 }, \
1582 { 0xC4, 0x40, C_ALL, "br_inst_retired.far_branch"                        , 0x0, ATTR_NONE, 0x0 }, \
1583 { 0xC5, 0x00, C_ALL, "br_misp_retired.all_branches"                      , 0x0, ATTR_NONE, 0x0 }, \
1584 { 0xC5, 0x01, C_ALL, "br_misp_retired.conditional"                       , 0x0, ATTR_NONE, 0x0 }, \
1585 { 0xC5, 0x02, C_ALL, "br_misp_retired.near_call"                         , 0x0, ATTR_NONE, 0x0 }, \
1586 { 0xC5, 0x04, C_ALL, "br_misp_retired.all_branches"                      , 0x0, ATTR_NONE, 0x0 }, \
1587 { 0xC5, 0x10, C_ALL, "br_misp_retired.not_taken"                         , 0x0, ATTR_NONE, 0x0 }, \
1588 { 0xC5, 0x20, C_ALL, "br_misp_retired.taken"                             , 0x0, ATTR_NONE, 0x0 }, \
1589 { 0xCA, 0x02, C_ALL, "fp_assist.x87_output"                              , 0x0, ATTR_NONE, 0x0 }, \
1590 { 0xCA, 0x04, C_ALL, "fp_assist.x87_input"                               , 0x0, ATTR_NONE, 0x0 }, \
1591 { 0xCA, 0x08, C_ALL, "fp_assist.simd_output"                             , 0x0, ATTR_NONE, 0x0 }, \
1592 { 0xCA, 0x10, C_ALL, "fp_assist.simd_input"                              , 0x0, ATTR_NONE, 0x0 }, \
1593 { 0xCA, 0x1E, C_ALL, "fp_assist.any"                                     , 0x0, ATTR_NONE, 0x0 }, \
1594 { 0xCC, 0x20, C_ALL, "rob_misc_events.lbr_inserts"                       , 0x0, ATTR_NONE, 0x0 }, \
1595 /* { 0xCD, 0x01, C3   , "mem_trans_retired.load_latency"                    , 0x0, ATTR_NONE, 0x3F6 }, ignore events that require msr_offset */ /* See Section "MSR_PEBS_LD_LAT_THRESHOLD" */ \
1596 { 0xCD, 0x02, C3   , "mem_trans_retired.precise_store"                   , 0x0, ATTR_NONE, 0x0 }, /* See Section "Precise Store Facility" */ \
1597 { 0xD0, 0x11, C_ALL, "mem_uops_retired.stlb_miss_loads"                  , 0x0, ATTR_NONE, 0x0 }, \
1598 { 0xD0, 0x12, C_ALL, "mem_uops_retired.stlb_miss_stores"                 , 0x0, ATTR_NONE, 0x0 }, \
1599 { 0xD0, 0x21, C_ALL, "mem_uops_retired.lock_loads"                       , 0x0, ATTR_NONE, 0x0 }, \
1600 { 0xD0, 0x22, C_ALL, "mem_uops_retired.lock_stores"                      , 0x0, ATTR_NONE, 0x0 }, \
1601 { 0xD0, 0x41, C_ALL, "mem_uops_retired.split_loads"                      , 0x0, ATTR_NONE, 0x0 }, \
1602 { 0xD0, 0x42, C_ALL, "mem_uops_retired.split_stores"                     , 0x0, ATTR_NONE, 0x0 }, \
1603 { 0xD0, 0x81, C_ALL, "mem_uops_retired.all_loads"                        , 0x0, ATTR_NONE, 0x0 }, \
1604 { 0xD0, 0x82, C_ALL, "mem_uops_retired.all_stores"                       , 0x0, ATTR_NONE, 0x0 }, \
1605 { 0xD1, 0x01, C_ALL, "mem_load_uops_retired.l1_hit"                      , 0x0, ATTR_NONE, 0x0 }, \
1606 { 0xD1, 0x02, C_ALL, "mem_load_uops_retired.l2_hit"                      , 0x0, ATTR_NONE, 0x0 }, \
1607 { 0xD1, 0x04, C_ALL, "mem_load_uops_retired.llc_hit"                     , 0x0, ATTR_NONE, 0x0 }, \
1608 { 0xD1, 0x08, C_ALL, "mem_load_uops_retired.l1_miss"                     , 0x0, ATTR_PEBS, 0x0 }, \
1609 { 0xD1, 0x10, C_ALL, "mem_load_uops_retired.l2_miss"                     , 0x0, ATTR_PEBS, 0x0 }, \
1610 { 0xD1, 0x20, C_ALL, "mem_load_uops_retired.llc_miss"                    , 0x0, ATTR_NONE, 0x0 }, \
1611 { 0xD1, 0x40, C_ALL, "mem_load_uops_retired.hit_lfb"                     , 0x0, ATTR_NONE, 0x0 }, \
1612 { 0xD2, 0x01, C_ALL, "mem_load_uops_llc_hit_retired.xsnp_miss"           , 0x0, ATTR_NONE, 0x0 }, \
1613 { 0xD2, 0x02, C_ALL, "mem_load_uops_llc_hit_retired.xsnp_hit"            , 0x0, ATTR_NONE, 0x0 }, \
1614 { 0xD2, 0x04, C_ALL, "mem_load_uops_llc_hit_retired.xsnp_hitm"           , 0x0, ATTR_NONE, 0x0 }, \
1615 { 0xD2, 0x08, C_ALL, "mem_load_uops_llc_hit_retired.xsnp_none"           , 0x0, ATTR_NONE, 0x0 }, \
1616 { 0xD3, 0x01, C_ALL, "mem_load_uops_llc_miss_retired.local_dram"         , 0x0, ATTR_NONE, 0x0 }, \
1617 { 0xE6, 0x1F, C_ALL, "baclears.any"                                      , 0x0, ATTR_NONE, 0x0 }, \
1618 { 0xF0, 0x01, C_ALL, "l2_trans.demand_data_rd"                           , 0x0, ATTR_NONE, 0x0 }, \
1619 { 0xF0, 0x02, C_ALL, "l2_trans.rfo"                                      , 0x0, ATTR_NONE, 0x0 }, \
1620 { 0xF0, 0x04, C_ALL, "l2_trans.code_rd"                                  , 0x0, ATTR_NONE, 0x0 }, \
1621 { 0xF0, 0x08, C_ALL, "l2_trans.all_pf"                                   , 0x0, ATTR_NONE, 0x0 }, \
1622 { 0xF0, 0x10, C_ALL, "l2_trans.l1d_wb"                                   , 0x0, ATTR_NONE, 0x0 }, \
1623 { 0xF0, 0x20, C_ALL, "l2_trans.l2_fill"                                  , 0x0, ATTR_NONE, 0x0 }, \
1624 { 0xF0, 0x40, C_ALL, "l2_trans.l2_wb"                                    , 0x0, ATTR_NONE, 0x0 }, \
1625 { 0xF0, 0x80, C_ALL, "l2_trans.all_requests"                             , 0x0, ATTR_NONE, 0x0 }, \
1626 { 0xF1, 0x01, C_ALL, "l2_lines_in.i"                                     , 0x0, ATTR_NONE, 0x0 }, \
1627 { 0xF1, 0x02, C_ALL, "l2_lines_in.s"                                     , 0x0, ATTR_NONE, 0x0 }, \
1628 { 0xF1, 0x04, C_ALL, "l2_lines_in.e"                                     , 0x0, ATTR_NONE, 0x0 }, \
1629 { 0xF1, 0x07, C_ALL, "l2_lines_in.all"                                   , 0x0, ATTR_NONE, 0x0 }, \
1630 { 0xF2, 0x01, C_ALL, "l2_lines_out.demand_clean"                         , 0x0, ATTR_NONE, 0x0 }, \
1631 { 0xF2, 0x02, C_ALL, "l2_lines_out.demand_dirty"                         , 0x0, ATTR_NONE, 0x0 }, \
1632 { 0xF2, 0x04, C_ALL, "l2_lines_out.pf_clean"                             , 0x0, ATTR_NONE, 0x0 }, \
1633 { 0xF2, 0x08, C_ALL, "l2_lines_out.pf_dirty"                             , 0x0, ATTR_NONE, 0x0 }, \
1634 { 0xF2, 0x0A, C_ALL, "l2_lines_out.dirty_all"                            , 0x0, ATTR_NONE, 0x0 }, \
1635 /* end of #define */
1636
1637 #define EVENTS_FAM6_MOD62_ONLY \
1638 { 0xD3, 0x01, C_ALL, "mem_load_uops_llc_miss_retired.local_dram"         , 0x0, ATTR_NONE, 0x0 }, \
1639 { 0xD3, 0x04, C_ALL, "mem_load_uops_llc_miss_retired.remote_dram"        , 0x0, ATTR_NONE, 0x0 }, \
1640 { 0xD3, 0x10, C_ALL, "mem_load_uops_llc_miss_retired.remote_hitm"        , 0x0, ATTR_NONE, 0x0 }, \
1641 { 0xD3, 0x20, C_ALL, "mem_load_uops_llc_miss_retired.remote_fwd"         , 0x0, ATTR_NONE, 0x0 }, \
1642 /* end of #define */
1643
1644 /* Intel Haswell Processor */
1645 /*
1646  * The Haswell tables take into account Bug 17006019
1647  *   libcpc counter names should be based on public Intel documentation -- Haswell
1648  * and are basically from the
1649  * Intel SDM, June 2013, Section 19.3, Table 19-2 and Table 19-3.
1650  * We omit the Table 19-4 uncore events.
1651  */
1652
1653 #define EVENTS_FAM6_MOD60 \
1654 { 0x03, 0x02, C_ALL, "ld_blocks.store_forward"                           , 0x0, ATTR_NONE, 0x0 }, \
1655 { 0x03, 0x08, C_ALL, "ld_blocks.no_sr"                                   , 0x0, ATTR_NONE, 0x0 }, \
1656 { 0x05, 0x01, C_ALL, "misalign_mem_ref.loads"                            , 0x0, ATTR_NONE, 0x0 }, \
1657 { 0x05, 0x02, C_ALL, "misalign_mem_ref.stores"                           , 0x0, ATTR_NONE, 0x0 }, \
1658 { 0x07, 0x01, C_ALL, "ld_blocks_partial.address_alias"                   , 0x0, ATTR_NONE, 0x0 }, \
1659 { 0x08, 0x01, C_ALL, "dtlb_load_misses.miss_causes_a_walk"               , 0x0, ATTR_NONE, 0x0 }, \
1660 { 0x08, 0x02, C_ALL, "dtlb_load_misses.walk_completed_4k"                , 0x0, ATTR_NONE, 0x0 }, \
1661 { 0x08, 0x04, C_ALL, "dtlb_load_misses.walk_completed_2m_4m"             , 0x0, ATTR_NONE, 0x0 }, \
1662 { 0x08, 0x0E, C_ALL, "dtlb_load_misses.walk_completed"                   , 0x0, ATTR_NONE, 0x0 }, \
1663 { 0x08, 0x10, C_ALL, "dtlb_load_misses.walk_duration"                    , 0x0, ATTR_NONE, 0x0 }, \
1664 { 0x08, 0x20, C_ALL, "dtlb_load_misses.stlb_hit_4k"                      , 0x0, ATTR_NONE, 0x0 }, \
1665 { 0x08, 0x40, C_ALL, "dtlb_load_misses.stlb_hit_2m"                      , 0x0, ATTR_NONE, 0x0 }, \
1666 { 0x08, 0x60, C_ALL, "dtlb_load_misses.stlb_hit"                         , 0x0, ATTR_NONE, 0x0 }, \
1667 { 0x08, 0x80, C_ALL, "dtlb_load_misses.pde_cache_miss"                   , 0x0, ATTR_NONE, 0x0 }, \
1668 { 0x0D, 0x03, C_ALL, "int_misc.recovery_cycles"                          , 0x1, ATTR_NONE, 0x0 }, \
1669 { 0x0D, 0x03, C_ALL, "int_misc.recovery_cycles_occurrences"              , 0x1, ATTR_EDGE, 0x0 }, \
1670 { 0x0E, 0x01, C_ALL, "uops_issued.any"                                   , 0x0, ATTR_NONE, 0x0 }, \
1671 { 0x0E, 0x01, C_ALL, "uops_issued.stall_cycles"                          , 0x1, ATTR_INV , 0x0 }, \
1672 { 0x0E, 0x01, C_ALL, "uops_issued.core_stall_cycles"                     , 0x1, ATTR_INV | ATTR_ANY, 0x0 }, \
1673 { 0x0E, 0x10, C_ALL, "uops_issued.flags_merge"                           , 0x0, ATTR_NONE, 0x0 }, \
1674 { 0x0E, 0x20, C_ALL, "uops_issued.slow_lea"                              , 0x0, ATTR_NONE, 0x0 }, \
1675 { 0x0E, 0x40, C_ALL, "uops_issued.single_mul"                            , 0x0, ATTR_NONE, 0x0 }, \
1676 { 0x24, 0x21, C_ALL, "l2_rqsts.demand_data_rd_miss"                      , 0x0, ATTR_NONE, 0x0 }, \
1677 { 0x24, 0x22, C_ALL, "l2_rqsts.rfo_miss"                                 , 0x0, ATTR_NONE, 0x0 }, \
1678 { 0x24, 0x24, C_ALL, "l2_rqsts.code_rd_miss"                             , 0x0, ATTR_NONE, 0x0 }, \
1679 { 0x24, 0x27, C_ALL, "l2_rqsts.all_demand_miss"                          , 0x0, ATTR_NONE, 0x0 }, \
1680 { 0x24, 0x30, C_ALL, "l2_rqsts.l2_pf_miss"                               , 0x0, ATTR_NONE, 0x0 }, \
1681 { 0x24, 0x3F, C_ALL, "l2_rqsts.miss"                                     , 0x0, ATTR_NONE, 0x0 }, \
1682 { 0x24, 0x41, C_ALL, "l2_rqsts.demand_data_rd_hit"                       , 0x0, ATTR_NONE, 0x0 }, \
1683 { 0x24, 0x42, C_ALL, "l2_rqsts.rfo_hit"                                  , 0x0, ATTR_NONE, 0x0 }, \
1684 { 0x24, 0x44, C_ALL, "l2_rqsts.code_rd_hit"                              , 0x0, ATTR_NONE, 0x0 }, \
1685 { 0x24, 0x50, C_ALL, "l2_rqsts.l2_pf_hit"                                , 0x0, ATTR_NONE, 0x0 }, \
1686 { 0x24, 0xE1, C_ALL, "l2_rqsts.all_demand_data_rd"                       , 0x0, ATTR_NONE, 0x0 }, \
1687 { 0x24, 0xE2, C_ALL, "l2_rqsts.all_rfo"                                  , 0x0, ATTR_NONE, 0x0 }, \
1688 { 0x24, 0xE4, C_ALL, "l2_rqsts.all_code_rd"                              , 0x0, ATTR_NONE, 0x0 }, \
1689 { 0x24, 0xE7, C_ALL, "l2_rqsts.all_demand_references"                    , 0x0, ATTR_NONE, 0x0 }, \
1690 { 0x24, 0xF8, C_ALL, "l2_rqsts.all_pf"                                   , 0x0, ATTR_NONE, 0x0 }, \
1691 { 0x24, 0xFF, C_ALL, "l2_rqsts.references"                               , 0x0, ATTR_NONE, 0x0 }, \
1692 { 0x27, 0x50, C_ALL, "l2_demand_rqsts.wb_hit"                            , 0x0, ATTR_NONE, 0x0 }, \
1693 { 0x2E, 0x4F, C_ALL, "longest_lat_cache.reference"                       , 0x0, ATTR_NONE, 0x0 }, \
1694 { 0x2E, 0x41, C_ALL, "longest_lat_cache.miss"                            , 0x0, ATTR_NONE, 0x0 }, \
1695 { 0x3C, 0x00, C_ALL, "cpu_clk_unhalted.thread_p"                         , 0x0, ATTR_NONE, 0x0 }, \
1696 { 0x3C, 0x01, C_ALL, "cpu_clk_thread_unhalted.ref_xclk"                  , 0x0, ATTR_NONE, 0x0 }, \
1697 { 0x48, 0x01, C(2) , "l1d_pend_miss.pending"                             , 0x0, ATTR_NONE, 0x0 }, \
1698 { 0x48, 0x01, C(2) , "l1d_pend_miss.pending_cycles"                      , 0x1, ATTR_NONE, 0x0 }, \
1699 { 0x48, 0x01, C(2) , "l1d_pend_miss.occurences"                          , 0x1, ATTR_EDGE, 0x0 }, \
1700 { 0x49, 0x01, C_ALL, "dtlb_store_misses.miss_causes_a_walk"              , 0x0, ATTR_NONE, 0x0 }, \
1701 { 0x49, 0x02, C_ALL, "dtlb_store_misses.walk_completed_4k"               , 0x0, ATTR_NONE, 0x0 }, \
1702 { 0x49, 0x04, C_ALL, "dtlb_store_misses.walk_completed_2m_4m"            , 0x0, ATTR_NONE, 0x0 }, \
1703 { 0x49, 0x0E, C_ALL, "dtlb_store_misses.walk_completed"                  , 0x0, ATTR_NONE, 0x0 }, \
1704 { 0x49, 0x10, C_ALL, "dtlb_store_misses.walk_duration"                   , 0x0, ATTR_NONE, 0x0 }, \
1705 { 0x49, 0x20, C_ALL, "dtlb_store_misses.stlb_hit_4k"                     , 0x0, ATTR_NONE, 0x0 }, \
1706 { 0x49, 0x40, C_ALL, "dtlb_store_misses.stlb_hit_2m"                     , 0x0, ATTR_NONE, 0x0 }, \
1707 { 0x49, 0x60, C_ALL, "dtlb_store_misses.stlb_hit"                        , 0x0, ATTR_NONE, 0x0 }, \
1708 { 0x49, 0x80, C_ALL, "dtlb_store_misses.pde_cache_miss"                  , 0x0, ATTR_NONE, 0x0 }, \
1709 { 0x4C, 0x01, C_ALL, "load_hit_pre.sw_pf"                                , 0x0, ATTR_NONE, 0x0 }, \
1710 { 0x4C, 0x02, C_ALL, "load_hit_pre.hw_pf"                                , 0x0, ATTR_NONE, 0x0 }, \
1711 { 0x51, 0x01, C_ALL, "l1d.replacement"                                   , 0x0, ATTR_NONE, 0x0 }, \
1712 { 0x54, 0x01, C_ALL, "tx_mem.abort_conflict"                             , 0x0, ATTR_NONE, 0x0 }, \
1713 { 0x54, 0x02, C_ALL, "tx_mem.abort_capacity"                             , 0x0, ATTR_NONE, 0x0 }, \
1714 { 0x54, 0x04, C_ALL, "tx_mem.abort_hle_store_to_elided_lock"             , 0x0, ATTR_NONE, 0x0 }, \
1715 { 0x54, 0x08, C_ALL, "tx_mem.abort_hle_elision_buffer_not_empty"         , 0x0, ATTR_NONE, 0x0 }, \
1716 { 0x54, 0x10, C_ALL, "tx_mem.abort_hle_elision_buffer_mismatch"          , 0x0, ATTR_NONE, 0x0 }, \
1717 { 0x54, 0x20, C_ALL, "tx_mem.abort_hle_elision_buffer_unsupported_alignment"  , 0x0, ATTR_NONE, 0x0 }, \
1718 { 0x54, 0x40, C_ALL, "tx_mem.abort_hle_elision_buffer_full"              , 0x0, ATTR_NONE, 0x0 }, \
1719 { 0x58, 0x01, C_ALL, "move_elimination.int_eliminated"                   , 0x0, ATTR_NONE, 0x0 }, \
1720 { 0x58, 0x02, C_ALL, "move_elimination.simd_eliminated"                  , 0x0, ATTR_NONE, 0x0 }, \
1721 { 0x58, 0x04, C_ALL, "move_elimination.int_not_eliminated"               , 0x0, ATTR_NONE, 0x0 }, \
1722 { 0x58, 0x08, C_ALL, "move_elimination.simd_not_eliminated"              , 0x0, ATTR_NONE, 0x0 }, \
1723 { 0x5C, 0x01, C_ALL, "cpl_cycles.ring0"                                  , 0x0, ATTR_NONE, 0x0 }, \
1724 { 0x5C, 0x01, C_ALL, "cpl_cycles.ring0_trans"                            , 0x0, ATTR_EDGE, 0x0 }, \
1725 { 0x5C, 0x02, C_ALL, "cpl_cycles.ring123"                                , 0x0, ATTR_NONE, 0x0 }, \
1726 { 0x5D, 0x01, C_ALL, "tx_exec.misc1"                                     , 0x0, ATTR_NONE, 0x0 }, \
1727 { 0x5D, 0x02, C_ALL, "tx_exec.misc2"                                     , 0x0, ATTR_NONE, 0x0 }, \
1728 { 0x5D, 0x04, C_ALL, "tx_exec.misc3"                                     , 0x0, ATTR_NONE, 0x0 }, \
1729 { 0x5D, 0x08, C_ALL, "tx_exec.misc4"                                     , 0x0, ATTR_NONE, 0x0 }, \
1730 { 0x5D, 0x10, C_ALL, "tx_exec.misc5"                                     , 0x0, ATTR_NONE, 0x0 }, \
1731 { 0x5E, 0x01, C_ALL, "rs_events.empty_cycles"                            , 0x0, ATTR_NONE, 0x0 }, \
1732 { 0x60, 0x01, C_ALL, "offcore_requests_outstanding.demand_data_rd"       , 0x0, ATTR_NONE, 0x0 }, \
1733 { 0x60, 0x01, C_ALL, "offcore_requests_outstanding.cycles_with_demand_data_rd", 0x1, ATTR_NONE, 0x0 }, \
1734 { 0x60, 0x02, C_ALL, "offcore_requests_outstanding.demand_code_rd"       , 0x0, ATTR_NONE, 0x0 }, \
1735 { 0x60, 0x02, C_ALL, "offcore_requests_outstanding.demand_code_rd_cycles", 0x1, ATTR_NONE, 0x0 }, \
1736 { 0x60, 0x04, C_ALL, "offcore_requests_outstanding.demand_rfo"           , 0x0, ATTR_NONE, 0x0 }, \
1737 { 0x60, 0x04, C_ALL, "offcore_requests_outstanding.demand_rfo_cycles"    , 0x1, ATTR_NONE, 0x0 }, \
1738 { 0x60, 0x08, C_ALL, "offcore_requests_outstanding.all_data_rd"          , 0x0, ATTR_NONE, 0x0 }, \
1739 { 0x60, 0x08, C_ALL, "offcore_requests_outstanding.cycles_with_data_rd"  , 0x1, ATTR_NONE, 0x0 }, \
1740 { 0x63, 0x01, C_ALL, "lock_cycles.split_lock_uc_lock_duration"           , 0x0, ATTR_NONE, 0x0 }, \
1741 { 0x63, 0x02, C_ALL, "lock_cycles.cache_lock_duration"                   , 0x0, ATTR_NONE, 0x0 }, \
1742 { 0x79, 0x02, C_ALL, "idq.empty"                                         , 0x0, ATTR_NONE, 0x0 }, \
1743 { 0x79, 0x04, C_ALL, "idq.mite_uops"                                     , 0x0, ATTR_NONE, 0x0 }, \
1744 { 0x79, 0x04, C_ALL, "idq.mite_cycles"                                   , 0x1, ATTR_NONE, 0x0 }, \
1745 { 0x79, 0x20, C_ALL, "idq.ms_mite_uops"                                  , 0x0, ATTR_NONE, 0x0 }, \
1746 { 0x79, 0x20, C_ALL, "idq.ms_mite_cycles"                                , 0x1, ATTR_NONE, 0x0 }, \
1747 { 0x79, 0x24, C_ALL, "idq.all_mite_cycles_any_uops"                      , 0x1, ATTR_NONE, 0x0 }, \
1748 { 0x79, 0x24, C_ALL, "idq.all_mite_cycles_4_uops"                        , 0x4, ATTR_NONE, 0x0 }, \
1749 { 0x79, 0x08, C_ALL, "idq.dsb_uops"                                      , 0x0, ATTR_NONE, 0x0 }, \
1750 { 0x79, 0x08, C_ALL, "idq.dsb_cycles"                                    , 0x1, ATTR_NONE, 0x0 }, \
1751 { 0x79, 0x10, C_ALL, "idq.ms_dsb_uops"                                   , 0x0, ATTR_NONE, 0x0 }, \
1752 { 0x79, 0x10, C_ALL, "idq.ms_dsb_cycles"                                 , 0x1, ATTR_NONE, 0x0 }, \
1753 { 0x79, 0x10, C_ALL, "idq.ms_dsb_occur"                                  , 0x1, ATTR_EDGE, 0x0 }, \
1754 { 0x79, 0x18, C_ALL, "idq.all_dsb_cycles_any_uops"                       , 0x1, ATTR_NONE, 0x0 }, \
1755 { 0x79, 0x18, C_ALL, "idq.all_dsb_cycles_4_uops"                         , 0x4, ATTR_NONE, 0x0 }, \
1756 { 0x79, 0x30, C_ALL, "idq.ms_uops"                                       , 0x0, ATTR_NONE, 0x0 }, \
1757 { 0x79, 0x30, C_ALL, "idq.ms_cycles"                                     , 0x1, ATTR_NONE, 0x0 }, \
1758 { 0x79, 0x3C, C_ALL, "idq.mite_all_uops"                                 , 0x0, ATTR_NONE, 0x0 }, \
1759 { 0x80, 0x02, C_ALL, "icache.misses"                                     , 0x0, ATTR_NONE, 0x0 }, \
1760 { 0x85, 0x01, C_ALL, "itlb_misses.miss_causes_a_walk"                    , 0x0, ATTR_NONE, 0x0 }, \
1761 { 0x85, 0x02, C_ALL, "itlb_misses.walk_completed_4k"                     , 0x0, ATTR_NONE, 0x0 }, \
1762 { 0x85, 0x04, C_ALL, "itlb_misses.walk_completed_2m_4m"                  , 0x0, ATTR_NONE, 0x0 }, \
1763 { 0x85, 0x0E, C_ALL, "itlb_misses.walk_completed"                        , 0x0, ATTR_NONE, 0x0 }, \
1764 { 0x85, 0x10, C_ALL, "itlb_misses.walk_duration"                         , 0x0, ATTR_NONE, 0x0 }, \
1765 { 0x85, 0x20, C_ALL, "itlb_misses.stlb_hit_4k"                           , 0x0, ATTR_NONE, 0x0 }, \
1766 { 0x85, 0x40, C_ALL, "itlb_misses.stlb_hit_2m"                           , 0x0, ATTR_NONE, 0x0 }, \
1767 { 0x85, 0x60, C_ALL, "itlb_misses.stlb_hit"                              , 0x0, ATTR_NONE, 0x0 }, \
1768 { 0x87, 0x01, C_ALL, "ild_stall.lcp"                                     , 0x0, ATTR_NONE, 0x0 }, \
1769 { 0x87, 0x04, C_ALL, "ild_stall.iq_full"                                 , 0x0, ATTR_NONE, 0x0 }, \
1770 { 0x88, 0x41, C_ALL, "br_inst_exec.nontaken_conditional"                 , 0x0, ATTR_NONE, 0x0 }, \
1771 { 0x88, 0x81, C_ALL, "br_inst_exec.taken_conditional"                    , 0x0, ATTR_NONE, 0x0 }, \
1772 { 0x88, 0x82, C_ALL, "br_inst_exec.taken_direct_jump"                    , 0x0, ATTR_NONE, 0x0 }, \
1773 { 0x88, 0x84, C_ALL, "br_inst_exec.taken_indirect_jump_non_call_ret"     , 0x0, ATTR_NONE, 0x0 }, \
1774 { 0x88, 0x88, C_ALL, "br_inst_exec.taken_indirect_near_return"           , 0x0, ATTR_NONE, 0x0 }, \
1775 { 0x88, 0x90, C_ALL, "br_inst_exec.taken_direct_near_call"               , 0x0, ATTR_NONE, 0x0 }, \
1776 { 0x88, 0xA0, C_ALL, "br_inst_exec.taken_indirect_near_call"             , 0x0, ATTR_NONE, 0x0 }, \
1777 { 0x88, 0xFF, C_ALL, "br_inst_exec.all_branches"                         , 0x0, ATTR_NONE, 0x0 }, \
1778 { 0x89, 0x41, C_ALL, "br_misp_exec.nontaken_conditional"                 , 0x0, ATTR_NONE, 0x0 }, \
1779 { 0x89, 0x81, C_ALL, "br_misp_exec.taken_conditional"                    , 0x0, ATTR_NONE, 0x0 }, \
1780 { 0x89, 0x84, C_ALL, "br_misp_exec.taken_indirect_jump_non_call_ret"     , 0x0, ATTR_NONE, 0x0 }, \
1781 { 0x89, 0x88, C_ALL, "br_misp_exec.taken_return_near"                    , 0x0, ATTR_NONE, 0x0 }, \
1782 { 0x89, 0x90, C_ALL, "br_misp_exec.taken_direct_near_call"               , 0x0, ATTR_NONE, 0x0 }, \
1783 { 0x89, 0xA0, C_ALL, "br_misp_exec.taken_indirect_near_call"             , 0x0, ATTR_NONE, 0x0 }, \
1784 { 0x89, 0xFF, C_ALL, "br_misp_exec.all_branches"                         , 0x0, ATTR_NONE, 0x0 }, \
1785 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.core"                       , 0x0, ATTR_NONE, 0x0 }, \
1786 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.cycles_0_uops_deliv.core"   , 0x4, ATTR_NONE, 0x0 }, \
1787 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.cycles_le_1_uop_deliv.core" , 0x3, ATTR_NONE, 0x0 }, \
1788 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.cycles_le_2_uop_deliv.core" , 0x2, ATTR_NONE, 0x0 }, \
1789 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.cycles_le_3_uop_deliv.core" , 0x1, ATTR_NONE, 0x0 }, \
1790 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.cycles_fe_was_ok"           , 0x1, ATTR_NONE, 0x0 }, \
1791 { 0xA1, 0x01, C_ALL, "uops_executed_port.port_0"                         , 0x0, ATTR_NONE, 0x0 }, \
1792 { 0xA1, 0x02, C_ALL, "uops_executed_port.port_1"                         , 0x0, ATTR_NONE, 0x0 }, \
1793 { 0xA1, 0x04, C_ALL, "uops_executed_port.port_2"                         , 0x0, ATTR_NONE, 0x0 }, \
1794 { 0xA1, 0x08, C_ALL, "uops_executed_port.port_3"                         , 0x0, ATTR_NONE, 0x0 }, \
1795 { 0xA1, 0x10, C_ALL, "uops_executed_port.port_4"                         , 0x0, ATTR_NONE, 0x0 }, \
1796 { 0xA1, 0x20, C_ALL, "uops_executed_port.port_5"                         , 0x0, ATTR_NONE, 0x0 }, \
1797 { 0xA1, 0x40, C_ALL, "uops_executed_port.port_6"                         , 0x0, ATTR_NONE, 0x0 }, \
1798 { 0xA1, 0x80, C_ALL, "uops_executed_port.port_7"                         , 0x0, ATTR_NONE, 0x0 }, \
1799 { 0xA1, 0x01, C_ALL, "uops_executed_port.port_0_core"                    , 0x0, ATTR_ANY , 0x0 }, \
1800 { 0xA1, 0x02, C_ALL, "uops_executed_port.port_1_core"                    , 0x0, ATTR_ANY , 0x0 }, \
1801 { 0xA1, 0x04, C_ALL, "uops_executed_port.port_2_core"                    , 0x0, ATTR_ANY , 0x0 }, \
1802 { 0xA1, 0x08, C_ALL, "uops_executed_port.port_3_core"                    , 0x0, ATTR_ANY , 0x0 }, \
1803 { 0xA1, 0x10, C_ALL, "uops_executed_port.port_4_core"                    , 0x0, ATTR_ANY , 0x0 }, \
1804 { 0xA1, 0x20, C_ALL, "uops_executed_port.port_5_core"                    , 0x0, ATTR_ANY , 0x0 }, \
1805 { 0xA1, 0x40, C_ALL, "uops_executed_port.port_6_core"                    , 0x0, ATTR_ANY , 0x0 }, \
1806 { 0xA1, 0x80, C_ALL, "uops_executed_port.port_7_core"                    , 0x0, ATTR_ANY , 0x0 }, \
1807 { 0xA2, 0x01, C_ALL, "resource_stalls.any"                               , 0x0, ATTR_NONE, 0x0 }, \
1808 { 0xA2, 0x04, C_ALL, "resource_stalls.rs"                                , 0x0, ATTR_NONE, 0x0 }, \
1809 { 0xA2, 0x08, C_ALL, "resource_stalls.sb"                                , 0x0, ATTR_NONE, 0x0 }, \
1810 { 0xA2, 0x10, C_ALL, "resource_stalls.rob"                               , 0x0, ATTR_NONE, 0x0 }, \
1811 { 0xA3, 0x01, C_ALL, "cycle_activity.cycles_l2_pending"                  , 0x0, ATTR_NONE, 0x0 }, \
1812 { 0xA3, 0x01, C_ALL, "cycle_activity.cycles_l2_pending_cycles"           , 0x2, ATTR_NONE, 0x0 }, \
1813 { 0xA3, 0x02, C_ALL, "cycle_activity.cycles_ldm_pending"                 , 0x0, ATTR_NONE, 0x0 }, \
1814 { 0xA3, 0x02, C_ALL, "cycle_activity.cycles_ldm_pending_cycles"          , 0x2, ATTR_NONE, 0x0 }, \
1815 { 0xA3, 0x05, C_ALL, "cycle_activity.stalls_l2_pending"                  , 0x0, ATTR_NONE, 0x0 }, \
1816 { 0xA3, 0x08, C(2) , "cycle_activity.cycles_l1d_pending"                 , 0x0, ATTR_NONE, 0x0 }, \
1817 { 0xA3, 0x08, C(2) , "cycle_activity.cycles_l1d_pending_cycles"          , 0x8, ATTR_NONE, 0x0 }, \
1818 { 0xA8, 0x01, C_ALL, "lsd.uops"                                          , 0x0, ATTR_NONE, 0x0 }, \
1819 { 0xAE, 0x01, C_ALL, "itlb.itlb_flush"                                   , 0x0, ATTR_NONE, 0x0 }, \
1820 { 0xB0, 0x01, C_ALL, "offcore_requests.demand_data_rd"                   , 0x0, ATTR_NONE, 0x0 }, \
1821 { 0xB0, 0x02, C_ALL, "offcore_requests.demand_code_rd"                   , 0x0, ATTR_NONE, 0x0 }, \
1822 { 0xB0, 0x04, C_ALL, "offcore_requests.demand_rfo"                       , 0x0, ATTR_NONE, 0x0 }, \
1823 { 0xB0, 0x08, C_ALL, "offcore_requests.all_data_rd"                      , 0x0, ATTR_NONE, 0x0 }, \
1824 { 0xB1, 0x02, C_ALL, "uops_executed.core"                                , 0x0, ATTR_NONE, 0x0 }, \
1825 /* { 0xB7, 0x01, C_ALL, "off_core_response_0"                               , 0x0, ATTR_NONE, 0x1A6 }, omit events requiring MSR programming */ \
1826 /* { 0xBB, 0x01, C_ALL, "off_core_response_1"                               , 0x0, ATTR_NONE, 0x1A7 }, omit events requiring MSR programming */ \
1827 { 0xBC, 0x11, C_ALL, "page_walker_loads.dtlb_l1"                         , 0x0, ATTR_NONE, 0x0 }, \
1828 { 0xBC, 0x21, C_ALL, "page_walker_loads.itlb_l1"                         , 0x0, ATTR_NONE, 0x0 }, \
1829 { 0xBC, 0x12, C_ALL, "page_walker_loads.dtlb_l2"                         , 0x0, ATTR_NONE, 0x0 }, \
1830 { 0xBC, 0x22, C_ALL, "page_walker_loads.itlb_l2"                         , 0x0, ATTR_NONE, 0x0 }, \
1831 { 0xBC, 0x14, C_ALL, "page_walker_loads.dtlb_l3"                         , 0x0, ATTR_NONE, 0x0 }, \
1832 { 0xBC, 0x24, C_ALL, "page_walker_loads.itlb_l3"                         , 0x0, ATTR_NONE, 0x0 }, \
1833 { 0xBC, 0x18, C_ALL, "page_walker_loads.dtlb_memory"                     , 0x0, ATTR_NONE, 0x0 }, \
1834 { 0xBC, 0x28, C_ALL, "page_walker_loads.itlb_memory"                     , 0x0, ATTR_NONE, 0x0 }, \
1835 { 0xBD, 0x01, C_ALL, "tlb_flush.dtlb_thread"                             , 0x0, ATTR_NONE, 0x0 }, \
1836 { 0xBD, 0x20, C_ALL, "tlb_flush.stlb_any"                                , 0x0, ATTR_NONE, 0x0 }, \
1837 { 0xC0, 0x00, C_ALL, "inst_retired.any_p"                                , 0x0, ATTR_NONE, 0x0 }, \
1838 { 0xC0, 0x01, C(1) , "inst_retired.prec_dist"                            , 0x0, ATTR_NONE, 0x0 }, \
1839 { 0xC1, 0x08, C_ALL, "other_assists.avx_to_sse"                          , 0x0, ATTR_NONE, 0x0 }, \
1840 { 0xC1, 0x10, C_ALL, "other_assists.sse_to_avx"                          , 0x0, ATTR_NONE, 0x0 }, \
1841 { 0xC1, 0x40, C_ALL, "other_assists.any_wb_assist"                       , 0x0, ATTR_NONE, 0x0 }, \
1842 { 0xC2, 0x01, C_ALL, "uops_retired.all"                                  , 0x0, ATTR_PEBS, 0x0 }, \
1843 { 0xC2, 0x01, C_ALL, "uops_retired.stall_cycles"                         , 0x1, ATTR_INV , 0x0 }, \
1844 { 0xC2, 0x02, C_ALL, "uops_retired.retire_slots"                         , 0x0, ATTR_PEBS, 0x0 }, \
1845 { 0xC3, 0x02, C_ALL, "machine_clears.memory_ordering"                    , 0x0, ATTR_NONE, 0x0 }, \
1846 { 0xC3, 0x04, C_ALL, "machine_clears.smc"                                , 0x0, ATTR_NONE, 0x0 }, \
1847 { 0xC3, 0x20, C_ALL, "machine_clears.maskmov"                            , 0x0, ATTR_NONE, 0x0 }, \
1848 { 0xC4, 0x00, C_ALL, "br_inst_retired.all_branches"                      , 0x0, ATTR_NONE, 0x0 }, \
1849 { 0xC4, 0x01, C_ALL, "br_inst_retired.conditional"                       , 0x0, ATTR_PEBS, 0x0 }, \
1850 { 0xC4, 0x02, C_ALL, "br_inst_retired.near_call"                         , 0x0, ATTR_PEBS, 0x0 }, \
1851 { 0xC4, 0x04, C_ALL, "br_inst_retired.all_branches"                      , 0x0, ATTR_PEBS, 0x0 }, \
1852 { 0xC4, 0x08, C_ALL, "br_inst_retired.near_return"                       , 0x0, ATTR_PEBS, 0x0 }, \
1853 { 0xC4, 0x10, C_ALL, "br_inst_retired.not_taken"                         , 0x0, ATTR_PEBS, 0x0 }, \
1854 { 0xC4, 0x20, C_ALL, "br_inst_retired.near_taken"                        , 0x0, ATTR_PEBS, 0x0 }, \
1855 { 0xC4, 0x40, C_ALL, "br_inst_retired.far_branch"                        , 0x0, ATTR_NONE, 0x0 }, \
1856 { 0xC5, 0x00, C_ALL, "br_misp_retired.all_branches"                      , 0x0, ATTR_NONE, 0x0 }, \
1857 { 0xC5, 0x01, C_ALL, "br_misp_retired.conditional"                       , 0x0, ATTR_PEBS, 0x0 }, \
1858 { 0xC5, 0x04, C_ALL, "br_misp_retired.all_branches"                      , 0x0, ATTR_PEBS, 0x0 }, \
1859 { 0xC5, 0x20, C_ALL, "br_misp_retired.near_taken"                        , 0x0, ATTR_NONE, 0x0 }, \
1860 { 0xC8, 0x01, C_ALL, "hle_retired.start"                                 , 0x0, ATTR_NONE, 0x0 }, \
1861 { 0xC8, 0x02, C_ALL, "hle_retired.commit"                                , 0x0, ATTR_NONE, 0x0 }, \
1862 { 0xC8, 0x04, C_ALL, "hle_retired.aborted"                               , 0x0, ATTR_PEBS, 0x0 }, \
1863 { 0xC8, 0x08, C_ALL, "hle_retired.aborted_misc1"                         , 0x0, ATTR_NONE, 0x0 }, \
1864 { 0xC8, 0x10, C_ALL, "hle_retired.aborted_misc2"                         , 0x0, ATTR_NONE, 0x0 }, \
1865 { 0xC8, 0x20, C_ALL, "hle_retired.aborted_misc3"                         , 0x0, ATTR_NONE, 0x0 }, \
1866 { 0xC8, 0x40, C_ALL, "hle_retired.aborted_misc4"                         , 0x0, ATTR_NONE, 0x0 }, \
1867 { 0xC8, 0x80, C_ALL, "hle_retired.aborted_misc5"                         , 0x0, ATTR_NONE, 0x0 }, \
1868 { 0xC9, 0x01, C_ALL, "rtm_retired.start"                                 , 0x0, ATTR_NONE, 0x0 }, \
1869 { 0xC9, 0x02, C_ALL, "rtm_retired.commit"                                , 0x0, ATTR_NONE, 0x0 }, \
1870 { 0xC9, 0x04, C_ALL, "rtm_retired.aborted"                               , 0x0, ATTR_PEBS, 0x0 }, \
1871 { 0xC9, 0x08, C_ALL, "rtm_retired.aborted_misc1"                         , 0x0, ATTR_NONE, 0x0 }, \
1872 { 0xC9, 0x10, C_ALL, "rtm_retired.aborted_misc2"                         , 0x0, ATTR_NONE, 0x0 }, \
1873 { 0xC9, 0x20, C_ALL, "rtm_retired.aborted_misc3"                         , 0x0, ATTR_NONE, 0x0 }, \
1874 { 0xC9, 0x40, C_ALL, "rtm_retired.aborted_misc4"                         , 0x0, ATTR_NONE, 0x0 }, \
1875 { 0xC9, 0x80, C_ALL, "rtm_retired.aborted_misc5"                         , 0x0, ATTR_NONE, 0x0 }, \
1876 { 0xCA, 0x02, C_ALL, "fp_assist.x87_output"                              , 0x0, ATTR_NONE, 0x0 }, \
1877 { 0xCA, 0x04, C_ALL, "fp_assist.x87_input"                               , 0x0, ATTR_NONE, 0x0 }, \
1878 { 0xCA, 0x08, C_ALL, "fp_assist.simd_output"                             , 0x0, ATTR_NONE, 0x0 }, \
1879 { 0xCA, 0x10, C_ALL, "fp_assist.simd_input"                              , 0x0, ATTR_NONE, 0x0 }, \
1880 { 0xCA, 0x1E, C_ALL, "fp_assist.any"                                     , 0x0, ATTR_NONE, 0x0 }, \
1881 { 0xCC, 0x20, C_ALL, "rob_misc_events.lbr_inserts"                       , 0x0, ATTR_NONE, 0x0 }, \
1882 /* { 0xCD, 0x01, C_ALL, "mem_trans_retired.load_latency"                    , 0x0, ATTR_NONE, 0x3F6 }, omit events requiring MSR programming */ \
1883 { 0xD0, 0x11, C_ALL, "mem_uops_retired.stlb_miss_loads"                  , 0x0, ATTR_PEBS, 0x0 }, \
1884 { 0xD0, 0x12, C_ALL, "mem_uops_retired.stlb_miss_stores"                 , 0x0, ATTR_PEBS, 0x0 }, \
1885 { 0xD0, 0x21, C_ALL, "mem_uops_retired.lock_loads"                       , 0x0, ATTR_PEBS, 0x0 }, \
1886 { 0xD0, 0x22, C_ALL, "mem_uops_retired.lock_stores"                      , 0x0, ATTR_PEBS, 0x0 }, \
1887 { 0xD0, 0x41, C_ALL, "mem_uops_retired.split_loads"                      , 0x0, ATTR_PEBS, 0x0 }, \
1888 { 0xD0, 0x42, C_ALL, "mem_uops_retired.split_stores"                     , 0x0, ATTR_PEBS, 0x0 }, \
1889 { 0xD0, 0x81, C_ALL, "mem_uops_retired.all_loads"                        , 0x0, ATTR_PEBS, 0x0 }, \
1890 { 0xD0, 0x82, C_ALL, "mem_uops_retired.all_stores"                       , 0x0, ATTR_PEBS, 0x0 }, \
1891 { 0xD1, 0x01, C_ALL, "mem_load_uops_retired.l1_hit"                      , 0x0, ATTR_PEBS, 0x0 }, \
1892 { 0xD1, 0x02, C_ALL, "mem_load_uops_retired.l2_hit"                      , 0x0, ATTR_PEBS, 0x0 }, \
1893 { 0xD1, 0x04, C_ALL, "mem_load_uops_retired.l3_hit"                      , 0x0, ATTR_PEBS, 0x0 }, \
1894 { 0xD1, 0x08, C_ALL, "mem_load_uops_retired.l1_miss"                     , 0x0, ATTR_PEBS, 0x0 }, \
1895 { 0xD1, 0x10, C_ALL, "mem_load_uops_retired.l2_miss"                     , 0x0, ATTR_PEBS, 0x0 }, \
1896 { 0xD1, 0x20, C_ALL, "mem_load_uops_retired.l3_miss"                     , 0x0, ATTR_PEBS, 0x0 }, \
1897 { 0xD1, 0x40, C_ALL, "mem_load_uops_retired.hit_lfb"                     , 0x0, ATTR_NONE, 0x0 }, \
1898 { 0xD2, 0x01, C_ALL, "mem_load_uops_l3_hit_retired.xsnp_miss"            , 0x0, ATTR_PEBS, 0x0 }, \
1899 { 0xD2, 0x02, C_ALL, "mem_load_uops_l3_hit_retired.xsnp_hit"             , 0x0, ATTR_PEBS, 0x0 }, \
1900 { 0xD2, 0x04, C_ALL, "mem_load_uops_l3_hit_retired.xsnp_hitm"            , 0x0, ATTR_PEBS, 0x0 }, \
1901 { 0xD2, 0x08, C_ALL, "mem_load_uops_l3_hit_retired.xsnp_none"            , 0x0, ATTR_PEBS, 0x0 }, \
1902 { 0xD3, 0x01, C_ALL, "mem_load_uops_l3_miss_retired.local_dram"          , 0x0, ATTR_PEBS, 0x0 }, \
1903 { 0xE6, 0x1F, C_ALL, "baclears.any"                                      , 0x0, ATTR_NONE, 0x0 }, \
1904 { 0xF0, 0x01, C_ALL, "l2_trans.demand_data_rd"                           , 0x0, ATTR_NONE, 0x0 }, \
1905 { 0xF0, 0x02, C_ALL, "l2_trans.rfo"                                      , 0x0, ATTR_NONE, 0x0 }, \
1906 { 0xF0, 0x04, C_ALL, "l2_trans.code_rd"                                  , 0x0, ATTR_NONE, 0x0 }, \
1907 { 0xF0, 0x08, C_ALL, "l2_trans.all_pf"                                   , 0x0, ATTR_NONE, 0x0 }, \
1908 { 0xF0, 0x10, C_ALL, "l2_trans.l1d_wb"                                   , 0x0, ATTR_NONE, 0x0 }, \
1909 { 0xF0, 0x20, C_ALL, "l2_trans.l2_fill"                                  , 0x0, ATTR_NONE, 0x0 }, \
1910 { 0xF0, 0x40, C_ALL, "l2_trans.l2_wb"                                    , 0x0, ATTR_NONE, 0x0 }, \
1911 { 0xF0, 0x80, C_ALL, "l2_trans.all_requests"                             , 0x0, ATTR_NONE, 0x0 }, \
1912 { 0xF1, 0x01, C_ALL, "l2_lines_in.i"                                     , 0x0, ATTR_NONE, 0x0 }, \
1913 { 0xF1, 0x02, C_ALL, "l2_lines_in.s"                                     , 0x0, ATTR_NONE, 0x0 }, \
1914 { 0xF1, 0x04, C_ALL, "l2_lines_in.e"                                     , 0x0, ATTR_NONE, 0x0 }, \
1915 { 0xF1, 0x07, C_ALL, "l2_lines_in.all"                                   , 0x0, ATTR_NONE, 0x0 }, \
1916 { 0xF2, 0x05, C_ALL, "l2_lines_out.demand_clean"                         , 0x0, ATTR_NONE, 0x0 }, \
1917 { 0xF2, 0x06, C_ALL, "l2_lines_out.demand_dirty"                         , 0x0, ATTR_NONE, 0x0 }, \
1918 /* end of #define */
1919
1920 /* Intel Broadwell Processor */
1921 /*
1922  * This table is essentially taken from:
1923  *   https://grok.cz.oracle.com/source/xref/on12-clone/usr/src/uts/intel/pcbe/bdw_pcbe_tbl.c
1924  */
1925
1926 #define EVENTS_FAM6_MOD61 \
1927 { 0x03, 0x02, C_ALL, "ld_blocks.store_forward"                           , 0x0, ATTR_NONE, 0x0 }, \
1928 { 0x03, 0x08, C_ALL, "ld_blocks.no_sr"                                   , 0x0, ATTR_NONE, 0x0 }, \
1929  \
1930 { 0x05, 0x01, C_ALL, "misalign_mem_ref.loads"                            , 0x0, ATTR_NONE, 0x0 }, \
1931 { 0x05, 0x02, C_ALL, "misalign_mem_ref.stores"                           , 0x0, ATTR_NONE, 0x0 }, \
1932  \
1933 { 0x07, 0x01, C_ALL, "ld_blocks_partial.address_alias"                   , 0x0, ATTR_NONE, 0x0 }, \
1934  \
1935 { 0x08, 0x01, C_ALL, "dtlb_load_misses.miss_causes_a_walk"               , 0x0, ATTR_NONE, 0x0 }, \
1936 { 0x08, 0x02, C_ALL, "dtlb_load_misses.walk_completed_4k"                , 0x0, ATTR_NONE, 0x0 }, \
1937 { 0x08, 0x04, C_ALL, "dtlb_load_misses.walk_completed_2m_4m"             , 0x0, ATTR_NONE, 0x0 }, \
1938 { 0x08, 0x0E, C_ALL, "dtlb_load_misses.walk_completed"                   , 0x0, ATTR_NONE, 0x0 }, \
1939 { 0x08, 0x10, C_ALL, "dtlb_load_misses.walk_duration"                    , 0x0, ATTR_NONE, 0x0 }, \
1940 { 0x08, 0x20, C_ALL, "dtlb_load_misses.stlb_hit_4k"                      , 0x0, ATTR_NONE, 0x0 }, \
1941 { 0x08, 0x40, C_ALL, "dtlb_load_misses.stlb_hit_2m"                      , 0x0, ATTR_NONE, 0x0 }, \
1942 { 0x08, 0x60, C_ALL, "dtlb_load_misses.stlb_hit"                         , 0x0, ATTR_NONE, 0x0 }, \
1943 { 0x08, 0x80, C_ALL, "dtlb_load_misses.pde_cache_miss"                   , 0x0, ATTR_NONE, 0x0 }, \
1944  \
1945 { 0x0D, 0x03, C_ALL, "int_misc.recovery_cycles"                          , 0x1, ATTR_NONE, 0x0 }, \
1946 { 0x0D, 0x03, C_ALL, "int_misc.recovery_cycles_any"                      , 0x1, ATTR_ANY , 0x0 }, \
1947 /* Private event, not public by Intel */ \
1948 { 0x0D, 0x03, C_ALL, "int_misc.recovery_cycles_occurrences"              , 0x1, ATTR_EDGE, 0x0 }, \
1949 { 0x0D, 0x08, C_ALL, "int_misc.rat_stall_cycles"                         , 0x0, ATTR_NONE, 0x0 }, \
1950  \
1951 { 0x0E, 0x01, C_ALL, "uops_issued.any"                                   , 0x0, ATTR_NONE, 0x0 }, \
1952 { 0x0E, 0x10, C_ALL, "uops_issued.flags_merge"                           , 0x0, ATTR_NONE, 0x0 }, \
1953 { 0x0E, 0x20, C_ALL, "uops_issued.slow_lea"                              , 0x0, ATTR_NONE, 0x0 }, \
1954 { 0x0E, 0x40, C_ALL, "uops_issued.single_mul"                            , 0x0, ATTR_NONE, 0x0 }, \
1955 { 0x0E, 0x01, C_ALL, "uops_issued.stall_cycles"                          , 0x1, ATTR_INV , 0x0 }, \
1956 { 0x0E, 0x01, C_ALL, "uops_issued.core_stall_cycles"                     , 0x1,(ATTR_INV | ATTR_ANY), 0x0 }, \
1957  \
1958 { 0x14, 0x01, C_ALL, "arith.fpu_div_active"                              , 0x0, ATTR_NONE, 0x0 }, \
1959  \
1960 { 0x24, 0x21, C_ALL, "l2_rqsts.demand_data_rd_miss"                      , 0x0, ATTR_NONE, 0x0 }, \
1961 { 0x24, 0x41, C_ALL, "l2_rqsts.demand_data_rd_hit"                       , 0x0, ATTR_NONE, 0x0 }, \
1962 { 0x24, 0x30, C_ALL, "l2_rqsts.l2_pf_miss"                               , 0x0, ATTR_NONE, 0x0 }, \
1963 { 0x24, 0x50, C_ALL, "l2_rqsts.l2_pf_hit"                                , 0x0, ATTR_NONE, 0x0 }, \
1964 { 0x24, 0xE1, C_ALL, "l2_rqsts.all_demand_data_rd"                       , 0x0, ATTR_NONE, 0x0 }, \
1965 { 0x24, 0xE2, C_ALL, "l2_rqsts.all_rfo"                                  , 0x0, ATTR_NONE, 0x0 }, \
1966 { 0x24, 0xE4, C_ALL, "l2_rqsts.all_code_rd"                              , 0x0, ATTR_NONE, 0x0 }, \
1967 { 0x24, 0xF8, C_ALL, "l2_rqsts.all_pf"                                   , 0x0, ATTR_NONE, 0x0 }, \
1968 { 0x24, 0x42, C_ALL, "l2_rqsts.rfo_hit"                                  , 0x0, ATTR_NONE, 0x0 }, \
1969 { 0x24, 0x22, C_ALL, "l2_rqsts.rfo_miss"                                 , 0x0, ATTR_NONE, 0x0 }, \
1970 { 0x24, 0x44, C_ALL, "l2_rqsts.code_rd_hit"                              , 0x0, ATTR_NONE, 0x0 }, \
1971 { 0x24, 0x24, C_ALL, "l2_rqsts.code_rd_miss"                             , 0x0, ATTR_NONE, 0x0 }, \
1972 { 0x24, 0x27, C_ALL, "l2_rqsts.all_demand_miss"                          , 0x0, ATTR_NONE, 0x0 }, \
1973 { 0x24, 0xE7, C_ALL, "l2_rqsts.all_demand_references"                    , 0x0, ATTR_NONE, 0x0 }, \
1974 { 0x24, 0x3F, C_ALL, "l2_rqsts.miss"                                     , 0x0, ATTR_NONE, 0x0 }, \
1975 { 0x24, 0xFF, C_ALL, "l2_rqsts.references"                               , 0x0, ATTR_NONE, 0x0 }, \
1976  \
1977 { 0x27, 0x50, C_ALL, "l2_demand_rqsts.wb_hit"                            , 0x0, ATTR_NONE, 0x0 }, \
1978  \
1979 { 0x3C, 0x00, C_ALL, "cpu_clk_unhalted.thread_p"                         , 0x0, ATTR_NONE, 0x0 }, \
1980 { 0x3C, 0x00, C_ALL, "cpu_clk_unhalted.thread_p_any"                     , 0x0, ATTR_ANY , 0x0 }, \
1981 { 0x3C, 0x01, C_ALL, "cpu_clk_thread_unhalted.ref_xclk"                  , 0x0, ATTR_NONE, 0x0 }, \
1982 { 0x3C, 0x01, C_ALL, "cpu_clk_thread_unhalted.ref_xclk_any"              , 0x0, ATTR_ANY , 0x0 }, \
1983 { 0x3C, 0x02, C_ALL, "cpu_clk_thread_unhalted.one_thread_active"         , 0x0, ATTR_NONE, 0x0 }, \
1984  \
1985 { 0x48, 0x01, C(2) , "l1d_pend_miss.pending"                             , 0x0, ATTR_NONE, 0x0 }, \
1986 { 0x48, 0x01, C(2) , "l1d_pend_miss.pending_cycles"                      , 0x1, ATTR_NONE, 0x0 }, \
1987 { 0x48, 0x01, C(2) , "l1d_pend_miss.pending_cycles_any"                  , 0x1, ATTR_ANY , 0x0 }, \
1988 /* Private event, not public by Intel */ \
1989 { 0x48, 0x01, C(2) , "l1d_pend_miss.occurences"                          , 0x1, ATTR_EDGE, 0x0 }, \
1990 { 0x48, 0x02, C_ALL, "l1d_pend_miss.fb_full"                             , 0x1, ATTR_NONE, 0x0 }, \
1991  \
1992 { 0x49, 0x01, C_ALL, "dtlb_store_misses.miss_causes_a_walk"              , 0x0, ATTR_NONE, 0x0 }, \
1993 { 0x49, 0x02, C_ALL, "dtlb_store_misses.walk_completed_4k"               , 0x0, ATTR_NONE, 0x0 }, \
1994 { 0x49, 0x04, C_ALL, "dtlb_store_misses.walk_completed_2m_4m"            , 0x0, ATTR_NONE, 0x0 }, \
1995 { 0x49, 0x0E, C_ALL, "dtlb_store_misses.walk_completed"                  , 0x0, ATTR_NONE, 0x0 }, \
1996 { 0x49, 0x10, C_ALL, "dtlb_store_misses.walk_duration"                   , 0x0, ATTR_NONE, 0x0 }, \
1997 { 0x49, 0x20, C_ALL, "dtlb_store_misses.stlb_hit_4k"                     , 0x0, ATTR_NONE, 0x0 }, \
1998 { 0x49, 0x40, C_ALL, "dtlb_store_misses.stlb_hit_2m"                     , 0x0, ATTR_NONE, 0x0 }, \
1999 { 0x49, 0x60, C_ALL, "dtlb_store_misses.stlb_hit"                        , 0x0, ATTR_NONE, 0x0 }, \
2000 { 0x49, 0x80, C_ALL, "dtlb_store_misses.pde_cache_miss"                  , 0x0, ATTR_NONE, 0x0 }, \
2001  \
2002 { 0x4C, 0x01, C_ALL, "load_hit_pre.sw_pf"                                , 0x0, ATTR_NONE, 0x0 }, \
2003 { 0x4C, 0x02, C_ALL, "load_hit_pre.hw_pf"                                , 0x0, ATTR_NONE, 0x0 }, \
2004  \
2005 { 0x4F, 0x10, C_ALL, "ept.walk_cycles"                                   , 0x0, ATTR_NONE, 0x0 }, \
2006  \
2007 { 0x51, 0x01, C_ALL, "l1d.replacement"                                   , 0x0, ATTR_NONE, 0x0 }, \
2008  \
2009 { 0x54, 0x01, C_ALL, "tx_mem.abort_conflict"                             , 0x0, ATTR_TSX , 0x0 }, \
2010 { 0x54, 0x02, C_ALL, "tx_mem.abort_capacity_write"                       , 0x0, ATTR_TSX , 0x0 }, \
2011 { 0x54, 0x04, C_ALL, "tx_mem.abort_hle_store_to_elided_lock"             , 0x0, ATTR_TSX , 0x0 }, \
2012 { 0x54, 0x08, C_ALL, "tx_mem.abort_hle_elision_buffer_not_empty"         , 0x0, ATTR_TSX , 0x0 }, \
2013 { 0x54, 0x10, C_ALL, "tx_mem.abort_hle_elision_buffer_mismatch"          , 0x0, ATTR_TSX , 0x0 }, \
2014 { 0x54, 0x20, C_ALL, "tx_mem.abort_hle_elision_buffer_unsupported_alignment"  , 0x0, ATTR_TSX , 0x0 }, \
2015 { 0x54, 0x40, C_ALL, "tx_mem.hle_elision_buffer_full"                    , 0x0, ATTR_TSX , 0x0 }, \
2016  \
2017 { 0x58, 0x01, C_ALL, "move_elimination.int_eliminated"                   , 0x0, ATTR_NONE, 0x0 }, \
2018 { 0x58, 0x02, C_ALL, "move_elimination.simd_eliminated"                  , 0x0, ATTR_NONE, 0x0 }, \
2019 { 0x58, 0x04, C_ALL, "move_elimination.int_not_eliminated"               , 0x0, ATTR_NONE, 0x0 }, \
2020 { 0x58, 0x08, C_ALL, "move_elimination.simd_not_eliminated"              , 0x0, ATTR_NONE, 0x0 }, \
2021  \
2022 { 0x5C, 0x01, C_ALL, "cpl_cycles.ring0"                                  , 0x0, ATTR_NONE, 0x0 }, \
2023 { 0x5C, 0x01, C_ALL, "cpl_cycles.ring0_trans"                            , 0x1, ATTR_EDGE, 0x0 }, \
2024 { 0x5C, 0x02, C_ALL, "cpl_cycles.ring123"                                , 0x0, ATTR_NONE, 0x0 }, \
2025  \
2026 { 0x5D, 0x01, C_ALL, "tx_exec.misc1"                                     , 0x0, ATTR_TSX , 0x0 }, \
2027 { 0x5D, 0x02, C_ALL, "tx_exec.misc2"                                     , 0x0, ATTR_TSX , 0x0 }, \
2028 { 0x5D, 0x04, C_ALL, "tx_exec.misc3"                                     , 0x0, ATTR_TSX , 0x0 }, \
2029 { 0x5D, 0x08, C_ALL, "tx_exec.misc4"                                     , 0x0, ATTR_TSX , 0x0 }, \
2030 { 0x5D, 0x10, C_ALL, "tx_exec.misc5"                                     , 0x0, ATTR_TSX , 0x0 }, \
2031  \
2032 { 0x5E, 0x01, C_ALL, "rs_events.empty_cycles"                            , 0x0, ATTR_NONE, 0x0 }, \
2033 { 0x5E, 0x01, C_ALL, "rs_events.empty_end"                               , 0x1, (ATTR_INV | ATTR_EDGE), 0x0 }, \
2034  \
2035 { 0x60, 0x01, C_ALL, "offcore_requests_outstanding.demand_data_rd"       , 0x0, ATTR_NONE, 0x0 }, \
2036 { 0x60, 0x01, C_ALL, "offcore_requests_outstanding.cycles_with_demand_data_rd", 0x1, ATTR_NONE, 0x0 }, \
2037 { 0x60, 0x01, C_ALL, "offcore_requests_outstanding.demand_data_rd_ge_6 " , 0x6, ATTR_NONE, 0x0 }, \
2038 { 0x60, 0x02, C_ALL, "offcore_requests_outstanding.demand_code_rd"       , 0x0, ATTR_NONE, 0x0 }, \
2039 /* Private event, not public by Intel */ \
2040 { 0x60, 0x02, C_ALL, "offcore_requests_outstanding.demand_code_rd_cycles", 0x1, ATTR_NONE, 0x0 }, \
2041 { 0x60, 0x04, C_ALL, "offcore_requests_outstanding.demand_rfo"           , 0x0, ATTR_NONE, 0x0 }, \
2042 /* Private event, not public by Intel */ \
2043 { 0x60, 0x04, C_ALL, "offcore_requests_outstanding.demand_rfo_cycles"    , 0x1, ATTR_NONE, 0x0 }, \
2044 { 0x60, 0x08, C_ALL, "offcore_requests_outstanding.all_data_rd"          , 0x0, ATTR_NONE, 0x0 }, \
2045 { 0x60, 0x08, C_ALL, "offcore_requests_outstanding.cycles_with_data_rd"  , 0x1, ATTR_NONE, 0x0 }, \
2046  \
2047 { 0x63, 0x01, C_ALL, "lock_cycles.split_lock_uc_lock_duration"           , 0x0, ATTR_NONE, 0x0 }, \
2048 { 0x63, 0x02, C_ALL, "lock_cycles.cache_lock_duration"                   , 0x0, ATTR_NONE, 0x0 }, \
2049  \
2050 { 0x79, 0x02, C_ALL, "idq.empty"                                         , 0x0, ATTR_NONE, 0x0 }, \
2051 { 0x79, 0x04, C_ALL, "idq.mite_uops"                                     , 0x0, ATTR_NONE, 0x0 }, \
2052 { 0x79, 0x04, C_ALL, "idq.mite_cycles"                                   , 0x1, ATTR_NONE, 0x0 }, \
2053 { 0x79, 0x08, C_ALL, "idq.dsb_uops"                                      , 0x0, ATTR_NONE, 0x0 }, \
2054 { 0x79, 0x08, C_ALL, "idq.dsb_cycles"                                    , 0x1, ATTR_NONE, 0x0 }, \
2055 { 0x79, 0x10, C_ALL, "idq.ms_dsb_uops"                                   , 0x0, ATTR_NONE, 0x0 }, \
2056 { 0x79, 0x10, C_ALL, "idq.ms_dsb_cycles"                                 , 0x1, ATTR_NONE, 0x0 }, \
2057 { 0x79, 0x10, C_ALL, "idq.ms_dsb_occur"                                  , 0x1, ATTR_EDGE, 0x0 }, \
2058 { 0x79, 0x18, C_ALL, "idq.all_dsb_cycles_4_uops"                         , 0x4, ATTR_NONE, 0x0 }, \
2059 { 0x79, 0x18, C_ALL, "idq.all_dsb_cycles_any_uops"                       , 0x1, ATTR_NONE, 0x0 }, \
2060 { 0x79, 0x20, C_ALL, "idq.ms_mite_uops"                                  , 0x0, ATTR_NONE, 0x0 }, \
2061 { 0x79, 0x24, C_ALL, "idq.all_mite_cycles_4_uops"                        , 0x4, ATTR_NONE, 0x0 }, \
2062 { 0x79, 0x24, C_ALL, "idq.all_mite_cycles_any_uops"                      , 0x1, ATTR_NONE, 0x0 }, \
2063 { 0x79, 0x30, C_ALL, "idq.ms_uops"                                       , 0x0, ATTR_NONE, 0x0 }, \
2064 { 0x79, 0x30, C_ALL, "idq.ms_cycles"                                     , 0x1, ATTR_NONE, 0x0 }, \
2065 { 0x79, 0x30, C_ALL, "idq.ms_switches"                                   , 0x1, ATTR_EDGE, 0x0 }, \
2066 { 0x79, 0x3C, C_ALL, "idq.mite_all_uops"                                 , 0x0, ATTR_NONE, 0x0 }, \
2067  \
2068 { 0x80, 0x01, C_ALL, "icache.hit"                                        , 0x0, ATTR_NONE, 0x0 }, \
2069 { 0x80, 0x02, C_ALL, "icache.misses"                                     , 0x0, ATTR_NONE, 0x0 }, \
2070 { 0x80, 0x04, C_ALL, "icache.ifdata_stall"                               , 0x0, ATTR_NONE, 0x0 }, \
2071  \
2072 { 0x85, 0x01, C_ALL, "itlb_misses.miss_causes_a_walk"                    , 0x0, ATTR_NONE, 0x0 }, \
2073 { 0x85, 0x02, C_ALL, "itlb_misses.walk_completed_4k"                     , 0x0, ATTR_NONE, 0x0 }, \
2074 { 0x85, 0x04, C_ALL, "itlb_misses.walk_completed_2m_4m"                  , 0x0, ATTR_NONE, 0x0 }, \
2075 { 0x85, 0x0E, C_ALL, "itlb_misses.walk_completed"                        , 0x0, ATTR_NONE, 0x0 }, \
2076 { 0x85, 0x10, C_ALL, "itlb_misses.walk_duration"                         , 0x0, ATTR_NONE, 0x0 }, \
2077 { 0x85, 0x20, C_ALL, "itlb_misses.stlb_hit_4k"                           , 0x0, ATTR_NONE, 0x0 }, \
2078 { 0x85, 0x40, C_ALL, "itlb_misses.stlb_hit_2m"                           , 0x0, ATTR_NONE, 0x0 }, \
2079 { 0x85, 0x60, C_ALL, "itlb_misses.stlb_hit"                              , 0x0, ATTR_NONE, 0x0 }, \
2080  \
2081 { 0x87, 0x01, C_ALL, "ild_stall.lcp"                                     , 0x0, ATTR_NONE, 0x0 }, \
2082 { 0x87, 0x04, C_ALL, "ild_stall.iq_full"                                 , 0x0, ATTR_NONE, 0x0 }, \
2083  \
2084 { 0x88, 0x41, C_ALL, "br_inst_exec.nontaken_conditional"                 , 0x0, ATTR_NONE, 0x0 }, \
2085 { 0x88, 0x81, C_ALL, "br_inst_exec.taken_conditional"                    , 0x0, ATTR_NONE, 0x0 }, \
2086 { 0x88, 0x82, C_ALL, "br_inst_exec.taken_direct_jump"                    , 0x0, ATTR_NONE, 0x0 }, \
2087 { 0x88, 0x84, C_ALL, "br_inst_exec.taken_indirect_jump_non_call_ret"     , 0x0, ATTR_NONE, 0x0 }, \
2088 { 0x88, 0x88, C_ALL, "br_inst_exec.taken_indirect_near_return"           , 0x0, ATTR_NONE, 0x0 }, \
2089 { 0x88, 0x90, C_ALL, "br_inst_exec.taken_direct_near_call"               , 0x0, ATTR_NONE, 0x0 }, \
2090 { 0x88, 0xA0, C_ALL, "br_inst_exec.taken_indirect_near_call"             , 0x0, ATTR_NONE, 0x0 }, \
2091 { 0x88, 0xC1, C_ALL, "br_inst_exec.all_conditional"                      , 0x0, ATTR_NONE, 0x0 }, \
2092 { 0x88, 0xC2, C_ALL, "br_inst_exec.all_direct_jmp"                       , 0x0, ATTR_NONE, 0x0 }, \
2093 { 0x88, 0xC4, C_ALL, "br_inst_exec.all_indirect_jump_non_call_ret"       , 0x0, ATTR_NONE, 0x0 }, \
2094 { 0x88, 0xC8, C_ALL, "br_inst_exec.all_indirect_near_return"             , 0x0, ATTR_NONE, 0x0 }, \
2095 { 0x88, 0xD0, C_ALL, "br_inst_exec.all_direct_near_call"                 , 0x0, ATTR_NONE, 0x0 }, \
2096 { 0x88, 0xFF, C_ALL, "br_inst_exec.all_branches"                         , 0x0, ATTR_NONE, 0x0 }, \
2097  \
2098 { 0x89, 0x41, C_ALL, "br_misp_exec.nontaken_conditional"                 , 0x0, ATTR_NONE, 0x0 }, \
2099 { 0x89, 0x81, C_ALL, "br_misp_exec.taken_conditional"                    , 0x0, ATTR_NONE, 0x0 }, \
2100 { 0x89, 0x84, C_ALL, "br_misp_exec.taken_indirect_jump_non_call_ret"     , 0x0, ATTR_NONE, 0x0 }, \
2101 /* Private event, not public by Intel */ \
2102 { 0x89, 0x88, C_ALL, "br_misp_exec.taken_return_near"                    , 0x0, ATTR_NONE, 0x0 }, \
2103 { 0x89, 0xC1, C_ALL, "br_misp_exec.all_conditional"                      , 0x0, ATTR_NONE, 0x0 }, \
2104 { 0x89, 0xC4, C_ALL, "br_misp_exec.all_indirect_jump_non_call_ret"       , 0x0, ATTR_NONE, 0x0 }, \
2105 { 0x89, 0xA0, C_ALL, "br_misp_exec.taken_indirect_near_call"             , 0x0, ATTR_NONE, 0x0 }, \
2106 { 0x89, 0xFF, C_ALL, "br_misp_exec.all_branches"                         , 0x0, ATTR_NONE, 0x0 }, \
2107  \
2108 /* Use Cmask to qualify uop b/w */ \
2109 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.core"                       , 0x0, ATTR_NONE, 0x0 }, \
2110 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.cycles_0_uops_deliv.core"   , 0x4, ATTR_NONE, 0x0 }, \
2111 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.cycles_le_1_uop_deliv.core" , 0x3, ATTR_NONE, 0x0 }, \
2112 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.cycles_le_2_uop_deliv.core" , 0x2, ATTR_NONE, 0x0 }, \
2113 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.cycles_le_3_uop_deliv.core" , 0x1, ATTR_NONE, 0x0 }, \
2114 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.cycles_fe_was_ok"           , 0x1, ATTR_INV , 0x0 }, \
2115  \
2116 { 0xA0, 0x03, C_ALL, "uop_dispatches_cancelled.simd_prf"                 , 0x0, ATTR_NONE, 0x0 }, \
2117  \
2118 { 0xA1, 0x01, C_ALL, "uops_executed_port.port_0"                         , 0x0, ATTR_NONE, 0x0 }, \
2119 { 0xA1, 0x02, C_ALL, "uops_executed_port.port_1"                         , 0x0, ATTR_NONE, 0x0 }, \
2120 { 0xA1, 0x04, C_ALL, "uops_executed_port.port_2"                         , 0x0, ATTR_NONE, 0x0 }, \
2121 { 0xA1, 0x08, C_ALL, "uops_executed_port.port_3"                         , 0x0, ATTR_NONE, 0x0 }, \
2122 { 0xA1, 0x10, C_ALL, "uops_executed_port.port_4"                         , 0x0, ATTR_NONE, 0x0 }, \
2123 { 0xA1, 0x20, C_ALL, "uops_executed_port.port_5"                         , 0x0, ATTR_NONE, 0x0 }, \
2124 { 0xA1, 0x40, C_ALL, "uops_executed_port.port_6"                         , 0x0, ATTR_NONE, 0x0 }, \
2125 { 0xA1, 0x80, C_ALL, "uops_executed_port.port_7"                         , 0x0, ATTR_NONE, 0x0 }, \
2126 { 0xA1, 0x01, C_ALL, "uops_executed_port.port_0_core"                    , 0x0, ATTR_ANY , 0x0 }, \
2127 { 0xA1, 0x02, C_ALL, "uops_executed_port.port_1_core"                    , 0x0, ATTR_ANY , 0x0 }, \
2128 { 0xA1, 0x04, C_ALL, "uops_executed_port.port_2_core"                    , 0x0, ATTR_ANY , 0x0 }, \
2129 { 0xA1, 0x08, C_ALL, "uops_executed_port.port_3_core"                    , 0x0, ATTR_ANY , 0x0 }, \
2130 { 0xA1, 0x10, C_ALL, "uops_executed_port.port_4_core"                    , 0x0, ATTR_ANY , 0x0 }, \
2131 { 0xA1, 0x20, C_ALL, "uops_executed_port.port_5_core"                    , 0x0, ATTR_ANY , 0x0 }, \
2132 { 0xA1, 0x40, C_ALL, "uops_executed_port.port_6_core"                    , 0x0, ATTR_ANY , 0x0 }, \
2133 { 0xA1, 0x80, C_ALL, "uops_executed_port.port_7_core"                    , 0x0, ATTR_ANY , 0x0 }, \
2134  \
2135 { 0xA2, 0x01, C_ALL, "resource_stalls.any"                               , 0x0, ATTR_NONE, 0x0 }, \
2136 { 0xA2, 0x04, C_ALL, "resource_stalls.rs"                                , 0x0, ATTR_NONE, 0x0 }, \
2137 { 0xA2, 0x08, C_ALL, "resource_stalls.sb"                                , 0x0, ATTR_NONE, 0x0 }, \
2138 { 0xA2, 0x10, C_ALL, "resource_stalls.rob"                               , 0x0, ATTR_NONE, 0x0 }, \
2139  \
2140 { 0xA3, 0x01, C_ALL, "cycle_activity.cycles_l2_pending"                  , 0x1, ATTR_NONE, 0x0 }, \
2141 { 0xA3, 0x02, C_ALL, "cycle_activity.cycles_ldm_pending"                 , 0x2, ATTR_NONE, 0x0 }, \
2142 { 0xA3, 0x04, C_ALL, "cycle_activity.cycles_no_execute"                  , 0x4, ATTR_NONE, 0x0 }, \
2143 { 0xA3, 0x05, C_ALL, "cycle_activity.stalls_l2_pending"                  , 0x5, ATTR_NONE, 0x0 }, \
2144 { 0xA3, 0x06, C_ALL, "cycle_activity.stalls_ldm_pending"                 , 0x6, ATTR_NONE, 0x0 }, \
2145 { 0xA3, 0x08, C(2) , "cycle_activity.cycles_l1d_pending"                 , 0x8, ATTR_NONE, 0x0 }, \
2146 { 0xA3, 0x0C, C(2) , "cycle_activity.stalls_l1d_pending"                 , 0xC, ATTR_NONE, 0x0 }, \
2147  \
2148 { 0xA8, 0x01, C_ALL, "lsd.uops"                                          , 0x0, ATTR_NONE, 0x0 }, \
2149 { 0xA8, 0x01, C_ALL, "lsd.cycles_active"                                 , 0x1, ATTR_NONE, 0x0 }, \
2150 { 0xA8, 0x01, C_ALL, "lsd.cycles_4_uops"                                 , 0x4, ATTR_NONE, 0x0 }, \
2151  \
2152 { 0xAB, 0x02, C_ALL, "dsb2mite_switches.penalty_cycles"                  , 0x0, ATTR_NONE, 0x0 }, \
2153  \
2154 { 0xAE, 0x01, C_ALL, "itlb.itlb_flush"                                   , 0x0, ATTR_NONE, 0x0 }, \
2155  \
2156 { 0xB0, 0x01, C_ALL, "offcore_requests.demand_data_rd"                   , 0x0, ATTR_NONE, 0x0 }, \
2157 { 0xB0, 0x02, C_ALL, "offcore_requests.demand_code_rd"                   , 0x0, ATTR_NONE, 0x0 }, \
2158 { 0xB0, 0x04, C_ALL, "offcore_requests.demand_rfo"                       , 0x0, ATTR_NONE, 0x0 }, \
2159 { 0xB0, 0x08, C_ALL, "offcore_requests.all_data_rd"                      , 0x0, ATTR_NONE, 0x0 }, \
2160  \
2161 { 0xB1, 0x01, C_ALL, "uops_executed.thread"                              , 0x0, ATTR_NONE, 0x0 }, \
2162 { 0xB1, 0x01, C_ALL, "uops_executed.stall_cycles"                        , 0x1, ATTR_INV , 0x0 }, \
2163 { 0xB1, 0x01, C_ALL, "uops_executed.cycles_ge_1_uop_exec"                , 0x1, ATTR_NONE, 0x0 }, \
2164 { 0xB1, 0x01, C_ALL, "uops_executed.cycles_ge_2_uops_exec"               , 0x2, ATTR_NONE, 0x0 }, \
2165 { 0xB1, 0x01, C_ALL, "uops_executed.cycles_ge_3_uops_exec"               , 0x3, ATTR_NONE, 0x0 }, \
2166 { 0xB1, 0x01, C_ALL, "uops_executed.cycles_ge_4_uops_exec"               , 0x4, ATTR_NONE, 0x0 }, \
2167 { 0xB1, 0x02, C_ALL, "uops_executed.core"                                , 0x0, ATTR_NONE, 0x0 }, \
2168 { 0xB1, 0x02, C_ALL, "uops_executed.core_cycles_none"                    , 0x0, ATTR_INV , 0x0 }, \
2169 { 0xB1, 0x02, C_ALL, "uops_executed.core_cycles_ge_1"                    , 0x1, ATTR_NONE, 0x0 }, \
2170 { 0xB1, 0x02, C_ALL, "uops_executed.core_cycles_ge_2"                    , 0x2, ATTR_NONE, 0x0 }, \
2171 { 0xB1, 0x02, C_ALL, "uops_executed.core_cycles_ge_3"                    , 0x3, ATTR_NONE, 0x0 }, \
2172 { 0xB1, 0x02, C_ALL, "uops_executed.core_cycles_ge_4"                    , 0x4, ATTR_NONE, 0x0 }, \
2173  \
2174 { 0xB2, 0x01, C_ALL, "offcore_requests_buffer.sq_full"                   , 0x0, ATTR_NONE, 0x0 }, \
2175  \
2176 /* \
2177  * See Section "Off-core Response Performance Monitoring" \
2178  * \
2179  * Though these two off_core events support all counters, only 1 of \
2180  * them can be used at any given time. This is due to the extra MSR \
2181  * programming required. \
2182  */ \
2183 /* { 0xB7, 0x01, C_ALL, "offcore_response_0"                                , 0x0, ATTR_NONE, OFFCORE_RSP_0 }, omit events requiring MSR programming */ \
2184 /* { 0xBB, 0x01, C_ALL, "offcore_response_1"                                , 0x0, ATTR_NONE, OFFCORE_RSP_1 }, omit events requiring MSR programming */ \
2185  \
2186 { 0xBC, 0x11, C_ALL, "page_walker_loads.dtlb_l1"                         , 0x0, ATTR_NONE, 0x0 }, \
2187 { 0xBC, 0x21, C_ALL, "page_walker_loads.itlb_l1"                         , 0x0, ATTR_NONE, 0x0 }, \
2188 { 0xBC, 0x12, C_ALL, "page_walker_loads.dtlb_l2"                         , 0x0, ATTR_NONE, 0x0 }, \
2189 { 0xBC, 0x22, C_ALL, "page_walker_loads.itlb_l2"                         , 0x0, ATTR_NONE, 0x0 }, \
2190 { 0xBC, 0x14, C_ALL, "page_walker_loads.dtlb_l3"                         , 0x0, ATTR_NONE, 0x0 }, \
2191 { 0xBC, 0x24, C_ALL, "page_walker_loads.itlb_l3"                         , 0x0, ATTR_NONE, 0x0 }, \
2192 { 0xBC, 0x18, C_ALL, "page_walker_loads.dtlb_memory"                     , 0x0, ATTR_NONE, 0x0 }, \
2193 /* itlb_memory is not in the Intel SDM or spreadsheet for Broadwell;  "cputrack -h" does have it though */ \
2194 { 0xBC, 0x28, C_ALL, "page_walker_loads.itlb_memory"                     , 0x0, ATTR_NONE, 0x0 }, \
2195  \
2196 { 0xBD, 0x01, C_ALL, "tlb_flush.dtlb_thread"                             , 0x0, ATTR_NONE, 0x0 }, \
2197 { 0xBD, 0x20, C_ALL, "tlb_flush.stlb_any"                                , 0x0, ATTR_NONE, 0x0 }, \
2198  \
2199 { 0xC0, 0x00, C_ALL, "inst_retired.any_p"                                , 0x0, ATTR_NONE, 0x0 }, \
2200 { 0xC0, 0x02, C_ALL, "inst_retired.x87"                                  , 0x0, ATTR_NONE, 0x0 }, \
2201  \
2202 { 0xC1, 0x08, C_ALL, "other_assists.avx_to_sse"                          , 0x0, ATTR_NONE, 0x0 }, \
2203 { 0xC1, 0x10, C_ALL, "other_assists.sse_to_avx"                          , 0x0, ATTR_NONE, 0x0 }, \
2204 { 0xC1, 0x40, C_ALL, "other_assists.any_wb_assist"                       , 0x0, ATTR_NONE, 0x0 }, \
2205  \
2206 { 0xC2, 0x01, C_ALL, "uops_retired.all"                                  , 0x0, ATTR_PEBS, 0x0 }, \
2207 { 0xC2, 0x01, C_ALL, "uops_retired.stall_cycles"                         , 0x1, ATTR_INV , 0x0 }, \
2208 { 0xC2, 0x01, C_ALL, "uops_retired.total_cycles"                         , 0xA, ATTR_INV , 0x0 }, \
2209 { 0xC2, 0x01, C_ALL, "uops_retired.core_stall_cycles"                    , 0x1, (ATTR_INV | ATTR_ANY), 0x0 }, \
2210 { 0xC2, 0x02, C_ALL, "uops_retired.retire_slots"                         , 0x0, ATTR_PEBS, 0x0 }, \
2211  \
2212 { 0xC3, 0x01, C_ALL, "machine_clears.cycles"                             , 0x0, ATTR_NONE, 0x0 }, \
2213 { 0xC3, 0x01, C_ALL, "machine_clears.count"                              , 0x1, ATTR_EDGE, 0x0 }, \
2214 { 0xC3, 0x02, C_ALL, "machine_clears.memory_ordering"                    , 0x0, ATTR_NONE, 0x0 }, \
2215 { 0xC3, 0x04, C_ALL, "machine_clears.smc"                                , 0x0, ATTR_NONE, 0x0 }, \
2216 { 0xC3, 0x20, C_ALL, "machine_clears.maskmov"                            , 0x0, ATTR_NONE, 0x0 }, \
2217  \
2218 { 0xC4, 0x01, C_ALL, "br_inst_retired.conditional"                       , 0x0, ATTR_PEBS, 0x0 }, \
2219 { 0xC4, 0x02, C_ALL, "br_inst_retired.near_call"                         , 0x0, ATTR_PEBS, 0x0 }, \
2220 { 0xC4, 0x08, C_ALL, "br_inst_retired.near_return"                       , 0x0, ATTR_PEBS, 0x0 }, \
2221 { 0xC4, 0x10, C_ALL, "br_inst_retired.not_taken"                         , 0x0, ATTR_NONE, 0x0 }, \
2222 { 0xC4, 0x20, C_ALL, "br_inst_retired.near_taken"                        , 0x0, ATTR_PEBS, 0x0 }, \
2223 { 0xC4, 0x40, C_ALL, "br_inst_retired.far_branch"                        , 0x0, ATTR_NONE, 0x0 }, \
2224 { 0xC4, 0x02, C_ALL, "br_inst_retired.near_call_r3"                      , 0x0, ATTR_PEBS, 0x0 }, \
2225  \
2226 { 0xC5, 0x01, C_ALL, "br_misp_retired.conditional"                       , 0x0, ATTR_PEBS, 0x0 }, \
2227 { 0xC5, 0x20, C_ALL, "br_misp_retired.near_taken"                        , 0x0, ATTR_PEBS, 0x0 }, \
2228  \
2229 { 0xC7, 0x01, C_ALL, "fp_arith_inst_retired.scalar_double"               , 0x0, ATTR_PEBS, 0x0 }, \
2230 { 0xC7, 0x02, C_ALL, "fp_arith_inst_retired.scalar_single"               , 0x0, ATTR_PEBS, 0x0 }, \
2231 { 0xC7, 0x03, C_ALL, "fp_arith_inst_retired.scalar"                      , 0x0, ATTR_PEBS, 0x0 }, \
2232 { 0xC7, 0x04, C_ALL, "fp_arith_inst_retired.128b_packed_double"          , 0x0, ATTR_PEBS, 0x0 }, \
2233 { 0xC7, 0x08, C_ALL, "fp_arith_inst_retired.128b_packed_single"          , 0x0, ATTR_PEBS, 0x0 }, \
2234 { 0xC7, 0x10, C_ALL, "fp_arith_inst_retired.256b_packed_double"          , 0x0, ATTR_PEBS, 0x0 }, \
2235 { 0xC7, 0x15, C_ALL, "fp_arith_inst_retired.double"                      , 0x0, ATTR_PEBS, 0x0 }, \
2236 { 0xC7, 0x20, C_ALL, "fp_arith_inst_retired.256b_packed_single"          , 0x0, ATTR_PEBS, 0x0 }, \
2237 { 0xC7, 0x2A, C_ALL, "fp_arith_inst_retired.single"                      , 0x0, ATTR_PEBS, 0x0 }, \
2238 { 0xC7, 0x3C, C_ALL, "fp_arith_inst_retired.packed"                      , 0x0, ATTR_PEBS, 0x0 }, \
2239  \
2240 { 0xC8, 0x01, C_ALL, "hle_retired.start"                                 , 0x0, ATTR_TSX , 0x0 }, \
2241 { 0xC8, 0x02, C_ALL, "hle_retired.commit"                                , 0x0, ATTR_TSX , 0x0 }, \
2242 { 0xC8, 0x04, C_ALL, "hle_retired.aborted"                               , 0x0, ATTR_PEBS | ATTR_TSX, 0x0 }, \
2243 { 0xC8, 0x08, C_ALL, "hle_retired.aborted_misc1"                         , 0x0, ATTR_TSX , 0x0 }, \
2244 { 0xC8, 0x10, C_ALL, "hle_retired.aborted_misc2"                         , 0x0, ATTR_TSX , 0x0 }, \
2245 { 0xC8, 0x20, C_ALL, "hle_retired.aborted_misc3"                         , 0x0, ATTR_TSX , 0x0 }, \
2246 { 0xC8, 0x40, C_ALL, "hle_retired.aborted_misc4"                         , 0x0, ATTR_TSX , 0x0 }, \
2247 { 0xC8, 0x80, C_ALL, "hle_retired.aborted_misc5"                         , 0x0, ATTR_TSX , 0x0 }, \
2248  \
2249 { 0xC9, 0x01, C_ALL, "rtm_retired.start"                                 , 0x0, ATTR_TSX , 0x0 }, \
2250 { 0xC9, 0x02, C_ALL, "rtm_retired.commit"                                , 0x0, ATTR_TSX , 0x0 }, \
2251 { 0xC9, 0x04, C_ALL, "rtm_retired.aborted"                               , 0x0, ATTR_PEBS | ATTR_TSX, 0x0 }, \
2252 { 0xC9, 0x08, C_ALL, "rtm_retired.aborted_misc1"                         , 0x0, ATTR_TSX , 0x0 }, \
2253 { 0xC9, 0x10, C_ALL, "rtm_retired.aborted_misc2"                         , 0x0, ATTR_TSX , 0x0 }, \
2254 { 0xC9, 0x20, C_ALL, "rtm_retired.aborted_misc3"                         , 0x0, ATTR_TSX , 0x0 }, \
2255 { 0xC9, 0x40, C_ALL, "rtm_retired.aborted_misc4"                         , 0x0, ATTR_TSX , 0x0 }, \
2256 { 0xC9, 0x80, C_ALL, "rtm_retired.aborted_misc5"                         , 0x0, ATTR_TSX , 0x0 }, \
2257  \
2258 { 0xCA, 0x02, C_ALL, "fp_assist.x87_output"                              , 0x0, ATTR_NONE, 0x0 }, \
2259 { 0xCA, 0x04, C_ALL, "fp_assist.x87_input"                               , 0x0, ATTR_NONE, 0x0 }, \
2260 { 0xCA, 0x08, C_ALL, "fp_assist.simd_output"                             , 0x0, ATTR_NONE, 0x0 }, \
2261 { 0xCA, 0x10, C_ALL, "fp_assist.simd_input"                              , 0x0, ATTR_NONE, 0x0 }, \
2262 { 0xCA, 0x1E, C_ALL, "fp_assist.any"                                     , 0x1, ATTR_NONE, 0x0 }, \
2263  \
2264 { 0xCC, 0x20, C_ALL, "rob_misc_events.lbr_inserts"                       , 0x0, ATTR_NONE, 0x0 }, \
2265  \
2266 /* See Section "MSR_PEBS_LD_LAT_THRESHOLD" */ \
2267 /* { 0xCD, 0x01, C(3) , "mem_trans_retired.load_latency"                    , 0x0, ATTR_PEBS_ONLY_LD_LAT, PEBS_LD_LAT_THRESHOLD }, omit events requiring MSR programming */ \
2268  \
2269 /* \
2270  * Event 0xD0 must be combined with umasks 0x1(loads) or 0x2(stores) \
2271  */ \
2272 { 0xD0, 0x11, C_ALL, "mem_uops_retired.stlb_miss_loads"                  , 0x0, ATTR_PEBS, 0x0 }, \
2273 { 0xD0, 0x12, C_ALL, "mem_uops_retired.stlb_miss_stores"                 , 0x0, ATTR_PEBS, 0x0 }, \
2274 { 0xD0, 0x21, C_ALL, "mem_uops_retired.lock_loads"                       , 0x0, ATTR_PEBS, 0x0 }, \
2275 /* Private event, not public by Intel */ \
2276 { 0xD0, 0x22, C_ALL, "mem_uops_retired.lock_stores"                      , 0x0, ATTR_PEBS, 0x0 }, \
2277 { 0xD0, 0x41, C_ALL, "mem_uops_retired.split_loads"                      , 0x0, ATTR_PEBS, 0x0 }, \
2278 { 0xD0, 0x42, C_ALL, "mem_uops_retired.split_stores"                     , 0x0, ATTR_PEBS, 0x0 }, \
2279 { 0xD0, 0x81, C_ALL, "mem_uops_retired.all_loads"                        , 0x0, ATTR_PEBS, 0x0 }, \
2280 { 0xD0, 0x82, C_ALL, "mem_uops_retired.all_stores"                       , 0x0, ATTR_PEBS, 0x0 }, \
2281  \
2282 { 0xD1, 0x01, C_ALL, "mem_load_uops_retired.l1_hit"                      , 0x0, ATTR_PEBS, 0x0 }, \
2283 { 0xD1, 0x02, C_ALL, "mem_load_uops_retired.l2_hit"                      , 0x0, ATTR_PEBS, 0x0 }, \
2284 { 0xD1, 0x04, C_ALL, "mem_load_uops_retired.l3_hit"                      , 0x0, ATTR_PEBS, 0x0 }, \
2285 { 0xD1, 0x08, C_ALL, "mem_load_uops_retired.l1_miss"                     , 0x0, ATTR_PEBS, 0x0 }, \
2286 { 0xD1, 0x10, C_ALL, "mem_load_uops_retired.l2_miss"                     , 0x0, ATTR_PEBS, 0x0 }, \
2287 { 0xD1, 0x20, C_ALL, "mem_load_uops_retired.l3_miss"                     , 0x0, ATTR_PEBS, 0x0 }, \
2288 { 0xD1, 0x40, C_ALL, "mem_load_uops_retired.hit_lfb"                     , 0x0, ATTR_PEBS, 0x0 }, \
2289  \
2290 { 0xD2, 0x01, C_ALL, "mem_load_uops_l3_hit_retired.xsnp_miss"            , 0x0, ATTR_PEBS, 0x0 }, \
2291 { 0xD2, 0x02, C_ALL, "mem_load_uops_l3_hit_retired.xsnp_hit"             , 0x0, ATTR_PEBS, 0x0 }, \
2292 { 0xD2, 0x04, C_ALL, "mem_load_uops_l3_hit_retired.xsnp_hitm"            , 0x0, ATTR_PEBS, 0x0 }, \
2293 { 0xD2, 0x08, C_ALL, "mem_load_uops_l3_hit_retired.xsnp_none"            , 0x0, ATTR_PEBS, 0x0 }, \
2294  \
2295 { 0xD3, 0x01, C_ALL, "mem_load_uops_l3_miss_retired.local_dram"          , 0x0, ATTR_PEBS, 0x0 }, \
2296  \
2297 /* The mem_load_l4_miss_retired events are not in "cputrack -h" output nor in the Intel spreadsheet. */ \
2298 /* { 0xD5, 0x01, C_ALL, "mem_load_l4_miss_retired.local_hit"                , 0x0, ATTR_NONE, 0x0 }, */ \
2299 /* { 0xD5, 0x04, C_ALL, "mem_load_l4_miss_retired.local_miss"               , 0x0, ATTR_NONE, 0x0 }, */ \
2300  \
2301 { 0xE6, 0x1F, C_ALL, "baclears.any"                                      , 0x0, ATTR_NONE, 0x0 }, \
2302  \
2303 { 0xF0, 0x01, C_ALL, "l2_trans.demand_data_rd"                           , 0x0, ATTR_NONE, 0x0 }, \
2304 { 0xF0, 0x02, C_ALL, "l2_trans.rfo"                                      , 0x0, ATTR_NONE, 0x0 }, \
2305 { 0xF0, 0x04, C_ALL, "l2_trans.code_rd"                                  , 0x0, ATTR_NONE, 0x0 }, \
2306 { 0xF0, 0x08, C_ALL, "l2_trans.all_pf"                                   , 0x0, ATTR_NONE, 0x0 }, \
2307 { 0xF0, 0x10, C_ALL, "l2_trans.l1d_wb"                                   , 0x0, ATTR_NONE, 0x0 }, \
2308 { 0xF0, 0x20, C_ALL, "l2_trans.l2_fill"                                  , 0x0, ATTR_NONE, 0x0 }, \
2309 { 0xF0, 0x40, C_ALL, "l2_trans.l2_wb"                                    , 0x0, ATTR_NONE, 0x0 }, \
2310 { 0xF0, 0x80, C_ALL, "l2_trans.all_requests"                             , 0x0, ATTR_NONE, 0x0 }, \
2311  \
2312 { 0xF1, 0x01, C_ALL, "l2_lines_in.i"                                     , 0x0, ATTR_NONE, 0x0 }, \
2313 { 0xF1, 0x02, C_ALL, "l2_lines_in.s"                                     , 0x0, ATTR_NONE, 0x0 }, \
2314 { 0xF1, 0x04, C_ALL, "l2_lines_in.e"                                     , 0x0, ATTR_NONE, 0x0 }, \
2315 { 0xF1, 0x07, C_ALL, "l2_lines_in.all"                                   , 0x0, ATTR_NONE, 0x0 }, \
2316  \
2317 { 0xF2, 0x05, C_ALL, "l2_lines_out.demand_clean"                         , 0x0, ATTR_NONE, 0x0 }, \
2318 /* end of #define */
2319
2320
2321 /* Intel Skylake Processor */
2322 /*
2323  * This table is essentially taken from:
2324  *   https://grok.cz.oracle.com/source/xref/on12-clone/usr/src/uts/intel/pcbe/skl_pcbe_tbl.c
2325  * Also:
2326  *   https://grok.cz.oracle.com/source/xref/on12-clone/usr/src/uts/intel/pcbe/fam6_pcbe.h
2327  * { 0xc0, 0x00, C_ALL, "inst_retired.any_p" },         \
2328  * { 0x3c, 0x01, C_ALL, "cpu_clk_unhalted.ref_p" },     \
2329  * { 0x2e, 0x4f, C_ALL, "longest_lat_cache.reference" },        \
2330  * { 0x2e, 0x41, C_ALL, "longest_lat_cache.miss" },     \
2331  * { 0xc4, 0x00, C_ALL, "br_inst_retired.all_branches" },       \
2332  * { 0xc5, 0x00, C_ALL, "br_misp_retired.all_branches" }
2333  * And:
2334  * https://grok.cz.oracle.com/source/xref/on12-clone/usr/src/uts/intel/pcbe/core_pcbe.c
2335  *      { 0x3c, 0x00, C_ALL, "cpu_clk_unhalted.core" },
2336  *      { 0x3c, 0x00, C_ALL, "cpu_clk_unhalted.thread_p" },
2337  */
2338 #define EVENTS_FAM6_MOD78 \
2339 { 0x03, 0x02, C_ALL, "ld_blocks.store_forward"                           , 0x0, ATTR_NONE, 0x0 }, \
2340 { 0x03, 0x08, C_ALL, "ld_blocks.no_sr"                                   , 0x0, ATTR_NONE, 0x0 }, \
2341 { 0x07, 0x01, C_ALL, "ld_blocks_partial.address_alias"                   , 0x0, ATTR_NONE, 0x0 }, \
2342 { 0x08, 0x01, C_ALL, "dtlb_load_misses.miss_causes_a_walk"               , 0x0, ATTR_NONE, 0x0 }, \
2343 { 0x08, 0x02, C_ALL, "dtlb_load_misses.walk_completed_4k"                , 0x0, ATTR_NONE, 0x0 }, \
2344 { 0x08, 0x04, C_ALL, "dtlb_load_misses.walk_completed_2m_4m"             , 0x0, ATTR_NONE, 0x0 }, \
2345 { 0x08, 0x08, C_ALL, "dtlb_load_misses.walk_completed_1g"                , 0x0, ATTR_NONE, 0x0 }, \
2346 { 0x08, 0x0E, C_ALL, "dtlb_load_misses.walk_completed"                   , 0x0, ATTR_NONE, 0x0 }, \
2347 { 0x08, 0x10, C_ALL, "dtlb_load_misses.walk_pending"                     , 0x0, ATTR_NONE, 0x0 }, \
2348 { 0x08, 0x10, C_ALL, "dtlb_load_misses.walk_active"                      , 0x1, ATTR_NONE, 0x0 }, \
2349 { 0x08, 0x20, C_ALL, "dtlb_load_misses.stlb_hit"                         , 0x0, ATTR_NONE, 0x0 }, \
2350 { 0x0D, 0x01, C_ALL, "int_misc.recovery_cycles"                          , 0x0, ATTR_NONE, 0x0 }, \
2351 { 0x0D, 0x01, C_ALL, "int_misc.recovery_cycles_any"                      , 0x0, ATTR_ANY, 0x0 }, \
2352 { 0x0D, 0x80, C_ALL, "int_misc.clear_resteer_cycles"                     , 0x0, ATTR_NONE, 0x0 }, \
2353 { 0x0E, 0x01, C_ALL, "uops_issued.any"                                   , 0x0, ATTR_NONE, 0x0 }, \
2354 { 0x0E, 0x01, C_ALL, "uops_issued.stall_cycles"                          , 0x1, ATTR_INV, 0x0 }, \
2355 { 0x0E, 0x02, C_ALL, "uops_issued.vector_width_mismatch"                 , 0x0, ATTR_NONE, 0x0 }, \
2356 { 0x0E, 0x20, C_ALL, "uops_issued.slow_lea"                              , 0x0, ATTR_NONE, 0x0 }, \
2357 { 0x14, 0x01, C_ALL, "arith.divider_active"                              , 0x1, ATTR_NONE, 0x0 }, \
2358 { 0x24, 0x21, C_ALL, "l2_rqsts.demand_data_rd_miss"                      , 0x0, ATTR_NONE, 0x0 }, \
2359 { 0x24, 0x22, C_ALL, "l2_rqsts.rfo_miss"                                 , 0x0, ATTR_NONE, 0x0 }, \
2360 { 0x24, 0x24, C_ALL, "l2_rqsts.code_rd_miss"                             , 0x0, ATTR_NONE, 0x0 }, \
2361 { 0x24, 0x27, C_ALL, "l2_rqsts.all_demand_miss"                          , 0x0, ATTR_NONE, 0x0 }, \
2362 { 0x24, 0x38, C_ALL, "l2_rqsts.pf_miss"                                  , 0x0, ATTR_NONE, 0x0 }, \
2363 { 0x24, 0x3F, C_ALL, "l2_rqsts.miss"                                     , 0x0, ATTR_NONE, 0x0 }, \
2364 { 0x24, 0x41, C_ALL, "l2_rqsts.demand_data_rd_hit"                       , 0x0, ATTR_NONE, 0x0 }, \
2365 { 0x24, 0x42, C_ALL, "l2_rqsts.rfo_hit"                                  , 0x0, ATTR_NONE, 0x0 }, \
2366 { 0x24, 0x44, C_ALL, "l2_rqsts.code_rd_hit"                              , 0x0, ATTR_NONE, 0x0 }, \
2367 { 0x24, 0xD8, C_ALL, "l2_rqsts.pf_hit"                                   , 0x0, ATTR_NONE, 0x0 }, \
2368 { 0x24, 0xE1, C_ALL, "l2_rqsts.all_demand_data_rd"                       , 0x0, ATTR_NONE, 0x0 }, \
2369 { 0x24, 0xE2, C_ALL, "l2_rqsts.all_rfo"                                  , 0x0, ATTR_NONE, 0x0 }, \
2370 { 0x24, 0xE4, C_ALL, "l2_rqsts.all_code_rd"                              , 0x0, ATTR_NONE, 0x0 }, \
2371 { 0x24, 0xE7, C_ALL, "l2_rqsts.all_demand_references"                    , 0x0, ATTR_NONE, 0x0 }, \
2372 { 0x24, 0xF8, C_ALL, "l2_rqsts.all_pf"                                   , 0x0, ATTR_NONE, 0x0 }, \
2373 { 0x24, 0xFF, C_ALL, "l2_rqsts.references"                               , 0x0, ATTR_NONE, 0x0 }, \
2374 { 0x2e, 0x4f, C_ALL, "longest_lat_cache.reference"                       , 0x0, ATTR_NONE, 0x0 }, \
2375 { 0x2e, 0x41, C_ALL, "longest_lat_cache.miss"                            , 0x0, ATTR_NONE, 0x0 }, \
2376 { 0x3c, 0x00, C_ALL, "cpu_clk_unhalted.thread_p"                         , 0x0, ATTR_NONE, 0x0 }, \
2377 { 0x3C, 0x00, C_ALL, "cpu_clk_unhalted.thread_p_any"                     , 0x0, ATTR_ANY, 0x0 }, \
2378 { 0x3C, 0x00, C_ALL, "cpu_clk_unhalted.ring0_trans"                      , 0x1, ATTR_EDGE, 0x0 }, \
2379 { 0x3C, 0x01, C_ALL, "cpu_clk_unhalted.ref_p"                            , 0x0, ATTR_NONE, 0x0 }, \
2380 { 0x3C, 0x01, C_ALL, "cpu_clk_thread_unhalted.ref_xclk"                  , 0x0, ATTR_NONE, 0x0 }, \
2381 { 0x3C, 0x01, C_ALL, "cpu_clk_thread_unhalted.ref_xclk_any"              , 0x0, ATTR_ANY, 0x0 }, \
2382 { 0x3C, 0x02, C_ALL, "cpu_clk_thread_unhalted.one_thread_active"         , 0x0, ATTR_NONE, 0x0 }, \
2383 { 0x48, 0x01, C_ALL, "l1d_pend_miss.pending"                             , 0x0, ATTR_NONE, 0x0 }, \
2384 { 0x48, 0x01, C_ALL, "l1d_pend_miss.pending_cycles"                      , 0x1, ATTR_NONE, 0x0 }, \
2385 { 0x48, 0x01, C_ALL, "l1d_pend_miss.pending_cycles_any"                  , 0x1, ATTR_ANY, 0x0 }, \
2386 { 0x48, 0x02, C_ALL, "l1d_pend_miss.fb_full"                             , 0x0, ATTR_NONE, 0x0 }, \
2387 { 0x49, 0x01, C_ALL, "dtlb_store_misses.miss_causes_a_walk"              , 0x0, ATTR_NONE, 0x0 }, \
2388 { 0x49, 0x02, C_ALL, "dtlb_store_misses.walk_completed_4k"               , 0x0, ATTR_NONE, 0x0 }, \
2389 { 0x49, 0x04, C_ALL, "dtlb_store_misses.walk_completed_2m_4m"            , 0x0, ATTR_NONE, 0x0 }, \
2390 { 0x49, 0x08, C_ALL, "dtlb_store_misses.walk_completed_1g"               , 0x0, ATTR_NONE, 0x0 }, \
2391 { 0x49, 0x0E, C_ALL, "dtlb_store_misses.walk_completed"                  , 0x0, ATTR_NONE, 0x0 }, \
2392 { 0x49, 0x10, C_ALL, "dtlb_store_misses.walk_pending"                    , 0x0, ATTR_NONE, 0x0 }, \
2393 { 0x49, 0x10, C_ALL, "dtlb_store_misses.walk_active"                     , 0x1, ATTR_NONE, 0x0 }, \
2394 { 0x49, 0x20, C_ALL, "dtlb_store_misses.stlb_hit"                        , 0x0, ATTR_NONE, 0x0 }, \
2395 { 0x4C, 0x01, C_ALL, "load_hit_pre.sw_pf"                                , 0x0, ATTR_NONE, 0x0 }, \
2396 { 0x4F, 0x10, C_ALL, "ept.walk_pending"                                  , 0x0, ATTR_NONE, 0x0 }, \
2397 { 0x51, 0x01, C_ALL, "l1d.replacement"                                   , 0x0, ATTR_NONE, 0x0 }, \
2398 { 0x54, 0x01, C_ALL, "tx_mem.abort_conflict"                             , 0x0, ATTR_TSX, 0x0 }, \
2399 { 0x54, 0x02, C_ALL, "tx_mem.abort_capacity"                             , 0x0, ATTR_TSX, 0x0 }, \
2400 { 0x54, 0x04, C_ALL, "tx_mem.abort_hle_store_to_elided_lock"             , 0x0, ATTR_TSX, 0x0 }, \
2401 { 0x54, 0x08, C_ALL, "tx_mem.abort_hle_elision_buffer_not_empty"         , 0x0, ATTR_TSX, 0x0 }, \
2402 { 0x54, 0x10, C_ALL, "tx_mem.abort_hle_elision_buffer_mismatch"          , 0x0, ATTR_TSX, 0x0 }, \
2403 { 0x54, 0x20, C_ALL, "tx_mem.abort_hle_elision_buffer_unsupported_alignment",   0x0, ATTR_TSX, 0x0 }, \
2404 { 0x54, 0x40, C_ALL, "tx_mem.hle_elision_buffer_full"                    , 0x0, ATTR_TSX, 0x0 }, \
2405 { 0x5D, 0x01, C_ALL, "tx_exec.misc1"                                     , 0x0, ATTR_TSX, 0x0 }, \
2406 { 0x5D, 0x02, C_ALL, "tx_exec.misc2"                                     , 0x0, ATTR_TSX, 0x0 }, \
2407 { 0x5D, 0x04, C_ALL, "tx_exec.misc3"                                     , 0x0, ATTR_TSX, 0x0 }, \
2408 { 0x5D, 0x08, C_ALL, "tx_exec.misc4"                                     , 0x0, ATTR_TSX, 0x0 }, \
2409 { 0x5D, 0x10, C_ALL, "tx_exec.misc5"                                     , 0x0, ATTR_TSX, 0x0 }, \
2410 { 0x5E, 0x01, C_ALL, "rs_events.empty_cycles"                            , 0x0, ATTR_NONE, 0x0 }, \
2411 { 0x5E, 0x01, C_ALL, "rs_events.empty_end"                               , 0x1, (ATTR_INV | ATTR_EDGE), 0x0 }, \
2412 { 0x60, 0x01, C_ALL, "offcore_requests_outstanding.demand_data_rd"       , 0x0, ATTR_NONE, 0x0 }, \
2413 { 0x60, 0x01, C_ALL, "offcore_requests_outstanding.cycles_with_demand_data_rd", 0x1, ATTR_NONE, 0x0 }, \
2414 { 0x60, 0x01, C_ALL, "offcore_requests_outstanding.demand_data_rd_ge_6"  , 0x6, ATTR_NONE, 0x0 }, \
2415 { 0x60, 0x02, C_ALL, "offcore_requests_outstanding.demand_code_rd"       , 0x0, ATTR_NONE, 0x0 }, \
2416 { 0x60, 0x02, C_ALL, "offcore_requests_outstanding.cycles_with_demand_code_rd", 0x1, ATTR_NONE, 0x0 }, \
2417 { 0x60, 0x04, C_ALL, "offcore_requests_outstanding.demand_rfo"           , 0x0, ATTR_NONE, 0x0 }, \
2418 { 0x60, 0x04, C_ALL, "offcore_requests_outstanding.cycles_with_demand_rfo",0x1, ATTR_NONE, 0x0 }, \
2419 { 0x60, 0x08, C_ALL, "offcore_requests_outstanding.all_data_rd"          , 0x0, ATTR_NONE, 0x0 }, \
2420 { 0x60, 0x08, C_ALL, "offcore_requests_outstanding.cycles_with_data_rd"  , 0x1, ATTR_NONE, 0x0 }, \
2421 { 0x60, 0x10, C_ALL, "offcore_requests_outstanding.l3_miss_demand_data_rd",0x0, ATTR_NONE, 0x0 }, \
2422 { 0x60, 0x10, C_ALL, "offcore_requests_outstanding.cycles_with_l3_miss_demand_data_rd", 0x1, ATTR_NONE, 0x0 }, \
2423 { 0x60, 0x10, C_ALL, "offcore_requests_outstanding.l3_miss_demand_data_rd_ge_6",0x6, ATTR_NONE, 0x0 }, \
2424 { 0x79, 0x04, C_ALL, "idq.mite_uops"                                     , 0x0, ATTR_NONE, 0x0 }, \
2425 { 0x79, 0x04, C_ALL, "idq.mite_cycles"                                   , 0x1, ATTR_NONE, 0x0 }, \
2426 { 0x79, 0x08, C_ALL, "idq.dsb_uops"                                      , 0x0, ATTR_NONE, 0x0 }, \
2427 { 0x79, 0x08, C_ALL, "idq.dsb_cycles"                                    , 0x1, ATTR_NONE, 0x0 }, \
2428 { 0x79, 0x10, C_ALL, "idq.ms_dsb_cycles"                                 , 0x1, ATTR_NONE, 0x0 }, \
2429 { 0x79, 0x18, C_ALL, "idq.all_dsb_cycles_4_uops"                         , 0x4, ATTR_NONE, 0x0 }, \
2430 { 0x79, 0x18, C_ALL, "idq.all_dsb_cycles_any_uops"                       , 0x1, ATTR_NONE, 0x0 }, \
2431 { 0x79, 0x20, C_ALL, "idq.ms_mite_uops"                                  , 0x0, ATTR_NONE, 0x0 }, \
2432 { 0x79, 0x24, C_ALL, "idq.all_mite_cycles_4_uops"                        , 0x4, ATTR_NONE, 0x0 }, \
2433 { 0x79, 0x24, C_ALL, "idq.all_mite_cycles_any_uops"                      , 0x1, ATTR_NONE, 0x0 }, \
2434 { 0x79, 0x30, C_ALL, "idq.ms_uops"                                       , 0x0, ATTR_NONE, 0x0 }, \
2435 { 0x79, 0x30, C_ALL, "idq.ms_cycles"                                     , 0x1, ATTR_NONE, 0x0 }, \
2436 { 0x79, 0x30, C_ALL, "idq.ms_switches"                                   , 0x1, ATTR_EDGE, 0x0 }, \
2437 { 0x80, 0x04, C_ALL, "icache_16b.ifdata_stall"                           , 0x0, ATTR_NONE, 0x0 }, \
2438 { 0x83, 0x01, C_ALL, "icache_64b.iftag_hit"                              , 0x0, ATTR_NONE, 0x0 }, \
2439 { 0x83, 0x02, C_ALL, "icache_64b.iftag_miss"                             , 0x0, ATTR_NONE, 0x0 }, \
2440 { 0x83, 0x04, C_ALL, "icache_64b.iftag_stall"                            , 0x0, ATTR_NONE, 0x0 }, \
2441 { 0x85, 0x01, C_ALL, "itlb_misses.miss_causes_a_walk"                    , 0x0, ATTR_NONE, 0x0 }, \
2442 { 0x85, 0x02, C_ALL, "itlb_misses.walk_completed_4k"                     , 0x0, ATTR_NONE, 0x0 }, \
2443 { 0x85, 0x04, C_ALL, "itlb_misses.walk_completed_2m_4m"                  , 0x0, ATTR_NONE, 0x0 }, \
2444 { 0x85, 0x08, C_ALL, "itlb_misses.walk_completed_1g"                     , 0x0, ATTR_NONE, 0x0 }, \
2445 { 0x85, 0x0E, C_ALL, "itlb_misses.walk_completed"                        , 0x0, ATTR_NONE, 0x0 }, \
2446 { 0x85, 0x10, C_ALL, "itlb_misses.walk_pending"                          , 0x0, ATTR_NONE, 0x0 }, \
2447 { 0x85, 0x10, C_ALL, "itlb_misses.walk_active"                           , 0x1, ATTR_NONE, 0x0 }, \
2448 { 0x85, 0x20, C_ALL, "itlb_misses.stlb_hit"                              , 0x0, ATTR_NONE, 0x0 }, \
2449 { 0x87, 0x01, C_ALL, "ild_stall.lcp"                                     , 0x0, ATTR_NONE, 0x0 }, \
2450 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.core"                       , 0x0, ATTR_NONE, 0x0 }, \
2451 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.cycles_0_uops_deliv.core"   , 0x4, ATTR_NONE, 0x0 }, \
2452 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.cycles_le_1_uop_deliv.core" , 0x3, ATTR_NONE, 0x0 }, \
2453 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.cycles_le_2_uop_deliv.core" , 0x2, ATTR_NONE, 0x0 }, \
2454 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.cycles_le_3_uop_deliv.core" , 0x1, ATTR_NONE, 0x0 }, \
2455 { 0x9C, 0x01, C_ALL, "idq_uops_not_delivered.cycles_fe_was_ok"           , 0x1, ATTR_INV, 0x0 }, \
2456 { 0xA1, 0x01, C_ALL, "uops_dispatched_port.port_0"                       , 0x0, ATTR_NONE, 0x0 }, \
2457 { 0xA1, 0x02, C_ALL, "uops_dispatched_port.port_1"                       , 0x0, ATTR_NONE, 0x0 }, \
2458 { 0xA1, 0x04, C_ALL, "uops_dispatched_port.port_2"                       , 0x0, ATTR_NONE, 0x0 }, \
2459 { 0xA1, 0x08, C_ALL, "uops_dispatched_port.port_3"                       , 0x0, ATTR_NONE, 0x0 }, \
2460 { 0xA1, 0x10, C_ALL, "uops_dispatched_port.port_4"                       , 0x0, ATTR_NONE, 0x0 }, \
2461 { 0xA1, 0x20, C_ALL, "uops_dispatched_port.port_5"                       , 0x0, ATTR_NONE, 0x0 }, \
2462 { 0xA1, 0x40, C_ALL, "uops_dispatched_port.port_6"                       , 0x0, ATTR_NONE, 0x0 }, \
2463 { 0xA1, 0x80, C_ALL, "uops_dispatched_port.port_7"                       , 0x0, ATTR_NONE, 0x0 }, \
2464 { 0xA2, 0x01, C_ALL, "resource_stalls.any"                               , 0x0, ATTR_NONE, 0x0 }, \
2465 { 0xA2, 0x08, C_ALL, "resource_stalls.sb"                                , 0x0, ATTR_NONE, 0x0 }, \
2466 { 0xA3, 0x01, C_ALL, "cycle_activity.cycles_l2_miss"                     , 0x1, ATTR_NONE, 0x0 }, \
2467 { 0xA3, 0x02, C_ALL, "cycle_activity.cycles_l3_miss"                     , 0x2, ATTR_NONE, 0x0 }, \
2468 { 0xA3, 0x04, C_ALL, "cycle_activity.stalls_total"                       , 0x4, ATTR_NONE, 0x0 }, \
2469 { 0xA3, 0x05, C_ALL, "cycle_activity.stalls_l2_miss"                     , 0x5, ATTR_NONE, 0x0 }, \
2470 { 0xA3, 0x06, C_ALL, "cycle_activity.stalls_l3_miss"                     , 0x6, ATTR_NONE, 0x0 }, \
2471 { 0xA3, 0x08, C_ALL, "cycle_activity.cycles_l1d_miss"                    , 0x8, ATTR_NONE, 0x0 }, \
2472 { 0xA3, 0x0C, C_ALL, "cycle_activity.stalls_l1d_miss"                    , 0xC, ATTR_NONE, 0x0 }, \
2473 { 0xA3, 0x10, C_ALL, "cycle_activity.cycles_mem_any"                     , 0x10,ATTR_NONE, 0x0 }, \
2474 { 0xA3, 0x14, C_ALL, "cycle_activity.stalls_mem_any"                     , 0x14,ATTR_NONE, 0x0 }, \
2475 { 0xA6, 0x01, C_ALL, "exe_activity.exe_bound_0_ports"                    , 0x0, ATTR_NONE, 0x0 }, \
2476 { 0xA6, 0x02, C_ALL, "exe_activity.1_ports_util"                         , 0x0, ATTR_NONE, 0x0 }, \
2477 { 0xA6, 0x04, C_ALL, "exe_activity.2_ports_util"                         , 0x0, ATTR_NONE, 0x0 }, \
2478 { 0xA6, 0x08, C_ALL, "exe_activity.3_ports_util"                         , 0x0, ATTR_NONE, 0x0 }, \
2479 { 0xA6, 0x10, C_ALL, "exe_activity.4_ports_util"                         , 0x0, ATTR_NONE, 0x0 }, \
2480 { 0xA6, 0x40, C_ALL, "exe_activity.bound_on_stores"                      , 0x0, ATTR_NONE, 0x0 }, \
2481 { 0xA8, 0x01, C_ALL, "lsd.uops"                                          , 0x0, ATTR_NONE, 0x0 }, \
2482 { 0xA8, 0x01, C_ALL, "lsd.cycles_active"                                 , 0x1, ATTR_NONE, 0x0 }, \
2483 { 0xA8, 0x01, C_ALL, "lsd.cycles_4_uops"                                 , 0x4, ATTR_NONE, 0x0 }, \
2484 { 0xAB, 0x02, C_ALL, "dsb2mite_switches.penalty_cycles"                  , 0x0, ATTR_NONE, 0x0 }, \
2485 { 0xAE, 0x01, C_ALL, "itlb.itlb_flush"                                   , 0x0, ATTR_NONE, 0x0 }, \
2486 { 0xB0, 0x01, C_ALL, "offcore_requests.demand_data_rd"                   , 0x0, ATTR_NONE, 0x0 }, \
2487 { 0xB0, 0x02, C_ALL, "offcore_requests.demand_code_rd"                   , 0x0, ATTR_NONE, 0x0 }, \
2488 { 0xB0, 0x04, C_ALL, "offcore_requests.demand_rfo"                       , 0x0, ATTR_NONE, 0x0 }, \
2489 { 0xB0, 0x08, C_ALL, "offcore_requests.all_data_rd"                      , 0x0, ATTR_NONE, 0x0 }, \
2490 { 0xB0, 0x10, C_ALL, "offcore_requests.l3_miss_demand_data_rd"           , 0x0, ATTR_NONE, 0x0 }, \
2491 { 0xB0, 0x80, C_ALL, "offcore_requests.all_requests"                     , 0x0, ATTR_NONE, 0x0 }, \
2492 { 0xB1, 0x01, C_ALL, "uops_executed.thread"                              , 0x0, ATTR_NONE, 0x0 }, \
2493 { 0xB1, 0x01, C_ALL, "uops_executed.cycles_ge_1_uop_exec"                , 0x1, ATTR_NONE, 0x0 }, \
2494 { 0xB1, 0x01, C_ALL, "uops_executed.cycles_ge_2_uops_exec"               , 0x2, ATTR_NONE, 0x0 }, \
2495 { 0xB1, 0x01, C_ALL, "uops_executed.cycles_ge_3_uops_exec"               , 0x3, ATTR_NONE, 0x0 }, \
2496 { 0xB1, 0x01, C_ALL, "uops_executed.cycles_ge_4_uops_exec"               , 0x4, ATTR_NONE, 0x0 }, \
2497 { 0xB1, 0x01, C_ALL, "uops_executed.stall_cycles"                        , 0x1, ATTR_INV, 0x0 }, \
2498 { 0xB1, 0x02, C_ALL, "uops_executed.core"                                , 0x0, ATTR_NONE, 0x0 }, \
2499 { 0xB1, 0x02, C_ALL, "uops_executed.core_cycles_none"                    , 0x1, ATTR_INV, 0x0 }, \
2500 { 0xB1, 0x02, C_ALL, "uops_executed.core_cycles_ge_1"                    , 0x1, ATTR_NONE, 0x0 }, \
2501 { 0xB1, 0x02, C_ALL, "uops_executed.core_cycles_ge_2"                    , 0x2, ATTR_NONE, 0x0 }, \
2502 { 0xB1, 0x02, C_ALL, "uops_executed.core_cycles_ge_3"                    , 0x3, ATTR_NONE, 0x0 }, \
2503 { 0xB1, 0x02, C_ALL, "uops_executed.core_cycles_ge_4"                    , 0x4, ATTR_NONE, 0x0 }, \
2504 { 0xB1, 0x10, C_ALL, "uops_executed.x87"                                 , 0x0, ATTR_NONE, 0x0 }, \
2505 { 0xB2, 0x01, C_ALL, "offcore_requests_buffer.sq_full"                   , 0x0, ATTR_NONE, 0x0 }, \
2506 \
2507         /* \
2508          * See Section "Off-core Response Performance Monitoring" \
2509          * \
2510          * Though these two off_core events support all counters, only 1 of \
2511          * them can be used at any given time. This is due to the extra MSR \
2512          * programming required. \
2513          */ \
2514 /* { 0xB7, 0x01, C_ALL, "offcore_response_0"                             , 0x0, ATTR_NONE, OFFCORE_RSP_0 }, omit events requiring MSR programming */ \
2515 /* { 0xBB, 0x01, C_ALL, "offcore_response_1"                             , 0x0, ATTR_NONE, OFFCORE_RSP_1 }, omit events requiring MSR programming */ \
2516 { 0xBD, 0x01, C_ALL, "tlb_flush.dtlb_thread"                             , 0x0, ATTR_NONE, 0x0 }, \
2517 { 0xBD, 0x20, C_ALL, "tlb_flush.stlb_any"                                , 0x0, ATTR_NONE, 0x0 }, \
2518 { 0xc0, 0x00, C_ALL, "inst_retired.any_p"                                , 0x0, ATTR_NONE, 0x0 }, \
2519 /* { 0xC0, 0x1, C(1), "inst_retired.prec_dist"                              , 0x0, ATTR_PEBS_ONLY, 0x0 }, omit PEBS-only events */ \
2520 /* { 0xC0, 0x1, (C(0) | C(2) | C(3)), "inst_retired.total_cycles_ps"        , 0x0A, (ATTR_PEBS_ONLY | ATTR_INV), 0x0 }, omit PEBS-only events */ \
2521 { 0xC1, 0x3F, C_ALL, "other_assists.any"                                 , 0x0, ATTR_NONE, 0x0 }, \
2522 { 0xC2, 0x01, C_ALL, "uops_retired.stall_cycles"                         , 0x1, ATTR_INV, 0x0 }, \
2523 { 0xC2, 0x01, C_ALL, "uops_retired.total_cycles"                         , 0x0A, ATTR_INV, 0x0 }, \
2524 { 0xC2, 0x02, C_ALL, "uops_retired.retire_slots"                         , 0x0, ATTR_NONE, 0x0 }, \
2525 { 0xC3, 0x01, C_ALL, "machine_clears.count"                              , 0x1, ATTR_EDGE, 0x0 }, \
2526 { 0xC3, 0x02, C_ALL, "machine_clears.memory_ordering"                    , 0x0, ATTR_NONE, 0x0 }, \
2527 { 0xC3, 0x04, C_ALL, "machine_clears.smc"                                , 0x0, ATTR_NONE, 0x0 }, \
2528 { 0xc4, 0x00, C_ALL, "br_inst_retired.all_branches"                      , 0x0, ATTR_NONE, 0x0 }, \
2529 { 0xC4, 0x01, C_ALL, "br_inst_retired.conditional"                       , 0x0, ATTR_PEBS, 0x0 }, \
2530 { 0xC4, 0x02, C_ALL, "br_inst_retired.near_call"                         , 0x0, ATTR_PEBS, 0x0 }, \
2531 /* { 0xC4, 0x04, C_ALL, "br_inst_retired.all_branches_pebs"                 , 0x0, ATTR_PEBS_ONLY, 0x0 }, omit PEBS-only events */ \
2532 { 0xC4, 0x08, C_ALL, "br_inst_retired.near_return"                       , 0x0, ATTR_PEBS, 0x0 }, \
2533 { 0xC4, 0x10, C_ALL, "br_inst_retired.not_taken"                         , 0x0, ATTR_NONE, 0x0 }, \
2534 { 0xC4, 0x20, C_ALL, "br_inst_retired.near_taken"                        , 0x0, ATTR_PEBS, 0x0 }, \
2535 { 0xC4, 0x40, C_ALL, "br_inst_retired.far_branch"                        , 0x0, ATTR_PEBS, 0x0 }, \
2536 { 0xc5, 0x00, C_ALL, "br_misp_retired.all_branches"                      , 0x0, ATTR_NONE, 0x0 }, \
2537 { 0xC5, 0x01, C_ALL, "br_misp_retired.conditional"                       , 0x0, ATTR_PEBS, 0x0 }, \
2538 { 0xC5, 0x02, C_ALL, "br_misp_retired.near_call"                         , 0x0, ATTR_PEBS, 0x0 }, \
2539 /* { 0xC5, 0x04, C_ALL, "br_misp_retired.all_branches_pebs"                 , 0x0, ATTR_PEBS_ONLY, 0x0 }, omit PEBS-only events */ \
2540 { 0xC5, 0x20, C_ALL, "br_misp_retired.near_taken"                        , 0x0, ATTR_PEBS, 0x0 }, \
2541 /* { 0xC6, 0x01, C_ALL, "frontend_retired"                                  , 0x0, ATTR_PEBS, MSR_PEBS_FRONTEND}, omit events requiring MSR programming */ \
2542 { 0xC7, 0x01, C_ALL, "fp_arith_inst_retired.scalar_double"               , 0x0, ATTR_NONE, 0x0 }, \
2543 { 0xC7, 0x02, C_ALL, "fp_arith_inst_retired.scalar_single"               , 0x0, ATTR_NONE, 0x0 }, \
2544 { 0xC7, 0x04, C_ALL, "fp_arith_inst_retired.128b_packed_double"          , 0x0, ATTR_NONE, 0x0 }, \
2545 { 0xC7, 0x08, C_ALL, "fp_arith_inst_retired.128b_packed_single"          , 0x0, ATTR_NONE, 0x0 }, \
2546 { 0xC7, 0x10, C_ALL, "fp_arith_inst_retired.256b_packed_double"          , 0x0, ATTR_NONE, 0x0 }, \
2547 { 0xC7, 0x20, C_ALL, "fp_arith_inst_retired.256b_packed_single"          , 0x0, ATTR_NONE, 0x0 }, \
2548 { 0xC8, 0x01, C_ALL, "hle_retired.start"                                 , 0x0, ATTR_TSX, 0x0 }, \
2549 { 0xC8, 0x02, C_ALL, "hle_retired.commit"                                , 0x0, ATTR_TSX, 0x0 }, \
2550 { 0xC8, 0x04, C_ALL, "hle_retired.aborted"                               , 0x0, ATTR_PEBS | ATTR_TSX, 0x0 }, \
2551 { 0xC8, 0x08, C_ALL, "hle_retired.aborted_mem"                           , 0x0, ATTR_TSX, 0x0 }, \
2552 { 0xC8, 0x10, C_ALL, "hle_retired.aborted_timer"                         , 0x0, ATTR_TSX, 0x0 }, \
2553 { 0xC8, 0x20, C_ALL, "hle_retired.aborted_unfriendly"                    , 0x0, ATTR_TSX, 0x0 }, \
2554 { 0xC8, 0x40, C_ALL, "hle_retired.aborted_memtype"                       , 0x0, ATTR_TSX, 0x0 }, \
2555 { 0xC8, 0x80, C_ALL, "hle_retired.aborted_events"                        , 0x0, ATTR_TSX, 0x0 }, \
2556 { 0xC9, 0x01, C_ALL, "rtm_retired.start"                                 , 0x0, ATTR_TSX, 0x0 }, \
2557 { 0xC9, 0x02, C_ALL, "rtm_retired.commit"                                , 0x0, ATTR_TSX, 0x0 }, \
2558 { 0xC9, 0x04, C_ALL, "rtm_retired.aborted"                               , 0x0, ATTR_PEBS | ATTR_TSX, 0x0 }, \
2559 { 0xC9, 0x08, C_ALL, "rtm_retired.aborted_mem"                           , 0x0, ATTR_TSX, 0x0 }, \
2560 { 0xC9, 0x10, C_ALL, "rtm_retired.aborted_timer"                         , 0x0, ATTR_TSX, 0x0 }, \
2561 { 0xC9, 0x20, C_ALL, "rtm_retired.aborted_unfriendly"                    , 0x0, ATTR_TSX, 0x0 }, \
2562 { 0xC9, 0x40, C_ALL, "rtm_retired.aborted_memtype"                       , 0x0, ATTR_TSX, 0x0 }, \
2563 { 0xC9, 0x80, C_ALL, "rtm_retired.aborted_events"                        , 0x0, ATTR_TSX, 0x0 }, \
2564 { 0xCA, 0x1E, C_ALL, "fp_assist.any"                                     , 0x1, ATTR_NONE, 0x0 }, \
2565 { 0xCB, 0x01, C_ALL, "hw_interrupts.received"                            , 0x0, ATTR_NONE, 0x0 }, \
2566 { 0xCC, 0x20, C_ALL, "rob_misc_events.lbr_inserts"                       , 0x0, ATTR_NONE, 0x0 }, \
2567 /* { 0xCD, 0x01, C_ALL, "mem_trans_retired.load_latency"                    , 0x0, ATTR_PEBS_ONLY_LD_LAT, PEBS_LD_LAT_THRESHOLD }, omit events requiring MSR programming */ \
2568 { 0xD0, 0x11, C_ALL, "mem_inst_retired.stlb_miss_loads"                 , 0x0, ATTR_PEBS, 0x0 }, \
2569 { 0xD0, 0x12, C_ALL, "mem_inst_retired.stlb_miss_stores"                 , 0x0, ATTR_PEBS, 0x0 }, \
2570 { 0xD0, 0x21, C_ALL, "mem_inst_retired.lock_loads"                       , 0x0, ATTR_PEBS, 0x0 }, \
2571 { 0xD0, 0x41, C_ALL, "mem_inst_retired.split_loads"                      , 0x0, ATTR_PEBS, 0x0 }, \
2572 { 0xD0, 0x42, C_ALL, "mem_inst_retired.split_stores"                     , 0x0, ATTR_PEBS, 0x0 }, \
2573 { 0xD0, 0x81, C_ALL, "mem_inst_retired.all_loads"                        , 0x0, ATTR_PEBS, 0x0 }, \
2574 { 0xD0, 0x82, C_ALL, "mem_inst_retired.all_stores"                       , 0x0, ATTR_PEBS, 0x0 }, \
2575 { 0xD1, 0x01, C_ALL, "mem_load_retired.l1_hit"                           , 0x0, ATTR_PEBS, 0x0 }, \
2576 { 0xD1, 0x02, C_ALL, "mem_load_retired.l2_hit"                           , 0x0, ATTR_PEBS, 0x0 }, \
2577 { 0xD1, 0x04, C_ALL, "mem_load_retired.l3_hit"                           , 0x0, ATTR_PEBS, 0x0 }, \
2578 { 0xD1, 0x08, C_ALL, "mem_load_retired.l1_miss"                          , 0x0, ATTR_PEBS, 0x0 }, \
2579 { 0xD1, 0x10, C_ALL, "mem_load_retired.l2_miss"                          , 0x0, ATTR_PEBS, 0x0 }, \
2580 { 0xD1, 0x20, C_ALL, "mem_load_retired.l3_miss"                          , 0x0, ATTR_PEBS, 0x0 }, \
2581 { 0xD1, 0x40, C_ALL, "mem_load_retired.fb_hit"                           , 0x0, ATTR_PEBS, 0x0 }, \
2582 { 0xD2, 0x01, C_ALL, "mem_load_l3_hit_retired.xsnp_miss"                 , 0x0, ATTR_PEBS, 0x0 }, \
2583 { 0xD2, 0x02, C_ALL, "mem_load_l3_hit_retired.xsnp_hit"                  , 0x0, ATTR_PEBS, 0x0 }, \
2584 { 0xD2, 0x04, C_ALL, "mem_load_l3_hit_retired.xsnp_hitm"                 , 0x0, ATTR_PEBS, 0x0 }, \
2585 { 0xD2, 0x08, C_ALL, "mem_load_l3_hit_retired.xsnp_none"                 , 0x0, ATTR_PEBS, 0x0 }, \
2586 { 0xD4, 0x04, C_ALL, "mem_load_misc_retired.uc"                          , 0x0, ATTR_PEBS, 0x0 }, \
2587 { 0xE6, 0x01, C_ALL, "baclears.any"                                      , 0x0, ATTR_NONE, 0x0 }, \
2588 { 0xF0, 0x40, C_ALL, "l2_trans.l2_wb"                                    , 0x0, ATTR_NONE, 0x0 }, \
2589 { 0xF1, 0x1F, C_ALL, "l2_lines_in.all"                                   , 0x0, ATTR_NONE, 0x0 }, \
2590 { 0xF2, 0x01, C_ALL, "l2_lines_out.silent"                               , 0x0, ATTR_NONE, 0x0 }, \
2591 { 0xF2, 0x02, C_ALL, "l2_lines_out.non_silent"                           , 0x0, ATTR_NONE, 0x0 }, \
2592 { 0xF2, 0x04, C_ALL, "l2_lines_out.useless_hwpf"                         , 0x0, ATTR_NONE, 0x0 }, \
2593 { 0xF4, 0x10, C_ALL, "sq_misc.split_lock"                                , 0x0, ATTR_NONE, 0x0 }, \
2594 /* end of #define */
2595
2596 #define NT_END {0, 0, 0, NULL, 0x0, ATTR_NONE, 0x0 } /* end-of-table */
2597
2598 static const struct events_table_t *events_table = NULL;
2599
2600 const struct events_table_t events_fam6_mod23[] = {
2601   ARCH_EVENTS
2602   EVENTS_FAM6_MOD23
2603   NT_END
2604 };
2605
2606 const struct events_table_t events_fam6_mod28[] = {
2607   ARCH_EVENTS
2608   EVENTS_FAM6_MOD28
2609   NT_END
2610 };
2611
2612 const struct events_table_t events_fam6_mod26[] = {
2613   ARCH_EVENTS
2614   EVENTS_FAM6_MOD26
2615   NT_END
2616 };
2617
2618 const struct events_table_t events_fam6_mod46[] = {
2619   ARCH_EVENTS
2620   EVENTS_FAM6_MOD26
2621   EVENTS_FAM6_MOD46_ONLY
2622   NT_END
2623 };
2624
2625 const struct events_table_t events_fam6_mod37[] = {
2626   ARCH_EVENTS
2627   EVENTS_FAM6_MOD37
2628   EVENTS_FAM6_MOD37_ALSO
2629   NT_END
2630 };
2631
2632 const struct events_table_t events_fam6_mod47[] = {
2633   ARCH_EVENTS
2634   EVENTS_FAM6_MOD37
2635   NT_END
2636 };
2637
2638 const struct events_table_t events_fam6_mod42[] = {
2639   ARCH_EVENTS
2640   EVENTS_FAM6_MOD42
2641   EVENTS_FAM6_MOD42_ONLY
2642   NT_END
2643 };
2644
2645 const struct events_table_t events_fam6_mod45[] = {
2646   ARCH_EVENTS
2647   EVENTS_FAM6_MOD42
2648   EVENTS_FAM6_MOD45_ONLY
2649   NT_END
2650 };
2651
2652 const struct events_table_t events_fam6_mod58[] = {
2653   ARCH_EVENTS
2654   EVENTS_FAM6_MOD58
2655   NT_END
2656 };
2657
2658 const struct events_table_t events_fam6_mod62[] = {
2659   ARCH_EVENTS
2660   EVENTS_FAM6_MOD58
2661   EVENTS_FAM6_MOD62_ONLY
2662   NT_END
2663 };
2664
2665 const struct events_table_t events_fam6_mod60[] = {
2666   ARCH_EVENTS
2667   EVENTS_FAM6_MOD60
2668   NT_END
2669 };
2670
2671 const struct events_table_t events_fam6_mod61[] = {
2672   ARCH_EVENTS
2673   EVENTS_FAM6_MOD61
2674   NT_END
2675 };
2676
2677 const struct events_table_t events_fam6_mod78[] = {
2678   ARCH_EVENTS
2679   EVENTS_FAM6_MOD78
2680   NT_END
2681 };
2682
2683 const struct events_table_t events_fam6_unknown[] = {
2684   ARCH_EVENTS
2685   NT_END
2686 };
2687
2688 const struct events_table_t events_fam_arm[] = {
2689 //      ARCH_EVENTS
2690 //    *eventnum = pevent->eventselect;
2691 //    *eventnum |= (pevent->unitmask << PERFCTR_UMASK_SHIFT);
2692 //    *eventnum |= (pevent->attrs << 16);
2693 //    *eventnum |= (pevent->cmask << 24);
2694 // eventselect, unitmask, supported_counters, name, cmask, attrs, msr_offset
2695
2696 // Hardware event
2697 #define HWE(nm, id)     { id, 0, C_ALL, nm, PERF_TYPE_HARDWARE, 0, 0 },
2698   HWE("branch-instructions",    PERF_COUNT_HW_BRANCH_INSTRUCTIONS)
2699   HWE("branch-misses",          PERF_COUNT_HW_BRANCH_MISSES)
2700   HWE("bus-cycles",             PERF_COUNT_HW_BUS_CYCLES)
2701   HWE("cache-misses",           PERF_COUNT_HW_CACHE_MISSES)
2702   HWE("cache-references",       PERF_COUNT_HW_CACHE_REFERENCES)
2703   HWE("cycles",                 PERF_COUNT_HW_CPU_CYCLES)
2704   HWE("instructions",           PERF_COUNT_HW_INSTRUCTIONS)
2705   HWE("ref-cycles",             PERF_COUNT_HW_REF_CPU_CYCLES)
2706   HWE("stalled-cycles-backend", PERF_COUNT_HW_STALLED_CYCLES_BACKEND)
2707   HWE("stalled-cycles-frontend", PERF_COUNT_HW_STALLED_CYCLES_FRONTEND)
2708
2709 // Software event
2710 #define SWE(nm, id)     { id, 0, C_ALL, nm, PERF_TYPE_SOFTWARE, 0, 0 },
2711   SWE("alignment-faults",       PERF_COUNT_SW_ALIGNMENT_FAULTS)
2712   SWE("context-switches",       PERF_COUNT_SW_CONTEXT_SWITCHES)
2713   SWE("cpu-clock",              PERF_COUNT_SW_CPU_CLOCK)
2714   SWE("cpu-migrations",         PERF_COUNT_SW_CPU_MIGRATIONS)
2715   SWE("emulation-faults",       PERF_COUNT_SW_EMULATION_FAULTS)
2716   SWE("major-faults",           PERF_COUNT_SW_PAGE_FAULTS_MAJ)
2717   SWE("minor-faults",           PERF_COUNT_SW_PAGE_FAULTS_MIN)
2718   SWE("page-faults",            PERF_COUNT_SW_PAGE_FAULTS)
2719   SWE("task-clock",             PERF_COUNT_SW_TASK_CLOCK)
2720
2721 // Hardware cache event
2722 #define HWCE(nm, id, op, res)   { id | (op << 8) | (res << 16), 0, C_ALL, nm, PERF_TYPE_HW_CACHE, 0, 0 },
2723   HWCE("L1-dcache-load-misses", PERF_COUNT_HW_CACHE_L1D,  PERF_COUNT_HW_CACHE_OP_READ,  PERF_COUNT_HW_CACHE_RESULT_MISS)
2724   HWCE("L1-dcache-loads",       PERF_COUNT_HW_CACHE_L1D,  PERF_COUNT_HW_CACHE_OP_READ,  PERF_COUNT_HW_CACHE_RESULT_ACCESS)
2725   HWCE("L1-dcache-store-misses",PERF_COUNT_HW_CACHE_L1D,  PERF_COUNT_HW_CACHE_RESULT_MISS, PERF_COUNT_HW_CACHE_RESULT_ACCESS)
2726   HWCE("L1-dcache-stores",      PERF_COUNT_HW_CACHE_L1D,  PERF_COUNT_HW_CACHE_OP_WRITE, PERF_COUNT_HW_CACHE_RESULT_ACCESS)
2727   HWCE("L1-icache-load-misses", PERF_COUNT_HW_CACHE_L1I,  PERF_COUNT_HW_CACHE_OP_READ,  PERF_COUNT_HW_CACHE_RESULT_MISS)
2728   HWCE("L1-icache-loads",       PERF_COUNT_HW_CACHE_L1I,  PERF_COUNT_HW_CACHE_OP_READ,  PERF_COUNT_HW_CACHE_RESULT_ACCESS)
2729 //    HWCE("branch-load-misses",)
2730 //    HWCE("branch-loads",)
2731   HWCE("dTLB-load-misses",      PERF_COUNT_HW_CACHE_DTLB, PERF_COUNT_HW_CACHE_OP_READ,  PERF_COUNT_HW_CACHE_RESULT_MISS)
2732   HWCE("dTLB-loads",            PERF_COUNT_HW_CACHE_DTLB, PERF_COUNT_HW_CACHE_OP_READ,  PERF_COUNT_HW_CACHE_RESULT_ACCESS)
2733   HWCE("iTLB-load-misses",      PERF_COUNT_HW_CACHE_ITLB, PERF_COUNT_HW_CACHE_OP_READ,  PERF_COUNT_HW_CACHE_RESULT_MISS)
2734   HWCE("iTLB-loads",            PERF_COUNT_HW_CACHE_ITLB, PERF_COUNT_HW_CACHE_OP_READ,  PERF_COUNT_HW_CACHE_RESULT_ACCESS)
2735
2736   NT_END
2737 };
2738
2739 static int
2740 core_pcbe_init (void)
2741 {
2742   switch (cpuid_getvendor ())
2743     {
2744     case ARM_CPU_IMP_ARM:
2745     case ARM_CPU_IMP_BRCM:
2746     case ARM_CPU_IMP_CAVIUM:
2747     case ARM_CPU_IMP_APM:
2748     case ARM_CPU_IMP_QCOM:
2749       snprintf (core_impl_name, sizeof (core_impl_name), "%s", AARCH64_VENDORSTR_ARM);
2750       events_table = events_fam_arm;
2751       num_gpc = 4;  // MEZ: a real implementation is needed
2752       num_ffc = 0;
2753       total_pmc = num_gpc + num_ffc;
2754       return 0;
2755     case X86_VENDOR_Intel:
2756       break;
2757     default:
2758       return -1;
2759     }
2760
2761 #if defined(__i386__) || defined(__x86_64)
2762   /* No Architectural Performance Monitoring Leaf returned by CPUID */
2763   if (get_cpuid_info ()->cpi_maxeax < 0xa)
2764     return (-1);
2765
2766   /* Obtain the Architectural Performance Monitoring Leaf */
2767   cpuid_regs_t cp;
2768   my_cpuid (0xa, &cp);
2769   uint32_t versionid = cp.eax & 0xFF;
2770
2771   /*
2772    * Fixed-Function Counters (FFC)
2773    *
2774    * All Family 6 Model 15 and Model 23 processors have fixed-function
2775    * counters.  These counters were made Architectural with
2776    * Family 6 Model 15 Stepping 9.
2777    */
2778   switch (versionid)
2779     {
2780     case 0:
2781       return -1;
2782     case 2:
2783       num_ffc = cp.edx & 0x1F;
2784       /*
2785        * Some processors have an errata (AW34) where
2786        * versionid is reported as 2 when actually 1.
2787        * In this case, fixed-function counters are
2788        * model-specific as in Version 1.
2789        */
2790       if (num_ffc != 0)
2791         break;
2792       /* FALLTHROUGH */
2793     case 1:
2794       num_ffc = 3;
2795       versionid = 1;
2796       break;
2797     default:
2798       num_ffc = cp.edx & 0x1F;
2799       break;
2800     }
2801   if (num_ffc >= 64)
2802     return (-1);
2803   uint64_t known_ffc_num = sizeof (ffc_names) / sizeof (char *) - 1; /* -1 for EOT */
2804   if (num_ffc > known_ffc_num)
2805     /*
2806      * The system seems to have more fixed-function counters than
2807      * what this PCBE is able to handle correctly.  Default to the
2808      * maximum number of fixed-function counters that this driver
2809      * is aware of.
2810      */
2811     num_ffc = known_ffc_num;
2812
2813   /*
2814    * General Purpose Counters (GPC)
2815    */
2816   num_gpc = (cp.eax >> 8) & 0xFF;
2817   if (num_gpc >= 64)
2818     return (-1);
2819   total_pmc = num_gpc + num_ffc;
2820   if (total_pmc > 64)   /* Too wide for the overflow bitmap */
2821     return (-1);
2822
2823   uint_t cpuid_model = cpuid_getmodel ();
2824
2825   /* GPC events for Family 6 Models 15 & 23 only */
2826   if ((cpuid_getfamily () == 6) &&
2827       ((cpuid_model == 15) || (cpuid_model == 23)))
2828     (void) snprintf (core_impl_name, IMPL_NAME_LEN, "Core Microarchitecture");
2829   else
2830     (void) snprintf (core_impl_name, IMPL_NAME_LEN,
2831                      "Intel Arch PerfMon v%d on Family %d Model %d",
2832                      versionid, cpuid_getfamily (), cpuid_model);
2833   /*
2834    * Process architectural and non-architectural events using GPC
2835    */
2836   if (num_gpc > 0)
2837     {
2838       switch (cpuid_model)
2839         {
2840         case 15: /* Core 2 */
2841         case 23:
2842           events_table = events_fam6_mod23;
2843           break;
2844         case 28: /* Atom */
2845           events_table = events_fam6_mod28;
2846           break;
2847         case 37: /* Westmere */
2848         case 44:
2849           events_table = events_fam6_mod37;
2850           break;
2851         case 47:
2852           events_table = events_fam6_mod47;
2853           break;
2854         case 26: /* Nehalem */
2855         case 30:
2856         case 31:
2857           events_table = events_fam6_mod26;
2858           break;
2859         case 46:
2860           events_table = events_fam6_mod46;
2861           break;
2862         case 42: /* Sandy Bridge */
2863           events_table = events_fam6_mod42;
2864           break;
2865         case 45:
2866           events_table = events_fam6_mod45;
2867           break;
2868         case 58: /* Ivy Bridge */
2869           events_table = events_fam6_mod58;
2870           break;
2871         case 62:
2872           events_table = events_fam6_mod62;
2873           break;
2874         case 60: /* Haswell */
2875         case 63:
2876         case 69:
2877         case 70:
2878           events_table = events_fam6_mod60;
2879           break;
2880         case 61: /* Broadwell */
2881         case 71:
2882         case 79:
2883         case 86:
2884           events_table = events_fam6_mod61;
2885           break;
2886         case 78: /* Skylake */
2887         case 85:
2888         case 94:
2889           events_table = events_fam6_mod78;
2890           break;
2891         default: /* unknown */
2892           events_table = events_fam6_unknown;
2893         }
2894     }
2895   /*
2896    * Fixed-function Counters (FFC) are already listed individually in
2897    * ffc_names[]
2898    */
2899 #endif
2900   return 0;
2901 }
2902
2903 static uint_t
2904 core_pcbe_ncounters ()
2905 {
2906   return total_pmc;
2907 }
2908
2909 static const char *
2910 core_pcbe_impl_name (void)
2911 {
2912   return core_impl_name;
2913 }
2914
2915 static const char *
2916 core_pcbe_cpuref (void)
2917 {
2918 #if defined(__aarch64__)
2919   return "";
2920 #elif defined(__i386__) || defined(__x86_64)
2921   switch (cpuid_getmodel ())
2922     {
2923     case 60: /* Haswell */
2924     case 63:
2925     case 69:
2926     case 70:
2927       return GTXT ("See Chapter 19 of the \"Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2\"\nOrder Number: 253669-047US, June 2013");
2928     case 61: /* Broadwell */
2929     case 71:
2930     case 79:
2931     case 86:
2932     case 78: /* Skylake */
2933     case 85:
2934     case 94:
2935       return GTXT ("See Chapter 19 of the \"Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide\"");
2936     default:
2937       return
2938       GTXT ("See Chapter 19 of the \"Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2\"\nOrder Number: 253669-045US, January 2013");
2939     }
2940 #endif
2941 }
2942
2943 static int
2944 core_pcbe_get_events (hwcf_hwc_cb_t *hwc_cb)
2945 {
2946   int count = 0;
2947   const struct events_table_t *pevent;
2948   for (pevent = events_table; pevent && pevent->name; pevent++)
2949     for (uint_t jj = 0; jj < num_gpc; jj++)
2950       if (C (jj) & pevent->supported_counters)
2951         {
2952           hwc_cb (jj, pevent->name);
2953           count++;
2954         }
2955
2956   for (int ii = 0; ii < sizeof (ffc_names) / sizeof (*ffc_names) && ffc_names[ii]; ii++)
2957     {
2958       hwc_cb (ii + num_gpc, ffc_names[ii]);
2959       count++;
2960     }
2961   /* add generic events here */
2962   return count;
2963 }
2964
2965 static int
2966 core_pcbe_get_eventnum (const char *eventname, uint_t pmc, eventsel_t *eventnum,
2967                         eventsel_t *valid_umask, uint_t *pmc_sel)
2968 {
2969   const struct events_table_t* pevent;
2970   *valid_umask = 0x0; /* by default, don't allow user umask */
2971   *pmc_sel = pmc; /* by default, use the requested pmc */
2972
2973   /* search non-ffc table */
2974   for (pevent = events_table; pevent && pevent->name; pevent++)
2975     {
2976       if (strcmp (eventname, pevent->name) == 0)
2977         {
2978           *eventnum = pevent->eventselect;
2979           *eventnum |= (pevent->unitmask << PERFCTR_UMASK_SHIFT);
2980           *eventnum |= (pevent->attrs << 16);
2981           *eventnum |= (pevent->cmask << 24);
2982
2983           if (pevent->msr_offset)
2984             {
2985               /*
2986                * Should also handle any pevent->msr_offset.
2987                * Can check libcpc's usr/src/uts/intel/pcbe/snb_pcbe.h,
2988                * function snb_gpc_configure().
2989                *
2990                * Actually, we should probably error out here
2991                * until the appropriate support has been added.
2992                * Also, we can comment out events that require
2993                * msr_offset so that they aren't even listed.
2994                */
2995             }
2996           if (!pevent->unitmask)
2997             *valid_umask = 0xff; /* allow umask if nothing set */
2998           return 0;
2999         }
3000     }
3001
3002   /* search ffc table */
3003   for (int ii = 0; ii < sizeof (ffc_names) / sizeof (*ffc_names) && ffc_names[ii]; ii++)
3004     {
3005       if (strcmp (eventname, ffc_names[ii]) == 0)
3006         {
3007           *eventnum = 0;
3008           *pmc_sel = ii | PERFCTR_FIXED_MAGIC;
3009           return 0;
3010         }
3011     }
3012   *eventnum = (eventsel_t) - 1;
3013   return -1;
3014 }
3015
3016 static hdrv_pcbe_api_t hdrv_pcbe_core_api = {
3017   core_pcbe_init,
3018   core_pcbe_ncounters,
3019   core_pcbe_impl_name,
3020   core_pcbe_cpuref,
3021   core_pcbe_get_events,
3022   core_pcbe_get_eventnum
3023 };