1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2018 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
57 typedef arelent, howto manager, Relocations, Relocations
62 This is the structure of a relocation entry:
66 .typedef enum bfd_reloc_status
68 . {* No errors detected. Note - the value 2 is used so that it
69 . will not be mistaken for the boolean TRUE or FALSE values. *}
72 . {* The relocation was performed, but there was an overflow. *}
75 . {* The address to relocate was not within the section supplied. *}
76 . bfd_reloc_outofrange,
78 . {* Used by special functions. *}
81 . {* Unsupported relocation size requested. *}
82 . bfd_reloc_notsupported,
87 . {* The symbol to relocate against was undefined. *}
88 . bfd_reloc_undefined,
90 . {* The relocation was performed, but may not be ok. If this type is
91 . returned, the error_message argument to bfd_perform_relocation
95 . bfd_reloc_status_type;
98 .typedef struct reloc_cache_entry
100 . {* A pointer into the canonical table of pointers. *}
101 . struct bfd_symbol **sym_ptr_ptr;
103 . {* offset in section. *}
104 . bfd_size_type address;
106 . {* addend for relocation value. *}
109 . {* Pointer to how to perform the required relocation. *}
110 . reloc_howto_type *howto;
120 Here is a description of each of the fields within an <<arelent>>:
124 The symbol table pointer points to a pointer to the symbol
125 associated with the relocation request. It is the pointer
126 into the table returned by the back end's
127 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
128 referenced through a pointer to a pointer so that tools like
129 the linker can fix up all the symbols of the same name by
130 modifying only one pointer. The relocation routine looks in
131 the symbol and uses the base of the section the symbol is
132 attached to and the value of the symbol as the initial
133 relocation offset. If the symbol pointer is zero, then the
134 section provided is looked up.
138 The <<address>> field gives the offset in bytes from the base of
139 the section data which owns the relocation record to the first
140 byte of relocatable information. The actual data relocated
141 will be relative to this point; for example, a relocation
142 type which modifies the bottom two bytes of a four byte word
143 would not touch the first byte pointed to in a big endian
148 The <<addend>> is a value provided by the back end to be added (!)
149 to the relocation offset. Its interpretation is dependent upon
150 the howto. For example, on the 68k the code:
155 | return foo[0x12345678];
158 Could be compiled into:
161 | moveb @@#12345678,d0
166 This could create a reloc pointing to <<foo>>, but leave the
167 offset in the data, something like:
169 |RELOCATION RECORDS FOR [.text]:
173 |00000000 4e56 fffc ; linkw fp,#-4
174 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
175 |0000000a 49c0 ; extbl d0
176 |0000000c 4e5e ; unlk fp
179 Using coff and an 88k, some instructions don't have enough
180 space in them to represent the full address range, and
181 pointers have to be loaded in two parts. So you'd get something like:
183 | or.u r13,r0,hi16(_foo+0x12345678)
184 | ld.b r2,r13,lo16(_foo+0x12345678)
187 This should create two relocs, both pointing to <<_foo>>, and with
188 0x12340000 in their addend field. The data would consist of:
190 |RELOCATION RECORDS FOR [.text]:
192 |00000002 HVRT16 _foo+0x12340000
193 |00000006 LVRT16 _foo+0x12340000
195 |00000000 5da05678 ; or.u r13,r0,0x5678
196 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
197 |00000008 f400c001 ; jmp r1
199 The relocation routine digs out the value from the data, adds
200 it to the addend to get the original offset, and then adds the
201 value of <<_foo>>. Note that all 32 bits have to be kept around
202 somewhere, to cope with carry from bit 15 to bit 16.
204 One further example is the sparc and the a.out format. The
205 sparc has a similar problem to the 88k, in that some
206 instructions don't have room for an entire offset, but on the
207 sparc the parts are created in odd sized lumps. The designers of
208 the a.out format chose to not use the data within the section
209 for storing part of the offset; all the offset is kept within
210 the reloc. Anything in the data should be ignored.
213 | sethi %hi(_foo+0x12345678),%g2
214 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
218 Both relocs contain a pointer to <<foo>>, and the offsets
221 |RELOCATION RECORDS FOR [.text]:
223 |00000004 HI22 _foo+0x12345678
224 |00000008 LO10 _foo+0x12345678
226 |00000000 9de3bf90 ; save %sp,-112,%sp
227 |00000004 05000000 ; sethi %hi(_foo+0),%g2
228 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
229 |0000000c 81c7e008 ; ret
230 |00000010 81e80000 ; restore
234 The <<howto>> field can be imagined as a
235 relocation instruction. It is a pointer to a structure which
236 contains information on what to do with all of the other
237 information in the reloc record and data section. A back end
238 would normally have a relocation instruction set and turn
239 relocations into pointers to the correct structure on input -
240 but it would be possible to create each howto field on demand.
246 <<enum complain_overflow>>
248 Indicates what sort of overflow checking should be done when
249 performing a relocation.
253 .enum complain_overflow
255 . {* Do not complain on overflow. *}
256 . complain_overflow_dont,
258 . {* Complain if the value overflows when considered as a signed
259 . number one bit larger than the field. ie. A bitfield of N bits
260 . is allowed to represent -2**n to 2**n-1. *}
261 . complain_overflow_bitfield,
263 . {* Complain if the value overflows when considered as a signed
265 . complain_overflow_signed,
267 . {* Complain if the value overflows when considered as an
268 . unsigned number. *}
269 . complain_overflow_unsigned
278 The <<reloc_howto_type>> is a structure which contains all the
279 information that libbfd needs to know to tie up a back end's data.
282 .struct bfd_symbol; {* Forward declaration. *}
284 .struct reloc_howto_struct
286 . {* The type field has mainly a documentary use - the back end can
287 . do what it wants with it, though normally the back end's
288 . external idea of what a reloc number is stored
289 . in this field. For example, a PC relative word relocation
290 . in a coff environment has the type 023 - because that's
291 . what the outside world calls a R_PCRWORD reloc. *}
294 . {* The value the final relocation is shifted right by. This drops
295 . unwanted data from the relocation. *}
296 . unsigned int rightshift;
298 . {* The size of the item to be relocated. This is *not* a
299 . power-of-two measure. To get the number of bytes operated
300 . on by a type of relocation, use bfd_get_reloc_size. *}
303 . {* The number of bits in the item to be relocated. This is used
304 . when doing overflow checking. *}
305 . unsigned int bitsize;
307 . {* The relocation is relative to the field being relocated. *}
308 . bfd_boolean pc_relative;
310 . {* The bit position of the reloc value in the destination.
311 . The relocated value is left shifted by this amount. *}
312 . unsigned int bitpos;
314 . {* What type of overflow error should be checked for when
316 . enum complain_overflow complain_on_overflow;
318 . {* If this field is non null, then the supplied function is
319 . called rather than the normal function. This allows really
320 . strange relocation methods to be accommodated. *}
321 . bfd_reloc_status_type (*special_function)
322 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
325 . {* The textual name of the relocation type. *}
328 . {* Some formats record a relocation addend in the section contents
329 . rather than with the relocation. For ELF formats this is the
330 . distinction between USE_REL and USE_RELA (though the code checks
331 . for USE_REL == 1/0). The value of this field is TRUE if the
332 . addend is recorded with the section contents; when performing a
333 . partial link (ld -r) the section contents (the data) will be
334 . modified. The value of this field is FALSE if addends are
335 . recorded with the relocation (in arelent.addend); when performing
336 . a partial link the relocation will be modified.
337 . All relocations for all ELF USE_RELA targets should set this field
338 . to FALSE (values of TRUE should be looked on with suspicion).
339 . However, the converse is not true: not all relocations of all ELF
340 . USE_REL targets set this field to TRUE. Why this is so is peculiar
341 . to each particular target. For relocs that aren't used in partial
342 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
343 . bfd_boolean partial_inplace;
345 . {* src_mask selects the part of the instruction (or data) to be used
346 . in the relocation sum. If the target relocations don't have an
347 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
348 . dst_mask to extract the addend from the section contents. If
349 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
350 . field should be zero. Non-zero values for ELF USE_RELA targets are
351 . bogus as in those cases the value in the dst_mask part of the
352 . section contents should be treated as garbage. *}
355 . {* dst_mask selects which parts of the instruction (or data) are
356 . replaced with a relocated value. *}
359 . {* When some formats create PC relative instructions, they leave
360 . the value of the pc of the place being relocated in the offset
361 . slot of the instruction, so that a PC relative relocation can
362 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
363 . Some formats leave the displacement part of an instruction
364 . empty (e.g., ELF); this flag signals the fact. *}
365 . bfd_boolean pcrel_offset;
375 The HOWTO define is horrible and will go away.
377 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
378 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
381 And will be replaced with the totally magic way. But for the
382 moment, we are compatible, so do it this way.
384 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
385 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
386 . NAME, FALSE, 0, 0, IN)
390 This is used to fill in an empty howto entry in an array.
392 .#define EMPTY_HOWTO(C) \
393 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
394 . NULL, FALSE, 0, 0, FALSE)
398 Helper routine to turn a symbol into a relocation value.
400 .#define HOWTO_PREPARE(relocation, symbol) \
402 . if (symbol != NULL) \
404 . if (bfd_is_com_section (symbol->section)) \
410 . relocation = symbol->value; \
422 unsigned int bfd_get_reloc_size (reloc_howto_type *);
425 For a reloc_howto_type that operates on a fixed number of bytes,
426 this returns the number of bytes operated on.
430 bfd_get_reloc_size (reloc_howto_type *howto)
453 How relocs are tied together in an <<asection>>:
455 .typedef struct relent_chain
458 . struct relent_chain *next;
464 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
465 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
472 bfd_reloc_status_type bfd_check_overflow
473 (enum complain_overflow how,
474 unsigned int bitsize,
475 unsigned int rightshift,
476 unsigned int addrsize,
480 Perform overflow checking on @var{relocation} which has
481 @var{bitsize} significant bits and will be shifted right by
482 @var{rightshift} bits, on a machine with addresses containing
483 @var{addrsize} significant bits. The result is either of
484 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
488 bfd_reloc_status_type
489 bfd_check_overflow (enum complain_overflow how,
490 unsigned int bitsize,
491 unsigned int rightshift,
492 unsigned int addrsize,
495 bfd_vma fieldmask, addrmask, signmask, ss, a;
496 bfd_reloc_status_type flag = bfd_reloc_ok;
498 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
499 we'll be permissive: extra bits in the field mask will
500 automatically extend the address mask for purposes of the
502 fieldmask = N_ONES (bitsize);
503 signmask = ~fieldmask;
504 addrmask = N_ONES (addrsize) | (fieldmask << rightshift);
505 a = (relocation & addrmask) >> rightshift;
509 case complain_overflow_dont:
512 case complain_overflow_signed:
513 /* If any sign bits are set, all sign bits must be set. That
514 is, A must be a valid negative address after shifting. */
515 signmask = ~ (fieldmask >> 1);
518 case complain_overflow_bitfield:
519 /* Bitfields are sometimes signed, sometimes unsigned. We
520 explicitly allow an address wrap too, which means a bitfield
521 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
522 if the value has some, but not all, bits set outside the
525 if (ss != 0 && ss != ((addrmask >> rightshift) & signmask))
526 flag = bfd_reloc_overflow;
529 case complain_overflow_unsigned:
530 /* We have an overflow if the address does not fit in the field. */
531 if ((a & signmask) != 0)
532 flag = bfd_reloc_overflow;
544 bfd_reloc_offset_in_range
547 bfd_boolean bfd_reloc_offset_in_range
548 (reloc_howto_type *howto,
551 bfd_size_type offset);
554 Returns TRUE if the reloc described by @var{HOWTO} can be
555 applied at @var{OFFSET} octets in @var{SECTION}.
559 /* HOWTO describes a relocation, at offset OCTET. Return whether the
560 relocation field is within SECTION of ABFD. */
563 bfd_reloc_offset_in_range (reloc_howto_type *howto,
568 bfd_size_type octet_end = bfd_get_section_limit_octets (abfd, section);
569 bfd_size_type reloc_size = bfd_get_reloc_size (howto);
571 /* The reloc field must be contained entirely within the section.
572 Allow zero length fields (marker relocs or NONE relocs where no
573 relocation will be performed) at the end of the section. */
574 return octet <= octet_end && octet + reloc_size <= octet_end;
579 bfd_perform_relocation
582 bfd_reloc_status_type bfd_perform_relocation
584 arelent *reloc_entry,
586 asection *input_section,
588 char **error_message);
591 If @var{output_bfd} is supplied to this function, the
592 generated image will be relocatable; the relocations are
593 copied to the output file after they have been changed to
594 reflect the new state of the world. There are two ways of
595 reflecting the results of partial linkage in an output file:
596 by modifying the output data in place, and by modifying the
597 relocation record. Some native formats (e.g., basic a.out and
598 basic coff) have no way of specifying an addend in the
599 relocation type, so the addend has to go in the output data.
600 This is no big deal since in these formats the output data
601 slot will always be big enough for the addend. Complex reloc
602 types with addends were invented to solve just this problem.
603 The @var{error_message} argument is set to an error message if
604 this return @code{bfd_reloc_dangerous}.
608 bfd_reloc_status_type
609 bfd_perform_relocation (bfd *abfd,
610 arelent *reloc_entry,
612 asection *input_section,
614 char **error_message)
617 bfd_reloc_status_type flag = bfd_reloc_ok;
618 bfd_size_type octets;
619 bfd_vma output_base = 0;
620 reloc_howto_type *howto = reloc_entry->howto;
621 asection *reloc_target_output_section;
624 symbol = *(reloc_entry->sym_ptr_ptr);
626 /* If we are not producing relocatable output, return an error if
627 the symbol is not defined. An undefined weak symbol is
628 considered to have a value of zero (SVR4 ABI, p. 4-27). */
629 if (bfd_is_und_section (symbol->section)
630 && (symbol->flags & BSF_WEAK) == 0
631 && output_bfd == NULL)
632 flag = bfd_reloc_undefined;
634 /* If there is a function supplied to handle this relocation type,
635 call it. It'll return `bfd_reloc_continue' if further processing
637 if (howto && howto->special_function)
639 bfd_reloc_status_type cont;
641 /* Note - we do not call bfd_reloc_offset_in_range here as the
642 reloc_entry->address field might actually be valid for the
643 backend concerned. It is up to the special_function itself
644 to call bfd_reloc_offset_in_range if needed. */
645 cont = howto->special_function (abfd, reloc_entry, symbol, data,
646 input_section, output_bfd,
648 if (cont != bfd_reloc_continue)
652 if (bfd_is_abs_section (symbol->section)
653 && output_bfd != NULL)
655 reloc_entry->address += input_section->output_offset;
659 /* PR 17512: file: 0f67f69d. */
661 return bfd_reloc_undefined;
663 /* Is the address of the relocation really within the section? */
664 octets = reloc_entry->address * bfd_octets_per_byte (abfd);
665 if (!bfd_reloc_offset_in_range (howto, abfd, input_section, octets))
666 return bfd_reloc_outofrange;
668 /* Work out which section the relocation is targeted at and the
669 initial relocation command value. */
671 /* Get symbol value. (Common symbols are special.) */
672 if (bfd_is_com_section (symbol->section))
675 relocation = symbol->value;
677 reloc_target_output_section = symbol->section->output_section;
679 /* Convert input-section-relative symbol value to absolute. */
680 if ((output_bfd && ! howto->partial_inplace)
681 || reloc_target_output_section == NULL)
684 output_base = reloc_target_output_section->vma;
686 relocation += output_base + symbol->section->output_offset;
688 /* Add in supplied addend. */
689 relocation += reloc_entry->addend;
691 /* Here the variable relocation holds the final address of the
692 symbol we are relocating against, plus any addend. */
694 if (howto->pc_relative)
696 /* This is a PC relative relocation. We want to set RELOCATION
697 to the distance between the address of the symbol and the
698 location. RELOCATION is already the address of the symbol.
700 We start by subtracting the address of the section containing
703 If pcrel_offset is set, we must further subtract the position
704 of the location within the section. Some targets arrange for
705 the addend to be the negative of the position of the location
706 within the section; for example, i386-aout does this. For
707 i386-aout, pcrel_offset is FALSE. Some other targets do not
708 include the position of the location; for example, ELF.
709 For those targets, pcrel_offset is TRUE.
711 If we are producing relocatable output, then we must ensure
712 that this reloc will be correctly computed when the final
713 relocation is done. If pcrel_offset is FALSE we want to wind
714 up with the negative of the location within the section,
715 which means we must adjust the existing addend by the change
716 in the location within the section. If pcrel_offset is TRUE
717 we do not want to adjust the existing addend at all.
719 FIXME: This seems logical to me, but for the case of
720 producing relocatable output it is not what the code
721 actually does. I don't want to change it, because it seems
722 far too likely that something will break. */
725 input_section->output_section->vma + input_section->output_offset;
727 if (howto->pcrel_offset)
728 relocation -= reloc_entry->address;
731 if (output_bfd != NULL)
733 if (! howto->partial_inplace)
735 /* This is a partial relocation, and we want to apply the relocation
736 to the reloc entry rather than the raw data. Modify the reloc
737 inplace to reflect what we now know. */
738 reloc_entry->addend = relocation;
739 reloc_entry->address += input_section->output_offset;
744 /* This is a partial relocation, but inplace, so modify the
747 If we've relocated with a symbol with a section, change
748 into a ref to the section belonging to the symbol. */
750 reloc_entry->address += input_section->output_offset;
753 if (abfd->xvec->flavour == bfd_target_coff_flavour
754 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
755 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
757 /* For m68k-coff, the addend was being subtracted twice during
758 relocation with -r. Removing the line below this comment
759 fixes that problem; see PR 2953.
761 However, Ian wrote the following, regarding removing the line below,
762 which explains why it is still enabled: --djm
764 If you put a patch like that into BFD you need to check all the COFF
765 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
766 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
767 problem in a different way. There may very well be a reason that the
768 code works as it does.
770 Hmmm. The first obvious point is that bfd_perform_relocation should
771 not have any tests that depend upon the flavour. It's seem like
772 entirely the wrong place for such a thing. The second obvious point
773 is that the current code ignores the reloc addend when producing
774 relocatable output for COFF. That's peculiar. In fact, I really
775 have no idea what the point of the line you want to remove is.
777 A typical COFF reloc subtracts the old value of the symbol and adds in
778 the new value to the location in the object file (if it's a pc
779 relative reloc it adds the difference between the symbol value and the
780 location). When relocating we need to preserve that property.
782 BFD handles this by setting the addend to the negative of the old
783 value of the symbol. Unfortunately it handles common symbols in a
784 non-standard way (it doesn't subtract the old value) but that's a
785 different story (we can't change it without losing backward
786 compatibility with old object files) (coff-i386 does subtract the old
787 value, to be compatible with existing coff-i386 targets, like SCO).
789 So everything works fine when not producing relocatable output. When
790 we are producing relocatable output, logically we should do exactly
791 what we do when not producing relocatable output. Therefore, your
792 patch is correct. In fact, it should probably always just set
793 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
794 add the value into the object file. This won't hurt the COFF code,
795 which doesn't use the addend; I'm not sure what it will do to other
796 formats (the thing to check for would be whether any formats both use
797 the addend and set partial_inplace).
799 When I wanted to make coff-i386 produce relocatable output, I ran
800 into the problem that you are running into: I wanted to remove that
801 line. Rather than risk it, I made the coff-i386 relocs use a special
802 function; it's coff_i386_reloc in coff-i386.c. The function
803 specifically adds the addend field into the object file, knowing that
804 bfd_perform_relocation is not going to. If you remove that line, then
805 coff-i386.c will wind up adding the addend field in twice. It's
806 trivial to fix; it just needs to be done.
808 The problem with removing the line is just that it may break some
809 working code. With BFD it's hard to be sure of anything. The right
810 way to deal with this is simply to build and test at least all the
811 supported COFF targets. It should be straightforward if time and disk
812 space consuming. For each target:
814 2) generate some executable, and link it using -r (I would
815 probably use paranoia.o and link against newlib/libc.a, which
816 for all the supported targets would be available in
817 /usr/cygnus/progressive/H-host/target/lib/libc.a).
818 3) make the change to reloc.c
819 4) rebuild the linker
821 6) if the resulting object files are the same, you have at least
823 7) if they are different you have to figure out which version is
826 relocation -= reloc_entry->addend;
827 reloc_entry->addend = 0;
831 reloc_entry->addend = relocation;
836 /* FIXME: This overflow checking is incomplete, because the value
837 might have overflowed before we get here. For a correct check we
838 need to compute the value in a size larger than bitsize, but we
839 can't reasonably do that for a reloc the same size as a host
841 FIXME: We should also do overflow checking on the result after
842 adding in the value contained in the object file. */
843 if (howto->complain_on_overflow != complain_overflow_dont
844 && flag == bfd_reloc_ok)
845 flag = bfd_check_overflow (howto->complain_on_overflow,
848 bfd_arch_bits_per_address (abfd),
851 /* Either we are relocating all the way, or we don't want to apply
852 the relocation to the reloc entry (probably because there isn't
853 any room in the output format to describe addends to relocs). */
855 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
856 (OSF version 1.3, compiler version 3.11). It miscompiles the
870 x <<= (unsigned long) s.i0;
874 printf ("succeeded (%lx)\n", x);
878 relocation >>= (bfd_vma) howto->rightshift;
880 /* Shift everything up to where it's going to be used. */
881 relocation <<= (bfd_vma) howto->bitpos;
883 /* Wait for the day when all have the mask in them. */
886 i instruction to be left alone
887 o offset within instruction
888 r relocation offset to apply
897 (( i i i i i o o o o o from bfd_get<size>
898 and S S S S S) to get the size offset we want
899 + r r r r r r r r r r) to get the final value to place
900 and D D D D D to chop to right size
901 -----------------------
904 ( i i i i i o o o o o from bfd_get<size>
905 and N N N N N ) get instruction
906 -----------------------
912 -----------------------
913 = R R R R R R R R R R put into bfd_put<size>
917 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
923 long x = bfd_get_24 (abfd, (bfd_byte *) data + octets);
925 bfd_put_24 (abfd, (bfd_vma) x, (unsigned char *) data + octets);
931 char x = bfd_get_8 (abfd, (char *) data + octets);
933 bfd_put_8 (abfd, x, (unsigned char *) data + octets);
939 short x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
941 bfd_put_16 (abfd, (bfd_vma) x, (unsigned char *) data + octets);
946 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
948 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
953 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
954 relocation = -relocation;
956 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
962 long x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
963 relocation = -relocation;
965 bfd_put_16 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
976 bfd_vma x = bfd_get_64 (abfd, (bfd_byte *) data + octets);
978 bfd_put_64 (abfd, x, (bfd_byte *) data + octets);
985 return bfd_reloc_other;
993 bfd_install_relocation
996 bfd_reloc_status_type bfd_install_relocation
998 arelent *reloc_entry,
999 void *data, bfd_vma data_start,
1000 asection *input_section,
1001 char **error_message);
1004 This looks remarkably like <<bfd_perform_relocation>>, except it
1005 does not expect that the section contents have been filled in.
1006 I.e., it's suitable for use when creating, rather than applying
1009 For now, this function should be considered reserved for the
1013 bfd_reloc_status_type
1014 bfd_install_relocation (bfd *abfd,
1015 arelent *reloc_entry,
1017 bfd_vma data_start_offset,
1018 asection *input_section,
1019 char **error_message)
1022 bfd_reloc_status_type flag = bfd_reloc_ok;
1023 bfd_size_type octets;
1024 bfd_vma output_base = 0;
1025 reloc_howto_type *howto = reloc_entry->howto;
1026 asection *reloc_target_output_section;
1030 symbol = *(reloc_entry->sym_ptr_ptr);
1032 /* If there is a function supplied to handle this relocation type,
1033 call it. It'll return `bfd_reloc_continue' if further processing
1035 if (howto && howto->special_function)
1037 bfd_reloc_status_type cont;
1039 /* Note - we do not call bfd_reloc_offset_in_range here as the
1040 reloc_entry->address field might actually be valid for the
1041 backend concerned. It is up to the special_function itself
1042 to call bfd_reloc_offset_in_range if needed. */
1043 /* XXX - The special_function calls haven't been fixed up to deal
1044 with creating new relocations and section contents. */
1045 cont = howto->special_function (abfd, reloc_entry, symbol,
1046 /* XXX - Non-portable! */
1047 ((bfd_byte *) data_start
1048 - data_start_offset),
1049 input_section, abfd, error_message);
1050 if (cont != bfd_reloc_continue)
1054 if (bfd_is_abs_section (symbol->section))
1056 reloc_entry->address += input_section->output_offset;
1057 return bfd_reloc_ok;
1060 /* No need to check for howto != NULL if !bfd_is_abs_section as
1061 it will have been checked in `bfd_perform_relocation already'. */
1063 /* Is the address of the relocation really within the section? */
1064 octets = reloc_entry->address * bfd_octets_per_byte (abfd);
1065 if (!bfd_reloc_offset_in_range (howto, abfd, input_section, octets))
1066 return bfd_reloc_outofrange;
1068 /* Work out which section the relocation is targeted at and the
1069 initial relocation command value. */
1071 /* Get symbol value. (Common symbols are special.) */
1072 if (bfd_is_com_section (symbol->section))
1075 relocation = symbol->value;
1077 reloc_target_output_section = symbol->section->output_section;
1079 /* Convert input-section-relative symbol value to absolute. */
1080 if (! howto->partial_inplace)
1083 output_base = reloc_target_output_section->vma;
1085 relocation += output_base + symbol->section->output_offset;
1087 /* Add in supplied addend. */
1088 relocation += reloc_entry->addend;
1090 /* Here the variable relocation holds the final address of the
1091 symbol we are relocating against, plus any addend. */
1093 if (howto->pc_relative)
1095 /* This is a PC relative relocation. We want to set RELOCATION
1096 to the distance between the address of the symbol and the
1097 location. RELOCATION is already the address of the symbol.
1099 We start by subtracting the address of the section containing
1102 If pcrel_offset is set, we must further subtract the position
1103 of the location within the section. Some targets arrange for
1104 the addend to be the negative of the position of the location
1105 within the section; for example, i386-aout does this. For
1106 i386-aout, pcrel_offset is FALSE. Some other targets do not
1107 include the position of the location; for example, ELF.
1108 For those targets, pcrel_offset is TRUE.
1110 If we are producing relocatable output, then we must ensure
1111 that this reloc will be correctly computed when the final
1112 relocation is done. If pcrel_offset is FALSE we want to wind
1113 up with the negative of the location within the section,
1114 which means we must adjust the existing addend by the change
1115 in the location within the section. If pcrel_offset is TRUE
1116 we do not want to adjust the existing addend at all.
1118 FIXME: This seems logical to me, but for the case of
1119 producing relocatable output it is not what the code
1120 actually does. I don't want to change it, because it seems
1121 far too likely that something will break. */
1124 input_section->output_section->vma + input_section->output_offset;
1126 if (howto->pcrel_offset && howto->partial_inplace)
1127 relocation -= reloc_entry->address;
1130 if (! howto->partial_inplace)
1132 /* This is a partial relocation, and we want to apply the relocation
1133 to the reloc entry rather than the raw data. Modify the reloc
1134 inplace to reflect what we now know. */
1135 reloc_entry->addend = relocation;
1136 reloc_entry->address += input_section->output_offset;
1141 /* This is a partial relocation, but inplace, so modify the
1144 If we've relocated with a symbol with a section, change
1145 into a ref to the section belonging to the symbol. */
1146 reloc_entry->address += input_section->output_offset;
1149 if (abfd->xvec->flavour == bfd_target_coff_flavour
1150 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
1151 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
1154 /* For m68k-coff, the addend was being subtracted twice during
1155 relocation with -r. Removing the line below this comment
1156 fixes that problem; see PR 2953.
1158 However, Ian wrote the following, regarding removing the line below,
1159 which explains why it is still enabled: --djm
1161 If you put a patch like that into BFD you need to check all the COFF
1162 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1163 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1164 problem in a different way. There may very well be a reason that the
1165 code works as it does.
1167 Hmmm. The first obvious point is that bfd_install_relocation should
1168 not have any tests that depend upon the flavour. It's seem like
1169 entirely the wrong place for such a thing. The second obvious point
1170 is that the current code ignores the reloc addend when producing
1171 relocatable output for COFF. That's peculiar. In fact, I really
1172 have no idea what the point of the line you want to remove is.
1174 A typical COFF reloc subtracts the old value of the symbol and adds in
1175 the new value to the location in the object file (if it's a pc
1176 relative reloc it adds the difference between the symbol value and the
1177 location). When relocating we need to preserve that property.
1179 BFD handles this by setting the addend to the negative of the old
1180 value of the symbol. Unfortunately it handles common symbols in a
1181 non-standard way (it doesn't subtract the old value) but that's a
1182 different story (we can't change it without losing backward
1183 compatibility with old object files) (coff-i386 does subtract the old
1184 value, to be compatible with existing coff-i386 targets, like SCO).
1186 So everything works fine when not producing relocatable output. When
1187 we are producing relocatable output, logically we should do exactly
1188 what we do when not producing relocatable output. Therefore, your
1189 patch is correct. In fact, it should probably always just set
1190 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1191 add the value into the object file. This won't hurt the COFF code,
1192 which doesn't use the addend; I'm not sure what it will do to other
1193 formats (the thing to check for would be whether any formats both use
1194 the addend and set partial_inplace).
1196 When I wanted to make coff-i386 produce relocatable output, I ran
1197 into the problem that you are running into: I wanted to remove that
1198 line. Rather than risk it, I made the coff-i386 relocs use a special
1199 function; it's coff_i386_reloc in coff-i386.c. The function
1200 specifically adds the addend field into the object file, knowing that
1201 bfd_install_relocation is not going to. If you remove that line, then
1202 coff-i386.c will wind up adding the addend field in twice. It's
1203 trivial to fix; it just needs to be done.
1205 The problem with removing the line is just that it may break some
1206 working code. With BFD it's hard to be sure of anything. The right
1207 way to deal with this is simply to build and test at least all the
1208 supported COFF targets. It should be straightforward if time and disk
1209 space consuming. For each target:
1211 2) generate some executable, and link it using -r (I would
1212 probably use paranoia.o and link against newlib/libc.a, which
1213 for all the supported targets would be available in
1214 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1215 3) make the change to reloc.c
1216 4) rebuild the linker
1218 6) if the resulting object files are the same, you have at least
1220 7) if they are different you have to figure out which version is
1222 relocation -= reloc_entry->addend;
1223 /* FIXME: There should be no target specific code here... */
1224 if (strcmp (abfd->xvec->name, "coff-z8k") != 0)
1225 reloc_entry->addend = 0;
1229 reloc_entry->addend = relocation;
1233 /* FIXME: This overflow checking is incomplete, because the value
1234 might have overflowed before we get here. For a correct check we
1235 need to compute the value in a size larger than bitsize, but we
1236 can't reasonably do that for a reloc the same size as a host
1238 FIXME: We should also do overflow checking on the result after
1239 adding in the value contained in the object file. */
1240 if (howto->complain_on_overflow != complain_overflow_dont)
1241 flag = bfd_check_overflow (howto->complain_on_overflow,
1244 bfd_arch_bits_per_address (abfd),
1247 /* Either we are relocating all the way, or we don't want to apply
1248 the relocation to the reloc entry (probably because there isn't
1249 any room in the output format to describe addends to relocs). */
1251 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1252 (OSF version 1.3, compiler version 3.11). It miscompiles the
1266 x <<= (unsigned long) s.i0;
1268 printf ("failed\n");
1270 printf ("succeeded (%lx)\n", x);
1274 relocation >>= (bfd_vma) howto->rightshift;
1276 /* Shift everything up to where it's going to be used. */
1277 relocation <<= (bfd_vma) howto->bitpos;
1279 /* Wait for the day when all have the mask in them. */
1282 i instruction to be left alone
1283 o offset within instruction
1284 r relocation offset to apply
1293 (( i i i i i o o o o o from bfd_get<size>
1294 and S S S S S) to get the size offset we want
1295 + r r r r r r r r r r) to get the final value to place
1296 and D D D D D to chop to right size
1297 -----------------------
1300 ( i i i i i o o o o o from bfd_get<size>
1301 and N N N N N ) get instruction
1302 -----------------------
1308 -----------------------
1309 = R R R R R R R R R R put into bfd_put<size>
1313 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1315 data = (bfd_byte *) data_start + (octets - data_start_offset);
1317 switch (howto->size)
1321 char x = bfd_get_8 (abfd, data);
1323 bfd_put_8 (abfd, x, data);
1329 short x = bfd_get_16 (abfd, data);
1331 bfd_put_16 (abfd, (bfd_vma) x, data);
1336 long x = bfd_get_32 (abfd, data);
1338 bfd_put_32 (abfd, (bfd_vma) x, data);
1343 long x = bfd_get_24 (abfd, data);
1345 bfd_put_24 (abfd, (bfd_vma) x, data);
1350 long x = bfd_get_32 (abfd, data);
1351 relocation = -relocation;
1353 bfd_put_32 (abfd, (bfd_vma) x, data);
1363 bfd_vma x = bfd_get_64 (abfd, data);
1365 bfd_put_64 (abfd, x, data);
1369 return bfd_reloc_other;
1375 /* This relocation routine is used by some of the backend linkers.
1376 They do not construct asymbol or arelent structures, so there is no
1377 reason for them to use bfd_perform_relocation. Also,
1378 bfd_perform_relocation is so hacked up it is easier to write a new
1379 function than to try to deal with it.
1381 This routine does a final relocation. Whether it is useful for a
1382 relocatable link depends upon how the object format defines
1385 FIXME: This routine ignores any special_function in the HOWTO,
1386 since the existing special_function values have been written for
1387 bfd_perform_relocation.
1389 HOWTO is the reloc howto information.
1390 INPUT_BFD is the BFD which the reloc applies to.
1391 INPUT_SECTION is the section which the reloc applies to.
1392 CONTENTS is the contents of the section.
1393 ADDRESS is the address of the reloc within INPUT_SECTION.
1394 VALUE is the value of the symbol the reloc refers to.
1395 ADDEND is the addend of the reloc. */
1397 bfd_reloc_status_type
1398 _bfd_final_link_relocate (reloc_howto_type *howto,
1400 asection *input_section,
1407 bfd_size_type octets = address * bfd_octets_per_byte (input_bfd);
1409 /* Sanity check the address. */
1410 if (!bfd_reloc_offset_in_range (howto, input_bfd, input_section, octets))
1411 return bfd_reloc_outofrange;
1413 /* This function assumes that we are dealing with a basic relocation
1414 against a symbol. We want to compute the value of the symbol to
1415 relocate to. This is just VALUE, the value of the symbol, plus
1416 ADDEND, any addend associated with the reloc. */
1417 relocation = value + addend;
1419 /* If the relocation is PC relative, we want to set RELOCATION to
1420 the distance between the symbol (currently in RELOCATION) and the
1421 location we are relocating. Some targets (e.g., i386-aout)
1422 arrange for the contents of the section to be the negative of the
1423 offset of the location within the section; for such targets
1424 pcrel_offset is FALSE. Other targets (e.g., ELF) simply leave
1425 the contents of the section as zero; for such targets
1426 pcrel_offset is TRUE. If pcrel_offset is FALSE we do not need to
1427 subtract out the offset of the location within the section (which
1428 is just ADDRESS). */
1429 if (howto->pc_relative)
1431 relocation -= (input_section->output_section->vma
1432 + input_section->output_offset);
1433 if (howto->pcrel_offset)
1434 relocation -= address;
1437 return _bfd_relocate_contents (howto, input_bfd, relocation,
1439 + address * bfd_octets_per_byte (input_bfd));
1442 /* Relocate a given location using a given value and howto. */
1444 bfd_reloc_status_type
1445 _bfd_relocate_contents (reloc_howto_type *howto,
1452 bfd_reloc_status_type flag;
1453 unsigned int rightshift = howto->rightshift;
1454 unsigned int bitpos = howto->bitpos;
1456 /* If the size is negative, negate RELOCATION. This isn't very
1458 if (howto->size < 0)
1459 relocation = -relocation;
1461 /* Get the value we are going to relocate. */
1462 size = bfd_get_reloc_size (howto);
1468 return bfd_reloc_ok;
1470 x = bfd_get_8 (input_bfd, location);
1473 x = bfd_get_16 (input_bfd, location);
1476 x = bfd_get_24 (input_bfd, location);
1479 x = bfd_get_32 (input_bfd, location);
1483 x = bfd_get_64 (input_bfd, location);
1490 /* Check for overflow. FIXME: We may drop bits during the addition
1491 which we don't check for. We must either check at every single
1492 operation, which would be tedious, or we must do the computations
1493 in a type larger than bfd_vma, which would be inefficient. */
1494 flag = bfd_reloc_ok;
1495 if (howto->complain_on_overflow != complain_overflow_dont)
1497 bfd_vma addrmask, fieldmask, signmask, ss;
1500 /* Get the values to be added together. For signed and unsigned
1501 relocations, we assume that all values should be truncated to
1502 the size of an address. For bitfields, all the bits matter.
1503 See also bfd_check_overflow. */
1504 fieldmask = N_ONES (howto->bitsize);
1505 signmask = ~fieldmask;
1506 addrmask = (N_ONES (bfd_arch_bits_per_address (input_bfd))
1507 | (fieldmask << rightshift));
1508 a = (relocation & addrmask) >> rightshift;
1509 b = (x & howto->src_mask & addrmask) >> bitpos;
1510 addrmask >>= rightshift;
1512 switch (howto->complain_on_overflow)
1514 case complain_overflow_signed:
1515 /* If any sign bits are set, all sign bits must be set.
1516 That is, A must be a valid negative address after
1518 signmask = ~(fieldmask >> 1);
1521 case complain_overflow_bitfield:
1522 /* Much like the signed check, but for a field one bit
1523 wider. We allow a bitfield to represent numbers in the
1524 range -2**n to 2**n-1, where n is the number of bits in the
1525 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1526 can't overflow, which is exactly what we want. */
1528 if (ss != 0 && ss != (addrmask & signmask))
1529 flag = bfd_reloc_overflow;
1531 /* We only need this next bit of code if the sign bit of B
1532 is below the sign bit of A. This would only happen if
1533 SRC_MASK had fewer bits than BITSIZE. Note that if
1534 SRC_MASK has more bits than BITSIZE, we can get into
1535 trouble; we would need to verify that B is in range, as
1536 we do for A above. */
1537 ss = ((~howto->src_mask) >> 1) & howto->src_mask;
1540 /* Set all the bits above the sign bit. */
1543 /* Now we can do the addition. */
1546 /* See if the result has the correct sign. Bits above the
1547 sign bit are junk now; ignore them. If the sum is
1548 positive, make sure we did not have all negative inputs;
1549 if the sum is negative, make sure we did not have all
1550 positive inputs. The test below looks only at the sign
1551 bits, and it really just
1552 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1554 We mask with addrmask here to explicitly allow an address
1555 wrap-around. The Linux kernel relies on it, and it is
1556 the only way to write assembler code which can run when
1557 loaded at a location 0x80000000 away from the location at
1558 which it is linked. */
1559 if (((~(a ^ b)) & (a ^ sum)) & signmask & addrmask)
1560 flag = bfd_reloc_overflow;
1563 case complain_overflow_unsigned:
1564 /* Checking for an unsigned overflow is relatively easy:
1565 trim the addresses and add, and trim the result as well.
1566 Overflow is normally indicated when the result does not
1567 fit in the field. However, we also need to consider the
1568 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1569 input is 0x80000000, and bfd_vma is only 32 bits; then we
1570 will get sum == 0, but there is an overflow, since the
1571 inputs did not fit in the field. Instead of doing a
1572 separate test, we can check for this by or-ing in the
1573 operands when testing for the sum overflowing its final
1575 sum = (a + b) & addrmask;
1576 if ((a | b | sum) & signmask)
1577 flag = bfd_reloc_overflow;
1585 /* Put RELOCATION in the right bits. */
1586 relocation >>= (bfd_vma) rightshift;
1587 relocation <<= (bfd_vma) bitpos;
1589 /* Add RELOCATION to the right bits of X. */
1590 x = ((x & ~howto->dst_mask)
1591 | (((x & howto->src_mask) + relocation) & howto->dst_mask));
1593 /* Put the relocated value back in the object file. */
1599 bfd_put_8 (input_bfd, x, location);
1602 bfd_put_16 (input_bfd, x, location);
1605 bfd_put_24 (input_bfd, x, location);
1608 bfd_put_32 (input_bfd, x, location);
1612 bfd_put_64 (input_bfd, x, location);
1622 /* Clear a given location using a given howto, by applying a fixed relocation
1623 value and discarding any in-place addend. This is used for fixed-up
1624 relocations against discarded symbols, to make ignorable debug or unwind
1625 information more obvious. */
1628 _bfd_clear_contents (reloc_howto_type *howto,
1630 asection *input_section,
1636 /* Get the value we are going to relocate. */
1637 size = bfd_get_reloc_size (howto);
1645 x = bfd_get_8 (input_bfd, location);
1648 x = bfd_get_16 (input_bfd, location);
1651 x = bfd_get_24 (input_bfd, location);
1654 x = bfd_get_32 (input_bfd, location);
1658 x = bfd_get_64 (input_bfd, location);
1665 /* Zero out the unwanted bits of X. */
1666 x &= ~howto->dst_mask;
1668 /* For a range list, use 1 instead of 0 as placeholder. 0
1669 would terminate the list, hiding any later entries. */
1670 if (strcmp (bfd_get_section_name (input_bfd, input_section),
1671 ".debug_ranges") == 0
1672 && (howto->dst_mask & 1) != 0)
1675 /* Put the relocated value back in the object file. */
1682 bfd_put_8 (input_bfd, x, location);
1685 bfd_put_16 (input_bfd, x, location);
1688 bfd_put_24 (input_bfd, x, location);
1691 bfd_put_32 (input_bfd, x, location);
1695 bfd_put_64 (input_bfd, x, location);
1706 howto manager, , typedef arelent, Relocations
1711 When an application wants to create a relocation, but doesn't
1712 know what the target machine might call it, it can find out by
1713 using this bit of code.
1722 The insides of a reloc code. The idea is that, eventually, there
1723 will be one enumerator for every type of relocation we ever do.
1724 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1725 return a howto pointer.
1727 This does mean that the application must determine the correct
1728 enumerator value; you can't get a howto pointer from a random set
1749 Basic absolute relocations of N bits.
1764 PC-relative relocations. Sometimes these are relative to the address
1765 of the relocation itself; sometimes they are relative to the start of
1766 the section containing the relocation. It depends on the specific target.
1771 Section relative relocations. Some targets need this for DWARF2.
1774 BFD_RELOC_32_GOT_PCREL
1776 BFD_RELOC_16_GOT_PCREL
1778 BFD_RELOC_8_GOT_PCREL
1784 BFD_RELOC_LO16_GOTOFF
1786 BFD_RELOC_HI16_GOTOFF
1788 BFD_RELOC_HI16_S_GOTOFF
1792 BFD_RELOC_64_PLT_PCREL
1794 BFD_RELOC_32_PLT_PCREL
1796 BFD_RELOC_24_PLT_PCREL
1798 BFD_RELOC_16_PLT_PCREL
1800 BFD_RELOC_8_PLT_PCREL
1808 BFD_RELOC_LO16_PLTOFF
1810 BFD_RELOC_HI16_PLTOFF
1812 BFD_RELOC_HI16_S_PLTOFF
1826 BFD_RELOC_68K_GLOB_DAT
1828 BFD_RELOC_68K_JMP_SLOT
1830 BFD_RELOC_68K_RELATIVE
1832 BFD_RELOC_68K_TLS_GD32
1834 BFD_RELOC_68K_TLS_GD16
1836 BFD_RELOC_68K_TLS_GD8
1838 BFD_RELOC_68K_TLS_LDM32
1840 BFD_RELOC_68K_TLS_LDM16
1842 BFD_RELOC_68K_TLS_LDM8
1844 BFD_RELOC_68K_TLS_LDO32
1846 BFD_RELOC_68K_TLS_LDO16
1848 BFD_RELOC_68K_TLS_LDO8
1850 BFD_RELOC_68K_TLS_IE32
1852 BFD_RELOC_68K_TLS_IE16
1854 BFD_RELOC_68K_TLS_IE8
1856 BFD_RELOC_68K_TLS_LE32
1858 BFD_RELOC_68K_TLS_LE16
1860 BFD_RELOC_68K_TLS_LE8
1862 Relocations used by 68K ELF.
1865 BFD_RELOC_32_BASEREL
1867 BFD_RELOC_16_BASEREL
1869 BFD_RELOC_LO16_BASEREL
1871 BFD_RELOC_HI16_BASEREL
1873 BFD_RELOC_HI16_S_BASEREL
1879 Linkage-table relative.
1884 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1887 BFD_RELOC_32_PCREL_S2
1889 BFD_RELOC_16_PCREL_S2
1891 BFD_RELOC_23_PCREL_S2
1893 These PC-relative relocations are stored as word displacements --
1894 i.e., byte displacements shifted right two bits. The 30-bit word
1895 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1896 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1897 signed 16-bit displacement is used on the MIPS, and the 23-bit
1898 displacement is used on the Alpha.
1905 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1906 the target word. These are used on the SPARC.
1913 For systems that allocate a Global Pointer register, these are
1914 displacements off that register. These relocation types are
1915 handled specially, because the value the register will have is
1916 decided relatively late.
1921 BFD_RELOC_SPARC_WDISP22
1927 BFD_RELOC_SPARC_GOT10
1929 BFD_RELOC_SPARC_GOT13
1931 BFD_RELOC_SPARC_GOT22
1933 BFD_RELOC_SPARC_PC10
1935 BFD_RELOC_SPARC_PC22
1937 BFD_RELOC_SPARC_WPLT30
1939 BFD_RELOC_SPARC_COPY
1941 BFD_RELOC_SPARC_GLOB_DAT
1943 BFD_RELOC_SPARC_JMP_SLOT
1945 BFD_RELOC_SPARC_RELATIVE
1947 BFD_RELOC_SPARC_UA16
1949 BFD_RELOC_SPARC_UA32
1951 BFD_RELOC_SPARC_UA64
1953 BFD_RELOC_SPARC_GOTDATA_HIX22
1955 BFD_RELOC_SPARC_GOTDATA_LOX10
1957 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1959 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1961 BFD_RELOC_SPARC_GOTDATA_OP
1963 BFD_RELOC_SPARC_JMP_IREL
1965 BFD_RELOC_SPARC_IRELATIVE
1967 SPARC ELF relocations. There is probably some overlap with other
1968 relocation types already defined.
1971 BFD_RELOC_SPARC_BASE13
1973 BFD_RELOC_SPARC_BASE22
1975 I think these are specific to SPARC a.out (e.g., Sun 4).
1985 BFD_RELOC_SPARC_OLO10
1987 BFD_RELOC_SPARC_HH22
1989 BFD_RELOC_SPARC_HM10
1991 BFD_RELOC_SPARC_LM22
1993 BFD_RELOC_SPARC_PC_HH22
1995 BFD_RELOC_SPARC_PC_HM10
1997 BFD_RELOC_SPARC_PC_LM22
1999 BFD_RELOC_SPARC_WDISP16
2001 BFD_RELOC_SPARC_WDISP19
2009 BFD_RELOC_SPARC_DISP64
2012 BFD_RELOC_SPARC_PLT32
2014 BFD_RELOC_SPARC_PLT64
2016 BFD_RELOC_SPARC_HIX22
2018 BFD_RELOC_SPARC_LOX10
2026 BFD_RELOC_SPARC_REGISTER
2030 BFD_RELOC_SPARC_SIZE32
2032 BFD_RELOC_SPARC_SIZE64
2034 BFD_RELOC_SPARC_WDISP10
2039 BFD_RELOC_SPARC_REV32
2041 SPARC little endian relocation
2043 BFD_RELOC_SPARC_TLS_GD_HI22
2045 BFD_RELOC_SPARC_TLS_GD_LO10
2047 BFD_RELOC_SPARC_TLS_GD_ADD
2049 BFD_RELOC_SPARC_TLS_GD_CALL
2051 BFD_RELOC_SPARC_TLS_LDM_HI22
2053 BFD_RELOC_SPARC_TLS_LDM_LO10
2055 BFD_RELOC_SPARC_TLS_LDM_ADD
2057 BFD_RELOC_SPARC_TLS_LDM_CALL
2059 BFD_RELOC_SPARC_TLS_LDO_HIX22
2061 BFD_RELOC_SPARC_TLS_LDO_LOX10
2063 BFD_RELOC_SPARC_TLS_LDO_ADD
2065 BFD_RELOC_SPARC_TLS_IE_HI22
2067 BFD_RELOC_SPARC_TLS_IE_LO10
2069 BFD_RELOC_SPARC_TLS_IE_LD
2071 BFD_RELOC_SPARC_TLS_IE_LDX
2073 BFD_RELOC_SPARC_TLS_IE_ADD
2075 BFD_RELOC_SPARC_TLS_LE_HIX22
2077 BFD_RELOC_SPARC_TLS_LE_LOX10
2079 BFD_RELOC_SPARC_TLS_DTPMOD32
2081 BFD_RELOC_SPARC_TLS_DTPMOD64
2083 BFD_RELOC_SPARC_TLS_DTPOFF32
2085 BFD_RELOC_SPARC_TLS_DTPOFF64
2087 BFD_RELOC_SPARC_TLS_TPOFF32
2089 BFD_RELOC_SPARC_TLS_TPOFF64
2091 SPARC TLS relocations
2100 BFD_RELOC_SPU_IMM10W
2104 BFD_RELOC_SPU_IMM16W
2108 BFD_RELOC_SPU_PCREL9a
2110 BFD_RELOC_SPU_PCREL9b
2112 BFD_RELOC_SPU_PCREL16
2122 BFD_RELOC_SPU_ADD_PIC
2127 BFD_RELOC_ALPHA_GPDISP_HI16
2129 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2130 "addend" in some special way.
2131 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2132 writing; when reading, it will be the absolute section symbol. The
2133 addend is the displacement in bytes of the "lda" instruction from
2134 the "ldah" instruction (which is at the address of this reloc).
2136 BFD_RELOC_ALPHA_GPDISP_LO16
2138 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2139 with GPDISP_HI16 relocs. The addend is ignored when writing the
2140 relocations out, and is filled in with the file's GP value on
2141 reading, for convenience.
2144 BFD_RELOC_ALPHA_GPDISP
2146 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2147 relocation except that there is no accompanying GPDISP_LO16
2151 BFD_RELOC_ALPHA_LITERAL
2153 BFD_RELOC_ALPHA_ELF_LITERAL
2155 BFD_RELOC_ALPHA_LITUSE
2157 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2158 the assembler turns it into a LDQ instruction to load the address of
2159 the symbol, and then fills in a register in the real instruction.
2161 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2162 section symbol. The addend is ignored when writing, but is filled
2163 in with the file's GP value on reading, for convenience, as with the
2166 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2167 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2168 but it generates output not based on the position within the .got
2169 section, but relative to the GP value chosen for the file during the
2172 The LITUSE reloc, on the instruction using the loaded address, gives
2173 information to the linker that it might be able to use to optimize
2174 away some literal section references. The symbol is ignored (read
2175 as the absolute section symbol), and the "addend" indicates the type
2176 of instruction using the register:
2177 1 - "memory" fmt insn
2178 2 - byte-manipulation (byte offset reg)
2179 3 - jsr (target of branch)
2182 BFD_RELOC_ALPHA_HINT
2184 The HINT relocation indicates a value that should be filled into the
2185 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2186 prediction logic which may be provided on some processors.
2189 BFD_RELOC_ALPHA_LINKAGE
2191 The LINKAGE relocation outputs a linkage pair in the object file,
2192 which is filled by the linker.
2195 BFD_RELOC_ALPHA_CODEADDR
2197 The CODEADDR relocation outputs a STO_CA in the object file,
2198 which is filled by the linker.
2201 BFD_RELOC_ALPHA_GPREL_HI16
2203 BFD_RELOC_ALPHA_GPREL_LO16
2205 The GPREL_HI/LO relocations together form a 32-bit offset from the
2209 BFD_RELOC_ALPHA_BRSGP
2211 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2212 share a common GP, and the target address is adjusted for
2213 STO_ALPHA_STD_GPLOAD.
2218 The NOP relocation outputs a NOP if the longword displacement
2219 between two procedure entry points is < 2^21.
2224 The BSR relocation outputs a BSR if the longword displacement
2225 between two procedure entry points is < 2^21.
2230 The LDA relocation outputs a LDA if the longword displacement
2231 between two procedure entry points is < 2^16.
2236 The BOH relocation outputs a BSR if the longword displacement
2237 between two procedure entry points is < 2^21, or else a hint.
2240 BFD_RELOC_ALPHA_TLSGD
2242 BFD_RELOC_ALPHA_TLSLDM
2244 BFD_RELOC_ALPHA_DTPMOD64
2246 BFD_RELOC_ALPHA_GOTDTPREL16
2248 BFD_RELOC_ALPHA_DTPREL64
2250 BFD_RELOC_ALPHA_DTPREL_HI16
2252 BFD_RELOC_ALPHA_DTPREL_LO16
2254 BFD_RELOC_ALPHA_DTPREL16
2256 BFD_RELOC_ALPHA_GOTTPREL16
2258 BFD_RELOC_ALPHA_TPREL64
2260 BFD_RELOC_ALPHA_TPREL_HI16
2262 BFD_RELOC_ALPHA_TPREL_LO16
2264 BFD_RELOC_ALPHA_TPREL16
2266 Alpha thread-local storage relocations.
2271 BFD_RELOC_MICROMIPS_JMP
2273 The MIPS jump instruction.
2276 BFD_RELOC_MIPS16_JMP
2278 The MIPS16 jump instruction.
2281 BFD_RELOC_MIPS16_GPREL
2283 MIPS16 GP relative reloc.
2288 High 16 bits of 32-bit value; simple reloc.
2293 High 16 bits of 32-bit value but the low 16 bits will be sign
2294 extended and added to form the final result. If the low 16
2295 bits form a negative number, we need to add one to the high value
2296 to compensate for the borrow when the low bits are added.
2304 BFD_RELOC_HI16_PCREL
2306 High 16 bits of 32-bit pc-relative value
2308 BFD_RELOC_HI16_S_PCREL
2310 High 16 bits of 32-bit pc-relative value, adjusted
2312 BFD_RELOC_LO16_PCREL
2314 Low 16 bits of pc-relative value
2317 BFD_RELOC_MIPS16_GOT16
2319 BFD_RELOC_MIPS16_CALL16
2321 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2322 16-bit immediate fields
2324 BFD_RELOC_MIPS16_HI16
2326 MIPS16 high 16 bits of 32-bit value.
2328 BFD_RELOC_MIPS16_HI16_S
2330 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2331 extended and added to form the final result. If the low 16
2332 bits form a negative number, we need to add one to the high value
2333 to compensate for the borrow when the low bits are added.
2335 BFD_RELOC_MIPS16_LO16
2340 BFD_RELOC_MIPS16_TLS_GD
2342 BFD_RELOC_MIPS16_TLS_LDM
2344 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2346 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2348 BFD_RELOC_MIPS16_TLS_GOTTPREL
2350 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2352 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2354 MIPS16 TLS relocations
2357 BFD_RELOC_MIPS_LITERAL
2359 BFD_RELOC_MICROMIPS_LITERAL
2361 Relocation against a MIPS literal section.
2364 BFD_RELOC_MICROMIPS_7_PCREL_S1
2366 BFD_RELOC_MICROMIPS_10_PCREL_S1
2368 BFD_RELOC_MICROMIPS_16_PCREL_S1
2370 microMIPS PC-relative relocations.
2373 BFD_RELOC_MIPS16_16_PCREL_S1
2375 MIPS16 PC-relative relocation.
2378 BFD_RELOC_MIPS_21_PCREL_S2
2380 BFD_RELOC_MIPS_26_PCREL_S2
2382 BFD_RELOC_MIPS_18_PCREL_S3
2384 BFD_RELOC_MIPS_19_PCREL_S2
2386 MIPS PC-relative relocations.
2389 BFD_RELOC_MICROMIPS_GPREL16
2391 BFD_RELOC_MICROMIPS_HI16
2393 BFD_RELOC_MICROMIPS_HI16_S
2395 BFD_RELOC_MICROMIPS_LO16
2397 microMIPS versions of generic BFD relocs.
2400 BFD_RELOC_MIPS_GOT16
2402 BFD_RELOC_MICROMIPS_GOT16
2404 BFD_RELOC_MIPS_CALL16
2406 BFD_RELOC_MICROMIPS_CALL16
2408 BFD_RELOC_MIPS_GOT_HI16
2410 BFD_RELOC_MICROMIPS_GOT_HI16
2412 BFD_RELOC_MIPS_GOT_LO16
2414 BFD_RELOC_MICROMIPS_GOT_LO16
2416 BFD_RELOC_MIPS_CALL_HI16
2418 BFD_RELOC_MICROMIPS_CALL_HI16
2420 BFD_RELOC_MIPS_CALL_LO16
2422 BFD_RELOC_MICROMIPS_CALL_LO16
2426 BFD_RELOC_MICROMIPS_SUB
2428 BFD_RELOC_MIPS_GOT_PAGE
2430 BFD_RELOC_MICROMIPS_GOT_PAGE
2432 BFD_RELOC_MIPS_GOT_OFST
2434 BFD_RELOC_MICROMIPS_GOT_OFST
2436 BFD_RELOC_MIPS_GOT_DISP
2438 BFD_RELOC_MICROMIPS_GOT_DISP
2440 BFD_RELOC_MIPS_SHIFT5
2442 BFD_RELOC_MIPS_SHIFT6
2444 BFD_RELOC_MIPS_INSERT_A
2446 BFD_RELOC_MIPS_INSERT_B
2448 BFD_RELOC_MIPS_DELETE
2450 BFD_RELOC_MIPS_HIGHEST
2452 BFD_RELOC_MICROMIPS_HIGHEST
2454 BFD_RELOC_MIPS_HIGHER
2456 BFD_RELOC_MICROMIPS_HIGHER
2458 BFD_RELOC_MIPS_SCN_DISP
2460 BFD_RELOC_MICROMIPS_SCN_DISP
2462 BFD_RELOC_MIPS_REL16
2464 BFD_RELOC_MIPS_RELGOT
2468 BFD_RELOC_MICROMIPS_JALR
2470 BFD_RELOC_MIPS_TLS_DTPMOD32
2472 BFD_RELOC_MIPS_TLS_DTPREL32
2474 BFD_RELOC_MIPS_TLS_DTPMOD64
2476 BFD_RELOC_MIPS_TLS_DTPREL64
2478 BFD_RELOC_MIPS_TLS_GD
2480 BFD_RELOC_MICROMIPS_TLS_GD
2482 BFD_RELOC_MIPS_TLS_LDM
2484 BFD_RELOC_MICROMIPS_TLS_LDM
2486 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2488 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2490 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2492 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2494 BFD_RELOC_MIPS_TLS_GOTTPREL
2496 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2498 BFD_RELOC_MIPS_TLS_TPREL32
2500 BFD_RELOC_MIPS_TLS_TPREL64
2502 BFD_RELOC_MIPS_TLS_TPREL_HI16
2504 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2506 BFD_RELOC_MIPS_TLS_TPREL_LO16
2508 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2512 MIPS ELF relocations.
2518 BFD_RELOC_MIPS_JUMP_SLOT
2520 MIPS ELF relocations (VxWorks and PLT extensions).
2524 BFD_RELOC_MOXIE_10_PCREL
2526 Moxie ELF relocations.
2538 BFD_RELOC_FT32_RELAX
2546 BFD_RELOC_FT32_DIFF32
2548 FT32 ELF relocations.
2552 BFD_RELOC_FRV_LABEL16
2554 BFD_RELOC_FRV_LABEL24
2560 BFD_RELOC_FRV_GPREL12
2562 BFD_RELOC_FRV_GPRELU12
2564 BFD_RELOC_FRV_GPREL32
2566 BFD_RELOC_FRV_GPRELHI
2568 BFD_RELOC_FRV_GPRELLO
2576 BFD_RELOC_FRV_FUNCDESC
2578 BFD_RELOC_FRV_FUNCDESC_GOT12
2580 BFD_RELOC_FRV_FUNCDESC_GOTHI
2582 BFD_RELOC_FRV_FUNCDESC_GOTLO
2584 BFD_RELOC_FRV_FUNCDESC_VALUE
2586 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2588 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2590 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2592 BFD_RELOC_FRV_GOTOFF12
2594 BFD_RELOC_FRV_GOTOFFHI
2596 BFD_RELOC_FRV_GOTOFFLO
2598 BFD_RELOC_FRV_GETTLSOFF
2600 BFD_RELOC_FRV_TLSDESC_VALUE
2602 BFD_RELOC_FRV_GOTTLSDESC12
2604 BFD_RELOC_FRV_GOTTLSDESCHI
2606 BFD_RELOC_FRV_GOTTLSDESCLO
2608 BFD_RELOC_FRV_TLSMOFF12
2610 BFD_RELOC_FRV_TLSMOFFHI
2612 BFD_RELOC_FRV_TLSMOFFLO
2614 BFD_RELOC_FRV_GOTTLSOFF12
2616 BFD_RELOC_FRV_GOTTLSOFFHI
2618 BFD_RELOC_FRV_GOTTLSOFFLO
2620 BFD_RELOC_FRV_TLSOFF
2622 BFD_RELOC_FRV_TLSDESC_RELAX
2624 BFD_RELOC_FRV_GETTLSOFF_RELAX
2626 BFD_RELOC_FRV_TLSOFF_RELAX
2628 BFD_RELOC_FRV_TLSMOFF
2630 Fujitsu Frv Relocations.
2634 BFD_RELOC_MN10300_GOTOFF24
2636 This is a 24bit GOT-relative reloc for the mn10300.
2638 BFD_RELOC_MN10300_GOT32
2640 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2643 BFD_RELOC_MN10300_GOT24
2645 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2648 BFD_RELOC_MN10300_GOT16
2650 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2653 BFD_RELOC_MN10300_COPY
2655 Copy symbol at runtime.
2657 BFD_RELOC_MN10300_GLOB_DAT
2661 BFD_RELOC_MN10300_JMP_SLOT
2665 BFD_RELOC_MN10300_RELATIVE
2667 Adjust by program base.
2669 BFD_RELOC_MN10300_SYM_DIFF
2671 Together with another reloc targeted at the same location,
2672 allows for a value that is the difference of two symbols
2673 in the same section.
2675 BFD_RELOC_MN10300_ALIGN
2677 The addend of this reloc is an alignment power that must
2678 be honoured at the offset's location, regardless of linker
2681 BFD_RELOC_MN10300_TLS_GD
2683 BFD_RELOC_MN10300_TLS_LD
2685 BFD_RELOC_MN10300_TLS_LDO
2687 BFD_RELOC_MN10300_TLS_GOTIE
2689 BFD_RELOC_MN10300_TLS_IE
2691 BFD_RELOC_MN10300_TLS_LE
2693 BFD_RELOC_MN10300_TLS_DTPMOD
2695 BFD_RELOC_MN10300_TLS_DTPOFF
2697 BFD_RELOC_MN10300_TLS_TPOFF
2699 Various TLS-related relocations.
2701 BFD_RELOC_MN10300_32_PCREL
2703 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2706 BFD_RELOC_MN10300_16_PCREL
2708 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2719 BFD_RELOC_386_GLOB_DAT
2721 BFD_RELOC_386_JUMP_SLOT
2723 BFD_RELOC_386_RELATIVE
2725 BFD_RELOC_386_GOTOFF
2729 BFD_RELOC_386_TLS_TPOFF
2731 BFD_RELOC_386_TLS_IE
2733 BFD_RELOC_386_TLS_GOTIE
2735 BFD_RELOC_386_TLS_LE
2737 BFD_RELOC_386_TLS_GD
2739 BFD_RELOC_386_TLS_LDM
2741 BFD_RELOC_386_TLS_LDO_32
2743 BFD_RELOC_386_TLS_IE_32
2745 BFD_RELOC_386_TLS_LE_32
2747 BFD_RELOC_386_TLS_DTPMOD32
2749 BFD_RELOC_386_TLS_DTPOFF32
2751 BFD_RELOC_386_TLS_TPOFF32
2753 BFD_RELOC_386_TLS_GOTDESC
2755 BFD_RELOC_386_TLS_DESC_CALL
2757 BFD_RELOC_386_TLS_DESC
2759 BFD_RELOC_386_IRELATIVE
2761 BFD_RELOC_386_GOT32X
2763 i386/elf relocations
2766 BFD_RELOC_X86_64_GOT32
2768 BFD_RELOC_X86_64_PLT32
2770 BFD_RELOC_X86_64_COPY
2772 BFD_RELOC_X86_64_GLOB_DAT
2774 BFD_RELOC_X86_64_JUMP_SLOT
2776 BFD_RELOC_X86_64_RELATIVE
2778 BFD_RELOC_X86_64_GOTPCREL
2780 BFD_RELOC_X86_64_32S
2782 BFD_RELOC_X86_64_DTPMOD64
2784 BFD_RELOC_X86_64_DTPOFF64
2786 BFD_RELOC_X86_64_TPOFF64
2788 BFD_RELOC_X86_64_TLSGD
2790 BFD_RELOC_X86_64_TLSLD
2792 BFD_RELOC_X86_64_DTPOFF32
2794 BFD_RELOC_X86_64_GOTTPOFF
2796 BFD_RELOC_X86_64_TPOFF32
2798 BFD_RELOC_X86_64_GOTOFF64
2800 BFD_RELOC_X86_64_GOTPC32
2802 BFD_RELOC_X86_64_GOT64
2804 BFD_RELOC_X86_64_GOTPCREL64
2806 BFD_RELOC_X86_64_GOTPC64
2808 BFD_RELOC_X86_64_GOTPLT64
2810 BFD_RELOC_X86_64_PLTOFF64
2812 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2814 BFD_RELOC_X86_64_TLSDESC_CALL
2816 BFD_RELOC_X86_64_TLSDESC
2818 BFD_RELOC_X86_64_IRELATIVE
2820 BFD_RELOC_X86_64_PC32_BND
2822 BFD_RELOC_X86_64_PLT32_BND
2824 BFD_RELOC_X86_64_GOTPCRELX
2826 BFD_RELOC_X86_64_REX_GOTPCRELX
2828 x86-64/elf relocations
2831 BFD_RELOC_NS32K_IMM_8
2833 BFD_RELOC_NS32K_IMM_16
2835 BFD_RELOC_NS32K_IMM_32
2837 BFD_RELOC_NS32K_IMM_8_PCREL
2839 BFD_RELOC_NS32K_IMM_16_PCREL
2841 BFD_RELOC_NS32K_IMM_32_PCREL
2843 BFD_RELOC_NS32K_DISP_8
2845 BFD_RELOC_NS32K_DISP_16
2847 BFD_RELOC_NS32K_DISP_32
2849 BFD_RELOC_NS32K_DISP_8_PCREL
2851 BFD_RELOC_NS32K_DISP_16_PCREL
2853 BFD_RELOC_NS32K_DISP_32_PCREL
2858 BFD_RELOC_PDP11_DISP_8_PCREL
2860 BFD_RELOC_PDP11_DISP_6_PCREL
2865 BFD_RELOC_PJ_CODE_HI16
2867 BFD_RELOC_PJ_CODE_LO16
2869 BFD_RELOC_PJ_CODE_DIR16
2871 BFD_RELOC_PJ_CODE_DIR32
2873 BFD_RELOC_PJ_CODE_REL16
2875 BFD_RELOC_PJ_CODE_REL32
2877 Picojava relocs. Not all of these appear in object files.
2888 BFD_RELOC_PPC_B16_BRTAKEN
2890 BFD_RELOC_PPC_B16_BRNTAKEN
2894 BFD_RELOC_PPC_BA16_BRTAKEN
2896 BFD_RELOC_PPC_BA16_BRNTAKEN
2900 BFD_RELOC_PPC_GLOB_DAT
2902 BFD_RELOC_PPC_JMP_SLOT
2904 BFD_RELOC_PPC_RELATIVE
2906 BFD_RELOC_PPC_LOCAL24PC
2908 BFD_RELOC_PPC_EMB_NADDR32
2910 BFD_RELOC_PPC_EMB_NADDR16
2912 BFD_RELOC_PPC_EMB_NADDR16_LO
2914 BFD_RELOC_PPC_EMB_NADDR16_HI
2916 BFD_RELOC_PPC_EMB_NADDR16_HA
2918 BFD_RELOC_PPC_EMB_SDAI16
2920 BFD_RELOC_PPC_EMB_SDA2I16
2922 BFD_RELOC_PPC_EMB_SDA2REL
2924 BFD_RELOC_PPC_EMB_SDA21
2926 BFD_RELOC_PPC_EMB_MRKREF
2928 BFD_RELOC_PPC_EMB_RELSEC16
2930 BFD_RELOC_PPC_EMB_RELST_LO
2932 BFD_RELOC_PPC_EMB_RELST_HI
2934 BFD_RELOC_PPC_EMB_RELST_HA
2936 BFD_RELOC_PPC_EMB_BIT_FLD
2938 BFD_RELOC_PPC_EMB_RELSDA
2940 BFD_RELOC_PPC_VLE_REL8
2942 BFD_RELOC_PPC_VLE_REL15
2944 BFD_RELOC_PPC_VLE_REL24
2946 BFD_RELOC_PPC_VLE_LO16A
2948 BFD_RELOC_PPC_VLE_LO16D
2950 BFD_RELOC_PPC_VLE_HI16A
2952 BFD_RELOC_PPC_VLE_HI16D
2954 BFD_RELOC_PPC_VLE_HA16A
2956 BFD_RELOC_PPC_VLE_HA16D
2958 BFD_RELOC_PPC_VLE_SDA21
2960 BFD_RELOC_PPC_VLE_SDA21_LO
2962 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2964 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2966 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2968 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2970 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2972 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2974 BFD_RELOC_PPC_16DX_HA
2976 BFD_RELOC_PPC_REL16DX_HA
2978 BFD_RELOC_PPC64_HIGHER
2980 BFD_RELOC_PPC64_HIGHER_S
2982 BFD_RELOC_PPC64_HIGHEST
2984 BFD_RELOC_PPC64_HIGHEST_S
2986 BFD_RELOC_PPC64_TOC16_LO
2988 BFD_RELOC_PPC64_TOC16_HI
2990 BFD_RELOC_PPC64_TOC16_HA
2994 BFD_RELOC_PPC64_PLTGOT16
2996 BFD_RELOC_PPC64_PLTGOT16_LO
2998 BFD_RELOC_PPC64_PLTGOT16_HI
3000 BFD_RELOC_PPC64_PLTGOT16_HA
3002 BFD_RELOC_PPC64_ADDR16_DS
3004 BFD_RELOC_PPC64_ADDR16_LO_DS
3006 BFD_RELOC_PPC64_GOT16_DS
3008 BFD_RELOC_PPC64_GOT16_LO_DS
3010 BFD_RELOC_PPC64_PLT16_LO_DS
3012 BFD_RELOC_PPC64_SECTOFF_DS
3014 BFD_RELOC_PPC64_SECTOFF_LO_DS
3016 BFD_RELOC_PPC64_TOC16_DS
3018 BFD_RELOC_PPC64_TOC16_LO_DS
3020 BFD_RELOC_PPC64_PLTGOT16_DS
3022 BFD_RELOC_PPC64_PLTGOT16_LO_DS
3024 BFD_RELOC_PPC64_ADDR16_HIGH
3026 BFD_RELOC_PPC64_ADDR16_HIGHA
3028 BFD_RELOC_PPC64_ADDR64_LOCAL
3030 BFD_RELOC_PPC64_ENTRY
3032 BFD_RELOC_PPC64_REL24_NOTOC
3034 Power(rs6000) and PowerPC relocations.
3043 BFD_RELOC_PPC_DTPMOD
3045 BFD_RELOC_PPC_TPREL16
3047 BFD_RELOC_PPC_TPREL16_LO
3049 BFD_RELOC_PPC_TPREL16_HI
3051 BFD_RELOC_PPC_TPREL16_HA
3055 BFD_RELOC_PPC_DTPREL16
3057 BFD_RELOC_PPC_DTPREL16_LO
3059 BFD_RELOC_PPC_DTPREL16_HI
3061 BFD_RELOC_PPC_DTPREL16_HA
3063 BFD_RELOC_PPC_DTPREL
3065 BFD_RELOC_PPC_GOT_TLSGD16
3067 BFD_RELOC_PPC_GOT_TLSGD16_LO
3069 BFD_RELOC_PPC_GOT_TLSGD16_HI
3071 BFD_RELOC_PPC_GOT_TLSGD16_HA
3073 BFD_RELOC_PPC_GOT_TLSLD16
3075 BFD_RELOC_PPC_GOT_TLSLD16_LO
3077 BFD_RELOC_PPC_GOT_TLSLD16_HI
3079 BFD_RELOC_PPC_GOT_TLSLD16_HA
3081 BFD_RELOC_PPC_GOT_TPREL16
3083 BFD_RELOC_PPC_GOT_TPREL16_LO
3085 BFD_RELOC_PPC_GOT_TPREL16_HI
3087 BFD_RELOC_PPC_GOT_TPREL16_HA
3089 BFD_RELOC_PPC_GOT_DTPREL16
3091 BFD_RELOC_PPC_GOT_DTPREL16_LO
3093 BFD_RELOC_PPC_GOT_DTPREL16_HI
3095 BFD_RELOC_PPC_GOT_DTPREL16_HA
3097 BFD_RELOC_PPC64_TPREL16_DS
3099 BFD_RELOC_PPC64_TPREL16_LO_DS
3101 BFD_RELOC_PPC64_TPREL16_HIGHER
3103 BFD_RELOC_PPC64_TPREL16_HIGHERA
3105 BFD_RELOC_PPC64_TPREL16_HIGHEST
3107 BFD_RELOC_PPC64_TPREL16_HIGHESTA
3109 BFD_RELOC_PPC64_DTPREL16_DS
3111 BFD_RELOC_PPC64_DTPREL16_LO_DS
3113 BFD_RELOC_PPC64_DTPREL16_HIGHER
3115 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3117 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3119 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3121 BFD_RELOC_PPC64_TPREL16_HIGH
3123 BFD_RELOC_PPC64_TPREL16_HIGHA
3125 BFD_RELOC_PPC64_DTPREL16_HIGH
3127 BFD_RELOC_PPC64_DTPREL16_HIGHA
3129 PowerPC and PowerPC64 thread-local storage relocations.
3134 IBM 370/390 relocations
3139 The type of reloc used to build a constructor table - at the moment
3140 probably a 32 bit wide absolute relocation, but the target can choose.
3141 It generally does map to one of the other relocation types.
3144 BFD_RELOC_ARM_PCREL_BRANCH
3146 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3147 not stored in the instruction.
3149 BFD_RELOC_ARM_PCREL_BLX
3151 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3152 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3153 field in the instruction.
3155 BFD_RELOC_THUMB_PCREL_BLX
3157 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3158 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3159 field in the instruction.
3161 BFD_RELOC_ARM_PCREL_CALL
3163 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3165 BFD_RELOC_ARM_PCREL_JUMP
3167 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3170 BFD_RELOC_THUMB_PCREL_BRANCH7
3172 BFD_RELOC_THUMB_PCREL_BRANCH9
3174 BFD_RELOC_THUMB_PCREL_BRANCH12
3176 BFD_RELOC_THUMB_PCREL_BRANCH20
3178 BFD_RELOC_THUMB_PCREL_BRANCH23
3180 BFD_RELOC_THUMB_PCREL_BRANCH25
3182 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3183 The lowest bit must be zero and is not stored in the instruction.
3184 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3185 "nn" one smaller in all cases. Note further that BRANCH23
3186 corresponds to R_ARM_THM_CALL.
3189 BFD_RELOC_ARM_OFFSET_IMM
3191 12-bit immediate offset, used in ARM-format ldr and str instructions.
3194 BFD_RELOC_ARM_THUMB_OFFSET
3196 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3199 BFD_RELOC_ARM_TARGET1
3201 Pc-relative or absolute relocation depending on target. Used for
3202 entries in .init_array sections.
3204 BFD_RELOC_ARM_ROSEGREL32
3206 Read-only segment base relative address.
3208 BFD_RELOC_ARM_SBREL32
3210 Data segment base relative address.
3212 BFD_RELOC_ARM_TARGET2
3214 This reloc is used for references to RTTI data from exception handling
3215 tables. The actual definition depends on the target. It may be a
3216 pc-relative or some form of GOT-indirect relocation.
3218 BFD_RELOC_ARM_PREL31
3220 31-bit PC relative address.
3226 BFD_RELOC_ARM_MOVW_PCREL
3228 BFD_RELOC_ARM_MOVT_PCREL
3230 BFD_RELOC_ARM_THUMB_MOVW
3232 BFD_RELOC_ARM_THUMB_MOVT
3234 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3236 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3238 Low and High halfword relocations for MOVW and MOVT instructions.
3241 BFD_RELOC_ARM_GOTFUNCDESC
3243 BFD_RELOC_ARM_GOTOFFFUNCDESC
3245 BFD_RELOC_ARM_FUNCDESC
3247 BFD_RELOC_ARM_FUNCDESC_VALUE
3249 BFD_RELOC_ARM_TLS_GD32_FDPIC
3251 BFD_RELOC_ARM_TLS_LDM32_FDPIC
3253 BFD_RELOC_ARM_TLS_IE32_FDPIC
3255 ARM FDPIC specific relocations.
3258 BFD_RELOC_ARM_JUMP_SLOT
3260 BFD_RELOC_ARM_GLOB_DAT
3266 BFD_RELOC_ARM_RELATIVE
3268 BFD_RELOC_ARM_GOTOFF
3272 BFD_RELOC_ARM_GOT_PREL
3274 Relocations for setting up GOTs and PLTs for shared libraries.
3277 BFD_RELOC_ARM_TLS_GD32
3279 BFD_RELOC_ARM_TLS_LDO32
3281 BFD_RELOC_ARM_TLS_LDM32
3283 BFD_RELOC_ARM_TLS_DTPOFF32
3285 BFD_RELOC_ARM_TLS_DTPMOD32
3287 BFD_RELOC_ARM_TLS_TPOFF32
3289 BFD_RELOC_ARM_TLS_IE32
3291 BFD_RELOC_ARM_TLS_LE32
3293 BFD_RELOC_ARM_TLS_GOTDESC
3295 BFD_RELOC_ARM_TLS_CALL
3297 BFD_RELOC_ARM_THM_TLS_CALL
3299 BFD_RELOC_ARM_TLS_DESCSEQ
3301 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3303 BFD_RELOC_ARM_TLS_DESC
3305 ARM thread-local storage relocations.
3308 BFD_RELOC_ARM_ALU_PC_G0_NC
3310 BFD_RELOC_ARM_ALU_PC_G0
3312 BFD_RELOC_ARM_ALU_PC_G1_NC
3314 BFD_RELOC_ARM_ALU_PC_G1
3316 BFD_RELOC_ARM_ALU_PC_G2
3318 BFD_RELOC_ARM_LDR_PC_G0
3320 BFD_RELOC_ARM_LDR_PC_G1
3322 BFD_RELOC_ARM_LDR_PC_G2
3324 BFD_RELOC_ARM_LDRS_PC_G0
3326 BFD_RELOC_ARM_LDRS_PC_G1
3328 BFD_RELOC_ARM_LDRS_PC_G2
3330 BFD_RELOC_ARM_LDC_PC_G0
3332 BFD_RELOC_ARM_LDC_PC_G1
3334 BFD_RELOC_ARM_LDC_PC_G2
3336 BFD_RELOC_ARM_ALU_SB_G0_NC
3338 BFD_RELOC_ARM_ALU_SB_G0
3340 BFD_RELOC_ARM_ALU_SB_G1_NC
3342 BFD_RELOC_ARM_ALU_SB_G1
3344 BFD_RELOC_ARM_ALU_SB_G2
3346 BFD_RELOC_ARM_LDR_SB_G0
3348 BFD_RELOC_ARM_LDR_SB_G1
3350 BFD_RELOC_ARM_LDR_SB_G2
3352 BFD_RELOC_ARM_LDRS_SB_G0
3354 BFD_RELOC_ARM_LDRS_SB_G1
3356 BFD_RELOC_ARM_LDRS_SB_G2
3358 BFD_RELOC_ARM_LDC_SB_G0
3360 BFD_RELOC_ARM_LDC_SB_G1
3362 BFD_RELOC_ARM_LDC_SB_G2
3364 ARM group relocations.
3369 Annotation of BX instructions.
3372 BFD_RELOC_ARM_IRELATIVE
3374 ARM support for STT_GNU_IFUNC.
3377 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3379 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3381 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3383 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3385 Thumb1 relocations to support execute-only code.
3388 BFD_RELOC_ARM_IMMEDIATE
3390 BFD_RELOC_ARM_ADRL_IMMEDIATE
3392 BFD_RELOC_ARM_T32_IMMEDIATE
3394 BFD_RELOC_ARM_T32_ADD_IMM
3396 BFD_RELOC_ARM_T32_IMM12
3398 BFD_RELOC_ARM_T32_ADD_PC12
3400 BFD_RELOC_ARM_SHIFT_IMM
3410 BFD_RELOC_ARM_CP_OFF_IMM
3412 BFD_RELOC_ARM_CP_OFF_IMM_S2
3414 BFD_RELOC_ARM_T32_CP_OFF_IMM
3416 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3418 BFD_RELOC_ARM_ADR_IMM
3420 BFD_RELOC_ARM_LDR_IMM
3422 BFD_RELOC_ARM_LITERAL
3424 BFD_RELOC_ARM_IN_POOL
3426 BFD_RELOC_ARM_OFFSET_IMM8
3428 BFD_RELOC_ARM_T32_OFFSET_U8
3430 BFD_RELOC_ARM_T32_OFFSET_IMM
3432 BFD_RELOC_ARM_HWLITERAL
3434 BFD_RELOC_ARM_THUMB_ADD
3436 BFD_RELOC_ARM_THUMB_IMM
3438 BFD_RELOC_ARM_THUMB_SHIFT
3440 These relocs are only used within the ARM assembler. They are not
3441 (at present) written to any object files.
3444 BFD_RELOC_SH_PCDISP8BY2
3446 BFD_RELOC_SH_PCDISP12BY2
3454 BFD_RELOC_SH_DISP12BY2
3456 BFD_RELOC_SH_DISP12BY4
3458 BFD_RELOC_SH_DISP12BY8
3462 BFD_RELOC_SH_DISP20BY8
3466 BFD_RELOC_SH_IMM4BY2
3468 BFD_RELOC_SH_IMM4BY4
3472 BFD_RELOC_SH_IMM8BY2
3474 BFD_RELOC_SH_IMM8BY4
3476 BFD_RELOC_SH_PCRELIMM8BY2
3478 BFD_RELOC_SH_PCRELIMM8BY4
3480 BFD_RELOC_SH_SWITCH16
3482 BFD_RELOC_SH_SWITCH32
3496 BFD_RELOC_SH_LOOP_START
3498 BFD_RELOC_SH_LOOP_END
3502 BFD_RELOC_SH_GLOB_DAT
3504 BFD_RELOC_SH_JMP_SLOT
3506 BFD_RELOC_SH_RELATIVE
3510 BFD_RELOC_SH_GOT_LOW16
3512 BFD_RELOC_SH_GOT_MEDLOW16
3514 BFD_RELOC_SH_GOT_MEDHI16
3516 BFD_RELOC_SH_GOT_HI16
3518 BFD_RELOC_SH_GOTPLT_LOW16
3520 BFD_RELOC_SH_GOTPLT_MEDLOW16
3522 BFD_RELOC_SH_GOTPLT_MEDHI16
3524 BFD_RELOC_SH_GOTPLT_HI16
3526 BFD_RELOC_SH_PLT_LOW16
3528 BFD_RELOC_SH_PLT_MEDLOW16
3530 BFD_RELOC_SH_PLT_MEDHI16
3532 BFD_RELOC_SH_PLT_HI16
3534 BFD_RELOC_SH_GOTOFF_LOW16
3536 BFD_RELOC_SH_GOTOFF_MEDLOW16
3538 BFD_RELOC_SH_GOTOFF_MEDHI16
3540 BFD_RELOC_SH_GOTOFF_HI16
3542 BFD_RELOC_SH_GOTPC_LOW16
3544 BFD_RELOC_SH_GOTPC_MEDLOW16
3546 BFD_RELOC_SH_GOTPC_MEDHI16
3548 BFD_RELOC_SH_GOTPC_HI16
3552 BFD_RELOC_SH_GLOB_DAT64
3554 BFD_RELOC_SH_JMP_SLOT64
3556 BFD_RELOC_SH_RELATIVE64
3558 BFD_RELOC_SH_GOT10BY4
3560 BFD_RELOC_SH_GOT10BY8
3562 BFD_RELOC_SH_GOTPLT10BY4
3564 BFD_RELOC_SH_GOTPLT10BY8
3566 BFD_RELOC_SH_GOTPLT32
3568 BFD_RELOC_SH_SHMEDIA_CODE
3574 BFD_RELOC_SH_IMMS6BY32
3580 BFD_RELOC_SH_IMMS10BY2
3582 BFD_RELOC_SH_IMMS10BY4
3584 BFD_RELOC_SH_IMMS10BY8
3590 BFD_RELOC_SH_IMM_LOW16
3592 BFD_RELOC_SH_IMM_LOW16_PCREL
3594 BFD_RELOC_SH_IMM_MEDLOW16
3596 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3598 BFD_RELOC_SH_IMM_MEDHI16
3600 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3602 BFD_RELOC_SH_IMM_HI16
3604 BFD_RELOC_SH_IMM_HI16_PCREL
3608 BFD_RELOC_SH_TLS_GD_32
3610 BFD_RELOC_SH_TLS_LD_32
3612 BFD_RELOC_SH_TLS_LDO_32
3614 BFD_RELOC_SH_TLS_IE_32
3616 BFD_RELOC_SH_TLS_LE_32
3618 BFD_RELOC_SH_TLS_DTPMOD32
3620 BFD_RELOC_SH_TLS_DTPOFF32
3622 BFD_RELOC_SH_TLS_TPOFF32
3626 BFD_RELOC_SH_GOTOFF20
3628 BFD_RELOC_SH_GOTFUNCDESC
3630 BFD_RELOC_SH_GOTFUNCDESC20
3632 BFD_RELOC_SH_GOTOFFFUNCDESC
3634 BFD_RELOC_SH_GOTOFFFUNCDESC20
3636 BFD_RELOC_SH_FUNCDESC
3638 Renesas / SuperH SH relocs. Not all of these appear in object files.
3661 BFD_RELOC_ARC_SECTOFF
3663 BFD_RELOC_ARC_S21H_PCREL
3665 BFD_RELOC_ARC_S21W_PCREL
3667 BFD_RELOC_ARC_S25H_PCREL
3669 BFD_RELOC_ARC_S25W_PCREL
3673 BFD_RELOC_ARC_SDA_LDST
3675 BFD_RELOC_ARC_SDA_LDST1
3677 BFD_RELOC_ARC_SDA_LDST2
3679 BFD_RELOC_ARC_SDA16_LD
3681 BFD_RELOC_ARC_SDA16_LD1
3683 BFD_RELOC_ARC_SDA16_LD2
3685 BFD_RELOC_ARC_S13_PCREL
3691 BFD_RELOC_ARC_32_ME_S
3693 BFD_RELOC_ARC_N32_ME
3695 BFD_RELOC_ARC_SECTOFF_ME
3697 BFD_RELOC_ARC_SDA32_ME
3701 BFD_RELOC_AC_SECTOFF_U8
3703 BFD_RELOC_AC_SECTOFF_U8_1
3705 BFD_RELOC_AC_SECTOFF_U8_2
3707 BFD_RELOC_AC_SECTOFF_S9
3709 BFD_RELOC_AC_SECTOFF_S9_1
3711 BFD_RELOC_AC_SECTOFF_S9_2
3713 BFD_RELOC_ARC_SECTOFF_ME_1
3715 BFD_RELOC_ARC_SECTOFF_ME_2
3717 BFD_RELOC_ARC_SECTOFF_1
3719 BFD_RELOC_ARC_SECTOFF_2
3721 BFD_RELOC_ARC_SDA_12
3723 BFD_RELOC_ARC_SDA16_ST2
3725 BFD_RELOC_ARC_32_PCREL
3731 BFD_RELOC_ARC_GOTPC32
3737 BFD_RELOC_ARC_GLOB_DAT
3739 BFD_RELOC_ARC_JMP_SLOT
3741 BFD_RELOC_ARC_RELATIVE
3743 BFD_RELOC_ARC_GOTOFF
3747 BFD_RELOC_ARC_S21W_PCREL_PLT
3749 BFD_RELOC_ARC_S25H_PCREL_PLT
3751 BFD_RELOC_ARC_TLS_DTPMOD
3753 BFD_RELOC_ARC_TLS_TPOFF
3755 BFD_RELOC_ARC_TLS_GD_GOT
3757 BFD_RELOC_ARC_TLS_GD_LD
3759 BFD_RELOC_ARC_TLS_GD_CALL
3761 BFD_RELOC_ARC_TLS_IE_GOT
3763 BFD_RELOC_ARC_TLS_DTPOFF
3765 BFD_RELOC_ARC_TLS_DTPOFF_S9
3767 BFD_RELOC_ARC_TLS_LE_S9
3769 BFD_RELOC_ARC_TLS_LE_32
3771 BFD_RELOC_ARC_S25W_PCREL_PLT
3773 BFD_RELOC_ARC_S21H_PCREL_PLT
3775 BFD_RELOC_ARC_NPS_CMEM16
3777 BFD_RELOC_ARC_JLI_SECTOFF
3782 BFD_RELOC_BFIN_16_IMM
3784 ADI Blackfin 16 bit immediate absolute reloc.
3786 BFD_RELOC_BFIN_16_HIGH
3788 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3790 BFD_RELOC_BFIN_4_PCREL
3792 ADI Blackfin 'a' part of LSETUP.
3794 BFD_RELOC_BFIN_5_PCREL
3798 BFD_RELOC_BFIN_16_LOW
3800 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3802 BFD_RELOC_BFIN_10_PCREL
3806 BFD_RELOC_BFIN_11_PCREL
3808 ADI Blackfin 'b' part of LSETUP.
3810 BFD_RELOC_BFIN_12_PCREL_JUMP
3814 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3816 ADI Blackfin Short jump, pcrel.
3818 BFD_RELOC_BFIN_24_PCREL_CALL_X
3820 ADI Blackfin Call.x not implemented.
3822 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3824 ADI Blackfin Long Jump pcrel.
3826 BFD_RELOC_BFIN_GOT17M4
3828 BFD_RELOC_BFIN_GOTHI
3830 BFD_RELOC_BFIN_GOTLO
3832 BFD_RELOC_BFIN_FUNCDESC
3834 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3836 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3838 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3840 BFD_RELOC_BFIN_FUNCDESC_VALUE
3842 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3844 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3846 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3848 BFD_RELOC_BFIN_GOTOFF17M4
3850 BFD_RELOC_BFIN_GOTOFFHI
3852 BFD_RELOC_BFIN_GOTOFFLO
3854 ADI Blackfin FD-PIC relocations.
3858 ADI Blackfin GOT relocation.
3860 BFD_RELOC_BFIN_PLTPC
3862 ADI Blackfin PLTPC relocation.
3864 BFD_ARELOC_BFIN_PUSH
3866 ADI Blackfin arithmetic relocation.
3868 BFD_ARELOC_BFIN_CONST
3870 ADI Blackfin arithmetic relocation.
3874 ADI Blackfin arithmetic relocation.
3878 ADI Blackfin arithmetic relocation.
3880 BFD_ARELOC_BFIN_MULT
3882 ADI Blackfin arithmetic relocation.
3886 ADI Blackfin arithmetic relocation.
3890 ADI Blackfin arithmetic relocation.
3892 BFD_ARELOC_BFIN_LSHIFT
3894 ADI Blackfin arithmetic relocation.
3896 BFD_ARELOC_BFIN_RSHIFT
3898 ADI Blackfin arithmetic relocation.
3902 ADI Blackfin arithmetic relocation.
3906 ADI Blackfin arithmetic relocation.
3910 ADI Blackfin arithmetic relocation.
3912 BFD_ARELOC_BFIN_LAND
3914 ADI Blackfin arithmetic relocation.
3918 ADI Blackfin arithmetic relocation.
3922 ADI Blackfin arithmetic relocation.
3926 ADI Blackfin arithmetic relocation.
3928 BFD_ARELOC_BFIN_COMP
3930 ADI Blackfin arithmetic relocation.
3932 BFD_ARELOC_BFIN_PAGE
3934 ADI Blackfin arithmetic relocation.
3936 BFD_ARELOC_BFIN_HWPAGE
3938 ADI Blackfin arithmetic relocation.
3940 BFD_ARELOC_BFIN_ADDR
3942 ADI Blackfin arithmetic relocation.
3945 BFD_RELOC_D10V_10_PCREL_R
3947 Mitsubishi D10V relocs.
3948 This is a 10-bit reloc with the right 2 bits
3951 BFD_RELOC_D10V_10_PCREL_L
3953 Mitsubishi D10V relocs.
3954 This is a 10-bit reloc with the right 2 bits
3955 assumed to be 0. This is the same as the previous reloc
3956 except it is in the left container, i.e.,
3957 shifted left 15 bits.
3961 This is an 18-bit reloc with the right 2 bits
3964 BFD_RELOC_D10V_18_PCREL
3966 This is an 18-bit reloc with the right 2 bits
3972 Mitsubishi D30V relocs.
3973 This is a 6-bit absolute reloc.
3975 BFD_RELOC_D30V_9_PCREL
3977 This is a 6-bit pc-relative reloc with
3978 the right 3 bits assumed to be 0.
3980 BFD_RELOC_D30V_9_PCREL_R
3982 This is a 6-bit pc-relative reloc with
3983 the right 3 bits assumed to be 0. Same
3984 as the previous reloc but on the right side
3989 This is a 12-bit absolute reloc with the
3990 right 3 bitsassumed to be 0.
3992 BFD_RELOC_D30V_15_PCREL
3994 This is a 12-bit pc-relative reloc with
3995 the right 3 bits assumed to be 0.
3997 BFD_RELOC_D30V_15_PCREL_R
3999 This is a 12-bit pc-relative reloc with
4000 the right 3 bits assumed to be 0. Same
4001 as the previous reloc but on the right side
4006 This is an 18-bit absolute reloc with
4007 the right 3 bits assumed to be 0.
4009 BFD_RELOC_D30V_21_PCREL
4011 This is an 18-bit pc-relative reloc with
4012 the right 3 bits assumed to be 0.
4014 BFD_RELOC_D30V_21_PCREL_R
4016 This is an 18-bit pc-relative reloc with
4017 the right 3 bits assumed to be 0. Same
4018 as the previous reloc but on the right side
4023 This is a 32-bit absolute reloc.
4025 BFD_RELOC_D30V_32_PCREL
4027 This is a 32-bit pc-relative reloc.
4030 BFD_RELOC_DLX_HI16_S
4045 BFD_RELOC_M32C_RL_JUMP
4047 BFD_RELOC_M32C_RL_1ADDR
4049 BFD_RELOC_M32C_RL_2ADDR
4051 Renesas M16C/M32C Relocations.
4056 Renesas M32R (formerly Mitsubishi M32R) relocs.
4057 This is a 24 bit absolute address.
4059 BFD_RELOC_M32R_10_PCREL
4061 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
4063 BFD_RELOC_M32R_18_PCREL
4065 This is an 18-bit reloc with the right 2 bits assumed to be 0.
4067 BFD_RELOC_M32R_26_PCREL
4069 This is a 26-bit reloc with the right 2 bits assumed to be 0.
4071 BFD_RELOC_M32R_HI16_ULO
4073 This is a 16-bit reloc containing the high 16 bits of an address
4074 used when the lower 16 bits are treated as unsigned.
4076 BFD_RELOC_M32R_HI16_SLO
4078 This is a 16-bit reloc containing the high 16 bits of an address
4079 used when the lower 16 bits are treated as signed.
4083 This is a 16-bit reloc containing the lower 16 bits of an address.
4085 BFD_RELOC_M32R_SDA16
4087 This is a 16-bit reloc containing the small data area offset for use in
4088 add3, load, and store instructions.
4090 BFD_RELOC_M32R_GOT24
4092 BFD_RELOC_M32R_26_PLTREL
4096 BFD_RELOC_M32R_GLOB_DAT
4098 BFD_RELOC_M32R_JMP_SLOT
4100 BFD_RELOC_M32R_RELATIVE
4102 BFD_RELOC_M32R_GOTOFF
4104 BFD_RELOC_M32R_GOTOFF_HI_ULO
4106 BFD_RELOC_M32R_GOTOFF_HI_SLO
4108 BFD_RELOC_M32R_GOTOFF_LO
4110 BFD_RELOC_M32R_GOTPC24
4112 BFD_RELOC_M32R_GOT16_HI_ULO
4114 BFD_RELOC_M32R_GOT16_HI_SLO
4116 BFD_RELOC_M32R_GOT16_LO
4118 BFD_RELOC_M32R_GOTPC_HI_ULO
4120 BFD_RELOC_M32R_GOTPC_HI_SLO
4122 BFD_RELOC_M32R_GOTPC_LO
4131 This is a 20 bit absolute address.
4133 BFD_RELOC_NDS32_9_PCREL
4135 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4137 BFD_RELOC_NDS32_WORD_9_PCREL
4139 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4141 BFD_RELOC_NDS32_15_PCREL
4143 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4145 BFD_RELOC_NDS32_17_PCREL
4147 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4149 BFD_RELOC_NDS32_25_PCREL
4151 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4153 BFD_RELOC_NDS32_HI20
4155 This is a 20-bit reloc containing the high 20 bits of an address
4156 used with the lower 12 bits
4158 BFD_RELOC_NDS32_LO12S3
4160 This is a 12-bit reloc containing the lower 12 bits of an address
4161 then shift right by 3. This is used with ldi,sdi...
4163 BFD_RELOC_NDS32_LO12S2
4165 This is a 12-bit reloc containing the lower 12 bits of an address
4166 then shift left by 2. This is used with lwi,swi...
4168 BFD_RELOC_NDS32_LO12S1
4170 This is a 12-bit reloc containing the lower 12 bits of an address
4171 then shift left by 1. This is used with lhi,shi...
4173 BFD_RELOC_NDS32_LO12S0
4175 This is a 12-bit reloc containing the lower 12 bits of an address
4176 then shift left by 0. This is used with lbisbi...
4178 BFD_RELOC_NDS32_LO12S0_ORI
4180 This is a 12-bit reloc containing the lower 12 bits of an address
4181 then shift left by 0. This is only used with branch relaxations
4183 BFD_RELOC_NDS32_SDA15S3
4185 This is a 15-bit reloc containing the small data area 18-bit signed offset
4186 and shift left by 3 for use in ldi, sdi...
4188 BFD_RELOC_NDS32_SDA15S2
4190 This is a 15-bit reloc containing the small data area 17-bit signed offset
4191 and shift left by 2 for use in lwi, swi...
4193 BFD_RELOC_NDS32_SDA15S1
4195 This is a 15-bit reloc containing the small data area 16-bit signed offset
4196 and shift left by 1 for use in lhi, shi...
4198 BFD_RELOC_NDS32_SDA15S0
4200 This is a 15-bit reloc containing the small data area 15-bit signed offset
4201 and shift left by 0 for use in lbi, sbi...
4203 BFD_RELOC_NDS32_SDA16S3
4205 This is a 16-bit reloc containing the small data area 16-bit signed offset
4208 BFD_RELOC_NDS32_SDA17S2
4210 This is a 17-bit reloc containing the small data area 17-bit signed offset
4211 and shift left by 2 for use in lwi.gp, swi.gp...
4213 BFD_RELOC_NDS32_SDA18S1
4215 This is a 18-bit reloc containing the small data area 18-bit signed offset
4216 and shift left by 1 for use in lhi.gp, shi.gp...
4218 BFD_RELOC_NDS32_SDA19S0
4220 This is a 19-bit reloc containing the small data area 19-bit signed offset
4221 and shift left by 0 for use in lbi.gp, sbi.gp...
4223 BFD_RELOC_NDS32_GOT20
4225 BFD_RELOC_NDS32_9_PLTREL
4227 BFD_RELOC_NDS32_25_PLTREL
4229 BFD_RELOC_NDS32_COPY
4231 BFD_RELOC_NDS32_GLOB_DAT
4233 BFD_RELOC_NDS32_JMP_SLOT
4235 BFD_RELOC_NDS32_RELATIVE
4237 BFD_RELOC_NDS32_GOTOFF
4239 BFD_RELOC_NDS32_GOTOFF_HI20
4241 BFD_RELOC_NDS32_GOTOFF_LO12
4243 BFD_RELOC_NDS32_GOTPC20
4245 BFD_RELOC_NDS32_GOT_HI20
4247 BFD_RELOC_NDS32_GOT_LO12
4249 BFD_RELOC_NDS32_GOTPC_HI20
4251 BFD_RELOC_NDS32_GOTPC_LO12
4255 BFD_RELOC_NDS32_INSN16
4257 BFD_RELOC_NDS32_LABEL
4259 BFD_RELOC_NDS32_LONGCALL1
4261 BFD_RELOC_NDS32_LONGCALL2
4263 BFD_RELOC_NDS32_LONGCALL3
4265 BFD_RELOC_NDS32_LONGJUMP1
4267 BFD_RELOC_NDS32_LONGJUMP2
4269 BFD_RELOC_NDS32_LONGJUMP3
4271 BFD_RELOC_NDS32_LOADSTORE
4273 BFD_RELOC_NDS32_9_FIXED
4275 BFD_RELOC_NDS32_15_FIXED
4277 BFD_RELOC_NDS32_17_FIXED
4279 BFD_RELOC_NDS32_25_FIXED
4281 BFD_RELOC_NDS32_LONGCALL4
4283 BFD_RELOC_NDS32_LONGCALL5
4285 BFD_RELOC_NDS32_LONGCALL6
4287 BFD_RELOC_NDS32_LONGJUMP4
4289 BFD_RELOC_NDS32_LONGJUMP5
4291 BFD_RELOC_NDS32_LONGJUMP6
4293 BFD_RELOC_NDS32_LONGJUMP7
4297 BFD_RELOC_NDS32_PLTREL_HI20
4299 BFD_RELOC_NDS32_PLTREL_LO12
4301 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4303 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4307 BFD_RELOC_NDS32_SDA12S2_DP
4309 BFD_RELOC_NDS32_SDA12S2_SP
4311 BFD_RELOC_NDS32_LO12S2_DP
4313 BFD_RELOC_NDS32_LO12S2_SP
4317 BFD_RELOC_NDS32_DWARF2_OP1
4319 BFD_RELOC_NDS32_DWARF2_OP2
4321 BFD_RELOC_NDS32_DWARF2_LEB
4323 for dwarf2 debug_line.
4325 BFD_RELOC_NDS32_UPDATE_TA
4327 for eliminate 16-bit instructions
4329 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4331 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4333 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4335 BFD_RELOC_NDS32_GOT_LO15
4337 BFD_RELOC_NDS32_GOT_LO19
4339 BFD_RELOC_NDS32_GOTOFF_LO15
4341 BFD_RELOC_NDS32_GOTOFF_LO19
4343 BFD_RELOC_NDS32_GOT15S2
4345 BFD_RELOC_NDS32_GOT17S2
4347 for PIC object relaxation
4352 This is a 5 bit absolute address.
4354 BFD_RELOC_NDS32_10_UPCREL
4356 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4358 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4360 If fp were omitted, fp can used as another gp.
4362 BFD_RELOC_NDS32_RELAX_ENTRY
4364 BFD_RELOC_NDS32_GOT_SUFF
4366 BFD_RELOC_NDS32_GOTOFF_SUFF
4368 BFD_RELOC_NDS32_PLT_GOT_SUFF
4370 BFD_RELOC_NDS32_MULCALL_SUFF
4374 BFD_RELOC_NDS32_PTR_COUNT
4376 BFD_RELOC_NDS32_PTR_RESOLVED
4378 BFD_RELOC_NDS32_PLTBLOCK
4380 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4382 BFD_RELOC_NDS32_RELAX_REGION_END
4384 BFD_RELOC_NDS32_MINUEND
4386 BFD_RELOC_NDS32_SUBTRAHEND
4388 BFD_RELOC_NDS32_DIFF8
4390 BFD_RELOC_NDS32_DIFF16
4392 BFD_RELOC_NDS32_DIFF32
4394 BFD_RELOC_NDS32_DIFF_ULEB128
4396 BFD_RELOC_NDS32_EMPTY
4398 relaxation relative relocation types
4400 BFD_RELOC_NDS32_25_ABS
4402 This is a 25 bit absolute address.
4404 BFD_RELOC_NDS32_DATA
4406 BFD_RELOC_NDS32_TRAN
4408 BFD_RELOC_NDS32_17IFC_PCREL
4410 BFD_RELOC_NDS32_10IFCU_PCREL
4412 For ex9 and ifc using.
4414 BFD_RELOC_NDS32_TPOFF
4416 BFD_RELOC_NDS32_TLS_LE_HI20
4418 BFD_RELOC_NDS32_TLS_LE_LO12
4420 BFD_RELOC_NDS32_TLS_LE_ADD
4422 BFD_RELOC_NDS32_TLS_LE_LS
4424 BFD_RELOC_NDS32_GOTTPOFF
4426 BFD_RELOC_NDS32_TLS_IE_HI20
4428 BFD_RELOC_NDS32_TLS_IE_LO12S2
4430 BFD_RELOC_NDS32_TLS_TPOFF
4432 BFD_RELOC_NDS32_TLS_LE_20
4434 BFD_RELOC_NDS32_TLS_LE_15S0
4436 BFD_RELOC_NDS32_TLS_LE_15S1
4438 BFD_RELOC_NDS32_TLS_LE_15S2
4444 BFD_RELOC_V850_9_PCREL
4446 This is a 9-bit reloc
4448 BFD_RELOC_V850_22_PCREL
4450 This is a 22-bit reloc
4453 BFD_RELOC_V850_SDA_16_16_OFFSET
4455 This is a 16 bit offset from the short data area pointer.
4457 BFD_RELOC_V850_SDA_15_16_OFFSET
4459 This is a 16 bit offset (of which only 15 bits are used) from the
4460 short data area pointer.
4462 BFD_RELOC_V850_ZDA_16_16_OFFSET
4464 This is a 16 bit offset from the zero data area pointer.
4466 BFD_RELOC_V850_ZDA_15_16_OFFSET
4468 This is a 16 bit offset (of which only 15 bits are used) from the
4469 zero data area pointer.
4471 BFD_RELOC_V850_TDA_6_8_OFFSET
4473 This is an 8 bit offset (of which only 6 bits are used) from the
4474 tiny data area pointer.
4476 BFD_RELOC_V850_TDA_7_8_OFFSET
4478 This is an 8bit offset (of which only 7 bits are used) from the tiny
4481 BFD_RELOC_V850_TDA_7_7_OFFSET
4483 This is a 7 bit offset from the tiny data area pointer.
4485 BFD_RELOC_V850_TDA_16_16_OFFSET
4487 This is a 16 bit offset from the tiny data area pointer.
4490 BFD_RELOC_V850_TDA_4_5_OFFSET
4492 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4495 BFD_RELOC_V850_TDA_4_4_OFFSET
4497 This is a 4 bit offset from the tiny data area pointer.
4499 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4501 This is a 16 bit offset from the short data area pointer, with the
4502 bits placed non-contiguously in the instruction.
4504 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4506 This is a 16 bit offset from the zero data area pointer, with the
4507 bits placed non-contiguously in the instruction.
4509 BFD_RELOC_V850_CALLT_6_7_OFFSET
4511 This is a 6 bit offset from the call table base pointer.
4513 BFD_RELOC_V850_CALLT_16_16_OFFSET
4515 This is a 16 bit offset from the call table base pointer.
4517 BFD_RELOC_V850_LONGCALL
4519 Used for relaxing indirect function calls.
4521 BFD_RELOC_V850_LONGJUMP
4523 Used for relaxing indirect jumps.
4525 BFD_RELOC_V850_ALIGN
4527 Used to maintain alignment whilst relaxing.
4529 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4531 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4534 BFD_RELOC_V850_16_PCREL
4536 This is a 16-bit reloc.
4538 BFD_RELOC_V850_17_PCREL
4540 This is a 17-bit reloc.
4544 This is a 23-bit reloc.
4546 BFD_RELOC_V850_32_PCREL
4548 This is a 32-bit reloc.
4550 BFD_RELOC_V850_32_ABS
4552 This is a 32-bit reloc.
4554 BFD_RELOC_V850_16_SPLIT_OFFSET
4556 This is a 16-bit reloc.
4558 BFD_RELOC_V850_16_S1
4560 This is a 16-bit reloc.
4562 BFD_RELOC_V850_LO16_S1
4564 Low 16 bits. 16 bit shifted by 1.
4566 BFD_RELOC_V850_CALLT_15_16_OFFSET
4568 This is a 16 bit offset from the call table base pointer.
4570 BFD_RELOC_V850_32_GOTPCREL
4574 BFD_RELOC_V850_16_GOT
4578 BFD_RELOC_V850_32_GOT
4582 BFD_RELOC_V850_22_PLT_PCREL
4586 BFD_RELOC_V850_32_PLT_PCREL
4594 BFD_RELOC_V850_GLOB_DAT
4598 BFD_RELOC_V850_JMP_SLOT
4602 BFD_RELOC_V850_RELATIVE
4606 BFD_RELOC_V850_16_GOTOFF
4610 BFD_RELOC_V850_32_GOTOFF
4625 This is a 8bit DP reloc for the tms320c30, where the most
4626 significant 8 bits of a 24 bit word are placed into the least
4627 significant 8 bits of the opcode.
4630 BFD_RELOC_TIC54X_PARTLS7
4632 This is a 7bit reloc for the tms320c54x, where the least
4633 significant 7 bits of a 16 bit word are placed into the least
4634 significant 7 bits of the opcode.
4637 BFD_RELOC_TIC54X_PARTMS9
4639 This is a 9bit DP reloc for the tms320c54x, where the most
4640 significant 9 bits of a 16 bit word are placed into the least
4641 significant 9 bits of the opcode.
4646 This is an extended address 23-bit reloc for the tms320c54x.
4649 BFD_RELOC_TIC54X_16_OF_23
4651 This is a 16-bit reloc for the tms320c54x, where the least
4652 significant 16 bits of a 23-bit extended address are placed into
4656 BFD_RELOC_TIC54X_MS7_OF_23
4658 This is a reloc for the tms320c54x, where the most
4659 significant 7 bits of a 23-bit extended address are placed into
4663 BFD_RELOC_C6000_PCR_S21
4665 BFD_RELOC_C6000_PCR_S12
4667 BFD_RELOC_C6000_PCR_S10
4669 BFD_RELOC_C6000_PCR_S7
4671 BFD_RELOC_C6000_ABS_S16
4673 BFD_RELOC_C6000_ABS_L16
4675 BFD_RELOC_C6000_ABS_H16
4677 BFD_RELOC_C6000_SBR_U15_B
4679 BFD_RELOC_C6000_SBR_U15_H
4681 BFD_RELOC_C6000_SBR_U15_W
4683 BFD_RELOC_C6000_SBR_S16
4685 BFD_RELOC_C6000_SBR_L16_B
4687 BFD_RELOC_C6000_SBR_L16_H
4689 BFD_RELOC_C6000_SBR_L16_W
4691 BFD_RELOC_C6000_SBR_H16_B
4693 BFD_RELOC_C6000_SBR_H16_H
4695 BFD_RELOC_C6000_SBR_H16_W
4697 BFD_RELOC_C6000_SBR_GOT_U15_W
4699 BFD_RELOC_C6000_SBR_GOT_L16_W
4701 BFD_RELOC_C6000_SBR_GOT_H16_W
4703 BFD_RELOC_C6000_DSBT_INDEX
4705 BFD_RELOC_C6000_PREL31
4707 BFD_RELOC_C6000_COPY
4709 BFD_RELOC_C6000_JUMP_SLOT
4711 BFD_RELOC_C6000_EHTYPE
4713 BFD_RELOC_C6000_PCR_H16
4715 BFD_RELOC_C6000_PCR_L16
4717 BFD_RELOC_C6000_ALIGN
4719 BFD_RELOC_C6000_FPHEAD
4721 BFD_RELOC_C6000_NOCMP
4723 TMS320C6000 relocations.
4728 This is a 48 bit reloc for the FR30 that stores 32 bits.
4732 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4735 BFD_RELOC_FR30_6_IN_4
4737 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4740 BFD_RELOC_FR30_8_IN_8
4742 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4745 BFD_RELOC_FR30_9_IN_8
4747 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4750 BFD_RELOC_FR30_10_IN_8
4752 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4755 BFD_RELOC_FR30_9_PCREL
4757 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4758 short offset into 8 bits.
4760 BFD_RELOC_FR30_12_PCREL
4762 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4763 short offset into 11 bits.
4766 BFD_RELOC_MCORE_PCREL_IMM8BY4
4768 BFD_RELOC_MCORE_PCREL_IMM11BY2
4770 BFD_RELOC_MCORE_PCREL_IMM4BY2
4772 BFD_RELOC_MCORE_PCREL_32
4774 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4778 Motorola Mcore relocations.
4787 BFD_RELOC_MEP_PCREL8A2
4789 BFD_RELOC_MEP_PCREL12A2
4791 BFD_RELOC_MEP_PCREL17A2
4793 BFD_RELOC_MEP_PCREL24A2
4795 BFD_RELOC_MEP_PCABS24A2
4807 BFD_RELOC_MEP_TPREL7
4809 BFD_RELOC_MEP_TPREL7A2
4811 BFD_RELOC_MEP_TPREL7A4
4813 BFD_RELOC_MEP_UIMM24
4815 BFD_RELOC_MEP_ADDR24A4
4817 BFD_RELOC_MEP_GNU_VTINHERIT
4819 BFD_RELOC_MEP_GNU_VTENTRY
4821 Toshiba Media Processor Relocations.
4825 BFD_RELOC_METAG_HIADDR16
4827 BFD_RELOC_METAG_LOADDR16
4829 BFD_RELOC_METAG_RELBRANCH
4831 BFD_RELOC_METAG_GETSETOFF
4833 BFD_RELOC_METAG_HIOG
4835 BFD_RELOC_METAG_LOOG
4837 BFD_RELOC_METAG_REL8
4839 BFD_RELOC_METAG_REL16
4841 BFD_RELOC_METAG_HI16_GOTOFF
4843 BFD_RELOC_METAG_LO16_GOTOFF
4845 BFD_RELOC_METAG_GETSET_GOTOFF
4847 BFD_RELOC_METAG_GETSET_GOT
4849 BFD_RELOC_METAG_HI16_GOTPC
4851 BFD_RELOC_METAG_LO16_GOTPC
4853 BFD_RELOC_METAG_HI16_PLT
4855 BFD_RELOC_METAG_LO16_PLT
4857 BFD_RELOC_METAG_RELBRANCH_PLT
4859 BFD_RELOC_METAG_GOTOFF
4863 BFD_RELOC_METAG_COPY
4865 BFD_RELOC_METAG_JMP_SLOT
4867 BFD_RELOC_METAG_RELATIVE
4869 BFD_RELOC_METAG_GLOB_DAT
4871 BFD_RELOC_METAG_TLS_GD
4873 BFD_RELOC_METAG_TLS_LDM
4875 BFD_RELOC_METAG_TLS_LDO_HI16
4877 BFD_RELOC_METAG_TLS_LDO_LO16
4879 BFD_RELOC_METAG_TLS_LDO
4881 BFD_RELOC_METAG_TLS_IE
4883 BFD_RELOC_METAG_TLS_IENONPIC
4885 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4887 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4889 BFD_RELOC_METAG_TLS_TPOFF
4891 BFD_RELOC_METAG_TLS_DTPMOD
4893 BFD_RELOC_METAG_TLS_DTPOFF
4895 BFD_RELOC_METAG_TLS_LE
4897 BFD_RELOC_METAG_TLS_LE_HI16
4899 BFD_RELOC_METAG_TLS_LE_LO16
4901 Imagination Technologies Meta relocations.
4906 BFD_RELOC_MMIX_GETA_1
4908 BFD_RELOC_MMIX_GETA_2
4910 BFD_RELOC_MMIX_GETA_3
4912 These are relocations for the GETA instruction.
4914 BFD_RELOC_MMIX_CBRANCH
4916 BFD_RELOC_MMIX_CBRANCH_J
4918 BFD_RELOC_MMIX_CBRANCH_1
4920 BFD_RELOC_MMIX_CBRANCH_2
4922 BFD_RELOC_MMIX_CBRANCH_3
4924 These are relocations for a conditional branch instruction.
4926 BFD_RELOC_MMIX_PUSHJ
4928 BFD_RELOC_MMIX_PUSHJ_1
4930 BFD_RELOC_MMIX_PUSHJ_2
4932 BFD_RELOC_MMIX_PUSHJ_3
4934 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4936 These are relocations for the PUSHJ instruction.
4940 BFD_RELOC_MMIX_JMP_1
4942 BFD_RELOC_MMIX_JMP_2
4944 BFD_RELOC_MMIX_JMP_3
4946 These are relocations for the JMP instruction.
4948 BFD_RELOC_MMIX_ADDR19
4950 This is a relocation for a relative address as in a GETA instruction or
4953 BFD_RELOC_MMIX_ADDR27
4955 This is a relocation for a relative address as in a JMP instruction.
4957 BFD_RELOC_MMIX_REG_OR_BYTE
4959 This is a relocation for an instruction field that may be a general
4960 register or a value 0..255.
4964 This is a relocation for an instruction field that may be a general
4967 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4969 This is a relocation for two instruction fields holding a register and
4970 an offset, the equivalent of the relocation.
4972 BFD_RELOC_MMIX_LOCAL
4974 This relocation is an assertion that the expression is not allocated as
4975 a global register. It does not modify contents.
4978 BFD_RELOC_AVR_7_PCREL
4980 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4981 short offset into 7 bits.
4983 BFD_RELOC_AVR_13_PCREL
4985 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4986 short offset into 12 bits.
4990 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4991 program memory address) into 16 bits.
4993 BFD_RELOC_AVR_LO8_LDI
4995 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4996 data memory address) into 8 bit immediate value of LDI insn.
4998 BFD_RELOC_AVR_HI8_LDI
5000 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5001 of data memory address) into 8 bit immediate value of LDI insn.
5003 BFD_RELOC_AVR_HH8_LDI
5005 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
5006 of program memory address) into 8 bit immediate value of LDI insn.
5008 BFD_RELOC_AVR_MS8_LDI
5010 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
5011 of 32 bit value) into 8 bit immediate value of LDI insn.
5013 BFD_RELOC_AVR_LO8_LDI_NEG
5015 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5016 (usually data memory address) into 8 bit immediate value of SUBI insn.
5018 BFD_RELOC_AVR_HI8_LDI_NEG
5020 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5021 (high 8 bit of data memory address) into 8 bit immediate value of
5024 BFD_RELOC_AVR_HH8_LDI_NEG
5026 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5027 (most high 8 bit of program memory address) into 8 bit immediate value
5028 of LDI or SUBI insn.
5030 BFD_RELOC_AVR_MS8_LDI_NEG
5032 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
5033 of 32 bit value) into 8 bit immediate value of LDI insn.
5035 BFD_RELOC_AVR_LO8_LDI_PM
5037 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
5038 command address) into 8 bit immediate value of LDI insn.
5040 BFD_RELOC_AVR_LO8_LDI_GS
5042 This is a 16 bit reloc for the AVR that stores 8 bit value
5043 (command address) into 8 bit immediate value of LDI insn. If the address
5044 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5047 BFD_RELOC_AVR_HI8_LDI_PM
5049 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5050 of command address) into 8 bit immediate value of LDI insn.
5052 BFD_RELOC_AVR_HI8_LDI_GS
5054 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5055 of command address) into 8 bit immediate value of LDI insn. If the address
5056 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5059 BFD_RELOC_AVR_HH8_LDI_PM
5061 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
5062 of command address) into 8 bit immediate value of LDI insn.
5064 BFD_RELOC_AVR_LO8_LDI_PM_NEG
5066 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5067 (usually command address) into 8 bit immediate value of SUBI insn.
5069 BFD_RELOC_AVR_HI8_LDI_PM_NEG
5071 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5072 (high 8 bit of 16 bit command address) into 8 bit immediate value
5075 BFD_RELOC_AVR_HH8_LDI_PM_NEG
5077 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5078 (high 6 bit of 22 bit command address) into 8 bit immediate
5083 This is a 32 bit reloc for the AVR that stores 23 bit value
5088 This is a 16 bit reloc for the AVR that stores all needed bits
5089 for absolute addressing with ldi with overflow check to linktime
5093 This is a 6 bit reloc for the AVR that stores offset for ldd/std
5096 BFD_RELOC_AVR_6_ADIW
5098 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
5103 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
5104 in .byte lo8(symbol)
5108 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
5109 in .byte hi8(symbol)
5113 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
5114 in .byte hlo8(symbol)
5118 BFD_RELOC_AVR_DIFF16
5120 BFD_RELOC_AVR_DIFF32
5122 AVR relocations to mark the difference of two local symbols.
5123 These are only needed to support linker relaxation and can be ignored
5124 when not relaxing. The field is set to the value of the difference
5125 assuming no relaxation. The relocation encodes the position of the
5126 second symbol so the linker can determine whether to adjust the field
5129 BFD_RELOC_AVR_LDS_STS_16
5131 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5132 lds and sts instructions supported only tiny core.
5136 This is a 6 bit reloc for the AVR that stores an I/O register
5137 number for the IN and OUT instructions
5141 This is a 5 bit reloc for the AVR that stores an I/O register
5142 number for the SBIC, SBIS, SBI and CBI instructions
5145 BFD_RELOC_RISCV_HI20
5147 BFD_RELOC_RISCV_PCREL_HI20
5149 BFD_RELOC_RISCV_PCREL_LO12_I
5151 BFD_RELOC_RISCV_PCREL_LO12_S
5153 BFD_RELOC_RISCV_LO12_I
5155 BFD_RELOC_RISCV_LO12_S
5157 BFD_RELOC_RISCV_GPREL12_I
5159 BFD_RELOC_RISCV_GPREL12_S
5161 BFD_RELOC_RISCV_TPREL_HI20
5163 BFD_RELOC_RISCV_TPREL_LO12_I
5165 BFD_RELOC_RISCV_TPREL_LO12_S
5167 BFD_RELOC_RISCV_TPREL_ADD
5169 BFD_RELOC_RISCV_CALL
5171 BFD_RELOC_RISCV_CALL_PLT
5173 BFD_RELOC_RISCV_ADD8
5175 BFD_RELOC_RISCV_ADD16
5177 BFD_RELOC_RISCV_ADD32
5179 BFD_RELOC_RISCV_ADD64
5181 BFD_RELOC_RISCV_SUB8
5183 BFD_RELOC_RISCV_SUB16
5185 BFD_RELOC_RISCV_SUB32
5187 BFD_RELOC_RISCV_SUB64
5189 BFD_RELOC_RISCV_GOT_HI20
5191 BFD_RELOC_RISCV_TLS_GOT_HI20
5193 BFD_RELOC_RISCV_TLS_GD_HI20
5197 BFD_RELOC_RISCV_TLS_DTPMOD32
5199 BFD_RELOC_RISCV_TLS_DTPREL32
5201 BFD_RELOC_RISCV_TLS_DTPMOD64
5203 BFD_RELOC_RISCV_TLS_DTPREL64
5205 BFD_RELOC_RISCV_TLS_TPREL32
5207 BFD_RELOC_RISCV_TLS_TPREL64
5209 BFD_RELOC_RISCV_ALIGN
5211 BFD_RELOC_RISCV_RVC_BRANCH
5213 BFD_RELOC_RISCV_RVC_JUMP
5215 BFD_RELOC_RISCV_RVC_LUI
5217 BFD_RELOC_RISCV_GPREL_I
5219 BFD_RELOC_RISCV_GPREL_S
5221 BFD_RELOC_RISCV_TPREL_I
5223 BFD_RELOC_RISCV_TPREL_S
5225 BFD_RELOC_RISCV_RELAX
5229 BFD_RELOC_RISCV_SUB6
5231 BFD_RELOC_RISCV_SET6
5233 BFD_RELOC_RISCV_SET8
5235 BFD_RELOC_RISCV_SET16
5237 BFD_RELOC_RISCV_SET32
5239 BFD_RELOC_RISCV_32_PCREL
5246 BFD_RELOC_RL78_NEG16
5248 BFD_RELOC_RL78_NEG24
5250 BFD_RELOC_RL78_NEG32
5252 BFD_RELOC_RL78_16_OP
5254 BFD_RELOC_RL78_24_OP
5256 BFD_RELOC_RL78_32_OP
5264 BFD_RELOC_RL78_DIR3U_PCREL
5268 BFD_RELOC_RL78_GPRELB
5270 BFD_RELOC_RL78_GPRELW
5272 BFD_RELOC_RL78_GPRELL
5276 BFD_RELOC_RL78_OP_SUBTRACT
5278 BFD_RELOC_RL78_OP_NEG
5280 BFD_RELOC_RL78_OP_AND
5282 BFD_RELOC_RL78_OP_SHRA
5286 BFD_RELOC_RL78_ABS16
5288 BFD_RELOC_RL78_ABS16_REV
5290 BFD_RELOC_RL78_ABS32
5292 BFD_RELOC_RL78_ABS32_REV
5294 BFD_RELOC_RL78_ABS16U
5296 BFD_RELOC_RL78_ABS16UW
5298 BFD_RELOC_RL78_ABS16UL
5300 BFD_RELOC_RL78_RELAX
5310 BFD_RELOC_RL78_SADDR
5312 Renesas RL78 Relocations.
5335 BFD_RELOC_RX_DIR3U_PCREL
5347 BFD_RELOC_RX_OP_SUBTRACT
5355 BFD_RELOC_RX_ABS16_REV
5359 BFD_RELOC_RX_ABS32_REV
5363 BFD_RELOC_RX_ABS16UW
5365 BFD_RELOC_RX_ABS16UL
5369 Renesas RX Relocations.
5382 32 bit PC relative PLT address.
5386 Copy symbol at runtime.
5388 BFD_RELOC_390_GLOB_DAT
5392 BFD_RELOC_390_JMP_SLOT
5396 BFD_RELOC_390_RELATIVE
5398 Adjust by program base.
5402 32 bit PC relative offset to GOT.
5408 BFD_RELOC_390_PC12DBL
5410 PC relative 12 bit shifted by 1.
5412 BFD_RELOC_390_PLT12DBL
5414 12 bit PC rel. PLT shifted by 1.
5416 BFD_RELOC_390_PC16DBL
5418 PC relative 16 bit shifted by 1.
5420 BFD_RELOC_390_PLT16DBL
5422 16 bit PC rel. PLT shifted by 1.
5424 BFD_RELOC_390_PC24DBL
5426 PC relative 24 bit shifted by 1.
5428 BFD_RELOC_390_PLT24DBL
5430 24 bit PC rel. PLT shifted by 1.
5432 BFD_RELOC_390_PC32DBL
5434 PC relative 32 bit shifted by 1.
5436 BFD_RELOC_390_PLT32DBL
5438 32 bit PC rel. PLT shifted by 1.
5440 BFD_RELOC_390_GOTPCDBL
5442 32 bit PC rel. GOT shifted by 1.
5450 64 bit PC relative PLT address.
5452 BFD_RELOC_390_GOTENT
5454 32 bit rel. offset to GOT entry.
5456 BFD_RELOC_390_GOTOFF64
5458 64 bit offset to GOT.
5460 BFD_RELOC_390_GOTPLT12
5462 12-bit offset to symbol-entry within GOT, with PLT handling.
5464 BFD_RELOC_390_GOTPLT16
5466 16-bit offset to symbol-entry within GOT, with PLT handling.
5468 BFD_RELOC_390_GOTPLT32
5470 32-bit offset to symbol-entry within GOT, with PLT handling.
5472 BFD_RELOC_390_GOTPLT64
5474 64-bit offset to symbol-entry within GOT, with PLT handling.
5476 BFD_RELOC_390_GOTPLTENT
5478 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5480 BFD_RELOC_390_PLTOFF16
5482 16-bit rel. offset from the GOT to a PLT entry.
5484 BFD_RELOC_390_PLTOFF32
5486 32-bit rel. offset from the GOT to a PLT entry.
5488 BFD_RELOC_390_PLTOFF64
5490 64-bit rel. offset from the GOT to a PLT entry.
5493 BFD_RELOC_390_TLS_LOAD
5495 BFD_RELOC_390_TLS_GDCALL
5497 BFD_RELOC_390_TLS_LDCALL
5499 BFD_RELOC_390_TLS_GD32
5501 BFD_RELOC_390_TLS_GD64
5503 BFD_RELOC_390_TLS_GOTIE12
5505 BFD_RELOC_390_TLS_GOTIE32
5507 BFD_RELOC_390_TLS_GOTIE64
5509 BFD_RELOC_390_TLS_LDM32
5511 BFD_RELOC_390_TLS_LDM64
5513 BFD_RELOC_390_TLS_IE32
5515 BFD_RELOC_390_TLS_IE64
5517 BFD_RELOC_390_TLS_IEENT
5519 BFD_RELOC_390_TLS_LE32
5521 BFD_RELOC_390_TLS_LE64
5523 BFD_RELOC_390_TLS_LDO32
5525 BFD_RELOC_390_TLS_LDO64
5527 BFD_RELOC_390_TLS_DTPMOD
5529 BFD_RELOC_390_TLS_DTPOFF
5531 BFD_RELOC_390_TLS_TPOFF
5533 s390 tls relocations.
5540 BFD_RELOC_390_GOTPLT20
5542 BFD_RELOC_390_TLS_GOTIE20
5544 Long displacement extension.
5547 BFD_RELOC_390_IRELATIVE
5549 STT_GNU_IFUNC relocation.
5552 BFD_RELOC_SCORE_GPREL15
5555 Low 16 bit for load/store
5557 BFD_RELOC_SCORE_DUMMY2
5561 This is a 24-bit reloc with the right 1 bit assumed to be 0
5563 BFD_RELOC_SCORE_BRANCH
5565 This is a 19-bit reloc with the right 1 bit assumed to be 0
5567 BFD_RELOC_SCORE_IMM30
5569 This is a 32-bit reloc for 48-bit instructions.
5571 BFD_RELOC_SCORE_IMM32
5573 This is a 32-bit reloc for 48-bit instructions.
5575 BFD_RELOC_SCORE16_JMP
5577 This is a 11-bit reloc with the right 1 bit assumed to be 0
5579 BFD_RELOC_SCORE16_BRANCH
5581 This is a 8-bit reloc with the right 1 bit assumed to be 0
5583 BFD_RELOC_SCORE_BCMP
5585 This is a 9-bit reloc with the right 1 bit assumed to be 0
5587 BFD_RELOC_SCORE_GOT15
5589 BFD_RELOC_SCORE_GOT_LO16
5591 BFD_RELOC_SCORE_CALL15
5593 BFD_RELOC_SCORE_DUMMY_HI16
5595 Undocumented Score relocs
5600 Scenix IP2K - 9-bit register number / data address
5604 Scenix IP2K - 4-bit register/data bank number
5606 BFD_RELOC_IP2K_ADDR16CJP
5608 Scenix IP2K - low 13 bits of instruction word address
5610 BFD_RELOC_IP2K_PAGE3
5612 Scenix IP2K - high 3 bits of instruction word address
5614 BFD_RELOC_IP2K_LO8DATA
5616 BFD_RELOC_IP2K_HI8DATA
5618 BFD_RELOC_IP2K_EX8DATA
5620 Scenix IP2K - ext/low/high 8 bits of data address
5622 BFD_RELOC_IP2K_LO8INSN
5624 BFD_RELOC_IP2K_HI8INSN
5626 Scenix IP2K - low/high 8 bits of instruction word address
5628 BFD_RELOC_IP2K_PC_SKIP
5630 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5634 Scenix IP2K - 16 bit word address in text section.
5636 BFD_RELOC_IP2K_FR_OFFSET
5638 Scenix IP2K - 7-bit sp or dp offset
5640 BFD_RELOC_VPE4KMATH_DATA
5642 BFD_RELOC_VPE4KMATH_INSN
5644 Scenix VPE4K coprocessor - data/insn-space addressing
5647 BFD_RELOC_VTABLE_INHERIT
5649 BFD_RELOC_VTABLE_ENTRY
5651 These two relocations are used by the linker to determine which of
5652 the entries in a C++ virtual function table are actually used. When
5653 the --gc-sections option is given, the linker will zero out the entries
5654 that are not used, so that the code for those functions need not be
5655 included in the output.
5657 VTABLE_INHERIT is a zero-space relocation used to describe to the
5658 linker the inheritance tree of a C++ virtual function table. The
5659 relocation's symbol should be the parent class' vtable, and the
5660 relocation should be located at the child vtable.
5662 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5663 virtual function table entry. The reloc's symbol should refer to the
5664 table of the class mentioned in the code. Off of that base, an offset
5665 describes the entry that is being used. For Rela hosts, this offset
5666 is stored in the reloc's addend. For Rel hosts, we are forced to put
5667 this offset in the reloc's section offset.
5670 BFD_RELOC_IA64_IMM14
5672 BFD_RELOC_IA64_IMM22
5674 BFD_RELOC_IA64_IMM64
5676 BFD_RELOC_IA64_DIR32MSB
5678 BFD_RELOC_IA64_DIR32LSB
5680 BFD_RELOC_IA64_DIR64MSB
5682 BFD_RELOC_IA64_DIR64LSB
5684 BFD_RELOC_IA64_GPREL22
5686 BFD_RELOC_IA64_GPREL64I
5688 BFD_RELOC_IA64_GPREL32MSB
5690 BFD_RELOC_IA64_GPREL32LSB
5692 BFD_RELOC_IA64_GPREL64MSB
5694 BFD_RELOC_IA64_GPREL64LSB
5696 BFD_RELOC_IA64_LTOFF22
5698 BFD_RELOC_IA64_LTOFF64I
5700 BFD_RELOC_IA64_PLTOFF22
5702 BFD_RELOC_IA64_PLTOFF64I
5704 BFD_RELOC_IA64_PLTOFF64MSB
5706 BFD_RELOC_IA64_PLTOFF64LSB
5708 BFD_RELOC_IA64_FPTR64I
5710 BFD_RELOC_IA64_FPTR32MSB
5712 BFD_RELOC_IA64_FPTR32LSB
5714 BFD_RELOC_IA64_FPTR64MSB
5716 BFD_RELOC_IA64_FPTR64LSB
5718 BFD_RELOC_IA64_PCREL21B
5720 BFD_RELOC_IA64_PCREL21BI
5722 BFD_RELOC_IA64_PCREL21M
5724 BFD_RELOC_IA64_PCREL21F
5726 BFD_RELOC_IA64_PCREL22
5728 BFD_RELOC_IA64_PCREL60B
5730 BFD_RELOC_IA64_PCREL64I
5732 BFD_RELOC_IA64_PCREL32MSB
5734 BFD_RELOC_IA64_PCREL32LSB
5736 BFD_RELOC_IA64_PCREL64MSB
5738 BFD_RELOC_IA64_PCREL64LSB
5740 BFD_RELOC_IA64_LTOFF_FPTR22
5742 BFD_RELOC_IA64_LTOFF_FPTR64I
5744 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5746 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5748 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5750 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5752 BFD_RELOC_IA64_SEGREL32MSB
5754 BFD_RELOC_IA64_SEGREL32LSB
5756 BFD_RELOC_IA64_SEGREL64MSB
5758 BFD_RELOC_IA64_SEGREL64LSB
5760 BFD_RELOC_IA64_SECREL32MSB
5762 BFD_RELOC_IA64_SECREL32LSB
5764 BFD_RELOC_IA64_SECREL64MSB
5766 BFD_RELOC_IA64_SECREL64LSB
5768 BFD_RELOC_IA64_REL32MSB
5770 BFD_RELOC_IA64_REL32LSB
5772 BFD_RELOC_IA64_REL64MSB
5774 BFD_RELOC_IA64_REL64LSB
5776 BFD_RELOC_IA64_LTV32MSB
5778 BFD_RELOC_IA64_LTV32LSB
5780 BFD_RELOC_IA64_LTV64MSB
5782 BFD_RELOC_IA64_LTV64LSB
5784 BFD_RELOC_IA64_IPLTMSB
5786 BFD_RELOC_IA64_IPLTLSB
5790 BFD_RELOC_IA64_LTOFF22X
5792 BFD_RELOC_IA64_LDXMOV
5794 BFD_RELOC_IA64_TPREL14
5796 BFD_RELOC_IA64_TPREL22
5798 BFD_RELOC_IA64_TPREL64I
5800 BFD_RELOC_IA64_TPREL64MSB
5802 BFD_RELOC_IA64_TPREL64LSB
5804 BFD_RELOC_IA64_LTOFF_TPREL22
5806 BFD_RELOC_IA64_DTPMOD64MSB
5808 BFD_RELOC_IA64_DTPMOD64LSB
5810 BFD_RELOC_IA64_LTOFF_DTPMOD22
5812 BFD_RELOC_IA64_DTPREL14
5814 BFD_RELOC_IA64_DTPREL22
5816 BFD_RELOC_IA64_DTPREL64I
5818 BFD_RELOC_IA64_DTPREL32MSB
5820 BFD_RELOC_IA64_DTPREL32LSB
5822 BFD_RELOC_IA64_DTPREL64MSB
5824 BFD_RELOC_IA64_DTPREL64LSB
5826 BFD_RELOC_IA64_LTOFF_DTPREL22
5828 Intel IA64 Relocations.
5831 BFD_RELOC_M68HC11_HI8
5833 Motorola 68HC11 reloc.
5834 This is the 8 bit high part of an absolute address.
5836 BFD_RELOC_M68HC11_LO8
5838 Motorola 68HC11 reloc.
5839 This is the 8 bit low part of an absolute address.
5841 BFD_RELOC_M68HC11_3B
5843 Motorola 68HC11 reloc.
5844 This is the 3 bit of a value.
5846 BFD_RELOC_M68HC11_RL_JUMP
5848 Motorola 68HC11 reloc.
5849 This reloc marks the beginning of a jump/call instruction.
5850 It is used for linker relaxation to correctly identify beginning
5851 of instruction and change some branches to use PC-relative
5854 BFD_RELOC_M68HC11_RL_GROUP
5856 Motorola 68HC11 reloc.
5857 This reloc marks a group of several instructions that gcc generates
5858 and for which the linker relaxation pass can modify and/or remove
5861 BFD_RELOC_M68HC11_LO16
5863 Motorola 68HC11 reloc.
5864 This is the 16-bit lower part of an address. It is used for 'call'
5865 instruction to specify the symbol address without any special
5866 transformation (due to memory bank window).
5868 BFD_RELOC_M68HC11_PAGE
5870 Motorola 68HC11 reloc.
5871 This is a 8-bit reloc that specifies the page number of an address.
5872 It is used by 'call' instruction to specify the page number of
5875 BFD_RELOC_M68HC11_24
5877 Motorola 68HC11 reloc.
5878 This is a 24-bit reloc that represents the address with a 16-bit
5879 value and a 8-bit page number. The symbol address is transformed
5880 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5882 BFD_RELOC_M68HC12_5B
5884 Motorola 68HC12 reloc.
5885 This is the 5 bits of a value.
5887 BFD_RELOC_XGATE_RL_JUMP
5889 Freescale XGATE reloc.
5890 This reloc marks the beginning of a bra/jal instruction.
5892 BFD_RELOC_XGATE_RL_GROUP
5894 Freescale XGATE reloc.
5895 This reloc marks a group of several instructions that gcc generates
5896 and for which the linker relaxation pass can modify and/or remove
5899 BFD_RELOC_XGATE_LO16
5901 Freescale XGATE reloc.
5902 This is the 16-bit lower part of an address. It is used for the '16-bit'
5905 BFD_RELOC_XGATE_GPAGE
5907 Freescale XGATE reloc.
5911 Freescale XGATE reloc.
5913 BFD_RELOC_XGATE_PCREL_9
5915 Freescale XGATE reloc.
5916 This is a 9-bit pc-relative reloc.
5918 BFD_RELOC_XGATE_PCREL_10
5920 Freescale XGATE reloc.
5921 This is a 10-bit pc-relative reloc.
5923 BFD_RELOC_XGATE_IMM8_LO
5925 Freescale XGATE reloc.
5926 This is the 16-bit lower part of an address. It is used for the '16-bit'
5929 BFD_RELOC_XGATE_IMM8_HI
5931 Freescale XGATE reloc.
5932 This is the 16-bit higher part of an address. It is used for the '16-bit'
5935 BFD_RELOC_XGATE_IMM3
5937 Freescale XGATE reloc.
5938 This is a 3-bit pc-relative reloc.
5940 BFD_RELOC_XGATE_IMM4
5942 Freescale XGATE reloc.
5943 This is a 4-bit pc-relative reloc.
5945 BFD_RELOC_XGATE_IMM5
5947 Freescale XGATE reloc.
5948 This is a 5-bit pc-relative reloc.
5950 BFD_RELOC_M68HC12_9B
5952 Motorola 68HC12 reloc.
5953 This is the 9 bits of a value.
5955 BFD_RELOC_M68HC12_16B
5957 Motorola 68HC12 reloc.
5958 This is the 16 bits of a value.
5960 BFD_RELOC_M68HC12_9_PCREL
5962 Motorola 68HC12/XGATE reloc.
5963 This is a PCREL9 branch.
5965 BFD_RELOC_M68HC12_10_PCREL
5967 Motorola 68HC12/XGATE reloc.
5968 This is a PCREL10 branch.
5970 BFD_RELOC_M68HC12_LO8XG
5972 Motorola 68HC12/XGATE reloc.
5973 This is the 8 bit low part of an absolute address and immediately precedes
5974 a matching HI8XG part.
5976 BFD_RELOC_M68HC12_HI8XG
5978 Motorola 68HC12/XGATE reloc.
5979 This is the 8 bit high part of an absolute address and immediately follows
5980 a matching LO8XG part.
5982 BFD_RELOC_S12Z_15_PCREL
5984 Freescale S12Z reloc.
5985 This is a 15 bit relative address. If the most significant bits are all zero
5986 then it may be truncated to 8 bits.
5990 BFD_RELOC_16C_NUM08_C
5994 BFD_RELOC_16C_NUM16_C
5998 BFD_RELOC_16C_NUM32_C
6000 BFD_RELOC_16C_DISP04
6002 BFD_RELOC_16C_DISP04_C
6004 BFD_RELOC_16C_DISP08
6006 BFD_RELOC_16C_DISP08_C
6008 BFD_RELOC_16C_DISP16
6010 BFD_RELOC_16C_DISP16_C
6012 BFD_RELOC_16C_DISP24
6014 BFD_RELOC_16C_DISP24_C
6016 BFD_RELOC_16C_DISP24a
6018 BFD_RELOC_16C_DISP24a_C
6022 BFD_RELOC_16C_REG04_C
6024 BFD_RELOC_16C_REG04a
6026 BFD_RELOC_16C_REG04a_C
6030 BFD_RELOC_16C_REG14_C
6034 BFD_RELOC_16C_REG16_C
6038 BFD_RELOC_16C_REG20_C
6042 BFD_RELOC_16C_ABS20_C
6046 BFD_RELOC_16C_ABS24_C
6050 BFD_RELOC_16C_IMM04_C
6054 BFD_RELOC_16C_IMM16_C
6058 BFD_RELOC_16C_IMM20_C
6062 BFD_RELOC_16C_IMM24_C
6066 BFD_RELOC_16C_IMM32_C
6068 NS CR16C Relocations.
6073 BFD_RELOC_CR16_NUM16
6075 BFD_RELOC_CR16_NUM32
6077 BFD_RELOC_CR16_NUM32a
6079 BFD_RELOC_CR16_REGREL0
6081 BFD_RELOC_CR16_REGREL4
6083 BFD_RELOC_CR16_REGREL4a
6085 BFD_RELOC_CR16_REGREL14
6087 BFD_RELOC_CR16_REGREL14a
6089 BFD_RELOC_CR16_REGREL16
6091 BFD_RELOC_CR16_REGREL20
6093 BFD_RELOC_CR16_REGREL20a
6095 BFD_RELOC_CR16_ABS20
6097 BFD_RELOC_CR16_ABS24
6103 BFD_RELOC_CR16_IMM16
6105 BFD_RELOC_CR16_IMM20
6107 BFD_RELOC_CR16_IMM24
6109 BFD_RELOC_CR16_IMM32
6111 BFD_RELOC_CR16_IMM32a
6113 BFD_RELOC_CR16_DISP4
6115 BFD_RELOC_CR16_DISP8
6117 BFD_RELOC_CR16_DISP16
6119 BFD_RELOC_CR16_DISP20
6121 BFD_RELOC_CR16_DISP24
6123 BFD_RELOC_CR16_DISP24a
6125 BFD_RELOC_CR16_SWITCH8
6127 BFD_RELOC_CR16_SWITCH16
6129 BFD_RELOC_CR16_SWITCH32
6131 BFD_RELOC_CR16_GOT_REGREL20
6133 BFD_RELOC_CR16_GOTC_REGREL20
6135 BFD_RELOC_CR16_GLOB_DAT
6137 NS CR16 Relocations.
6144 BFD_RELOC_CRX_REL8_CMP
6152 BFD_RELOC_CRX_REGREL12
6154 BFD_RELOC_CRX_REGREL22
6156 BFD_RELOC_CRX_REGREL28
6158 BFD_RELOC_CRX_REGREL32
6174 BFD_RELOC_CRX_SWITCH8
6176 BFD_RELOC_CRX_SWITCH16
6178 BFD_RELOC_CRX_SWITCH32
6183 BFD_RELOC_CRIS_BDISP8
6185 BFD_RELOC_CRIS_UNSIGNED_5
6187 BFD_RELOC_CRIS_SIGNED_6
6189 BFD_RELOC_CRIS_UNSIGNED_6
6191 BFD_RELOC_CRIS_SIGNED_8
6193 BFD_RELOC_CRIS_UNSIGNED_8
6195 BFD_RELOC_CRIS_SIGNED_16
6197 BFD_RELOC_CRIS_UNSIGNED_16
6199 BFD_RELOC_CRIS_LAPCQ_OFFSET
6201 BFD_RELOC_CRIS_UNSIGNED_4
6203 These relocs are only used within the CRIS assembler. They are not
6204 (at present) written to any object files.
6208 BFD_RELOC_CRIS_GLOB_DAT
6210 BFD_RELOC_CRIS_JUMP_SLOT
6212 BFD_RELOC_CRIS_RELATIVE
6214 Relocs used in ELF shared libraries for CRIS.
6216 BFD_RELOC_CRIS_32_GOT
6218 32-bit offset to symbol-entry within GOT.
6220 BFD_RELOC_CRIS_16_GOT
6222 16-bit offset to symbol-entry within GOT.
6224 BFD_RELOC_CRIS_32_GOTPLT
6226 32-bit offset to symbol-entry within GOT, with PLT handling.
6228 BFD_RELOC_CRIS_16_GOTPLT
6230 16-bit offset to symbol-entry within GOT, with PLT handling.
6232 BFD_RELOC_CRIS_32_GOTREL
6234 32-bit offset to symbol, relative to GOT.
6236 BFD_RELOC_CRIS_32_PLT_GOTREL
6238 32-bit offset to symbol with PLT entry, relative to GOT.
6240 BFD_RELOC_CRIS_32_PLT_PCREL
6242 32-bit offset to symbol with PLT entry, relative to this relocation.
6245 BFD_RELOC_CRIS_32_GOT_GD
6247 BFD_RELOC_CRIS_16_GOT_GD
6249 BFD_RELOC_CRIS_32_GD
6253 BFD_RELOC_CRIS_32_DTPREL
6255 BFD_RELOC_CRIS_16_DTPREL
6257 BFD_RELOC_CRIS_32_GOT_TPREL
6259 BFD_RELOC_CRIS_16_GOT_TPREL
6261 BFD_RELOC_CRIS_32_TPREL
6263 BFD_RELOC_CRIS_16_TPREL
6265 BFD_RELOC_CRIS_DTPMOD
6267 BFD_RELOC_CRIS_32_IE
6269 Relocs used in TLS code for CRIS.
6272 BFD_RELOC_OR1K_REL_26
6274 BFD_RELOC_OR1K_GOTPC_HI16
6276 BFD_RELOC_OR1K_GOTPC_LO16
6278 BFD_RELOC_OR1K_GOT16
6280 BFD_RELOC_OR1K_PLT26
6282 BFD_RELOC_OR1K_GOTOFF_HI16
6284 BFD_RELOC_OR1K_GOTOFF_LO16
6288 BFD_RELOC_OR1K_GLOB_DAT
6290 BFD_RELOC_OR1K_JMP_SLOT
6292 BFD_RELOC_OR1K_RELATIVE
6294 BFD_RELOC_OR1K_TLS_GD_HI16
6296 BFD_RELOC_OR1K_TLS_GD_LO16
6298 BFD_RELOC_OR1K_TLS_LDM_HI16
6300 BFD_RELOC_OR1K_TLS_LDM_LO16
6302 BFD_RELOC_OR1K_TLS_LDO_HI16
6304 BFD_RELOC_OR1K_TLS_LDO_LO16
6306 BFD_RELOC_OR1K_TLS_IE_HI16
6308 BFD_RELOC_OR1K_TLS_IE_LO16
6310 BFD_RELOC_OR1K_TLS_LE_HI16
6312 BFD_RELOC_OR1K_TLS_LE_LO16
6314 BFD_RELOC_OR1K_TLS_TPOFF
6316 BFD_RELOC_OR1K_TLS_DTPOFF
6318 BFD_RELOC_OR1K_TLS_DTPMOD
6320 OpenRISC 1000 Relocations.
6323 BFD_RELOC_H8_DIR16A8
6325 BFD_RELOC_H8_DIR16R8
6327 BFD_RELOC_H8_DIR24A8
6329 BFD_RELOC_H8_DIR24R8
6331 BFD_RELOC_H8_DIR32A16
6333 BFD_RELOC_H8_DISP32A16
6338 BFD_RELOC_XSTORMY16_REL_12
6340 BFD_RELOC_XSTORMY16_12
6342 BFD_RELOC_XSTORMY16_24
6344 BFD_RELOC_XSTORMY16_FPTR16
6346 Sony Xstormy16 Relocations.
6351 Self-describing complex relocations.
6363 Infineon Relocations.
6366 BFD_RELOC_VAX_GLOB_DAT
6368 BFD_RELOC_VAX_JMP_SLOT
6370 BFD_RELOC_VAX_RELATIVE
6372 Relocations used by VAX ELF.
6377 Morpho MT - 16 bit immediate relocation.
6381 Morpho MT - Hi 16 bits of an address.
6385 Morpho MT - Low 16 bits of an address.
6387 BFD_RELOC_MT_GNU_VTINHERIT
6389 Morpho MT - Used to tell the linker which vtable entries are used.
6391 BFD_RELOC_MT_GNU_VTENTRY
6393 Morpho MT - Used to tell the linker which vtable entries are used.
6395 BFD_RELOC_MT_PCINSN8
6397 Morpho MT - 8 bit immediate relocation.
6400 BFD_RELOC_MSP430_10_PCREL
6402 BFD_RELOC_MSP430_16_PCREL
6406 BFD_RELOC_MSP430_16_PCREL_BYTE
6408 BFD_RELOC_MSP430_16_BYTE
6410 BFD_RELOC_MSP430_2X_PCREL
6412 BFD_RELOC_MSP430_RL_PCREL
6414 BFD_RELOC_MSP430_ABS8
6416 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6418 BFD_RELOC_MSP430X_PCR20_EXT_DST
6420 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6422 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6424 BFD_RELOC_MSP430X_ABS20_EXT_DST
6426 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6428 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6430 BFD_RELOC_MSP430X_ABS20_ADR_DST
6432 BFD_RELOC_MSP430X_PCR16
6434 BFD_RELOC_MSP430X_PCR20_CALL
6436 BFD_RELOC_MSP430X_ABS16
6438 BFD_RELOC_MSP430_ABS_HI16
6440 BFD_RELOC_MSP430_PREL31
6442 BFD_RELOC_MSP430_SYM_DIFF
6444 msp430 specific relocation codes
6451 BFD_RELOC_NIOS2_CALL26
6453 BFD_RELOC_NIOS2_IMM5
6455 BFD_RELOC_NIOS2_CACHE_OPX
6457 BFD_RELOC_NIOS2_IMM6
6459 BFD_RELOC_NIOS2_IMM8
6461 BFD_RELOC_NIOS2_HI16
6463 BFD_RELOC_NIOS2_LO16
6465 BFD_RELOC_NIOS2_HIADJ16
6467 BFD_RELOC_NIOS2_GPREL
6469 BFD_RELOC_NIOS2_UJMP
6471 BFD_RELOC_NIOS2_CJMP
6473 BFD_RELOC_NIOS2_CALLR
6475 BFD_RELOC_NIOS2_ALIGN
6477 BFD_RELOC_NIOS2_GOT16
6479 BFD_RELOC_NIOS2_CALL16
6481 BFD_RELOC_NIOS2_GOTOFF_LO
6483 BFD_RELOC_NIOS2_GOTOFF_HA
6485 BFD_RELOC_NIOS2_PCREL_LO
6487 BFD_RELOC_NIOS2_PCREL_HA
6489 BFD_RELOC_NIOS2_TLS_GD16
6491 BFD_RELOC_NIOS2_TLS_LDM16
6493 BFD_RELOC_NIOS2_TLS_LDO16
6495 BFD_RELOC_NIOS2_TLS_IE16
6497 BFD_RELOC_NIOS2_TLS_LE16
6499 BFD_RELOC_NIOS2_TLS_DTPMOD
6501 BFD_RELOC_NIOS2_TLS_DTPREL
6503 BFD_RELOC_NIOS2_TLS_TPREL
6505 BFD_RELOC_NIOS2_COPY
6507 BFD_RELOC_NIOS2_GLOB_DAT
6509 BFD_RELOC_NIOS2_JUMP_SLOT
6511 BFD_RELOC_NIOS2_RELATIVE
6513 BFD_RELOC_NIOS2_GOTOFF
6515 BFD_RELOC_NIOS2_CALL26_NOAT
6517 BFD_RELOC_NIOS2_GOT_LO
6519 BFD_RELOC_NIOS2_GOT_HA
6521 BFD_RELOC_NIOS2_CALL_LO
6523 BFD_RELOC_NIOS2_CALL_HA
6525 BFD_RELOC_NIOS2_R2_S12
6527 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6529 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6531 BFD_RELOC_NIOS2_R2_T1I7_2
6533 BFD_RELOC_NIOS2_R2_T2I4
6535 BFD_RELOC_NIOS2_R2_T2I4_1
6537 BFD_RELOC_NIOS2_R2_T2I4_2
6539 BFD_RELOC_NIOS2_R2_X1I7_2
6541 BFD_RELOC_NIOS2_R2_X2L5
6543 BFD_RELOC_NIOS2_R2_F1I5_2
6545 BFD_RELOC_NIOS2_R2_L5I4X1
6547 BFD_RELOC_NIOS2_R2_T1X1I6
6549 BFD_RELOC_NIOS2_R2_T1X1I6_2
6551 Relocations used by the Altera Nios II core.
6556 PRU LDI 16-bit unsigned data-memory relocation.
6558 BFD_RELOC_PRU_U16_PMEMIMM
6560 PRU LDI 16-bit unsigned instruction-memory relocation.
6564 PRU relocation for two consecutive LDI load instructions that load a
6565 32 bit value into a register. If the higher bits are all zero, then
6566 the second instruction may be relaxed.
6568 BFD_RELOC_PRU_S10_PCREL
6570 PRU QBBx 10-bit signed PC-relative relocation.
6572 BFD_RELOC_PRU_U8_PCREL
6574 PRU 8-bit unsigned relocation used for the LOOP instruction.
6576 BFD_RELOC_PRU_32_PMEM
6578 BFD_RELOC_PRU_16_PMEM
6580 PRU Program Memory relocations. Used to convert from byte addressing to
6581 32-bit word addressing.
6583 BFD_RELOC_PRU_GNU_DIFF8
6585 BFD_RELOC_PRU_GNU_DIFF16
6587 BFD_RELOC_PRU_GNU_DIFF32
6589 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6591 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6593 PRU relocations to mark the difference of two local symbols.
6594 These are only needed to support linker relaxation and can be ignored
6595 when not relaxing. The field is set to the value of the difference
6596 assuming no relaxation. The relocation encodes the position of the
6597 second symbol so the linker can determine whether to adjust the field
6598 value. The PMEM variants encode the word difference, instead of byte
6599 difference between symbols.
6602 BFD_RELOC_IQ2000_OFFSET_16
6604 BFD_RELOC_IQ2000_OFFSET_21
6606 BFD_RELOC_IQ2000_UHI16
6611 BFD_RELOC_XTENSA_RTLD
6613 Special Xtensa relocation used only by PLT entries in ELF shared
6614 objects to indicate that the runtime linker should set the value
6615 to one of its own internal functions or data structures.
6617 BFD_RELOC_XTENSA_GLOB_DAT
6619 BFD_RELOC_XTENSA_JMP_SLOT
6621 BFD_RELOC_XTENSA_RELATIVE
6623 Xtensa relocations for ELF shared objects.
6625 BFD_RELOC_XTENSA_PLT
6627 Xtensa relocation used in ELF object files for symbols that may require
6628 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6630 BFD_RELOC_XTENSA_DIFF8
6632 BFD_RELOC_XTENSA_DIFF16
6634 BFD_RELOC_XTENSA_DIFF32
6636 Xtensa relocations to mark the difference of two local symbols.
6637 These are only needed to support linker relaxation and can be ignored
6638 when not relaxing. The field is set to the value of the difference
6639 assuming no relaxation. The relocation encodes the position of the
6640 first symbol so the linker can determine whether to adjust the field
6643 BFD_RELOC_XTENSA_SLOT0_OP
6645 BFD_RELOC_XTENSA_SLOT1_OP
6647 BFD_RELOC_XTENSA_SLOT2_OP
6649 BFD_RELOC_XTENSA_SLOT3_OP
6651 BFD_RELOC_XTENSA_SLOT4_OP
6653 BFD_RELOC_XTENSA_SLOT5_OP
6655 BFD_RELOC_XTENSA_SLOT6_OP
6657 BFD_RELOC_XTENSA_SLOT7_OP
6659 BFD_RELOC_XTENSA_SLOT8_OP
6661 BFD_RELOC_XTENSA_SLOT9_OP
6663 BFD_RELOC_XTENSA_SLOT10_OP
6665 BFD_RELOC_XTENSA_SLOT11_OP
6667 BFD_RELOC_XTENSA_SLOT12_OP
6669 BFD_RELOC_XTENSA_SLOT13_OP
6671 BFD_RELOC_XTENSA_SLOT14_OP
6673 Generic Xtensa relocations for instruction operands. Only the slot
6674 number is encoded in the relocation. The relocation applies to the
6675 last PC-relative immediate operand, or if there are no PC-relative
6676 immediates, to the last immediate operand.
6678 BFD_RELOC_XTENSA_SLOT0_ALT
6680 BFD_RELOC_XTENSA_SLOT1_ALT
6682 BFD_RELOC_XTENSA_SLOT2_ALT
6684 BFD_RELOC_XTENSA_SLOT3_ALT
6686 BFD_RELOC_XTENSA_SLOT4_ALT
6688 BFD_RELOC_XTENSA_SLOT5_ALT
6690 BFD_RELOC_XTENSA_SLOT6_ALT
6692 BFD_RELOC_XTENSA_SLOT7_ALT
6694 BFD_RELOC_XTENSA_SLOT8_ALT
6696 BFD_RELOC_XTENSA_SLOT9_ALT
6698 BFD_RELOC_XTENSA_SLOT10_ALT
6700 BFD_RELOC_XTENSA_SLOT11_ALT
6702 BFD_RELOC_XTENSA_SLOT12_ALT
6704 BFD_RELOC_XTENSA_SLOT13_ALT
6706 BFD_RELOC_XTENSA_SLOT14_ALT
6708 Alternate Xtensa relocations. Only the slot is encoded in the
6709 relocation. The meaning of these relocations is opcode-specific.
6711 BFD_RELOC_XTENSA_OP0
6713 BFD_RELOC_XTENSA_OP1
6715 BFD_RELOC_XTENSA_OP2
6717 Xtensa relocations for backward compatibility. These have all been
6718 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6720 BFD_RELOC_XTENSA_ASM_EXPAND
6722 Xtensa relocation to mark that the assembler expanded the
6723 instructions from an original target. The expansion size is
6724 encoded in the reloc size.
6726 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6728 Xtensa relocation to mark that the linker should simplify
6729 assembler-expanded instructions. This is commonly used
6730 internally by the linker after analysis of a
6731 BFD_RELOC_XTENSA_ASM_EXPAND.
6733 BFD_RELOC_XTENSA_TLSDESC_FN
6735 BFD_RELOC_XTENSA_TLSDESC_ARG
6737 BFD_RELOC_XTENSA_TLS_DTPOFF
6739 BFD_RELOC_XTENSA_TLS_TPOFF
6741 BFD_RELOC_XTENSA_TLS_FUNC
6743 BFD_RELOC_XTENSA_TLS_ARG
6745 BFD_RELOC_XTENSA_TLS_CALL
6747 Xtensa TLS relocations.
6752 8 bit signed offset in (ix+d) or (iy+d).
6770 BFD_RELOC_LM32_BRANCH
6772 BFD_RELOC_LM32_16_GOT
6774 BFD_RELOC_LM32_GOTOFF_HI16
6776 BFD_RELOC_LM32_GOTOFF_LO16
6780 BFD_RELOC_LM32_GLOB_DAT
6782 BFD_RELOC_LM32_JMP_SLOT
6784 BFD_RELOC_LM32_RELATIVE
6786 Lattice Mico32 relocations.
6789 BFD_RELOC_MACH_O_SECTDIFF
6791 Difference between two section addreses. Must be followed by a
6792 BFD_RELOC_MACH_O_PAIR.
6794 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6796 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6798 BFD_RELOC_MACH_O_PAIR
6800 Pair of relocation. Contains the first symbol.
6802 BFD_RELOC_MACH_O_SUBTRACTOR32
6804 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6806 BFD_RELOC_MACH_O_SUBTRACTOR64
6808 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6811 BFD_RELOC_MACH_O_X86_64_BRANCH32
6813 BFD_RELOC_MACH_O_X86_64_BRANCH8
6815 PCREL relocations. They are marked as branch to create PLT entry if
6818 BFD_RELOC_MACH_O_X86_64_GOT
6820 Used when referencing a GOT entry.
6822 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6824 Used when loading a GOT entry with movq. It is specially marked so that
6825 the linker could optimize the movq to a leaq if possible.
6827 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6829 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6831 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6833 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6835 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6837 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6839 BFD_RELOC_MACH_O_X86_64_TLV
6841 Used when referencing a TLV entry.
6845 BFD_RELOC_MACH_O_ARM64_ADDEND
6847 Addend for PAGE or PAGEOFF.
6849 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6851 Relative offset to page of GOT slot.
6853 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6855 Relative offset within page of GOT slot.
6857 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6859 Address of a GOT entry.
6862 BFD_RELOC_MICROBLAZE_32_LO
6864 This is a 32 bit reloc for the microblaze that stores the
6865 low 16 bits of a value
6867 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6869 This is a 32 bit pc-relative reloc for the microblaze that
6870 stores the low 16 bits of a value
6872 BFD_RELOC_MICROBLAZE_32_ROSDA
6874 This is a 32 bit reloc for the microblaze that stores a
6875 value relative to the read-only small data area anchor
6877 BFD_RELOC_MICROBLAZE_32_RWSDA
6879 This is a 32 bit reloc for the microblaze that stores a
6880 value relative to the read-write small data area anchor
6882 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6884 This is a 32 bit reloc for the microblaze to handle
6885 expressions of the form "Symbol Op Symbol"
6887 BFD_RELOC_MICROBLAZE_64_NONE
6889 This is a 64 bit reloc that stores the 32 bit pc relative
6890 value in two words (with an imm instruction). No relocation is
6891 done here - only used for relaxing
6893 BFD_RELOC_MICROBLAZE_64_GOTPC
6895 This is a 64 bit reloc that stores the 32 bit pc relative
6896 value in two words (with an imm instruction). The relocation is
6897 PC-relative GOT offset
6899 BFD_RELOC_MICROBLAZE_64_GOT
6901 This is a 64 bit reloc that stores the 32 bit pc relative
6902 value in two words (with an imm instruction). The relocation is
6905 BFD_RELOC_MICROBLAZE_64_PLT
6907 This is a 64 bit reloc that stores the 32 bit pc relative
6908 value in two words (with an imm instruction). The relocation is
6909 PC-relative offset into PLT
6911 BFD_RELOC_MICROBLAZE_64_GOTOFF
6913 This is a 64 bit reloc that stores the 32 bit GOT relative
6914 value in two words (with an imm instruction). The relocation is
6915 relative offset from _GLOBAL_OFFSET_TABLE_
6917 BFD_RELOC_MICROBLAZE_32_GOTOFF
6919 This is a 32 bit reloc that stores the 32 bit GOT relative
6920 value in a word. The relocation is relative offset from
6921 _GLOBAL_OFFSET_TABLE_
6923 BFD_RELOC_MICROBLAZE_COPY
6925 This is used to tell the dynamic linker to copy the value out of
6926 the dynamic object into the runtime process image.
6928 BFD_RELOC_MICROBLAZE_64_TLS
6932 BFD_RELOC_MICROBLAZE_64_TLSGD
6934 This is a 64 bit reloc that stores the 32 bit GOT relative value
6935 of the GOT TLS GD info entry in two words (with an imm instruction). The
6936 relocation is GOT offset.
6938 BFD_RELOC_MICROBLAZE_64_TLSLD
6940 This is a 64 bit reloc that stores the 32 bit GOT relative value
6941 of the GOT TLS LD info entry in two words (with an imm instruction). The
6942 relocation is GOT offset.
6944 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6946 This is a 32 bit reloc that stores the Module ID to GOT(n).
6948 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6950 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6952 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6954 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6957 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6959 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6960 to two words (uses imm instruction).
6962 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6964 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6965 to two words (uses imm instruction).
6967 BFD_RELOC_MICROBLAZE_64_TEXTPCREL
6969 This is a 64 bit reloc that stores the 32 bit pc relative
6970 value in two words (with an imm instruction). The relocation is
6971 PC-relative offset from start of TEXT.
6973 BFD_RELOC_MICROBLAZE_64_TEXTREL
6975 This is a 64 bit reloc that stores the 32 bit offset
6976 value in two words (with an imm instruction). The relocation is
6977 relative offset from start of TEXT.
6980 BFD_RELOC_AARCH64_RELOC_START
6982 AArch64 pseudo relocation code to mark the start of the AArch64
6983 relocation enumerators. N.B. the order of the enumerators is
6984 important as several tables in the AArch64 bfd backend are indexed
6985 by these enumerators; make sure they are all synced.
6987 BFD_RELOC_AARCH64_NULL
6989 Deprecated AArch64 null relocation code.
6991 BFD_RELOC_AARCH64_NONE
6993 AArch64 null relocation code.
6995 BFD_RELOC_AARCH64_64
6997 BFD_RELOC_AARCH64_32
6999 BFD_RELOC_AARCH64_16
7001 Basic absolute relocations of N bits. These are equivalent to
7002 BFD_RELOC_N and they were added to assist the indexing of the howto
7005 BFD_RELOC_AARCH64_64_PCREL
7007 BFD_RELOC_AARCH64_32_PCREL
7009 BFD_RELOC_AARCH64_16_PCREL
7011 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
7012 and they were added to assist the indexing of the howto table.
7014 BFD_RELOC_AARCH64_MOVW_G0
7016 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
7017 of an unsigned address/value.
7019 BFD_RELOC_AARCH64_MOVW_G0_NC
7021 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
7022 an address/value. No overflow checking.
7024 BFD_RELOC_AARCH64_MOVW_G1
7026 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
7027 of an unsigned address/value.
7029 BFD_RELOC_AARCH64_MOVW_G1_NC
7031 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
7032 of an address/value. No overflow checking.
7034 BFD_RELOC_AARCH64_MOVW_G2
7036 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
7037 of an unsigned address/value.
7039 BFD_RELOC_AARCH64_MOVW_G2_NC
7041 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
7042 of an address/value. No overflow checking.
7044 BFD_RELOC_AARCH64_MOVW_G3
7046 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
7047 of a signed or unsigned address/value.
7049 BFD_RELOC_AARCH64_MOVW_G0_S
7051 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7052 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7055 BFD_RELOC_AARCH64_MOVW_G1_S
7057 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
7058 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7061 BFD_RELOC_AARCH64_MOVW_G2_S
7063 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
7064 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7067 BFD_RELOC_AARCH64_MOVW_PREL_G0
7069 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7070 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7073 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
7075 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7076 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7079 BFD_RELOC_AARCH64_MOVW_PREL_G1
7081 AArch64 MOVK instruction with most significant bits 16 to 31
7084 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
7086 AArch64 MOVK instruction with most significant bits 16 to 31
7089 BFD_RELOC_AARCH64_MOVW_PREL_G2
7091 AArch64 MOVK instruction with most significant bits 32 to 47
7094 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
7096 AArch64 MOVK instruction with most significant bits 32 to 47
7099 BFD_RELOC_AARCH64_MOVW_PREL_G3
7101 AArch64 MOVK instruction with most significant bits 47 to 63
7104 BFD_RELOC_AARCH64_LD_LO19_PCREL
7106 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
7107 offset. The lowest two bits must be zero and are not stored in the
7108 instruction, giving a 21 bit signed byte offset.
7110 BFD_RELOC_AARCH64_ADR_LO21_PCREL
7112 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
7114 BFD_RELOC_AARCH64_ADR_HI21_PCREL
7116 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7117 offset, giving a 4KB aligned page base address.
7119 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
7121 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7122 offset, giving a 4KB aligned page base address, but with no overflow
7125 BFD_RELOC_AARCH64_ADD_LO12
7127 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
7128 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7130 BFD_RELOC_AARCH64_LDST8_LO12
7132 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
7133 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7135 BFD_RELOC_AARCH64_TSTBR14
7137 AArch64 14 bit pc-relative test bit and branch.
7138 The lowest two bits must be zero and are not stored in the instruction,
7139 giving a 16 bit signed byte offset.
7141 BFD_RELOC_AARCH64_BRANCH19
7143 AArch64 19 bit pc-relative conditional branch and compare & branch.
7144 The lowest two bits must be zero and are not stored in the instruction,
7145 giving a 21 bit signed byte offset.
7147 BFD_RELOC_AARCH64_JUMP26
7149 AArch64 26 bit pc-relative unconditional branch.
7150 The lowest two bits must be zero and are not stored in the instruction,
7151 giving a 28 bit signed byte offset.
7153 BFD_RELOC_AARCH64_CALL26
7155 AArch64 26 bit pc-relative unconditional branch and link.
7156 The lowest two bits must be zero and are not stored in the instruction,
7157 giving a 28 bit signed byte offset.
7159 BFD_RELOC_AARCH64_LDST16_LO12
7161 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7162 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7164 BFD_RELOC_AARCH64_LDST32_LO12
7166 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7167 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7169 BFD_RELOC_AARCH64_LDST64_LO12
7171 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7172 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7174 BFD_RELOC_AARCH64_LDST128_LO12
7176 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7177 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7179 BFD_RELOC_AARCH64_GOT_LD_PREL19
7181 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7182 offset of the global offset table entry for a symbol. The lowest two
7183 bits must be zero and are not stored in the instruction, giving a 21
7184 bit signed byte offset. This relocation type requires signed overflow
7187 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7189 Get to the page base of the global offset table entry for a symbol as
7190 part of an ADRP instruction using a 21 bit PC relative value.Used in
7191 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7193 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7195 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7196 the GOT entry for this symbol. Used in conjunction with
7197 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
7199 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7201 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7202 the GOT entry for this symbol. Used in conjunction with
7203 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
7205 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7207 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7208 for this symbol. Valid in LP64 ABI only.
7210 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7212 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7213 for this symbol. Valid in LP64 ABI only.
7215 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7217 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7218 the GOT entry for this symbol. Valid in LP64 ABI only.
7220 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7222 Scaled 14 bit byte offset to the page base of the global offset table.
7224 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7226 Scaled 15 bit byte offset to the page base of the global offset table.
7228 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7230 Get to the page base of the global offset table entry for a symbols
7231 tls_index structure as part of an adrp instruction using a 21 bit PC
7232 relative value. Used in conjunction with
7233 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7235 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7237 AArch64 TLS General Dynamic
7239 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7241 Unsigned 12 bit byte offset to global offset table entry for a symbols
7242 tls_index structure. Used in conjunction with
7243 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7245 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7247 AArch64 TLS General Dynamic relocation.
7249 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7251 AArch64 TLS General Dynamic relocation.
7253 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7255 AArch64 TLS INITIAL EXEC relocation.
7257 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7259 AArch64 TLS INITIAL EXEC relocation.
7261 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7263 AArch64 TLS INITIAL EXEC relocation.
7265 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7267 AArch64 TLS INITIAL EXEC relocation.
7269 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7271 AArch64 TLS INITIAL EXEC relocation.
7273 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7275 AArch64 TLS INITIAL EXEC relocation.
7277 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7279 bit[23:12] of byte offset to module TLS base address.
7281 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7283 Unsigned 12 bit byte offset to module TLS base address.
7285 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7287 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7289 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7291 Unsigned 12 bit byte offset to global offset table entry for a symbols
7292 tls_index structure. Used in conjunction with
7293 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7295 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7297 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7300 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7302 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7304 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7306 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7309 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7311 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7313 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7315 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7318 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7320 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7322 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7324 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7327 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7329 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7331 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7333 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7336 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7338 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7340 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7342 bit[15:0] of byte offset to module TLS base address.
7344 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7346 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7348 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7350 bit[31:16] of byte offset to module TLS base address.
7352 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7354 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7356 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7358 bit[47:32] of byte offset to module TLS base address.
7360 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7362 AArch64 TLS LOCAL EXEC relocation.
7364 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7366 AArch64 TLS LOCAL EXEC relocation.
7368 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7370 AArch64 TLS LOCAL EXEC relocation.
7372 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7374 AArch64 TLS LOCAL EXEC relocation.
7376 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7378 AArch64 TLS LOCAL EXEC relocation.
7380 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7382 AArch64 TLS LOCAL EXEC relocation.
7384 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7386 AArch64 TLS LOCAL EXEC relocation.
7388 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7390 AArch64 TLS LOCAL EXEC relocation.
7392 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
7394 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7397 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
7399 Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check.
7401 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
7403 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7406 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
7408 Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check.
7410 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
7412 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7415 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
7417 Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check.
7419 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
7421 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7424 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
7426 Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check.
7428 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7430 AArch64 TLS DESC relocation.
7432 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7434 AArch64 TLS DESC relocation.
7436 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7438 AArch64 TLS DESC relocation.
7440 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7442 AArch64 TLS DESC relocation.
7444 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7446 AArch64 TLS DESC relocation.
7448 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7450 AArch64 TLS DESC relocation.
7452 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7454 AArch64 TLS DESC relocation.
7456 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7458 AArch64 TLS DESC relocation.
7460 BFD_RELOC_AARCH64_TLSDESC_LDR
7462 AArch64 TLS DESC relocation.
7464 BFD_RELOC_AARCH64_TLSDESC_ADD
7466 AArch64 TLS DESC relocation.
7468 BFD_RELOC_AARCH64_TLSDESC_CALL
7470 AArch64 TLS DESC relocation.
7472 BFD_RELOC_AARCH64_COPY
7474 AArch64 TLS relocation.
7476 BFD_RELOC_AARCH64_GLOB_DAT
7478 AArch64 TLS relocation.
7480 BFD_RELOC_AARCH64_JUMP_SLOT
7482 AArch64 TLS relocation.
7484 BFD_RELOC_AARCH64_RELATIVE
7486 AArch64 TLS relocation.
7488 BFD_RELOC_AARCH64_TLS_DTPMOD
7490 AArch64 TLS relocation.
7492 BFD_RELOC_AARCH64_TLS_DTPREL
7494 AArch64 TLS relocation.
7496 BFD_RELOC_AARCH64_TLS_TPREL
7498 AArch64 TLS relocation.
7500 BFD_RELOC_AARCH64_TLSDESC
7502 AArch64 TLS relocation.
7504 BFD_RELOC_AARCH64_IRELATIVE
7506 AArch64 support for STT_GNU_IFUNC.
7508 BFD_RELOC_AARCH64_RELOC_END
7510 AArch64 pseudo relocation code to mark the end of the AArch64
7511 relocation enumerators that have direct mapping to ELF reloc codes.
7512 There are a few more enumerators after this one; those are mainly
7513 used by the AArch64 assembler for the internal fixup or to select
7514 one of the above enumerators.
7516 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7518 AArch64 pseudo relocation code to be used internally by the AArch64
7519 assembler and not (currently) written to any object files.
7521 BFD_RELOC_AARCH64_LDST_LO12
7523 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7524 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7526 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7528 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7529 used internally by the AArch64 assembler and not (currently) written to
7532 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7534 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7536 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
7538 AArch64 pseudo relocation code for TLS local exec mode. It's to be
7539 used internally by the AArch64 assembler and not (currently) written to
7542 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
7544 Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check.
7546 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7548 AArch64 pseudo relocation code to be used internally by the AArch64
7549 assembler and not (currently) written to any object files.
7551 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7553 AArch64 pseudo relocation code to be used internally by the AArch64
7554 assembler and not (currently) written to any object files.
7556 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7558 AArch64 pseudo relocation code to be used internally by the AArch64
7559 assembler and not (currently) written to any object files.
7561 BFD_RELOC_TILEPRO_COPY
7563 BFD_RELOC_TILEPRO_GLOB_DAT
7565 BFD_RELOC_TILEPRO_JMP_SLOT
7567 BFD_RELOC_TILEPRO_RELATIVE
7569 BFD_RELOC_TILEPRO_BROFF_X1
7571 BFD_RELOC_TILEPRO_JOFFLONG_X1
7573 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7575 BFD_RELOC_TILEPRO_IMM8_X0
7577 BFD_RELOC_TILEPRO_IMM8_Y0
7579 BFD_RELOC_TILEPRO_IMM8_X1
7581 BFD_RELOC_TILEPRO_IMM8_Y1
7583 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7585 BFD_RELOC_TILEPRO_MT_IMM15_X1
7587 BFD_RELOC_TILEPRO_MF_IMM15_X1
7589 BFD_RELOC_TILEPRO_IMM16_X0
7591 BFD_RELOC_TILEPRO_IMM16_X1
7593 BFD_RELOC_TILEPRO_IMM16_X0_LO
7595 BFD_RELOC_TILEPRO_IMM16_X1_LO
7597 BFD_RELOC_TILEPRO_IMM16_X0_HI
7599 BFD_RELOC_TILEPRO_IMM16_X1_HI
7601 BFD_RELOC_TILEPRO_IMM16_X0_HA
7603 BFD_RELOC_TILEPRO_IMM16_X1_HA
7605 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7607 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7609 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7611 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7613 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7615 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7617 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7619 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7621 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7623 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7625 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7627 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7629 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7631 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7633 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7635 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7637 BFD_RELOC_TILEPRO_MMSTART_X0
7639 BFD_RELOC_TILEPRO_MMEND_X0
7641 BFD_RELOC_TILEPRO_MMSTART_X1
7643 BFD_RELOC_TILEPRO_MMEND_X1
7645 BFD_RELOC_TILEPRO_SHAMT_X0
7647 BFD_RELOC_TILEPRO_SHAMT_X1
7649 BFD_RELOC_TILEPRO_SHAMT_Y0
7651 BFD_RELOC_TILEPRO_SHAMT_Y1
7653 BFD_RELOC_TILEPRO_TLS_GD_CALL
7655 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7657 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7659 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7661 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7663 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7665 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7667 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7669 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7671 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7673 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7675 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7677 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7679 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7681 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7683 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7685 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7687 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7689 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7691 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7693 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7695 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7697 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7699 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7701 BFD_RELOC_TILEPRO_TLS_TPOFF32
7703 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7705 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7707 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7709 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7711 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7713 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7715 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7717 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7719 Tilera TILEPro Relocations.
7721 BFD_RELOC_TILEGX_HW0
7723 BFD_RELOC_TILEGX_HW1
7725 BFD_RELOC_TILEGX_HW2
7727 BFD_RELOC_TILEGX_HW3
7729 BFD_RELOC_TILEGX_HW0_LAST
7731 BFD_RELOC_TILEGX_HW1_LAST
7733 BFD_RELOC_TILEGX_HW2_LAST
7735 BFD_RELOC_TILEGX_COPY
7737 BFD_RELOC_TILEGX_GLOB_DAT
7739 BFD_RELOC_TILEGX_JMP_SLOT
7741 BFD_RELOC_TILEGX_RELATIVE
7743 BFD_RELOC_TILEGX_BROFF_X1
7745 BFD_RELOC_TILEGX_JUMPOFF_X1
7747 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7749 BFD_RELOC_TILEGX_IMM8_X0
7751 BFD_RELOC_TILEGX_IMM8_Y0
7753 BFD_RELOC_TILEGX_IMM8_X1
7755 BFD_RELOC_TILEGX_IMM8_Y1
7757 BFD_RELOC_TILEGX_DEST_IMM8_X1
7759 BFD_RELOC_TILEGX_MT_IMM14_X1
7761 BFD_RELOC_TILEGX_MF_IMM14_X1
7763 BFD_RELOC_TILEGX_MMSTART_X0
7765 BFD_RELOC_TILEGX_MMEND_X0
7767 BFD_RELOC_TILEGX_SHAMT_X0
7769 BFD_RELOC_TILEGX_SHAMT_X1
7771 BFD_RELOC_TILEGX_SHAMT_Y0
7773 BFD_RELOC_TILEGX_SHAMT_Y1
7775 BFD_RELOC_TILEGX_IMM16_X0_HW0
7777 BFD_RELOC_TILEGX_IMM16_X1_HW0
7779 BFD_RELOC_TILEGX_IMM16_X0_HW1
7781 BFD_RELOC_TILEGX_IMM16_X1_HW1
7783 BFD_RELOC_TILEGX_IMM16_X0_HW2
7785 BFD_RELOC_TILEGX_IMM16_X1_HW2
7787 BFD_RELOC_TILEGX_IMM16_X0_HW3
7789 BFD_RELOC_TILEGX_IMM16_X1_HW3
7791 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7793 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7795 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7797 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7799 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7801 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7803 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7805 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7807 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7809 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7811 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7813 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7815 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7817 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7819 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7821 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7823 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7825 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7827 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7829 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7831 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7833 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7835 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7837 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7839 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7841 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7843 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7845 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7847 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7849 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7851 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7853 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7855 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7857 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7859 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7861 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7863 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7865 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7867 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7869 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7871 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7873 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7875 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7877 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7879 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7881 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7883 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7885 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7887 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7889 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7891 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7893 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7895 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7897 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7899 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7901 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7903 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7905 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7907 BFD_RELOC_TILEGX_TLS_DTPMOD64
7909 BFD_RELOC_TILEGX_TLS_DTPOFF64
7911 BFD_RELOC_TILEGX_TLS_TPOFF64
7913 BFD_RELOC_TILEGX_TLS_DTPMOD32
7915 BFD_RELOC_TILEGX_TLS_DTPOFF32
7917 BFD_RELOC_TILEGX_TLS_TPOFF32
7919 BFD_RELOC_TILEGX_TLS_GD_CALL
7921 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7923 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7925 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7927 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7929 BFD_RELOC_TILEGX_TLS_IE_LOAD
7931 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7933 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7935 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7937 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7939 Tilera TILE-Gx Relocations.
7942 BFD_RELOC_EPIPHANY_SIMM8
7944 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7946 BFD_RELOC_EPIPHANY_SIMM24
7948 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7950 BFD_RELOC_EPIPHANY_HIGH
7952 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7954 BFD_RELOC_EPIPHANY_LOW
7956 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7958 BFD_RELOC_EPIPHANY_SIMM11
7960 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7962 BFD_RELOC_EPIPHANY_IMM11
7964 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7966 BFD_RELOC_EPIPHANY_IMM8
7968 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7971 BFD_RELOC_VISIUM_HI16
7973 BFD_RELOC_VISIUM_LO16
7975 BFD_RELOC_VISIUM_IM16
7977 BFD_RELOC_VISIUM_REL16
7979 BFD_RELOC_VISIUM_HI16_PCREL
7981 BFD_RELOC_VISIUM_LO16_PCREL
7983 BFD_RELOC_VISIUM_IM16_PCREL
7988 BFD_RELOC_WASM32_LEB128
7990 BFD_RELOC_WASM32_LEB128_GOT
7992 BFD_RELOC_WASM32_LEB128_GOT_CODE
7994 BFD_RELOC_WASM32_LEB128_PLT
7996 BFD_RELOC_WASM32_PLT_INDEX
7998 BFD_RELOC_WASM32_ABS32_CODE
8000 BFD_RELOC_WASM32_COPY
8002 BFD_RELOC_WASM32_CODE_POINTER
8004 BFD_RELOC_WASM32_INDEX
8006 BFD_RELOC_WASM32_PLT_SIG
8008 WebAssembly relocations.
8011 BFD_RELOC_CKCORE_NONE
8013 BFD_RELOC_CKCORE_ADDR32
8015 BFD_RELOC_CKCORE_PCREL_IMM8BY4
8017 BFD_RELOC_CKCORE_PCREL_IMM11BY2
8019 BFD_RELOC_CKCORE_PCREL_IMM4BY2
8021 BFD_RELOC_CKCORE_PCREL32
8023 BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2
8025 BFD_RELOC_CKCORE_GNU_VTINHERIT
8027 BFD_RELOC_CKCORE_GNU_VTENTRY
8029 BFD_RELOC_CKCORE_RELATIVE
8031 BFD_RELOC_CKCORE_COPY
8033 BFD_RELOC_CKCORE_GLOB_DAT
8035 BFD_RELOC_CKCORE_JUMP_SLOT
8037 BFD_RELOC_CKCORE_GOTOFF
8039 BFD_RELOC_CKCORE_GOTPC
8041 BFD_RELOC_CKCORE_GOT32
8043 BFD_RELOC_CKCORE_PLT32
8045 BFD_RELOC_CKCORE_ADDRGOT
8047 BFD_RELOC_CKCORE_ADDRPLT
8049 BFD_RELOC_CKCORE_PCREL_IMM26BY2
8051 BFD_RELOC_CKCORE_PCREL_IMM16BY2
8053 BFD_RELOC_CKCORE_PCREL_IMM16BY4
8055 BFD_RELOC_CKCORE_PCREL_IMM10BY2
8057 BFD_RELOC_CKCORE_PCREL_IMM10BY4
8059 BFD_RELOC_CKCORE_ADDR_HI16
8061 BFD_RELOC_CKCORE_ADDR_LO16
8063 BFD_RELOC_CKCORE_GOTPC_HI16
8065 BFD_RELOC_CKCORE_GOTPC_LO16
8067 BFD_RELOC_CKCORE_GOTOFF_HI16
8069 BFD_RELOC_CKCORE_GOTOFF_LO16
8071 BFD_RELOC_CKCORE_GOT12
8073 BFD_RELOC_CKCORE_GOT_HI16
8075 BFD_RELOC_CKCORE_GOT_LO16
8077 BFD_RELOC_CKCORE_PLT12
8079 BFD_RELOC_CKCORE_PLT_HI16
8081 BFD_RELOC_CKCORE_PLT_LO16
8083 BFD_RELOC_CKCORE_ADDRGOT_HI16
8085 BFD_RELOC_CKCORE_ADDRGOT_LO16
8087 BFD_RELOC_CKCORE_ADDRPLT_HI16
8089 BFD_RELOC_CKCORE_ADDRPLT_LO16
8091 BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2
8093 BFD_RELOC_CKCORE_TOFFSET_LO16
8095 BFD_RELOC_CKCORE_DOFFSET_LO16
8097 BFD_RELOC_CKCORE_PCREL_IMM18BY2
8099 BFD_RELOC_CKCORE_DOFFSET_IMM18
8101 BFD_RELOC_CKCORE_DOFFSET_IMM18BY2
8103 BFD_RELOC_CKCORE_DOFFSET_IMM18BY4
8105 BFD_RELOC_CKCORE_GOTOFF_IMM18
8107 BFD_RELOC_CKCORE_GOT_IMM18BY4
8109 BFD_RELOC_CKCORE_PLT_IMM18BY4
8111 BFD_RELOC_CKCORE_PCREL_IMM7BY4
8113 BFD_RELOC_CKCORE_TLS_LE32
8115 BFD_RELOC_CKCORE_TLS_IE32
8117 BFD_RELOC_CKCORE_TLS_GD32
8119 BFD_RELOC_CKCORE_TLS_LDM32
8121 BFD_RELOC_CKCORE_TLS_LDO32
8123 BFD_RELOC_CKCORE_TLS_DTPMOD32
8125 BFD_RELOC_CKCORE_TLS_DTPOFF32
8127 BFD_RELOC_CKCORE_TLS_TPOFF32
8129 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4
8131 BFD_RELOC_CKCORE_NOJSRI
8133 BFD_RELOC_CKCORE_CALLGRAPH
8135 BFD_RELOC_CKCORE_IRELATIVE
8137 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4
8139 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4
8147 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
8152 bfd_reloc_type_lookup
8153 bfd_reloc_name_lookup
8156 reloc_howto_type *bfd_reloc_type_lookup
8157 (bfd *abfd, bfd_reloc_code_real_type code);
8158 reloc_howto_type *bfd_reloc_name_lookup
8159 (bfd *abfd, const char *reloc_name);
8162 Return a pointer to a howto structure which, when
8163 invoked, will perform the relocation @var{code} on data from the
8169 bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
8171 return BFD_SEND (abfd, reloc_type_lookup, (abfd, code));
8175 bfd_reloc_name_lookup (bfd *abfd, const char *reloc_name)
8177 return BFD_SEND (abfd, reloc_name_lookup, (abfd, reloc_name));
8180 static reloc_howto_type bfd_howto_32 =
8181 HOWTO (0, 00, 2, 32, FALSE, 0, complain_overflow_dont, 0, "VRT32", FALSE, 0xffffffff, 0xffffffff, TRUE);
8185 bfd_default_reloc_type_lookup
8188 reloc_howto_type *bfd_default_reloc_type_lookup
8189 (bfd *abfd, bfd_reloc_code_real_type code);
8192 Provides a default relocation lookup routine for any architecture.
8197 bfd_default_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
8201 case BFD_RELOC_CTOR:
8202 /* The type of reloc used in a ctor, which will be as wide as the
8203 address - so either a 64, 32, or 16 bitter. */
8204 switch (bfd_arch_bits_per_address (abfd))
8210 return &bfd_howto_32;
8226 bfd_get_reloc_code_name
8229 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
8232 Provides a printable name for the supplied relocation code.
8233 Useful mainly for printing error messages.
8237 bfd_get_reloc_code_name (bfd_reloc_code_real_type code)
8239 if (code > BFD_RELOC_UNUSED)
8241 return bfd_reloc_code_real_names[code];
8246 bfd_generic_relax_section
8249 bfd_boolean bfd_generic_relax_section
8252 struct bfd_link_info *,
8256 Provides default handling for relaxing for back ends which
8261 bfd_generic_relax_section (bfd *abfd ATTRIBUTE_UNUSED,
8262 asection *section ATTRIBUTE_UNUSED,
8263 struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
8266 if (bfd_link_relocatable (link_info))
8267 (*link_info->callbacks->einfo)
8268 (_("%P%F: --relax and -r may not be used together\n"));
8276 bfd_generic_gc_sections
8279 bfd_boolean bfd_generic_gc_sections
8280 (bfd *, struct bfd_link_info *);
8283 Provides default handling for relaxing for back ends which
8284 don't do section gc -- i.e., does nothing.
8288 bfd_generic_gc_sections (bfd *abfd ATTRIBUTE_UNUSED,
8289 struct bfd_link_info *info ATTRIBUTE_UNUSED)
8296 bfd_generic_lookup_section_flags
8299 bfd_boolean bfd_generic_lookup_section_flags
8300 (struct bfd_link_info *, struct flag_info *, asection *);
8303 Provides default handling for section flags lookup
8304 -- i.e., does nothing.
8305 Returns FALSE if the section should be omitted, otherwise TRUE.
8309 bfd_generic_lookup_section_flags (struct bfd_link_info *info ATTRIBUTE_UNUSED,
8310 struct flag_info *flaginfo,
8311 asection *section ATTRIBUTE_UNUSED)
8313 if (flaginfo != NULL)
8315 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported"));
8323 bfd_generic_merge_sections
8326 bfd_boolean bfd_generic_merge_sections
8327 (bfd *, struct bfd_link_info *);
8330 Provides default handling for SEC_MERGE section merging for back ends
8331 which don't have SEC_MERGE support -- i.e., does nothing.
8335 bfd_generic_merge_sections (bfd *abfd ATTRIBUTE_UNUSED,
8336 struct bfd_link_info *link_info ATTRIBUTE_UNUSED)
8343 bfd_generic_get_relocated_section_contents
8346 bfd_byte *bfd_generic_get_relocated_section_contents
8348 struct bfd_link_info *link_info,
8349 struct bfd_link_order *link_order,
8351 bfd_boolean relocatable,
8355 Provides default handling of relocation effort for back ends
8356 which can't be bothered to do it efficiently.
8361 bfd_generic_get_relocated_section_contents (bfd *abfd,
8362 struct bfd_link_info *link_info,
8363 struct bfd_link_order *link_order,
8365 bfd_boolean relocatable,
8368 bfd *input_bfd = link_order->u.indirect.section->owner;
8369 asection *input_section = link_order->u.indirect.section;
8371 arelent **reloc_vector;
8374 reloc_size = bfd_get_reloc_upper_bound (input_bfd, input_section);
8378 /* Read in the section. */
8379 if (!bfd_get_full_section_contents (input_bfd, input_section, &data))
8385 if (reloc_size == 0)
8388 reloc_vector = (arelent **) bfd_malloc (reloc_size);
8389 if (reloc_vector == NULL)
8392 reloc_count = bfd_canonicalize_reloc (input_bfd,
8396 if (reloc_count < 0)
8399 if (reloc_count > 0)
8403 for (parent = reloc_vector; *parent != NULL; parent++)
8405 char *error_message = NULL;
8407 bfd_reloc_status_type r;
8409 symbol = *(*parent)->sym_ptr_ptr;
8410 /* PR ld/19628: A specially crafted input file
8411 can result in a NULL symbol pointer here. */
8414 link_info->callbacks->einfo
8415 /* xgettext:c-format */
8416 (_("%X%P: %pB(%pA): error: relocation for offset %V has no value\n"),
8417 abfd, input_section, (* parent)->address);
8421 if (symbol->section && discarded_section (symbol->section))
8424 static reloc_howto_type none_howto
8425 = HOWTO (0, 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL,
8426 "unused", FALSE, 0, 0, FALSE);
8428 p = data + (*parent)->address * bfd_octets_per_byte (input_bfd);
8429 _bfd_clear_contents ((*parent)->howto, input_bfd, input_section,
8431 (*parent)->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
8432 (*parent)->addend = 0;
8433 (*parent)->howto = &none_howto;
8437 r = bfd_perform_relocation (input_bfd,
8441 relocatable ? abfd : NULL,
8446 asection *os = input_section->output_section;
8448 /* A partial link, so keep the relocs. */
8449 os->orelocation[os->reloc_count] = *parent;
8453 if (r != bfd_reloc_ok)
8457 case bfd_reloc_undefined:
8458 (*link_info->callbacks->undefined_symbol)
8459 (link_info, bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
8460 input_bfd, input_section, (*parent)->address, TRUE);
8462 case bfd_reloc_dangerous:
8463 BFD_ASSERT (error_message != NULL);
8464 (*link_info->callbacks->reloc_dangerous)
8465 (link_info, error_message,
8466 input_bfd, input_section, (*parent)->address);
8468 case bfd_reloc_overflow:
8469 (*link_info->callbacks->reloc_overflow)
8471 bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
8472 (*parent)->howto->name, (*parent)->addend,
8473 input_bfd, input_section, (*parent)->address);
8475 case bfd_reloc_outofrange:
8477 This error can result when processing some partially
8478 complete binaries. Do not abort, but issue an error
8480 link_info->callbacks->einfo
8481 /* xgettext:c-format */
8482 (_("%X%P: %pB(%pA): relocation \"%pR\" goes out of range\n"),
8483 abfd, input_section, * parent);
8486 case bfd_reloc_notsupported:
8488 This error can result when processing a corrupt binary.
8489 Do not abort. Issue an error message instead. */
8490 link_info->callbacks->einfo
8491 /* xgettext:c-format */
8492 (_("%X%P: %pB(%pA): relocation \"%pR\" is not supported\n"),
8493 abfd, input_section, * parent);
8497 /* PR 17512; file: 90c2a92e.
8498 Report unexpected results, without aborting. */
8499 link_info->callbacks->einfo
8500 /* xgettext:c-format */
8501 (_("%X%P: %pB(%pA): relocation \"%pR\" returns an unrecognized value %x\n"),
8502 abfd, input_section, * parent, r);
8510 free (reloc_vector);
8514 free (reloc_vector);
8520 _bfd_generic_set_reloc
8523 void _bfd_generic_set_reloc
8527 unsigned int count);
8530 Installs a new set of internal relocations in SECTION.
8534 _bfd_generic_set_reloc (bfd *abfd ATTRIBUTE_UNUSED,
8539 section->orelocation = relptr;
8540 section->reloc_count = count;
8545 _bfd_unrecognized_reloc
8548 bfd_boolean _bfd_unrecognized_reloc
8551 unsigned int r_type);
8554 Reports an unrecognized reloc.
8555 Written as a function in order to reduce code duplication.
8556 Returns FALSE so that it can be called from a return statement.
8560 _bfd_unrecognized_reloc (bfd * abfd, sec_ptr section, unsigned int r_type)
8562 /* xgettext:c-format */
8563 _bfd_error_handler (_("%pB: unrecognized relocation type %#x in section `%pA'"),
8564 abfd, r_type, section);
8566 /* PR 21803: Suggest the most likely cause of this error. */
8567 _bfd_error_handler (_("is this version of the linker - %s - out of date ?"),
8568 BFD_VERSION_STRING);
8570 bfd_set_error (bfd_error_bad_value);
8575 _bfd_norelocs_bfd_reloc_type_lookup
8577 bfd_reloc_code_real_type code ATTRIBUTE_UNUSED)
8579 return (reloc_howto_type *) _bfd_ptr_bfd_null_error (abfd);
8583 _bfd_norelocs_bfd_reloc_name_lookup (bfd *abfd,
8584 const char *reloc_name ATTRIBUTE_UNUSED)
8586 return (reloc_howto_type *) _bfd_ptr_bfd_null_error (abfd);
8590 _bfd_nodynamic_canonicalize_dynamic_reloc (bfd *abfd,
8591 arelent **relp ATTRIBUTE_UNUSED,
8592 asymbol **symp ATTRIBUTE_UNUSED)
8594 return _bfd_long_bfd_n1_error (abfd);