sim/v850/v850.igen

   1 :option::insn-bit-size:16
   2 :option::hi-bit-nr:15
   3
   4
   5 :option::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
   6 # start-sanitize-v850e
   7 :option::format-names:XI,XII,XIII
   8 # end-sanitize-v850e
   9 # start-sanitize-v850eq
  10 :option::format-names:XIV,XV
  11 # end-sanitize-v850eq
  12 :option::format-names:Z
  13
  14
  15 :model::v850:v850:
  16
  17 # start-sanitize-v850e
  18 :option::multi-sim:true
  19 :model::v850e:v850e:
  20 # end-sanitize-v850e
  21
  22 # start-sanitize-v850eq
  23 :option::multi-sim:true
  24 :model::v850eq:v850eq:
  25 # end-sanitize-v850eq
  26
  27
  28
  29 // Cache macros
  30
  31 :cache::unsigned:reg1:RRRRR:(RRRRR)
  32 :cache::unsigned:reg2:rrrrr:(rrrrr)
  33 :cache::unsigned:reg3:wwwww:(wwwww)
  34 :cache::unsigned:regID:rrrrr:(rrrrr)
  35
  36 :cache::unsigned:disp4:dddd:(dddd)
  37 # start-sanitize-v850e
  38 :cache::unsigned:disp5:dddd:(dddd << 1)
  39 # end-sanitize-v850e
  40 :cache::unsigned:disp7:ddddddd:ddddddd
  41 :cache::unsigned:disp8:ddddddd:(ddddddd << 1)
  42 :cache::unsigned:disp8:dddddd:(dddddd << 2)
  43 :cache::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
  44 :cache::unsigned:disp16:dddddddddddddddd:SEXT32 (dddddddddddddddd, 16 - 1)
  45 :cache::unsigned:disp16:ddddddddddddddd:SEXT32 (ddddddddddddddd << 1, 16 - 1)
  46 :cache::unsigned:disp22:dddddd,dddddddddddddddd:SEXT32 ((dddddd << 16) + (dddddddddddddddd << 1), 22 - 1)
  47 :cache::unsigned:disp22:dddddd,ddddddddddddddd:SEXT32 ((dddddd << 16) + (ddddddddddddddd << 2), 22 - 1)
  48
  49 :cache::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
  50 :cache::unsigned:imm6:iiiiii:iiiiii
  51 :cache::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
  52 # start-sanitize-v850eq
  53 :cache::unsigned:imm5:iiii:(32 - (iiii << 1))
  54 # end-sanitize-v850eq
  55 :cache::unsigned:imm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
  56 :cache::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
  57 # start-sanitize-v850e
  58 :cache::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
  59 :cache::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
  60 # end-sanitize-v850e
  61
  62 :cache::unsigned:vector:iiiii:iiiii
  63
  64 # start-sanitize-v850e
  65 :cache::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
  66 :cache::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
  67 # end-sanitize-v850e
  68
  69 :cache::unsigned:bit3:bbb:bbb
  70
  71
  72 // What do we do with an illegal instruction?
  73 :internal:::illegal
  74 {
  75   sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
  76                   (unsigned long) cia);
  77   sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
  78 }
  79
  80
  81
  82 // Add
  83
  84 rrrrr,001110,RRRRR:I:::add
  85 "add r<reg1>, r<reg2>"
  86 {
  87   COMPAT_1 (OP_1C0 ());
  88 }
  89
  90 rrrrr,010010,iiiii:II:::add
  91 "add <imm5>,r<reg2>"
  92 {
  93   COMPAT_1 (OP_240 ());
  94 }
  95
  96
  97
  98 // ADDI
  99 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
 100 "addi <imm16>, r<reg1>, r<reg2>"
 101 {
 102   COMPAT_2 (OP_600 ());
 103 }
 104
 105
 106
 107 // AND
 108 rrrrr,001010,RRRRR:I:::and
 109 "and r<reg1>, r<reg2>"
 110 {
 111   COMPAT_1 (OP_140 ());
 112 }
 113
 114
 115
 116 // ANDI
 117 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
 118 "andi <imm16>, r<reg1>, r<reg2>"
 119 {
 120   COMPAT_2 (OP_6C0 ());
 121 }
 122
 123
 124
 125 // Bcond
 126 // ddddd,1011,ddd,cccc:III:::Bcond
 127 // "b<cond> disp9"
 128
 129 ddddd,1011,ddd,0000:III:::bv
 130 "bv <disp9>"
 131 {
 132   COMPAT_1 (OP_580 ());
 133 }
 134
 135 ddddd,1011,ddd,0001:III:::bl
 136 "bl <disp9>"
 137 {
 138   COMPAT_1 (OP_581 ());
 139 }
 140
 141 ddddd,1011,ddd,0010:III:::be
 142 "be <disp9>"
 143 {
 144   COMPAT_1 (OP_582 ());
 145 }
 146
 147 ddddd,1011,ddd,0011:III:::bnh
 148 "bnh <disp9>"
 149 {
 150   COMPAT_1 (OP_583 ());
 151 }
 152
 153 ddddd,1011,ddd,0100:III:::bn
 154 "bn <disp9>"
 155 {
 156   COMPAT_1 (OP_584 ());
 157 }
 158
 159 ddddd,1011,ddd,0101:III:::br
 160 "br <disp9>"
 161 {
 162   COMPAT_1 (OP_585 ());
 163 }
 164
 165 ddddd,1011,ddd,0110:III:::blt
 166 "blt <disp9>"
 167 {
 168   COMPAT_1 (OP_586 ());
 169 }
 170
 171 ddddd,1011,ddd,0111:III:::ble
 172 "ble <disp9>"
 173 {
 174   COMPAT_1 (OP_587 ());
 175 }
 176
 177 ddddd,1011,ddd,1000:III:::bnv
 178 "bnv <disp9>"
 179 {
 180   COMPAT_1 (OP_588 ());
 181 }
 182
 183 ddddd,1011,ddd,1001:III:::bnl
 184 "bnl <disp9>"
 185 {
 186   COMPAT_1 (OP_589 ());
 187 }
 188
 189 ddddd,1011,ddd,1010:III:::bne
 190 "bne <disp9>"
 191 {
 192   COMPAT_1 (OP_58A ());
 193 }
 194
 195 ddddd,1011,ddd,1011:III:::bh
 196 "bh <disp9>"
 197 {
 198   COMPAT_1 (OP_58B ());
 199 }
 200
 201 ddddd,1011,ddd,1100:III:::bp
 202 "bp <disp9>"
 203 {
 204   COMPAT_1 (OP_58C ());
 205 }
 206
 207 ddddd,1011,ddd,1101:III:::bsa
 208 "bsa <disp9>"
 209 {
 210   COMPAT_1 (OP_58D ());
 211 }
 212
 213 ddddd,1011,ddd,1110:III:::bge
 214 "bge <disp9>"
 215 {
 216   COMPAT_1 (OP_58E ());
 217 }
 218
 219 ddddd,1011,ddd,1111:III:::bgt
 220 "bgt <disp9>"
 221 {
 222   COMPAT_1 (OP_58F ());
 223 }
 224
 225
 226
 227 // start-sanitize-v850e
 228 // BSH
 229 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
 230 *v850e
 231 // start-sanitize-v850eq
 232 *v850eq
 233 // end-sanitize-v850eq
 234 "bsh r<reg2>, r<reg3>"
 235 {
 236   COMPAT_2 (OP_34207E0 ());
 237 }
 238
 239
 240
 241 // end-sanitize-v850e
 242 // start-sanitize-v850e
 243 // BSW
 244 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
 245 *v850e
 246 // start-sanitize-v850eq
 247 *v850eq
 248 // end-sanitize-v850eq
 249 "bsw r<reg2>, reg3>"
 250 {
 251   COMPAT_2 (OP_34007E0 ());
 252 }
 253
 254
 255
 256 // end-sanitize-v850e
 257 // CALLT
 258 0000001000,iiiiii:II:::callt
 259 "callt <imm6>"
 260 {
 261   COMPAT_1 (OP_200 ());
 262 }
 263
 264
 265
 266 // CLR1
 267 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
 268 "clr1 <bit3>, <disp16>[r<reg1>]"
 269 {
 270   COMPAT_2 (OP_87C0 ());
 271 }
 272
 273 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
 274 "clr1 r<reg2>, [r<reg1>]"
 275 {
 276   COMPAT_2 (OP_E407E0 ());
 277 }
 278
 279
 280
 281 // CTRET
 282 0000011111100000 + 0000000101000100:X:::ctret
 283 "ctret"
 284 {
 285   COMPAT_2 (OP_14407E0 ());
 286 }
 287
 288
 289
 290 // start-sanitize-v850e
 291 // CMOV
 292 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
 293 *v850e
 294 // start-sanitize-v850eq
 295 *v850eq
 296 // end-sanitize-v850eq
 297 "cmov <cccc>, r<reg1>, r<reg2>, r<reg3>"
 298 {
 299   COMPAT_2 (OP_32007E0 ());
 300 }
 301
 302 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
 303 *v850e
 304 // start-sanitize-v850eq
 305 *v850eq
 306 // end-sanitize-v850eq
 307 "cmov <cccc>, <imm5>, r<reg2>, r<reg3>"
 308 {
 309   COMPAT_2 (OP_30007E0 ());
 310 }
 311
 312
 313
 314 // end-sanitize-v850e
 315 // CMP
 316 rrrrr,001111,RRRRR:I:::cmp
 317 "cmp r<reg1>, r<reg2>"
 318 {
 319   COMPAT_1 (OP_1E0 ());
 320 }
 321
 322 rrrrr,010011,iiiii:II:::cmp
 323 "cmp <imm5>, r<reg2>"
 324 {
 325   COMPAT_1 (OP_260 ());
 326 }
 327
 328
 329
 330 // DI
 331 0000011111100000 + 0000000101100000:X:::di
 332 "di"
 333 {
 334   COMPAT_2 (OP_16007E0 ());
 335 }
 336
 337
 338
 339 // start-sanitize-v850e
 340 // DISPOSE
 341 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
 342 // "dispose <imm5>, <list12>"
 343 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
 344 *v850e
 345 // start-sanitize-v850eq
 346 *v850eq
 347 // end-sanitize-v850eq
 348 "dispose <imm5>, <list12>":RRRRR == 0
 349 "dispose <imm5>, <list12>, [reg1]"
 350 {
 351   COMPAT_2 (OP_640 ());
 352 }
 353
 354
 355
 356 // end-sanitize-v850e
 357 // start-sanitize-v850e
 358 // DIV
 359 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
 360 *v850e
 361 "div r<reg1>, r<reg2>, r<reg3>"
 362 {
 363   COMPAT_2 (OP_2C007E0 ());
 364 }
 365
 366
 367
 368
 369 // end-sanitize-v850e
 370 // DIVH
 371 rrrrr!0,000010,RRRRR!0:I:::divh
 372 "divh r<reg1>, r<reg2>"
 373 {
 374   COMPAT_1 (OP_40 ());
 375 }
 376
 377 // start-sanitize-v850e
 378 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
 379 *v850e
 380 "divh r<reg1>, r<reg2>, r<reg3>"
 381 {
 382   COMPAT_2 (OP_28007E0 ());
 383 }
 384
 385 // end-sanitize-v850e
 386
 387
 388 // start-sanitize-v850e
 389 // DIVHU
 390 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
 391 *v850e
 392 "divhu r<reg1>, r<reg2>, r<reg3>"
 393 {
 394   COMPAT_2 (OP_28207E0 ());
 395 }
 396
 397
 398
 399 // end-sanitize-v850e
 400 // start-sanitize-v850e
 401 // DIVU
 402 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
 403 *v850e
 404 "divu r<reg1>, r<reg2>, r<reg3>"
 405 {
 406   COMPAT_2 (OP_2C207E0 ());
 407 }
 408
 409
 410
 411 // end-sanitize-v850e
 412 // EI
 413 1000011111100000 + 0000000101100000:X:::ei
 414 "ei"
 415 {
 416   COMPAT_2 (OP_16087E0 ());
 417 }
 418
 419
 420
 421 // HALT
 422 0000011111100000 + 0000000100100000:X:::halt
 423 "halt"
 424 {
 425   COMPAT_2 (OP_12007E0 ());
 426 }
 427
 428
 429
 430 // HSW
 431 // start-sanitize-v850e
 432 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
 433 *v850e
 434 // start-sanitize-v850eq
 435 *v850eq
 436 // end-sanitize-v850eq
 437 "hsw r<reg2>, r<reg3>"
 438 {
 439   COMPAT_2 (OP_34407E0 ());
 440 }
 441
 442
 443
 444 // end-sanitize-v850e
 445 // JARL
 446 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 447 "jarl <disp22>, r<reg2>"
 448 {
 449   COMPAT_2 (OP_780 ());
 450 }
 451
 452
 453
 454 // JMP
 455 00000000011,RRRRR:I:::jmp
 456 "jmp [r<reg1>]"
 457 {
 458   COMPAT_1 (0);
 459   trace_input ("jmp", OP_REG, 0);
 460   nia = State.regs[ reg1 ];
 461   trace_output (OP_REG);
 462 }
 463
 464
 465
 466 // JR
 467 0000011110,dddddd + ddddddddddddddd,0:V:::jr
 468 "jr <disp22>"
 469 {
 470   COMPAT_2 (OP_780 ());
 471 }
 472
 473
 474
 475 // LD
 476 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
 477 "ld.b <disp16>[r<reg1>, r<reg2>"
 478 {
 479   COMPAT_2 (OP_700 ());
 480 }
 481
 482 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
 483 "ld.h <disp16>[r<reg1>], r<reg2>"
 484 {
 485   COMPAT_2 (OP_720 ());
 486 }
 487
 488 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 489 "ld.w <disp16>[r<reg1>], r<reg2>"
 490 {
 491   COMPAT_2 (OP_10720 ());
 492 }
 493
 494 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
 495 "ld.bu <disp16>[r<reg1>], r<reg2>"
 496 {
 497   COMPAT_2 (OP_10780 ());
 498 }
 499
 500 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 501 "ld.hu <disp16>[r<reg1>], r<reg2>"
 502 {
 503   COMPAT_2 (OP_107E0 ());
 504 }
 505
 506
 507
 508 // LDSR
 509 //rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
 510 //"ldsr r<reg2>, r<regID>"
 511 //{
 512 //  COMPAT_2 (OP_2007E0 ());
 513 //}
 514 rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
 515 "ldsr r<reg1>, r<regID>"
 516 {
 517   COMPAT_2 (OP_2007E0 ());
 518 }
 519
 520
 521
 522 // MOV
 523 rrrrr!0,000000,RRRRR:I:::mov
 524 "mov r<reg1>, r<reg2>"
 525 {
 526   COMPAT_1 (OP_0 ());
 527 }
 528
 529 rrrrr!0,010000,iiiii:II:::mov
 530 "mov <imm5>, r<reg2>"
 531 {
 532   COMPAT_1 (OP_200 ());
 533 }
 534
 535 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
 536 "mov <imm32>, r<reg1>"
 537 {
 538   COMPAT_2 (OP_620 ());
 539 }
 540
 541
 542
 543 // MOVEA
 544 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
 545 "movea <imm16>, r<reg1>, r<reg2>"
 546 {
 547   COMPAT_2 (OP_620 ());
 548 }
 549
 550
 551
 552 // MOVHI
 553 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
 554 "movhi <imm16>, r<reg1>, r<reg2>"
 555 {
 556   COMPAT_2 (OP_640 ());
 557 }
 558
 559
 560
 561 // start-sanitize-v850e
 562 // MUL
 563 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
 564 *v850e
 565 // start-sanitize-v850eq
 566 *v850eq
 567 // end-sanitize-v850eq
 568 "mul r<reg1>, r<reg2>, r<reg3>"
 569 {
 570   COMPAT_2 (OP_22007E0 ());
 571 }
 572
 573 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
 574 *v850e
 575 // start-sanitize-v850eq
 576 *v850eq
 577 // end-sanitize-v850eq
 578 "mul <imm9>, r<reg2>, r<reg3>"
 579 {
 580   COMPAT_2 (OP_24007E0 ());
 581 }
 582
 583
 584
 585 // end-sanitize-v850e
 586 // MULH
 587 rrrrr!0,000111,RRRRR:I:::mulh
 588 "mulh r<reg1>, r<reg2>"
 589 {
 590   COMPAT_1 (OP_E0 ());
 591 }
 592
 593 rrrrr!0,010111,iiiii:II:::mulh
 594 "mulh <imm5>, r<reg2>"
 595 {
 596   COMPAT_1 (OP_2E0 ());
 597 }
 598
 599
 600
 601 // MULHI
 602 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
 603 "mulhi <imm16>, r<reg1>, r<reg2>"
 604 {
 605   COMPAT_2 (OP_6E0 ());
 606 }
 607
 608
 609
 610 // start-sanitize-v850e
 611 // MULU
 612 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
 613 *v850e
 614 // start-sanitize-v850eq
 615 *v850eq
 616 // end-sanitize-v850eq
 617 "mulu r<reg1>, r<reg2>, r<reg3>"
 618 {
 619   COMPAT_2 (OP_22207E0 ());
 620 }
 621
 622 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
 623 *v850e
 624 // start-sanitize-v850eq
 625 *v850eq
 626 // end-sanitize-v850eq
 627 "mulu <imm9>, r<reg2>, r<reg3>"
 628 {
 629   COMPAT_2 (OP_24207E0 ());
 630 }
 631
 632
 633
 634 // end-sanitize-v850e
 635 // NOP
 636 0000000000000000:I:::nop
 637 "nop"
 638 {
 639   COMPAT_1 (OP_0 ());
 640 }
 641
 642
 643
 644 // NOT
 645 rrrrr,000001,RRRRR:I:::not
 646 "not r<reg1>, r<reg2>"
 647 {
 648   COMPAT_1 (OP_20 ());
 649 }
 650
 651
 652
 653 // NOT1
 654 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
 655 "not1 <bit3>, <disp16>[r<reg1>]"
 656 {
 657   COMPAT_2 (OP_47C0 ());
 658 }
 659
 660 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
 661 "not1 r<reg2>, r<reg1>"
 662 {
 663   COMPAT_2 (OP_E207E0 ());
 664 }
 665
 666
 667
 668 // OR
 669 rrrrr,001000,RRRRR:I:::or
 670 "or r<reg1>, r<reg2>"
 671 {
 672   COMPAT_1 (OP_100 ());
 673 }
 674
 675
 676
 677 // ORI
 678 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
 679 "ori <imm16>, r<reg1>, r<reg2>"
 680 {
 681   COMPAT_2 (OP_680 ());
 682 }
 683
 684
 685
 686 // start-sanitize-v850e
 687 // PREPARE
 688 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
 689 *v850e
 690 // start-sanitize-v850eq
 691 *v850eq
 692 // end-sanitize-v850eq
 693 "prepare <list12>, <imm5>"
 694 {
 695   COMPAT_2 (OP_10780 ());
 696 }
 697
 698 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
 699 *v850e
 700 // start-sanitize-v850eq
 701 *v850eq
 702 // end-sanitize-v850eq
 703 "prepare <list12>, <imm5>, sp"
 704 {
 705   COMPAT_2 (OP_30780 ());
 706 }
 707
 708 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
 709 *v850e
 710 // start-sanitize-v850eq
 711 *v850eq
 712 // end-sanitize-v850eq
 713 "prepare <list12>, <imm5>, <uimm16>"
 714 {
 715   COMPAT_2 (OP_B0780 ());
 716 }
 717
 718 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
 719 *v850e
 720 // start-sanitize-v850eq
 721 *v850eq
 722 // end-sanitize-v850eq
 723 "prepare <list12>, <imm5>, <uimm16>"
 724 {
 725   COMPAT_2 (OP_130780 ());
 726 }
 727
 728 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
 729 *v850e
 730 // start-sanitize-v850eq
 731 *v850eq
 732 // end-sanitize-v850eq
 733 "prepare <list12>, <imm5>, <uimm32>"
 734 {
 735   COMPAT_2 (OP_1B0780 ());
 736 }
 737
 738
 739
 740 // end-sanitize-v850e
 741 // RETI
 742 0000011111100000 + 0000000101000000:X:::reti
 743 "reti"
 744 {
 745   COMPAT_2 (OP_14007E0 ());
 746 }
 747
 748
 749
 750 // SAR
 751 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
 752 "sar r<reg1>, r<reg2>"
 753 {
 754   COMPAT_2 (OP_A007E0 ());
 755 }
 756
 757 rrrrr,010101,iiiii:II:::sar
 758 "sar <imm5>, r<reg2>"
 759 {
 760   COMPAT_1 (OP_2A0 ());
 761 }
 762
 763
 764
 765 // SASF
 766 rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
 767 "sasf <cccc>, r<reg2>"
 768 {
 769   COMPAT_2 (OP_20007E0 ());
 770 }
 771
 772
 773
 774
 775 // SATADD
 776 rrrrr!0,000110,RRRRR:I:::satadd
 777 "satadd r<reg1>, r<reg2>"
 778 {
 779   COMPAT_1 (OP_C0 ());
 780 }
 781
 782 rrrrr!0,010001,iiiii:II:::satadd
 783 "satadd <imm5>, r<reg2>"
 784 {
 785   COMPAT_1 (OP_220 ());
 786 }
 787
 788
 789
 790 // SATSUB
 791 rrrrr!0,000101,RRRRR:I:::satsub
 792 "satsub r<reg1>, r<reg2>"
 793 {
 794   COMPAT_1 (OP_A0 ());
 795 }
 796
 797
 798
 799 // SATSUBI
 800 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
 801 "satsubi <imm16>, r<reg1>, r<reg2>"
 802 {
 803   COMPAT_2 (OP_660 ());
 804 }
 805
 806
 807
 808 // SATSUBR
 809 rrrrr!0,000100,RRRRR:I:::satsubr
 810 "satsubr r<reg1>, r<reg2>"
 811 {
 812   COMPAT_1 (OP_80 ());
 813 }
 814
 815
 816
 817 // SETF
 818 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
 819 "setf <cccc>, r<reg2>"
 820 {
 821   COMPAT_2 (OP_7E0 ());
 822 }
 823
 824
 825
 826 // SET1
 827 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
 828 "set1 <bit3>, <disp16>[r<reg1>]"
 829 {
 830   COMPAT_2 (OP_7C0 ());
 831 }
 832
 833 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
 834 "set1 r<reg2>, [r<reg1>]"
 835 {
 836   COMPAT_2 (OP_E007E0 ());
 837 }
 838
 839
 840
 841 // SHL
 842 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
 843 "shl r<reg1>, r<reg2>"
 844 {
 845   COMPAT_2 (OP_C007E0 ());
 846 }
 847
 848 rrrrr,010110,iiiii:II:::shl
 849 "shl <imm5>, r<reg2>"
 850 {
 851   COMPAT_1 (OP_2C0 ());
 852 }
 853
 854
 855
 856 // SHR
 857 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
 858 "shr r<reg1>, r<reg2>"
 859 {
 860   COMPAT_2 (OP_8007E0 ());
 861 }
 862
 863 rrrrr,010100,iiiii:II:::shr
 864 "shr <imm5>, r<reg2>"
 865 {
 866   COMPAT_1 (OP_280 ());
 867 }
 868
 869
 870
 871 // SLD
 872 rrrrr,0110,ddddddd:IV:::sld.b
 873 "sld.b <disp7>[ep], r<reg2>"
 874 {
 875   COMPAT_1 (OP_300 ());
 876 }
 877
 878 rrrrr,1000,ddddddd:IV:::sld.h
 879 "sld.h <disp8>[ep], r<reg2>"
 880 {
 881   COMPAT_1 (OP_400 ());
 882 }
 883
 884 rrrrr,1010,dddddd,0:IV:::sld.w
 885 "sld.w <disp8>[ep], r<reg2>"
 886 {
 887   COMPAT_1 (OP_500 ());
 888 }
 889
 890 // start-sanitize-v850e
 891 rrrrr!0,0000110,dddd:IV:::sld.bu
 892 "sld.bu <disp4>[ep], r<reg2>"
 893 {
 894   unsigned long result;
 895
 896   COMPAT_1 (0);
 897   result = load_mem (State.regs[30] + disp4, 1);
 898
 899   /* start-sanitize-v850eq */
 900   if (PSW & PSW_US) {
 901     trace_input ("sld.b", OP_LOAD16, 1);
 902
 903     State.regs[ reg2 ] = EXTEND8 (result);
 904   } else {
 905   /* end-sanitize-v850eq */
 906   trace_input ("sld.bu", OP_LOAD16, 1);
 907   State.regs[ reg2 ] = result;
 908   /* start-sanitize-v850eq */
 909   }
 910   /* end-sanitize-v850eq */
 911   trace_output (OP_LOAD16);
 912 }
 913
 914 // end-sanitize-v850e
 915 // start-sanitize-v850e
 916 rrrrr!0,0000111,dddd:IV:::sld.hu
 917 "sld.hu <disp5>[ep], r<reg2>"
 918 {
 919   COMPAT_1 (OP_70 ());
 920 }
 921
 922 // end-sanitize-v850e
 923
 924
 925 // SST
 926 rrrrr,0111,ddddddd:IV:::sst.b
 927 "sst.b r<reg2>, <disp7>[ep]"
 928 {
 929   COMPAT_1 (OP_380 ());
 930 }
 931
 932 rrrrr,1001,ddddddd:IV:::sst.h
 933 "sst.h r<reg2>, <disp8>[ep]"
 934 {
 935   COMPAT_1 (OP_480 ());
 936 }
 937
 938 rrrrr,1010,dddddd,1:IV:::sst.w
 939 "sst.w r<reg2>, <disp8>[ep]"
 940 {
 941   COMPAT_1 (OP_501 ());
 942 }
 943
 944
 945
 946 // ST
 947 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
 948 "st.b r<reg2>, <disp16>[r<reg1>]"
 949 {
 950   COMPAT_2 (OP_740 ());
 951 }
 952
 953 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
 954 "st.h r<reg2>, <disp16>[r<reg1>]"
 955 {
 956   COMPAT_2 (OP_760 ());
 957 }
 958
 959 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
 960 "st.w r<reg2>, <disp16>[r<reg1>]"
 961 {
 962   COMPAT_2 (OP_10760 ());
 963 }
 964
 965
 966
 967 // STSR
 968 //rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
 969 //"stsr r<regID>, r<reg2>"
 970 //{
 971 //  COMPAT_2 (OP_4007E0 ());
 972 //}
 973 rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
 974 "stsr r<regID>, r<reg1>"
 975 {
 976   COMPAT_2 (OP_4007E0 ());
 977 }
 978
 979
 980
 981 // SUB
 982 rrrrr,001101,RRRRR:I:::sub
 983 "sub r<reg1>, r<reg2>"
 984 {
 985   COMPAT_1 (OP_1A0 ());
 986 }
 987
 988
 989
 990 // SUBR
 991 rrrrr,001100,RRRRR:I:::subr
 992 "subr r<reg1>, r<reg2>"
 993 {
 994   COMPAT_1 (OP_180 ());
 995 }
 996
 997
 998
 999 // SWITCH
1000 00000000010,RRRRR:I:::switch
1001 "switch r<reg1>"
1002 {
1003   COMPAT_1 (OP_40 ());
1004 }
1005
1006
1007
1008 // SXB
1009 00000000101,RRRRR:I:::sxb
1010 "sxb r<reg1>"
1011 {
1012   COMPAT_1 (OP_A0 ());
1013 }
1014
1015
1016
1017 // SXH
1018 00000000111,RRRRR:I:::sxh
1019 "sxh r<reg1>"
1020 {
1021   COMPAT_1 (OP_E0 ());
1022 }
1023
1024
1025
1026 // TRAP
1027 00000111111,iiiii + 0000000100000000:X:::trap
1028 "trap <vector>"
1029 {
1030   COMPAT_2 (OP_10007E0 ());
1031 }
1032
1033
1034
1035 // TST
1036 rrrrr,001011,RRRRR:I:::tst
1037 "tst r<reg1>, r<reg2>"
1038 {
1039   COMPAT_1 (OP_160 ());
1040 }
1041
1042
1043
1044 // TST1
1045 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1046 "tst1 <bit3>, <disp16>[r<reg1>]"
1047 {
1048   COMPAT_2 (OP_C7C0 ());
1049 }
1050
1051 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1052 "tst1 r<reg2>, [r<reg1>]"
1053 {
1054   COMPAT_2 (OP_E607E0 ());
1055 }
1056
1057
1058
1059 // XOR
1060 rrrrr,001001,RRRRR:I:::xor
1061 "xor r<reg1>, r<reg2>"
1062 {
1063   COMPAT_1 (OP_120 ());
1064 }
1065
1066
1067
1068 // XORI
1069 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1070 "xori <imm16>, r<reg1>, r<reg2>"
1071 {
1072   COMPAT_2 (OP_6A0 ());
1073 }
1074
1075
1076
1077 // ZXB
1078 00000000100,RRRRR:I:::zxb
1079 "zxb r<reg1>"
1080 {
1081   COMPAT_1 (OP_80 ());
1082 }
1083
1084
1085
1086 // ZXH
1087 00000000110,RRRRR:I:::zxh
1088 "zxh r<reg1>"
1089 {
1090   COMPAT_1 (OP_C0 ());
1091 }
1092
1093
1094
1095 // Special - breakpoint
1096 // 1111111111111111:Z:::breakpoint
1097 // {
1098 //   COMPAT_2 (OP_FFFF ());
1099 // }
1100
1101
1102 // start-sanitize-v850eq
1103 // DIVHN
1104 rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
1105 *v850eq
1106 "divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1107 {
1108   COMPAT_2 (OP_28007E0 ());
1109 }
1110
1111
1112
1113 // DIVHUN
1114 rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
1115 *v850eq
1116 "divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1117 {
1118   COMPAT_2 (OP_28207E0 ());
1119 }
1120
1121
1122
1123 // DIVN
1124 rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
1125 *v850eq
1126 "divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1127 {
1128   COMPAT_2 (OP_2C007E0 ());
1129 }
1130
1131
1132
1133 // DIVUN
1134 rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
1135 *v850eq
1136 "divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1137 {
1138   COMPAT_2 (OP_2C207E0 ());
1139 }
1140
1141
1142
1143 // SDIVHN
1144 rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
1145 *v850eq
1146 "sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1147 {
1148   COMPAT_2 (OP_18007E0 ());
1149 }
1150
1151
1152
1153 // SDIVHUN
1154 rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
1155 *v850eq
1156 "sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1157 {
1158   COMPAT_2 (OP_18207E0 ());
1159 }
1160
1161
1162
1163 // SDIVN
1164 rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
1165 *v850eq
1166 "sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1167 {
1168   COMPAT_2 (OP_1C007E0 ());
1169 }
1170
1171
1172
1173 // SDIVUN
1174 rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
1175 *v850eq
1176 "sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1177 {
1178   COMPAT_2 (OP_1C207E0 ());
1179 }
1180
1181
1182
1183 // PUSHML
1184 000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
1185 *v850eq
1186 "pushml <list18>"
1187 {
1188   COMPAT_2 (OP_107E0 ());
1189 }
1190
1191
1192
1193 // PUSHHML
1194 000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
1195 *v850eq
1196 "pushhml <list18>"
1197 {
1198   COMPAT_2 (OP_307E0 ());
1199 }
1200
1201
1202
1203 // POPML
1204 000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
1205 *v850eq
1206 "popml <list18>"
1207 {
1208   COMPAT_2 (OP_107F0 ());
1209 }
1210
1211
1212
1213 // POPMH
1214 000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
1215 *v850eq
1216 "popmh <list18>"
1217 {
1218   COMPAT_2 (OP_307F0 ());
1219 }
1220
1221
1222 // end-sanitize-v850eq