3 * z8k-dis.c (unparse_intstr): Fixed formatting. Change
4 disassembly of indirect register memory accesses to be same
5 format the assembler accepts.
9 * sh-opc.h: Fix encoding of least significant nibble of the
10 DSP single data transfer instructions.
12 * sh-dis.c (print_insn_shx): Fix decoding of As opcode in DSP
17 * cgen-asm.in: Fix compile time warning messages in generated
19 * cgen-dis.in: The same.
20 * cgen-ibld.in: The same.
21 * fr30-asm.c: Regenerate.
22 * fr30-desc.c: Regenerate.
23 * fr30-dis.c: Regenerate.
24 * fr30-ibld.c: Regenerate.
25 * fr30-opc.c: Regenerate.
26 * m32r-asm.c: Regenerate.
27 * m32r-desc.c: Regenerate.
28 * m32r-dis.c: Regenerate.
29 * m32r-ibld.c: Regenerate.
30 * m32r-opc.c: Regenerate.
31 * m32r-opinst.c Regenerate.
32 * openrisc-asm.c: Regenerate.
33 * openrisc-desc.c: Regenerate.
34 * openrisc-dis.c: Regenerate.
35 * openrisc-ibld.c: Regenerate.
36 * openrisc-opc.c: Regenerate.
37 * openrisc-opc.h: Regenerate.
38 * Makefile.in: Regenerate.
39 * po/POTFILES.in: Regenerate.
40 * po/opcodes.pot: Regenerate.
44 * arm-opc.h (arm_opcodes): Add cirrus insns.
46 * arm-dis.c (print_insn_arm): Add 'I' case.
50 * po/POTFILES.in: Regenerate.
51 * configure: Regenerate.
55 * Makefile.am (Makefile): Depend on bfd/configure.in.
57 * Makefile.in: Regenerate.
61 * cgen-ibld.in (insert_1): Switched bfd_get_bits and bfd_set_bits
62 calls to cgen_get_insn_value and cgen_put_insn_value calls.
63 (extract_1): Switched bfd_get_bits call to cgen_get_insn_value call.
67 * Makefile.am: Update dependencies with "make dep-am".
68 * Makefile.in: Regenerate.
72 * arc-dis.c: Formatting fixes.
73 (my_sprintf): Define using VPARAMS, VA_OPEN, VA_FIXEDARG, VA_CLOSE.
77 * arc-dis.c: Don't include <ctype.h>.
78 * openrisc-desc.c: Likewise.
79 * openrisc-ibld.c: Likewise.
83 * fr30-opc.c: Fix compile time warning messages.
84 * i370-opc.c: Fix compile time warning messages.
85 * i960-dis.c: Fix compile time warning messages.
86 * m32r-asm.c: Fix compile time warning messages.
87 * m32r-desc.c: Fix compile time warning messages.
88 * m32r-dis.c: Fix compile time warning messages.
89 * m32r-ibld.c: Fix compile time warning messages.
90 * m32r-opc.c: Fix compile time warning messages.
91 * m32r-opinst.c: Fix compile time warning messages.
92 * ns32k-dis.c: Fix compile time warning messages.
93 * openrisc-asm.c: Fix compile time warning messages.
94 * openrisc-desc.c: Fix compile time warning messages.
95 * openrisc-dis.c: Fix compile time warning messages.
96 * openrisc-ibld.c: Fix compile time warning messages.
97 * openrisc-opc.c: Fix compile time warning messages.
98 * pdp11-dis.c: Fix compile time warning messages.
99 * tic54x-dis.c: Fix compile time warning messages.
100 * v850-opc.c: Fix compile time warning messages.
101 * vax-dis.c: Fix compile time warning messages.
102 * w65-opc.h: Fix compile time warning messages.
103 * z8k-opc.h: Fix compile time warning messages.
104 * z8kgen.c: Fix compile time warning messages.
108 * arm-dis.c: Fix compile time warning messages.
109 * cgen-asm.c: Fix compile time warning messages.
110 * cgen-dis.c: Fix compile time warning messages.
111 * cris-dis.c: Fix compile time warning messages.
112 * d10v-dis.c: Fix compile time warning messages.
113 * fr30-asm.c: Fix compile time warning messages.
114 * fr30-desc.c: Fix compile time warning messages.
115 * fr30-dis.c: Fix compile time warning messages.
116 * fr30-ibld.c: Fix compile time warning messages.
120 * cgen-asm.c: Include "safe-ctype.h" instead of <ctype.h>.
121 (cgen_parse_keyword): Use ISALNUM instead of isalnum.
122 * cgen-opc.c: Include "safe-ctype.h" instead of <ctype.h>.
123 (cgen_keyword_lookup_name): Use ISALPHA/TOLOWER instead of
125 (cgen_keyword_add): Use ISALNUM instead of isalnum.
126 (hash_keyword_name): Use TOLOWER instead of tolower.
127 * fr30-asm.c: Include "safe-ctype.h" instead of <ctype.h>.
128 (parse_insn_normal): Use TOLOWER/ISSPACE instead of
130 (fr30_cgen_assemble_insn): Use ISSPACE instead of isspace.
131 * fr30-desc.c: Don't include <ctype.h>.
132 * fr30-ibld.c: Likewise.
133 * ia64-gen.c: Include "safe-ctype.h" instead of <ctype.h>.
134 (load_insn_classes, parse_resource_users, load_depfile): Use
135 ISSPACE instead of isspace.
136 * m32r-asm.c: Include "safe-ctype.h" instead of <ctype.h>.
137 (parse_insn_normal): Use TOLOWER/ISSPACE instead of
139 (m32r_cgen_assemble_insn): Use ISSPACE instead of isspace.
140 * m32r-desc.c: Don't include <ctype.h>.
141 * m32r-ibld.c: Likewise.
142 * openrisc-asm.c: Include "safe-ctype.h" instead of <ctype.h>.
143 (parse_insn_normal): Use TOLOWER/ISSPACE instead of
145 (openrisc_cgen_assemble_insn): Use ISSPACE instead of isspace.
149 * Makefile.am: Add rules and dependencies to create the s/390 opcode
150 table out of s390-opc.txt automatically.
151 * configure.in: Add BFD_CC_FOR_BUILD to allow CC_FOR_BUILD to be used.
152 * s390-mkopc.c (dumpTable): Change output to create a complete file.
153 * s390-opc.c: New improved opcode format macros and remove the
154 pregenerated opcode table.
155 * s390-opc.txt: Adapt to new improved opcode format macros.
159 * ppc-opc.c (VXA, VXA_MASK): Fix mask bits.
163 * i386-dis.c (grps): Don't print the implicit al/ax/eax register
164 for opcode 0xf6 or 0xf7 forms of mul, imul, div, idiv insns.
169 * mips-dis.c: Add support for bfd_mach_mipsisa32 and
170 bfd_mach_mipsisa64. Remove bfd_mach_mips32, bfd_mach_mips32_4k,
175 * tic54x-opc.c: Add default initializers to avoid warnings.
177 * arc-opc.c: Include "sysdep.h" to get stdio.h as include file.
178 * arc-ext.c: Likewise.
182 * ppc-opc.c (icbt): Order correctly.
187 * ppc-opc.c (DS): Add PPC_OPERAND_DS flag.
189 (insert_ds): Complain if not a multiple of 4.
191 (XSYNC_MASK): Define.
192 (powerpc_opcodes): Add "slbmte", "lwsync", "ptesync", "slbmfev",
193 "slbmfee". Modify "sync" to use XSYNC_MASK and LS.
197 * h8500-opc.h: Add default initializers to h8500_table to shut up
202 * tic54x-dis.c: Add unused attributes where needed.
204 * z8k-dis.c (output_instr): Add unused attribute.
206 * h8300-dis.c: Add missing prototypes.
207 (bfd_h8_disassemble): Make static.
209 * cris-dis.c: Add missing prototype.
210 * h8500-dis.c: Likewise.
211 * m68hc11-dis.c: Likewise.
212 * pj-dis.c: Likewise.
213 * tic54x-dis.c: Likewise.
214 * v850-dis.c: Likewise.
215 * vax-dis.c: Likewise.
216 * w65-dis.c: Likewise.
217 * z8k-dis.c: Likewise.
219 * d10v-dis.c: Add missing prototype.
220 (dis_long): Remove unused variable.
221 (dis_2_short): Likewise.
223 * sh-dis.c: Add missing prototypes.
224 * v850-opc.c: Likewise.
225 Add unused attributes where needed.
227 * ns32k-dis.c: Add missing prototypes.
228 (bit_extract_simple): Remove unused variable.
232 * opcodes/s390-opc.c: Add "low or high" and "not low or high"
233 branch instructions for gcc 3.0.
234 * opcodes/s390-opc.txt: Likewise.
238 * i960-dis.c: Add parameters for prototypes
239 (ctrl): Add unused attributes.
243 * mips-dis.c: Add missing prototypes.
244 * a29k-dis.c: Likewise.
245 * arc-dis.c: Likewise.
246 * ia64-opc.c: Likewise.
248 * s390-dis.c: Add missing prototypes.
249 (init_disasm): Remove unused attribute since the parameter is
254 * mips-opc.c (M1): Define. Reformatted Code.
255 (mips_builtin_opcodes): Added performance counter opcodes mfpc, mfps,
260 * mips-opc.c: R3900s can support all branch likely INSN_MACROs where
261 the corresponding non-likely insn is in MIPS I.
265 * mcore-dis.c: Fix formatting.
266 * mips-dis.c: Likewise.
267 * pj-dis.c: Likewise.
268 * z8k-dis.c: Likewise.
272 * cgen-ibld.in (extract_normal): Match type of VALUE and MASK
273 to *VALUEP. Regenerate all cgen files.
277 * mips-dis.c (print_insn_mips): Remove OPCODE_IS_MEMBER's gp32
279 * mips-opc.c (G6): Undefine.
280 (mips_builtin_opcodes): Remove gp32 entry for "move". Add macro
281 as the first "move" alternative.
285 * configure.in: Add -Wstrict-prototypes and -Wmissing-prototypes
287 * configure: Regenerate.
291 * ppc-opc.c: Revert 2001-08-08.
295 * dis-buf.c (generic_strcat_address): Add missing prototype.
296 #if 0 the functions as it is unused.
301 * ppc-opc.c: Include "bfd.h".
302 (powerpc_operands): Add new field for reloc type.
306 * mips-dis.c (print_insn_arg): Don't use software integer registers
307 for coprocessor registers.
308 (get_mips_isa): Removed.
309 (is_newabi): New function, checks if NewABI is used.
310 (_print_insn_mips): Get distinction between old ABI and new ABI right.
314 * z8kgen.c: Fixed indentation of opt[] array. Include stdio.h to
315 get stderr definition.
316 (internal, gas): Removed warnings.
317 (gas): Create a correct final entry for created array.
318 * z8k-opc.h: Recreated with new z8kgen.
322 * i386-dis.c: Fix formatting.
326 * i386-dis.c: Change formatting conventions for architecture
327 i386:intel to better match the format of various intel i386
328 assemblers, like nasm, tasm or masm.
332 * Makefile.am: Update dependencies with "make dep-am".
333 * Makefile.in: Regenerate
337 * alpha-dis.c: Fix formatting.
338 * cris-dis.c: Likewise.
339 * d10v-dis.c: Likewise.
340 * d30v-dis.c: Likewise.
341 * m10300-dis.c: Likewise.
342 * tic54x-dis.c: Likewise.
346 * m68k-dis.c: Fix formatting.
347 * pj-dis.c: Likewise.
348 * s390-dis.c: Likewise.
349 * z8k-dis.c: Likewise.
353 * mips-opc.c (mips_builtin_opcodes): Sort c.le.s and c.lt.s
354 into the rest of the surrounding definitions.
358 * i386-dis.c (grps): Print l or w suffix, and require mem modrm
359 for lgdt, lidt, sgdt, sidt.
363 * arm-dis.c (print_insn_arm): Use decimal for offsets in LDR/STR.
367 * cgen-asm.in: Include "xregex.h" always to enable the libiberty
369 (@arch@_cgen_build_insn_regex): New routine from Graydon.
370 (@arch@_cgen_assemble_insn): Add Graydon's code to use regex
371 to verify if it is worth parsing the insn as insn "x". Also update
372 error message when insn is not a recognized format of the insn vs
373 when the insn is completely unrecognized.
377 * cgen-dis.in (print_insn): Use cgen_get_insn_value instead of
379 * cgen-opc.c (cgen_get_insn_value, cgen_put_insn_value): Respect
380 non-zero CGEN_CPU_DESC->insn_chunk_bitsize.
384 * i386-dis.c (set_op): Handle 64 bit and 32 bit mode.
385 (OP_J): Use bfd_vma for mask to work properly with 64 bits.
386 (op_address,op_riprel): Use bfd_vma to handle 64 bits.
390 * Makefile.am (CPUDIR): Define.
391 (stamp-m32r): Update dependencies.
393 (stamp-openrisc): Ditto.
394 * Makefile.in: Regenerate.
398 * ppc-opc.c: Fix encoding of 'clf' instruction.
402 * cgen-ibld.in (insert_normal): Support CGEN_IFLD_SIGN_OPT.
406 * cgen-asm.c (cgen_parse_keyword): Allow any first character.
407 * cgen-opc.c (cgen_keyword_add): Ignore special first
408 character when building nonalpha_chars field.
412 * m88k-dis.c: Format to conform to GNU coding standards.
416 * disassemble.c (disassembler_usage): Add unused attribute.
420 * mips-opc.c: Move prefx to start of the table.
424 * arc-opc.c (insert_st_syntax): Fix over-optimisation of ST
429 * m68k-opc.c: Add wdebug instruction.
433 * m10300-opc.c (mn10300_opcodes): Change opcode for AM33 subc.
437 * cgen-asm.c (cgen_parse_keyword): When looking for the
438 boundaries of a keyword, allow any special characters
439 that are actually in one of the allowed keyword.
440 * cgen-opc.c (cgen_keyword_add): Add any special characters
441 to the nonalpha_chars field.
445 * s390-opc.c: Add lgh instruction.
446 * s390-opc.txt: Likewise.
450 * i386-dis.c: Group function prototypes in one place.
451 (FLOATCODE): Redefine as 1.
452 (USE_GROUPS): Redefine as 2.
453 (USE_PREFIX_USER_TABLE): Redefine as 3.
454 (X86_64_SPECIAL): Define as 4.
455 (GRP1b..GRPAMD): Move USE_GROUPS to bytecode1, index to bytecode2.
456 (PREGRP0..PREGRP26): Similarly with USE_PREFIX_USER_TABLE.
457 (dis386_att, dis386_intel, disx86_64_att, disx86_64_intel): Delete.
458 (dis386): New table combining above four tables.
459 (dis386_twobyte_att, dis386_twobyte_intel): Delete.
460 (dis386_twobyte): New table combining above two tables.
461 (x86_64_table): New table to handle x86_64.
463 (float_mem_att, float_mem_intel): Delet.
464 (float_mem): New table combining above two tables.
465 (print_insn_i386): Modify for above.
467 (putop): Handle '{', '|' and '}' to select alternative mnemonics.
468 Return 0 on success, 1 if no valid alternative.
469 (putop <case 'F'>, <case 'H'>): Print nothing for intel_syntax.
470 (putop <case 'T'>): Move to case 'U', and share case 'Q' code.
471 (putop <case 'I'>): Move to case 'T', and share case 'P' code.
472 (OP_REG <case rAX_reg .. rDI_reg>): Handle as for eAX_reg .. eDI_reg
474 (OP_I <case q_mode>): Handle as for v_mode if not 64-bit mode.
475 (OP_I64): If not 64-bit mode, call OP_I.
476 OP_OFF64): If not 64-bit mode, call OP_OFF.
477 (OP_ST, OP_STi, OP_SEG, OP_DIR, OP_OFF, OP_OFF64, OP_MMX): Rename
478 'ignore'/'ignored' to 'bytemode'.
482 * configure.in: Sort 'ta' case statement.
483 * configure: Regenerate.
485 * i386-dis.c (dis386_att): Add 'H' to conditional branch and
487 (disx86_64_att): Likewise.
488 (dis386_twobyte_att): Likewise.
489 (print_insn_i386): Don't print branch hints as a prefix.
490 (putop): 'H' macro prints branch hints.
491 (get64): Kill compile warnings.
495 * sh-opc.h (sh_table): Don't use empty initializers.
499 * z8k-dis.c: Fix formatting.
500 (unpack_instr): Remove unused cases in switch statement. Add
501 safety abort() in default case.
502 (unparse_instr): Add safety abort() in default case.
506 * m68k-dis.c (print_insn_m68k): Fix typo.
507 * m68k-opc.c (m68k_opcodes): Correct allowed operands for
508 mcf (ColdFire) div, rem and moveb instructions.
512 * i386-dis.c (cond_jump_flag, loop_jcxz_flag): Define.
513 (cond_jump_mode, loop_jcxz_mode): Define.
514 (dis386_att): Add cond_jump_flag and loop_jcxz_flag as
515 appropriate, and 'F' suffix to loop insns.
516 (disx86_64_att): Likewise.
517 (dis386_twobyte_att): Likewise.
518 (print_insn_i386): Don't output addr prefix for loop, jcxz insns.
519 Output data size prefix for long conditional jumps. Output cs and
521 (putop): Handle 'F', and mark PREFIX_ADDR used for case 'E'.
522 (OP_J): Don't make PREFIX_DATA used.
526 * sh-opc.h (sh_table): Complete last element entry to avoid
531 * mips-dis.c (mips_isa_type): Add MIPS r12k support.
535 * arc-opc.c: Whitespace changes.
539 * cris-opc.c (cris_spec_regs): Add missing initializer field for
544 * cgen-dis.in (extract_normal): Complete support for min<base case.
548 * mips-dis.c (INSNLEN): Rename MAXLEN.
549 (std_reg_names): Replace by mips32_reg_names and mips64_reg_names.
550 (print_insn_arg): Remove $ prefix of register names.
551 (set_mips_isa_type): Remove.
552 (mips_isa_type): New function.
553 (get_mips_isa): New Function.
554 (print_insn_mips): Rename _print_insn_mips.
555 (_print_insn_mips): New function, contains code which was
556 duplicated in print_insn_big_mips and print_insn_little_mips.
557 (print_insn_big_mips): Moved code to _print_insn_mips.
558 (print_insn_little_mips): Likewise.
559 (print_mips16_insn_arg): Remove $ prefix of register names.
560 Print error message before abort.
564 * ppc-opc.c (powerpc_opcodes): Fixed extended opcode field of
565 simplified mnemonics used for setting PPC750-specific special
570 * i386-dis.c (print_insn_i386): Always set `mod', `reg' and
575 * arc-opc.c (arc_reg_names): Correct attribute for lp_count
576 register to r/w. Formatting fixes throughout file.
580 * i386-dis.c (prefix_user_table): Correct movq2dq, movdq2q, and
582 (twobyte_has_modrm): Update table.
583 (need_modrm): Give it file scope.
584 (MODRM_CHECK): Define.
585 (dofloat): Use MODRM_CHECK.
592 * cgen-dis.in (default_print_insn): Tolerate min<base instructions
593 even at end of a section.
594 * cgen-ibld.in (extract_normal): Tolerate min!=base!=max instructions
595 by ignoring precariously-unpacked insn_value in favor of raw buffer.
599 * disassemble.c (disassembler_usage): Remove unused attribute.
603 * m32r-dis.c, -asm.c, -ibld.c: Regenerated with disassembler fixes.
607 * cgen-dis.in (print_insn): Remove call to read_insn. Instead,
608 assume incoming buffer already has the base insn loaded. Handle
609 smaller-than-base instructions for variable-length case.
613 * i386-dis.c (Ev, Ed): Remove duplicate define.
616 (OP_XS): New function.
617 (dis386_twobyte_att): Correct pinsrw, pextrw, pmovmskb, and
619 (dis386_twobyte_intel): Likewise.
620 (prefix_user_table): Use MS for maskmovq operand.
624 * Makefile.am: Add OpenRISC target.
625 * Makefile.in: Regenerated.
627 * disassemble.c (disassembler): Recognize the OpenRISC disassembly.
629 * configure.in (bfd_openrisc_arch): Add target.
630 * configure: Regenerated.
632 * openrisc-asm.c: New file.
633 * openrisc-desc.c: Likewise.
634 * openrisc-desc.h: Likewise.
635 * openrisc-dis.c: Likewise.
636 * openrisc-ibld.c: Likewise.
637 * openrisc-opc.c: Likewise.
638 * openrisc-opc.h: Likewise.
642 * z8k-dis.c: add names of control registers (ctrl_names);
643 (seg_length): provides instruction length fixup for segmented
644 mode; (unpack_instr): correctly handle ARG_DISP16, ARG_DISP12,
645 CLASS_0DISP7, CLASS_1DISP7, CLASS_DISP8 and CLASS_PR cases;
646 (unparse_intr): handle CLASS_PR, print addresses without '#'
647 * z8k-opc.h: re-created with new z8kgen
648 * z8kgen.c: merged in fixes which were in existing z8k-opc.h; new
649 entries for ldctl/ldctlb instruction
653 * i386-dis.c: Add ffreep instruction.
657 * ppc-opc.c (insert_mbe): Shift mask initializer as long.
661 * i386-dis.c (PREGRP25): Define.
662 (dis386_twobyte_att): Use here in place of "movntq" entry.
663 (dis386_twobyte_intel): Likewise.
664 (prefix_user_table): Add PREGRP25 entry for "movntq" and "movntdq".
666 (dis386_twobyte_att): Use here.
667 (dis386_twobyte_intel): Likewise.
668 (prefix_user_table): Add PREGRP26 entry for "punpcklqdq".
669 (prefix_user_table <maskmovdqu>): XM operand, not MX.
670 (prefix_user_table): Cosmetic changes to "bad" entries.
674 * mips-opc.c: Remove extraneous whitespace.
675 * mips-dis.c: Remove extraneous whitespace.
679 * cgen-asm.in (@arch@_cgen_assemble_insn): Move tmp_errmsg
680 declaration inside CGEN_VERBOSE_ASSEMBLER_ERRORS conditional.
681 * cgen-ibld.in (put_insn_int_value): Mark cd parameter as unused
682 to allay a compiler warning.
686 * i386-dis.c (dis386_twobyte_att): Add entries for paddq, psubq.
687 (dis386_twobyte_intel): Likewise.
688 (twobyte_has_modrm): Set entry for paddq, psubq.
692 * cgen-dis.in (print_insn_@arch@): Add support for target machine
693 determination via CGEN_COMPUTE_MACH.
694 * fr30-desc.c: Regenerate.
695 * fr30-dis.c: Regenerate.
696 * fr30-opc.h: Regenerate.
697 * m32r-desc.c: Regenerate.
698 * m32r-dis.c: Regenerate.
699 * m32r-opc.h: Regenerate.
700 * m32r-opinst.c: Regenerate.
704 * configure.in: Remove the redundent AC_ARG_PROGRAM.
705 * configure: Rebuild.
709 * ia64-gen.c (fetch_insn_class): If xsect, then ignore comment and
710 notestr if larger than xsect.
711 (in_class): Handle format M5.
712 * ia64-asmtab.c: Regnerate.
716 * vax-dis.c (print_insn_vax): Only fetch two bytes if the info buffer
717 has more than one byte left to read.
721 * s390-opc.c: Add new opcodes. Smooth out formatting.
722 * s390-opc.txt: Add new opcodes.
726 * arm-dis.c (print_insn_thumb): Compute destination address
727 of BLX(1) instruction by taking bit 1 from PC and not from bit
732 * m68k-dis.c (print_insn_m68k): Recognize Coldfire CPUs
733 so command line switches will work.
737 * fr30-asm.c: Regenerate.
738 * fr30-desc.c: Regenerate.
739 * fr30-desc.h: Regenerate.
740 * fr30-dis.c: Regenerate.
741 * fr30-ibld.c: Regenerate.
742 * fr30-opc.c: Regenerate.
743 * fr30-opc.h: Regenerate.
744 * m32r-asm.c: Regenerate.
745 * m32r-desc.c: Regenerate.
746 * m32r-desc.h: Regenerate.
747 * m32r-dis.c: Regenerate.
748 * m32r-ibld.c: Regenerate.
749 * m32r-opc.c: Regenerate.
750 * m32r-opc.h: Regenerate.
751 * m32r-opinst.c: Regenerate.
755 * m68k-opc.c: fix cpushl according to Motorola. Enable
756 bunch of instructions for Coldfire 5407 and add all new.
760 * configure.in (BFD_VERSION): Do without grep.
761 * configure: Regenerate.
762 * Makefile.am: Run "make dep-am".
763 * Makefile.in: Regenerate.
767 * ia64-opc-a.c: Add missing pseudo-ops for "cmp" and "cmp4".
768 * ia64-asmtab.c: Regenerate.
772 * ia64-opc-d.c (ia64_opcodes_d): Break the "add" pattern into two
773 separate variants: one for IMM22 and the other for IMM14.
774 * ia64-asmtab.c: Regenerate.
778 * cgen-opc.c (cgen_get_insn_value): Add missing `return'.
782 * Makefile.am (ia64-ic.tbl): Remove the target.
783 (ia64-raw.tbl): Likewise.
784 (ia64-waw.tbl): Likewise.
785 (ia64-war.tbl): Likewise.
786 (ia64-asmtab.c): Generate it in the source directory.
787 * Makefile.in: Regenerated.
791 * Makefile.am: Add PDP-11 target.
792 * configure.in: Likewise.
793 * disassemble.c: Likewise.
794 * pdp11-dis.c: New file.
795 * pdp11-opc.c: New file.
799 * ia64-ic.tbl: Update from Intel. Add setf to fr-writers.
800 * ia64-asmtab.c: Regenerate.
804 * i386-dis.c (prefix_user_t): Add 'Y' to SSE ineger converison
810 * mips-dis.c (print_insn_arg): Use top four bits of the address of
811 the following instruction not of the jump itself for the jump
813 (print_mips16_insn_arg): Likewise.
817 * Makefile.am (stamp-lib): ranlib the libopcodes.a in the build
819 * Makefile.in: Regenerate.
823 * Makefile.am: Add linux target for S/390.
824 * Makefile.in: Likewise.
825 * configure.in: Likewise.
826 * disassemble.c: Likewise.
827 * s390-dis.c: New file.
828 * s390-mkopc.c: New file.
829 * s390-opc.c: New file.
830 * s390-opc.txt: New file.
834 * ia64-asmtab.c: Revert 2000-12-16 change.
838 * fr30-desc.h: Regenerate with CGEN_MAX_SYNTAX_ELEMENTS.
839 * m32r-desc.h: Regenerate.
843 * i386-dis.c (dis386_att, grps): Use 'T' for push/pop
844 (putop): Handle 'T', alphabetize order, fix 'I' handling in Intel syntax
848 * hppa-dis.c (print_insn_hppa): Handle '>' and '<' arg types.
852 * disassemble.c: Remove spurious white space.
856 * i386-dis.c (dis386_att, disx86_64_att): Fix ret, lret and iret
861 * configure.in: Add arc-ext.lo for bfd_arc_arch selection.
862 * Makefile.am (C_FILES): Add arc-ext.c.
863 (ALL_MACHINES) Add arc-ext.lo.
864 (INCLUDES) Add opcode directory to list.
865 New dependency entry for arc-ext.lo.
866 * disassemble.c (disassembler): Correct call to
867 arc_get_disassembler.
868 * arc-opc.c: New update for ARC, including full base
869 instructions for ARC variants.
870 * arc-dis.h, arc-dis.c: New update for ARC, including
871 extensibility functionality.
872 * arc-ext.h, arc-ext.c: New files for handling extensibility.
876 * i386-dis.c (PREGRP15 - PREGRP24): New.
877 (dis386_twobyt): Add SSE2 instructions.
878 (twobyte_uses_SSE_prefix: Rename from ... ; add new SSE instructions.
879 (twobyte_uses_f3_prefix): ... this one.
880 (grps): Add SSE instructions.
881 (prefix_user_table): Add two new slots; add SSE2 instructions.
882 (print_insn_i386): Rename uses_f3_prefix to uses_SSE_prefix;
883 Handle the REPNZ and Data16 prefixes as well; do proper lookup
884 to prefix_user_table.
885 (OP_E): Accept mfence and lfence as well.
886 (OP_MMX): Data16 prefix turns MMX to SSE; support REX extensions.
887 (OP_XMM): Support REX extensions.
893 * arm-dis.c (print_insn): Set pc to zero for instructions with
894 a reloc associated with them.
898 * cgen-asm.in (parse_insn_normal): Changed syn to be
899 CGEN_SYNTAX_CHAR_TYPE. Changed all references to *syn
900 as character to use CGEN_SYNTAX_CHAR macro and all comparisons
901 to '\0' to use 0 instead.
902 * cgen-dis.in (print_insn_normal): Ditto.
903 * cgen-ibld.in (insert_insn_normal, extract_insn_normal): Ditto.
907 * i386-dis.c: Add x86_64 support.
908 (rex): New static variable.
909 (REX_MODE64, REX_EXTX, REX_EXTY, REX_EXTZ): New constants.
910 (USED_REX): New macro.
911 (Ev, Ed, Rm, Iq, Iv64, Cm, Dm, Rm*, Ob64, Ov64): New macros.
912 (OP_I64, OP_OFF64, OP_IMREG): New functions.
913 (OP_REG, OP_OFF): Declare.
914 (get64, get32, get32s): New functions.
915 (r??_reg): New constants.
916 (dis386_att): Change templates of instruction implicitly promoted
917 to 64bit; change e?? to RMe?? for unwind RM byte instructions.
919 (dis386_intel): Likewise.
920 (dixx86_64_att): New table based on dis386_att.
921 (dixx86_64_intel): New table based on dis386_intel.
922 (names64, names8rex): New global variable.
923 (names32, names16): Add extended registers.
924 (prefix_user_t): Recognize rex prefixes.
925 (prefix_name): Print REX prefixes nicely.
926 (op_riprel): New global variable.
927 (start_pc): Set type to bfd_vma.
928 (print_insn_i386): Detect the 64bit mode and use proper table;
929 move ckprefix after initializing the buffer; output unused rex prefixes;
930 output information about target of RIP relative addresses.
931 (putop): Support 'O' and 'I'. Update handling of "P', 'Q', 'R' and 'S';
932 (print_operand_value): New function.
933 (OP_E, OP_G, OP_REG, OP_I, OP_J, OP_DIR, OP_OFF, OP_D): Add support for
934 REX prefix and new modes.
935 (get64, get32s): New.
936 (get32): Return bfd_signed_vma type.
937 (set_op): Initialize the op_riprel.
938 * disassemble.c (disassembler): Recognize the x86-64 disassembly.
942 cgen-dis.in (read_insn): Use bfd_get_bits()
946 * cgen-dis.c (hash_insn_array): Use bfd_put_bits().
947 (hash_insn_list): Likewise
948 * cgen-ibld.in (insert_1): Use bfd_put_bits() and bfd_get_bits().
949 (extract_1): Use bfd_get_bits().
950 (extract_normal): Apply sign extension to both extraction
952 * cgen-opc.c (cgen_get_insn_value): Use bfd_get_bits()
953 (cgen_put_insn_value): Use bfd_put_bits()
957 * cgen-asm.in (parse_insn_normal): Print better error message for
958 instructions with missing operands.
962 * cgen-opc.c: Include alloca.h if HAVE_ALLOCA_H is defined.
966 * Makefile.in: Regenerate.
967 * aclocal.m4: Regenerate.
968 * config.in: Regenerate.
969 * configure.in: Add spacing.
970 * configure: Regenerate.
971 * ia64-asmtab.c: Regenerate.
972 * po/opcodes.pot: Regenerate.
976 * cgen-asm.in (@arch@_cgen_assemble_insn): Prefer printing insert-time
977 error messages over later parse-time ones.
981 * ia64-dis.c (print_insn_ia64): Cast away const on ia64_free_opcode
983 * ia64-gen.c (insert_deplist): Cast sizeof result to int.
984 (print_dependency_table): Print NULL if semantics field not set.
985 (insert_opcode_dependencies): Mark cmp parameter as unused.
986 (print_main_table): Use fprintf_vma to print long long fields.
987 (main): Mark argv paramter as unused. Convert to old style definition.
988 * ia64-opc.c (ia64_find_dependency): Cast sizeof result to int.
989 * ia64-asmtab.c: Regnerate.
993 * m32r-dis.c (print_insn): Prevent re-read of instruction from
996 * fr30-dis.c: Regenerate.
1000 * configure.in: Add arc-ext.lo for bfd_arc_arch selection.
1001 * Makefile.am (C_FILES): Add arc-ext.c.
1002 (ALL_MACHINES) Add arc-ext.lo.
1003 (INCLUDES) Add opcode directory to list.
1004 New dependency entry for arc-ext.lo.
1005 * disassemble.c (disassembler): Correct call to
1006 arc_get_disassembler.
1007 * arc-opc.c: New update for ARC, including full base
1008 instructions for ARC variants.
1009 * arc-dis.h, arc-dis.c: New update for ARC, including
1010 extensibility functionality.
1011 * arc-ext.h, arc-ext.c: New files for handling extensibility.
1015 * mips-opc.c (mips_builtin_opcodes): Use the WR_HILO, RD_HILO,
1016 MOD_HILO, and MOD_LO macros.
1018 * mips-opc.c (M1, M2): Delete.
1019 (mips_builtin_opcodes): Remove all uses of M1.
1021 * mips-opc.c (mips_builtin_opcodes): Make the dmfc2 and dmtc2
1022 instructions take "G" format second operands and use the
1024 There are mfc3 and mtc3 opcodes, so add dmfc3 and dmtc3 opcodes to
1026 Delete "sel" code operands from mfc1 and mtc1.
1027 Add MIPS64 opcode changes (dclo, dclz), and "sel" code variants
1033 * mips-opc.c (mips_builtin_opcodes): Finish additions
1034 for MIPS32 support, and clean up existing entries for
1035 aesthetics, consistency with the MIPS32 ISA, and
1036 with consistency the rest of the table.
1040 * mips16-opc.c (mips16_opcodes): Add initialiser for membership
1045 mips-dis.c (print_insn_arg): Handle new 'U' and 'J' argument
1046 specifiers. Update 'B' for new constant names, and remove
1048 mips-opc.c (mips_builtin_opcodes): Place "pref" and "ssnop"
1049 near the top of the array, so they are disassembled properly.
1050 Enable "ssnop" for MIPS32. Add "break" variant with 20 bit
1051 code for MIPS32. Update "clo" and "clz" to use 'U' operand
1052 specifier. Add 'H' format specifier variants for "mfc1,"
1053 "mfc2," "mfc3," "mtc1," "mtc2," and "mtc3" for MIPS32. Update
1054 MIPS32 "sdbbp" to use 'B' operand specifier. Add MIPS32
1055 "wait" variant which uses 'J' operand specifier.
1057 * mips-dis.c (set_mips_isa_type): Update to use
1058 CPU_UNKNOWN and ISA_* constants. Add bfd_mach_mips32 case.
1059 Replace bfd_mach_mips4K with bfd_mach_mips32_4k case.
1060 * mips-opc.c (I32): New constant for instructions added in
1063 (mips_builtin_opcodes) Replace all uses of P4 with I32.
1065 * mips-dis.c (set_mips_isa_type): Add cases for
1066 bfd_mach_mips5 and bfd_mach_mips64.
1067 * mips-opc.c (I64): New definitions.
1069 * mips-dis.c (set_mips_isa_type): Add case for
1074 * sh-dis.c (print_insn_ddt): Make insn_x, insn_y unsigned.
1075 (print_insn_ppi): Make nib1, nib2, nib3 unsigned.
1076 Initialize variable dc to NULL.
1077 (print_insn_shx): Remove unused label d_reg_n.
1081 * arm-opc.h: Add new opcode formatting parameter 'B'.
1082 (arm_opcodes): Add XScale, v5, and v5te instructions.
1083 (thumb_opcodes): Add v5t instructions.
1085 * arm-dis.c (print_insn_arm): Handle new 'B' format
1087 (print_insn_thumb): Decode BLX(1) instruction.
1091 * mips-opc.c: Fix file header comment.
1095 * cris-dis.c (cris_get_disassembler): If abfd is NULL, return
1096 print_insn_cris_with_register_prefix.
1100 * sh-opc.h: The operand of `mov.w r0, (<disp>,GBR)' is IMM1, not 0.
1104 * cgen-dis.in (print_insn): All insns which can fit into insn_value
1105 must be loaded there in their entirety.
1109 * sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs.
1110 (compute_arch_mask): Add v8plusb and v9b machines.
1111 (print_insn_sparc): siam mode decoding, accept ASRs up to 25.
1112 * sparc-opc.c: Support for Cheetah instruction set.
1113 (prefetch_table): Add #invalidate.
1117 * mcore-dis.c (imsk): Change mask for OC to 0xFE00.
1121 * fr30-desc.h: Regenerate.
1122 * m32r-desc.h: Regenerate.
1123 * m32r-ibld.c: Regenerate.
1127 * ia64-ic.tbl: Update from Intel.
1128 * ia64-asmtab.c: Regenerate.
1132 * ia64-gen.c: Convert C++-style comments to C-style comments.
1133 * tic54x-dis.c: Likewise.
1137 Changes to add dollar prefix to registers for files where user symbols
1138 don't have a leading underscore. Fix formatting.
1139 * cris-dis.c (REGISTER_PREFIX_CHAR): New.
1140 (format_reg): Add parameter with_reg_prefix. All callers changed.
1141 (print_with_operands): Ditto.
1142 (print_insn_cris_generic): Renamed from print_insn_cris, add
1143 parameter with_reg_prefix.
1144 (print_insn_cris_with_register_prefix,
1145 print_insn_cris_without_register_prefix, cris_get_disassembler):
1147 * disassemble.c (disassembler) [ARCH_cris]: Call cris_get_disassembler.
1151 * ia64-opc-f.c (ia64_opcodes_f): Add fpcmp pseudo-ops for
1152 gt, ge, ngt, and nge.
1153 * ia64-asmtab.c: Regenerate.
1155 * ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change.
1156 * ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP.
1157 (lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62".
1158 * ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update.
1159 * ia64-asmtab.c: Regnerate.
1163 * mips-opc.c (mips_builtin_opcodes): Support cache instruction on 4K cores.
1164 Add mfc0 and mtc0 with sub-selection values.
1165 Add clo and clz opcodes.
1166 Add msub and msubu instructions for MIPS32.
1167 Add madd/maddu aliases for mad/madu for MIPS32.
1168 Support wait, deret, eret, movn, pref for MIPS32.
1169 Support tlbp, tlbr, tlbwi, tlbwr.
1172 * mips-dis.c (print_insn_arg): Print sdbbp 'm' args.
1173 (print_insn_arg): Handle 'H' args.
1174 (set_mips_isa_type): Recognize 4K.
1175 Use CPU_* defines instead of hardcoded numbers.
1179 * d30v-opc.c (d30v_operand_t): New operand type Rb2.
1180 (d30v_format_tab): Use Rb2 for modinc and moddec.
1184 * d30v-opc.c (d30v_format_tab): Use format Ra for
1189 * configure: Rebuilt with new libtool.m4.
1193 * configure: Regenerate.
1194 * po/opcodes.pot: Regenerate.
1198 * acinclude.m4: Include libtool and gettext macros from the
1200 * aclocal.m4, configure: Rebuilt.
1204 * tic80-dis.c: Fix formatting.
1208 * w65-dis.c: Fix formatting.
1212 * ppc-opc.c: Add XTLB macro for a few PPC 4xx extended mnemonics.
1213 (powerpc_opcodes): Add table entries for PPC 405 instructions.
1214 Changed rfci, icbt, mfdcr, dccci, mtdcr, iccci from PPC to PPC403
1215 instructions. Added extended mnemonic mftbl as defined in the
1216 405GP manual for all PPCs.
1220 * ia64-dis.c (print_insn_ia64): Add failed label after ia64_free_opcode
1221 call. Change last goto to use failed instead of done.
1225 * cgen-ibld.in (cgen_put_insn_int_value): New function.
1226 (insert_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P.
1227 (insert_insn_normal): Use cgen_put_insn_int_value with CGEN_INT_INSN_P.
1228 (extract_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P.
1229 * cgen-dis.in (read_insn): New static function.
1230 (print_insn): Use read_insn to read the insn into the buffer and set
1232 (print_insn): in CGEN_INT_INSN_P, make sure that the entire insn is
1234 * fr30-asm.c: Regenerated.
1235 * fr30-desc.c: Regenerated.
1236 * fr30-desc.h: Regenerated.
1237 * fr30-dis.c: Regenerated.
1238 * fr30-ibld.c: Regenerated.
1239 * fr30-opc.c: Regenerated.
1240 * fr30-opc.h: Regenerated.
1241 * m32r-asm.c: Regenerated.
1242 * m32r-desc.c: Regenerated.
1243 * m32r-desc.h: Regenerated.
1244 * m32r-dis.c: Regenerated.
1245 * m32r-ibld.c: Regenerated.
1246 * m32r-opc.c: Regenerated.
1250 * tic30-dis.c: Fix formatting.
1254 * sh-dis.c: Fix formatting.
1258 * ppc-opc.c (powerpc_opcodes): Add rfid, mtsrd, mtsrdin, mtmsrd.
1262 * z8k-dis.c: Fix formatting.
1266 * ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete
1267 break, mov-immediate, nop.
1268 * ia64-opc-f.c: Delete fpsub instructions.
1269 * ia64-opc-m.c: Add POSTINC to all instructions with postincrement
1270 address operand. Rewrite using macros to avoid long lines.
1271 * ia64-opc.h (POSTINC): Define.
1272 * ia64-asmtab.c: Regenerate.
1276 * ia64-ic.tbl: Add missing entries.
1280 * i860-dis.c (print_br_address): Change third argument from int
1285 * ia64-dis.c (print_insn_ia64): Get byte skip count correct
1286 for MLI templates. Handle IA64_OPND_TGT64.
1290 * cgen-dis.in, cgen-asm.in, cgen-ibld.in: New files.
1291 * cgen.sh: Likewise.
1295 * ia64-dis.c (print_insn_ia64): Call ia64_free_opcode at end.
1299 * avr-dis.c (avr_operand): Use PARAMS macro in declaration.
1300 Change return type from void to int. Check the combination
1301 of operands, return 1 if valid. Fix to avoid BUF overflow.
1302 Report undefined combinations of operands in COMMENT.
1303 Report internal errors to stderr. Output the adiw/sbiw
1304 constant operand in both decimal and hex.
1305 (print_insn_avr): Disassemble ldd/std with displacement of 0
1306 as ld/st. Check avr_operand () return value, handle invalid
1307 combinations of operands like unknown opcodes.
1311 * Makefile.am (CGEN, CGENDEPS, CGENDIR, CGENFLAGS): New.
1312 (run-cgen, stamp-m32r, stamp-fr30): New targets.
1313 * Makefile.in: Regenerate.
1314 * configure.in: Add --enable-cgen-maint option.
1315 * configure: Regenerate.
1319 * cgen-opc.c (cgen_hw_lookup_by_name): 'i' is now unsigned.
1320 (cgen_hw_lookup_by_num): Ditto.
1321 (cgen_operand_lookup_by_name): Ditto.
1322 (print_address): Ditto.
1323 (print_keyword): Ditto.
1324 * cgen-dis.c (hash_insn_array): Mark unused parameters with
1326 * cgen-asm.c (hash_insn_array): Mark unused parameters with
1328 (cgen_parse_keyword): Ditto.
1332 * i860-dis.c: New file.
1333 (print_insn_i860): New function.
1334 (print_br_address): New function.
1335 (sign_extend): New function.
1336 (BITWISE_OP): New macro.
1337 (I860_REG_PREFIX): New macro.
1338 (grnames, frnames, crnames): New structures.
1340 * disassemble.c (ARCH_i860): Define.
1341 (disassembler): Add check for bfd_arch_i860 to set disassemble
1342 function to print_insn_i860.
1344 * Makefile.in (CFILES): Added i860-dis.c.
1345 (ALL_MACHINES): Added i860-dis.lo.
1346 (i860-dis.lo): New dependences.
1348 * configure.in: New bits for bfd_i860_arch.
1350 * configure: Regenerated.
1354 * Makefile.am (CFILES): Add cris-dis.c and cris-opc.c.
1355 (ALL_MACHINES): Add cris-dis.lo and cris-opc.lo.
1356 (cris-dis.lo, cris-opc.lo): New rules.
1357 * Makefile.in: Rebuild.
1358 * configure.in (bfd_cris_arch): New target.
1359 * configure: Rebuild.
1360 * disassemble.c (ARCH_cris): Define.
1361 (disassembler): Support ARCH_cris.
1362 * cris-dis.c, cris-opc.c: New files.
1363 * po/POTFILES.in, po/opcodes.pot: Regenerate.
1367 * sparc-opc.c (sparc_opcodes): popc has 0 in rs1, not rs2.
1372 * ppc-opc.c (powerpc_opcodes): Correct suffix for vslw.
1377 * hppa-dis.c (fput_reg, fput_fp_reg, fput_fp_reg_r, fput_creg,
1378 fput_const, extract_3, extract_5_load, extract_5_store,
1379 extract_5r_store, extract_5R_store, extract_10U_store,
1380 extract_5Q_store, extract_11, extract_14, extract_16, extract_21,
1381 extract_12, extract_17, extract_22): Prototype.
1382 (print_insn_hppa): Rename inner block opcode -> opc to avoid
1383 shadowing outer block.
1392 * arm-dis.c (print_insn_arm): Output combinations of PSR flags.
1396 * avr-dis.c (avr_operand): Change _ () to _() around all strings
1397 marked for translation (exception from the usual coding style).
1398 (print_insn_avr): Initialize insn2 to avoid warnings.
1402 * h8300-dis.c (bfd_h8_disassemble): Improve readability.
1403 * h8500-dis.c: Fix formatting.
1407 * Makefile.am (DEP): Fix 2000-06-22. grep after running dep.sed
1408 (CLEANFILES): Add DEPA.
1409 * Makefile.in: Regenerate.
1413 * arm-dis.c (regnames): Add an additional register set to match
1414 the set used by GCC. Make it the default.
1418 * Makefile.am (DEP): grep for leading `/' in DEP1, and fail if we
1420 * Makefile.in: Regenerate.
1424 * Makefile.am: Rebuild dependency.
1425 * Makefile.in: Rebuild.
1429 * Makefile.in, configure: regenerate
1430 * disassemble.c (disassembler): Recognize ARCH_m68hc12,
1432 * m68hc11-dis.c (read_memory, print_insn, print_insn_m68hc12):
1434 * configure.in: Recognize m68hc12 and m68hc11.
1435 * m68hc11-dis.c, m68hc11-opc.c: New files for support of m68hc1x
1436 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
1437 and opcode generation for m68hc11 and m68hc12.
1441 * disassemble.c (disassembler): Refer to the PowerPC 620 using
1442 bfd_mach_ppc_620 instead of 620.
1446 * h8300-dis.c: Fix formatting.
1447 (bfd_h8_disassemble): Distinguish adds/subs, inc/dec.[wl]
1452 * avr-dis.c (avr_operand): Bugfix for jmp/call address.
1456 * avr-dis.c: completely rewritten.
1460 * h8300-dis.c: Follow the GNU coding style.
1461 (bfd_h8_disassemble) Fix a typo.
1465 * h8300-dis.c (bfd_h8_disassemble_init): Fix a typo.
1466 (bfd_h8_disassemble): Distinguish the operand size of inc/dev.[wl]
1467 correctly. Fix a typo.
1471 * opintl.h (_(String)): Explain why dgettext is used instead of
1476 * opintl.h (gettext, dgettext, dcgettext, textdomain,
1477 bindtextdomain): Replace defines with those from intl/libgettext.h
1478 to quieten gcc warnings.
1482 * Makefile.am: Update dependencies with "make dep-am"
1483 * Makefile.in: Regenerate.
1487 * m10300-dis.c (disassemble): Don't assume 32-bit longs when
1488 sign-extending operands.
1492 * d10v-opc.c (d10v_opcodes): add ALONE tag to all short branches
1497 * Makefile.am (LIBIBERTY): Define.
1501 * mips-dis.c (REGISTER_NAMES): Rename to STD_REGISTER_NAMES.
1502 (STD_REGISTER_NAMES): New name for REGISTER_NAMES.
1503 (reg_names): Rename to std_reg_names. Change it to a char **
1505 (std_reg_names): New name for reg_names.
1506 (set_mips_isa_type): Set reg_names to point to std_reg_names by
1511 * fr30-desc.h: Partially regenerated to account for changed
1512 CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros.
1513 * m32r-desc.h: Ditto.
1517 * arm-opc.h: Use upper case for flasg in MSR and MRS
1518 instructions. Allow any bit to be set in the field_mask of
1519 the MSR instruction.
1521 * arm-dis.c (print_insn_arm): Decode _x and _s bits of the
1522 field_mask of an MSR instruction.
1526 * arm-opc.h: Disassembly of thumb ldsb/ldsh
1527 instructions changed to ldrsb/ldrsh.
1531 * mips-dis.c (print_insn_arg): Don't mask top 32 bits of 64-bit
1532 target addresses for 'jal' and 'j'.
1536 * ppc-opc.c (powerpc_opcodes): Make the predicted-branch opcodes
1537 also available in common mode when powerpc syntax is being used.
1541 * m68k-dis.c (dummy_printer): Add ATTRIBUTE_UNUSED to args.
1542 (dummy_print_address): Ditto.
1546 * tic54x-opc.c: New.
1547 * tic54x-dis.c: New.
1548 * disassemble.c (disassembler): Add ARCH_tic54x.
1549 * configure.in: Added tic54x target.
1551 * Makefile.am: Add tic54x dependencies.
1552 * Makefile.in: Ditto.
1556 * ppc-opc.c (VA, VB, VC, VD, VS, SIMM, UIMM, SHB): New macros, for
1557 vector unit operands.
1558 (VX, VX_MASK, VXA, VXA_MASK, VXR, VXR_MASK): New macros, for vector
1559 unit instruction formats.
1560 (PPCVEC): New macro, mask for vector instructions.
1561 (powerpc_operands): Add table entries for above operand types.
1562 (powerpc_opcodes): Add table entries for vector instructions.
1564 * ppc-dis.c (print_insn_big_powerpc): Add PPC_OPCODE_ALTIVEC to mask.
1565 (print_insn_little_powerpc): Likewise.
1566 (print_insn_powerpc): Prepend 'v' when printing vector registers.
1570 * configure.in: Add bfd_powerpc_64_arch.
1571 * disassemble.c (disassembler): Use print_insn_big_powerpc for
1576 * fr30-desc.c (fr30_cgen_cpu_open): Initialise signed_overflow
1581 * avr-dis.c (reg_fmul_d): New. Extract destination register from
1583 (reg_fmul_r): New. Extract source register from FMUL instruction.
1584 (reg_muls_d): New. Extract destination register from MULS instruction.
1585 (reg_muls_r): New. Extract source register from MULS instruction.
1586 (reg_movw_d): New. Extract destination register from MOVW instruction.
1587 (reg_movw_r): New. Extract source register from MOVW instruction.
1588 (print_insn_avr): Handle MOVW, MULS, MULSU, FMUL, FMULS, FMULSU,
1589 EICALL, EIJMP, LPM r,Z, ELPM r,Z, SPM, ESPM instructions.
1593 * ia64-gen.c (general): Add an ordered table of primary
1594 opcode names, as well as priority fields to disassembly data
1595 structures to enforce a preferred disassembly format based on the
1596 ordering of the opcode tables.
1597 (load_insn_classes): Show a useful message if IC tables are missing.
1598 (load_depfile): Ditto.
1599 * ia64-asmtab.h (struct ia64_dis_names ): Add priority flag to
1600 distinguish preferred disassembly.
1601 * ia64-opc-f.c: Reorder some insn for preferred disassembly
1602 format. Fix incorrect flag on fma.s/fma.s.s0.
1603 * ia64-opc.c: Scan *all* disassembly matches and use the one with
1604 the highest priority.
1605 * ia64-opc-b.c: Use more abbreviations.
1606 * ia64-asmtab.c: Regenerate.
1610 * hppa-dis.c (extract_16): New function.
1611 (print_insn_hppa): Fix incorrect handling of 'fe'. Added handling of
1612 new operand types l,y,&,fe,fE,fx.
1620 * Makefile.am (HFILES): Add ia64-asmtab.h, ia64-opc.h.
1621 (CFILES): Add ia64-dis.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c,
1622 ia64-opc-i.c, ia64-opc-m.c, ia64-opc-d.c, ia64-opc.c, ia64-gen.c,
1624 (ALL_MACHINES): Add ia64-dis.lo, ia64-opc.lo.
1625 (ia64-ic.tbl, ia64-raw.tbl, ia64-waw.tbl, ia64-war.tbl, ia64-gen,
1626 ia64-gen.o, ia64-asmtab.c, ia64-dis.lo, ia64-opc.lo): New rules.
1627 * Makefile.in: Rebuild.
1628 * configure Rebuild.
1629 * configure.in (bfd_ia64_arch): New target.
1630 * disassemble.c (ARCH_ia64): Define.
1631 (disassembler): Support ARCH_ia64.
1632 * ia64-asmtab.c, ia64-asmtab.h, ia64-dis.c, ia64-gen.c ia64-ic.tbl,
1633 ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c ia64-opc-f.c, ia64-opc-i.c,
1634 ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl,
1635 ia64-war.tbl, ia64-waw.tbl: New files.
1639 * m10300-dis.c (HAVE_AM30, HAVE_AM33): Define.
1640 (disassemble): Use them.
1644 * sysdep.h: Include "ansidecl.h" not <ansidecl.h>
1645 * Makefile.am: Update dependencies.
1646 * Makefile.in: Regenerate.
1650 * a29k-dis.c, alpha-dis.c, alpha-opc.c, arc-dis.c, arc-opc.c,
1651 avr-dis.c, d10v-dis.c, d10v-opc.c, d30v-dis.c, d30v-opc.c,
1652 disassemble.c, h8300-dis.c, h8500-dis.c, hppa-dis.c, i370-dis.c,
1653 i370-opc.c, i960-dis.c, m10200-dis.c, m10200-opc.c, m10300-dis.c,
1654 m10300-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c, mcore-dis.c,
1655 mips-dis.c, mips-opc.c, mips16-opc.c, pj-dis.c, pj-opc.c,
1656 ppc-dis.c, ppc-opc.c, sh-dis.c, sparc-dis.c, sparc-opc.c,
1657 tic80-dis.c, tic80-opc.c, v850-dis.c, v850-opc.c, vax-dis.c,
1658 w65-dis.c, z8k-dis.c, z8kgen.c: Include sysdep.h. Remove
1659 ansidecl.h as sysdep.h includes it.
1663 * configure.in (WARN_CFLAGS): Set to -W -Wall by default. Add
1664 --enable-build-warnings option.
1665 * Makefile.am (AM_CFLAGS, WARN_CFLAGS): Add definitions.
1666 * Makefile.in, configure: Re-generate.
1670 * sh-opc.h (sh_table): Use A_DISP_PC / PCRELIMM_8BY2 for ldre & ldrs.
1671 stc GBR,@-<REG_N> is available for arch_sh1_up.
1672 Group parallel processing insn with identical mnemonics together.
1673 Make three-operand psha / pshl come first.
1677 * sh-opc.h (sh_nibble_type): Remove DISP_8 and DISP_4.
1678 Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT.
1679 (sh_arg_type): Add A_PC.
1680 (sh_table): Update entries using immediates. Add repeat.
1681 * sh-dis.c (print_insn_shx): Remove DISP_8 and DISP_4.
1682 Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT.
1686 * po/opcodes.pot: Regenerate.
1688 * Makefile.am (MKDEP): Use gcc -MM rather than mkdep.
1689 (DEP): Quote when passing vars to sub-make. Add warning message
1691 (DEP1): Rewrite for "gcc -MM".
1692 (CLEANFILES): Add DEP2.
1693 Update dependencies.
1694 * Makefile.in: Regenerate.
1698 * avr-dis.c: Syntax cleanup.
1699 (add0fff): Print the pc relative address as a signed number.
1700 (add03f8): Likewise.
1704 * disassemble.c (disassembler_usage): Don't use a prototype. Mark
1705 the parameter ATTRIBUTE_UNUSED.
1706 * ppc-opc.c: Add ATTRIBUTE_UNUSED as needed.
1710 * m10300-opc.c: SP-based offsets are always unsigned.
1714 * arm-opc.h (thumb_opcodes): Disassemble 0xde.. to "bal"
1715 [branch always] instead of "undefined".
1719 * d30v-opc.c (d30v_format_table): Move SHORT_AR to end of list of
1720 short instructions, from end of list of long instructions.
1724 * Makefile.am (CFILES): Add avr-dis.c.
1725 (ALL_MACHINES): Add avr-dis.lo.
1729 * avr-dis.c (add0fff, add03f8): Don't use structure bitfields to
1731 (print_insn_avr): Call function via pointer in K&R compatible way.
1732 (dispLDD, regPP, reg50, reg104, reg40, reg20w, lit404, lit204,
1733 add0fff, add03f8): Convert to old style function declaration and
1735 (avrdis_opcode): Add prototype.
1739 * avr-dis.c: New file. AVR disassembler.
1740 * configure.in (bfd_avr_arch): New architecture support.
1741 * disassemble.c: Likewise.
1742 * configure: Regenerate.
1746 * sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement.
1750 * d30v-dis.c (print_insn): Remove d*i hacks. Use per-operand
1751 flag to determine if operand is pc-relative.
1753 (d30v_format_table):
1754 (REL6S3): Renamed from IMM6S3.
1755 Added flag OPERAND_PCREL.
1756 (REL12S3, REL18S3, REL32): Split from IMM12S3, IMM18S3, REL32, with
1757 added flag OPERAND_PCREL.
1758 (IMM12S3U): Replaced with REL12S3.
1759 (SHORT_D2, LONG_D): Delay target is pc-relative.
1760 (SHORT_B2r, SHORT_B3r, SHORT_B3br, SHORT_D2r, LONG_Ur, LONG_2r):
1761 Split from SHORT_B2, SHORT_D2, SHORT_B3b, SHORT_D2, LONG_U, LONG_2r,
1762 using the REL* operands.
1763 (LONG_2br, LONG_Dr): Likewise, from LONG_2b, LONG_D.
1764 (SHORT_D1r, SHORT_D2Br, LONG_Dbr): Renamed from SHORT_D1, SHORT_D2B,
1765 LONG_Db, using REL* operands.
1766 (SHORT_U, SHORT_A5S): Removed stray alternatives.
1767 (d30v_opcode_table): Use new *r formats.
1771 * m32r-desc.c (m32r_cgen_cpu_open): Replace 'flags' with
1772 'signed_overflow_ok_p'.
1776 * Makefile.am (stamp-lib): Use $(LIBTOOL) --config to get the
1777 name of the libtool directory.
1778 * Makefile.in: Rebuild.
1782 * cgen-opc.c (cgen_set_signed_overflow_ok): New function.
1783 (cgen_clear_signed_overflow_ok): New function.
1784 (cgen_signed_overflow_ok_p): New function.
1788 * m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c,
1789 m32r-ibld.c, m32r-opc.h: Rebuild.
1793 * i370-dis.c, i370-opc.c: New.
1795 * disassemble.c (ARCH_i370): Define.
1796 (disassembler): Handle it.
1798 * Makefile.am: Add support for Linux/IBM 370.
1799 * configure.in: Likewise.
1801 * Makefile.in: Regenerate.
1802 * configure: Likewise.
1806 * d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp to
1807 ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel
1812 * mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER:
1814 * mips-opc.c (G6): New define.
1815 (mips_builtin_op): Add "move" definition for -gp32.
1820 * ppc-opc.c: Correct dcread--it takes 3 arguments, not 2.
1824 * dis-buf.c (buffer_read_memory): Change `length' param and all int
1829 * sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions.
1830 (print_insn_ppi): Likewise.
1831 (print_insn_shx): Use info->mach to select appropriate insn set.
1832 Add support for sh-dsp. Remove FD_REG_N support.
1833 * sh-opc.h (sh_nibble_type): Add new values for sh-dsp support.
1834 (sh_arg_type): Likewise. Remove FD_REG_N.
1835 (sh_dsp_reg_nums): New enum.
1836 (arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros.
1837 (arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise.
1838 (arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise.
1839 (arch_sh3_dsp_up): Likewise.
1840 (sh_opcode_info): New field: arch.
1841 (sh_table): Split up insn with FD_REG_N into ones with F_REG_N and
1842 D_REG_N. Fill in arch field. Add sh-dsp insns.
1846 * arm-dis.c: Change flavor name from atpcs-special to
1847 special-atpcs to prevent name conflict in gdb.
1848 (get_arm_regname_num_options, set_arm_regname_option,
1849 get_arm_regnames): New functions. API to access the several
1850 flavor of register names. Note: Used by gdb.
1851 (print_insn_thumb): Use the register name entry from the currently
1852 selected flavor for LR and PC.
1856 * mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR
1858 (mcore_table): Add "idly4", "psrclr", "psrset", "mulsh" and
1859 "mulsh.h" instructions.
1860 * mcore-dis.c (imsk array): Add masks for MULSH and OPSR
1862 (print_insn_mcore): Add support for little endian targets.
1863 Add support for MULSH and OPSR classes.
1867 * arm-dis.c (parse_arm_diassembler_option): Rename again.
1868 Previous delat did not take.
1872 * dis-buf.c (buffer_read_memory): Use octets_per_byte field
1873 to adjust target address bounds checking and calculate the
1874 appropriate octet offset into data.
1878 * arm-dis.c: (parse_disassembler_option): Rename to
1879 parse_arm_disassembler_option and allow to be exported.
1881 * disassemble.c (disassembler_usage): New function: Print out any
1882 target specific disassembler options.
1883 Call arm_disassembler_options() if the ARM architecture is being
1886 * arm-dis.c (NUM_ELEM): Define this macro if not already
1888 (arm_regname): New struct type for ARM register names.
1889 (arm_toggle_regnames): Delete.
1890 (parse_disassembler_option): Use register name structure.
1891 (print_insn): New function: Combines duplicate code found in
1892 print_insn_big_arm and print_insn_little_arm.
1893 (print_insn_big_arm): Call print_insn.
1894 (print_insn_little_arm): Call print_insn.
1895 (print_arm_disassembler_options): Display list of supported,
1896 ARM specific disassembler options.
1900 * arm-dis.c (printf_insn_big_arm): Treat ELF symbols with the
1901 ARM_STT_16BIT flag as Thumb code symbols.
1903 * arm-dis.c (printf_insn_little_arm): Ditto.
1907 * arm-dis.c (printf_insn_thumb): Prevent double dumping
1908 of raw thumb instructions.
1912 * mcore-opc.h (mcore_table): Add "add" as an alias for "addu".
1916 * arm-dis.c (streq): New macro.
1917 (strneq): New macro.
1918 (force_thumb): ew local variable.
1919 (parse_disassembler_option): New function: Parse a single, ARM
1920 specific disassembler command line switch.
1921 (parse_disassembler_option): Call parse_disassembler_option to
1922 parse individual command line switches.
1923 (print_insn_big_arm): Check force_thumb.
1924 (print_insn_little_arm): Check force_thumb.
1926 For older changes see ChangeLog-9899
1932 version-control: never