1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright (c) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
6 This file is part of GDB, GAS, and the GNU binutils.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "opcode/mips.h"
27 /* FIXME: These are needed to figure out if the code is mips16 or
28 not. The low bit of the address is often a good indicator. No
29 symbol table is available when this code runs out in an embedded
30 system as when it is used for disassembler support in a monitor. */
32 #if !defined(EMBEDDED_ENV)
33 #define SYMTAB_AVAILABLE 1
38 static int print_insn_mips16 PARAMS ((bfd_vma, struct disassemble_info *));
39 static void print_mips16_insn_arg
40 PARAMS ((int, const struct mips_opcode *, int, boolean, int, bfd_vma,
41 struct disassemble_info *));
43 /* Mips instructions are never longer than this many bytes. */
46 static void print_insn_arg PARAMS ((const char *, unsigned long, bfd_vma,
47 struct disassemble_info *));
48 static int _print_insn_mips PARAMS ((bfd_vma, unsigned long int,
49 struct disassemble_info *));
52 /* FIXME: This should be shared with gdb somehow. */
53 #define REGISTER_NAMES \
54 { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
55 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
56 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
57 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \
58 "sr", "lo", "hi", "bad", "cause","pc", \
59 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
60 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
61 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\
62 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\
63 "fsr", "fir", "fp", "inx", "rand", "tlblo","ctxt", "tlbhi",\
67 static CONST char * CONST reg_names[] = REGISTER_NAMES;
69 /* The mips16 register names. */
70 static const char * const mips16_reg_names[] =
72 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
77 print_insn_arg (d, l, pc, info)
79 register unsigned long int l;
81 struct disassemble_info *info;
90 (*info->fprintf_func) (info->stream, "%c", *d);
97 (*info->fprintf_func) (info->stream, "$%s",
98 reg_names[(l >> OP_SH_RS) & OP_MASK_RS]);
103 (*info->fprintf_func) (info->stream, "$%s",
104 reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
109 (*info->fprintf_func) (info->stream, "0x%x",
110 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
113 case 'j': /* same as i, but sign-extended */
115 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
118 (*info->fprintf_func) (info->stream, "%d",
123 (*info->fprintf_func) (info->stream, "0x%x",
124 (unsigned int) ((l >> OP_SH_PREFX)
129 (*info->fprintf_func) (info->stream, "0x%x",
130 (unsigned int) ((l >> OP_SH_CACHE)
135 (*info->print_address_func)
136 (((pc & ~ (bfd_vma) 0x0fffffff)
137 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)),
142 /* sign extend the displacement */
143 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
146 (*info->print_address_func)
147 ((delta << 2) + pc + 4,
152 (*info->fprintf_func) (info->stream, "$%s",
153 reg_names[(l >> OP_SH_RD) & OP_MASK_RD]);
157 (*info->fprintf_func) (info->stream, "$%s", reg_names[0]);
161 (*info->fprintf_func) (info->stream, "0x%x",
162 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
166 (*info->fprintf_func) (info->stream, "0x%x",
167 (l >> OP_SH_CODE) & OP_MASK_CODE);
172 (*info->fprintf_func) (info->stream, "0x%x",
173 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
177 (*info->fprintf_func) (info->stream, "0x%x",
178 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
182 (*info->fprintf_func) (info->stream, "0x%x",
183 (l >> OP_SH_SYSCALL) & OP_MASK_SYSCALL);
188 (*info->fprintf_func) (info->stream, "$f%d",
189 (l >> OP_SH_FS) & OP_MASK_FS);
195 (*info->fprintf_func) (info->stream, "$f%d",
196 (l >> OP_SH_FT) & OP_MASK_FT);
200 (*info->fprintf_func) (info->stream, "$f%d",
201 (l >> OP_SH_FD) & OP_MASK_FD);
205 (*info->fprintf_func) (info->stream, "$f%d",
206 (l >> OP_SH_FR) & OP_MASK_FR);
210 (*info->fprintf_func) (info->stream, "$%d",
211 (l >> OP_SH_RT) & OP_MASK_RT);
215 (*info->fprintf_func) (info->stream, "$%d",
216 (l >> OP_SH_RD) & OP_MASK_RD);
220 (*info->fprintf_func) (info->stream, "$fcc%d",
221 (l >> OP_SH_BCC) & OP_MASK_BCC);
225 (*info->fprintf_func) (info->stream, "$fcc%d",
226 (l >> OP_SH_CCC) & OP_MASK_CCC);
230 (*info->fprintf_func) (info->stream, "%d",
231 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
236 /* xgettext:c-format */
237 (*info->fprintf_func) (info->stream,
238 _("# internal error, undefined modifier(%c)"),
246 /* Figure out the MIPS ISA and CPU based on the machine number.
247 FIXME: What does this have to do with SYMTAB_AVAILABLE? */
250 set_mips_isa_type (mach, isa, cputype)
255 int target_processor = 0;
260 case bfd_mach_mips3000:
261 target_processor = 3000;
264 case bfd_mach_mips3900:
265 target_processor = 3900;
268 case bfd_mach_mips4000:
269 target_processor = 4000;
272 case bfd_mach_mips4010:
273 target_processor = 4010;
276 case bfd_mach_mips4100:
277 target_processor = 4100;
280 case bfd_mach_mips4111:
281 target_processor = 4100;
284 case bfd_mach_mips4300:
285 target_processor = 4300;
288 case bfd_mach_mips4400:
289 target_processor = 4400;
292 case bfd_mach_mips4600:
293 target_processor = 4600;
296 case bfd_mach_mips4650:
297 target_processor = 4650;
300 case bfd_mach_mips5000:
301 target_processor = 5000;
304 case bfd_mach_mips6000:
305 target_processor = 6000;
308 case bfd_mach_mips8000:
309 target_processor = 8000;
312 case bfd_mach_mips10000:
313 target_processor = 10000;
316 case bfd_mach_mips16:
317 target_processor = 16;
321 target_processor = 3000;
328 *cputype = target_processor;
331 #endif /* SYMTAB_AVAILABLE */
333 /* Print the mips instruction at address MEMADDR in debugged memory,
334 on using INFO. Returns length of the instruction, in bytes, which is
335 always 4. BIGENDIAN must be 1 if this is big-endian code, 0 if
336 this is little-endian code. */
339 _print_insn_mips (memaddr, word, info)
341 unsigned long int word;
342 struct disassemble_info *info;
344 register const struct mips_opcode *op;
345 int target_processor, mips_isa;
346 static boolean init = 0;
347 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
349 /* Build a hash table to shorten the search time. */
354 for (i = 0; i <= OP_MASK_OP; i++)
356 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
358 if (op->pinfo == INSN_MACRO)
360 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
371 #if ! SYMTAB_AVAILABLE
372 /* This is running out on a target machine, not in a host tool.
373 FIXME: Where does mips_target_info come from? */
374 target_processor = mips_target_info.processor;
375 mips_isa = mips_target_info.isa;
377 set_mips_isa_type (info->mach, &mips_isa, &target_processor);
380 info->bytes_per_chunk = 4;
381 info->display_endian = info->endian;
383 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
386 for (; op < &mips_opcodes[NUMOPCODES]; op++)
388 if (op->pinfo != INSN_MACRO && (word & op->mask) == op->match)
390 register const char *d;
392 if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor, 0))
395 (*info->fprintf_func) (info->stream, "%s", op->name);
398 if (d != NULL && *d != '\0')
400 (*info->fprintf_func) (info->stream, "\t");
401 for (; *d != '\0'; d++)
402 print_insn_arg (d, word, memaddr, info);
410 /* Handle undefined instructions. */
411 (*info->fprintf_func) (info->stream, "0x%x", word);
416 /* In an environment where we do not know the symbol type of the
417 instruction we are forced to assume that the low order bit of the
418 instructions' address may mark it as a mips16 instruction. If we
419 are single stepping, or the pc is within the disassembled function,
420 this works. Otherwise, we need a clue. Sometimes. */
423 print_insn_big_mips (memaddr, info)
425 struct disassemble_info *info;
431 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
432 /* Only a few tools will work this way. */
434 return print_insn_mips16 (memaddr, info);
439 || (info->flavour == bfd_target_elf_flavour
440 && info->symbols != NULL
441 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
443 return print_insn_mips16 (memaddr, info);
446 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
448 return _print_insn_mips (memaddr, (unsigned long) bfd_getb32 (buffer),
452 (*info->memory_error_func) (status, memaddr, info);
458 print_insn_little_mips (memaddr, info)
460 struct disassemble_info *info;
468 return print_insn_mips16 (memaddr, info);
473 || (info->flavour == bfd_target_elf_flavour
474 && info->symbols != NULL
475 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
477 return print_insn_mips16 (memaddr, info);
480 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
482 return _print_insn_mips (memaddr, (unsigned long) bfd_getl32 (buffer),
486 (*info->memory_error_func) (status, memaddr, info);
491 /* Disassemble mips16 instructions. */
494 print_insn_mips16 (memaddr, info)
496 struct disassemble_info *info;
504 const struct mips_opcode *op, *opend;
506 info->bytes_per_chunk = 2;
507 info->display_endian = info->endian;
509 info->insn_info_valid = 1;
510 info->branch_delay_insns = 0;
512 info->insn_type = dis_nonbranch;
516 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
519 (*info->memory_error_func) (status, memaddr, info);
525 if (info->endian == BFD_ENDIAN_BIG)
526 insn = bfd_getb16 (buffer);
528 insn = bfd_getl16 (buffer);
530 /* Handle the extend opcode specially. */
532 if ((insn & 0xf800) == 0xf000)
535 extend = insn & 0x7ff;
539 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
542 (*info->fprintf_func) (info->stream, "extend 0x%x",
543 (unsigned int) extend);
544 (*info->memory_error_func) (status, memaddr, info);
548 if (info->endian == BFD_ENDIAN_BIG)
549 insn = bfd_getb16 (buffer);
551 insn = bfd_getl16 (buffer);
553 /* Check for an extend opcode followed by an extend opcode. */
554 if ((insn & 0xf800) == 0xf000)
556 (*info->fprintf_func) (info->stream, "extend 0x%x",
557 (unsigned int) extend);
558 info->insn_type = dis_noninsn;
565 /* FIXME: Should probably use a hash table on the major opcode here. */
567 opend = mips16_opcodes + bfd_mips16_num_opcodes;
568 for (op = mips16_opcodes; op < opend; op++)
570 if (op->pinfo != INSN_MACRO && (insn & op->mask) == op->match)
574 if (strchr (op->args, 'a') != NULL)
578 (*info->fprintf_func) (info->stream, "extend 0x%x",
579 (unsigned int) extend);
580 info->insn_type = dis_noninsn;
588 status = (*info->read_memory_func) (memaddr, buffer, 2,
593 if (info->endian == BFD_ENDIAN_BIG)
594 extend = bfd_getb16 (buffer);
596 extend = bfd_getl16 (buffer);
601 (*info->fprintf_func) (info->stream, "%s", op->name);
602 if (op->args[0] != '\0')
603 (*info->fprintf_func) (info->stream, "\t");
605 for (s = op->args; *s != '\0'; s++)
609 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
610 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
612 /* Skip the register and the comma. */
618 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
619 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
621 /* Skip the register and the comma. */
625 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
629 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
631 info->branch_delay_insns = 1;
632 if (info->insn_type != dis_jsr)
633 info->insn_type = dis_branch;
641 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
642 (*info->fprintf_func) (info->stream, "0x%x", insn);
643 info->insn_type = dis_noninsn;
648 /* Disassemble an operand for a mips16 instruction. */
651 print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
653 const struct mips_opcode *op;
658 struct disassemble_info *info;
665 (*info->fprintf_func) (info->stream, "%c", type);
670 (*info->fprintf_func) (info->stream, "$%s",
671 mips16_reg_names[((l >> MIPS16OP_SH_RY)
672 & MIPS16OP_MASK_RY)]);
677 (*info->fprintf_func) (info->stream, "$%s",
678 mips16_reg_names[((l >> MIPS16OP_SH_RX)
679 & MIPS16OP_MASK_RX)]);
683 (*info->fprintf_func) (info->stream, "$%s",
684 mips16_reg_names[((l >> MIPS16OP_SH_RZ)
685 & MIPS16OP_MASK_RZ)]);
689 (*info->fprintf_func) (info->stream, "$%s",
690 mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z)
691 & MIPS16OP_MASK_MOVE32Z)]);
695 (*info->fprintf_func) (info->stream, "$%s", reg_names[0]);
699 (*info->fprintf_func) (info->stream, "$%s", reg_names[29]);
703 (*info->fprintf_func) (info->stream, "$pc");
707 (*info->fprintf_func) (info->stream, "$%s", reg_names[31]);
711 (*info->fprintf_func) (info->stream, "$%s",
712 reg_names[((l >> MIPS16OP_SH_REGR32)
713 & MIPS16OP_MASK_REGR32)]);
717 (*info->fprintf_func) (info->stream, "$%s",
718 reg_names[MIPS16OP_EXTRACT_REG32R (l)]);
744 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
756 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
762 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
768 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
774 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
780 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
786 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
787 info->insn_type = dis_dref;
793 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
794 info->insn_type = dis_dref;
800 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
801 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
802 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
804 info->insn_type = dis_dref;
811 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
812 info->insn_type = dis_dref;
817 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
822 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
826 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
831 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
832 /* FIXME: This might be lw, or it might be addiu to $sp or
833 $pc. We assume it's load. */
834 info->insn_type = dis_dref;
840 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
841 info->insn_type = dis_dref;
846 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
851 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
857 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
862 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
866 info->insn_type = dis_condbranch;
870 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
874 info->insn_type = dis_branch;
879 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
881 /* FIXME: This can be lw or la. We assume it is lw. */
882 info->insn_type = dis_dref;
888 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
890 info->insn_type = dis_dref;
896 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
905 if (signedp && immed >= (1 << (nbits - 1)))
908 if ((type == '<' || type == '>' || type == '[' || type == ']')
915 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
916 else if (extbits == 15)
917 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
919 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
920 immed &= (1 << extbits) - 1;
921 if (! extu && immed >= (1 << (extbits - 1)))
922 immed -= 1 << extbits;
926 (*info->fprintf_func) (info->stream, "%d", immed);
935 baseaddr = memaddr + 2;
938 baseaddr = memaddr - 2;
946 /* If this instruction is in the delay slot of a jr
947 instruction, the base address is the address of the
948 jr instruction. If it is in the delay slot of jalr
949 instruction, the base address is the address of the
950 jalr instruction. This test is unreliable: we have
951 no way of knowing whether the previous word is
952 instruction or data. */
953 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
956 && (((info->endian == BFD_ENDIAN_BIG
957 ? bfd_getb16 (buffer)
958 : bfd_getl16 (buffer))
959 & 0xf800) == 0x1800))
960 baseaddr = memaddr - 4;
963 status = (*info->read_memory_func) (memaddr - 2, buffer,
966 && (((info->endian == BFD_ENDIAN_BIG
967 ? bfd_getb16 (buffer)
968 : bfd_getl16 (buffer))
969 & 0xf81f) == 0xe800))
970 baseaddr = memaddr - 2;
973 val = (baseaddr & ~ ((1 << shift) - 1)) + immed;
974 (*info->print_address_func) (val, info);
983 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
984 (*info->print_address_func) ((memaddr & 0xf0000000) | l, info);
985 info->insn_type = dis_jsr;
986 info->target = (memaddr & 0xf0000000) | l;
987 info->branch_delay_insns = 1;
993 int need_comma, amask, smask;
997 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
999 amask = (l >> 3) & 7;
1001 if (amask > 0 && amask < 5)
1003 (*info->fprintf_func) (info->stream, "$%s", reg_names[4]);
1005 (*info->fprintf_func) (info->stream, "-$%s",
1006 reg_names[amask + 3]);
1010 smask = (l >> 1) & 3;
1013 (*info->fprintf_func) (info->stream, "%s??",
1014 need_comma ? "," : "");
1019 (*info->fprintf_func) (info->stream, "%s$%s",
1020 need_comma ? "," : "",
1023 (*info->fprintf_func) (info->stream, "-$%s",
1024 reg_names[smask + 15]);
1030 (*info->fprintf_func) (info->stream, "%s$%s",
1031 need_comma ? "," : "",
1036 if (amask == 5 || amask == 6)
1038 (*info->fprintf_func) (info->stream, "%s$f0",
1039 need_comma ? "," : "");
1041 (*info->fprintf_func) (info->stream, "-$f1");