3 * cgen.h (struct cgen_maybe_multi_ifield): Add "const PTR p" to union.
4 Constify "leaf" and "multi".
8 * h8300.h (h8_opcode): Remove 'noperands', 'idx', and 'size'
10 (h8_opcodes). Modify initializer and initializer macros to no
11 longer initialize the removed fields.
15 * tic4x.h (c4x_insts): Fixed LDHI constraint
19 * h8300.h (h8_opcode): Remove 'length' field.
20 (h8_opcodes): Mark as 'const' (both the declaration and
21 definition). Modify initializer and initializer macros to no
22 longer initialize the length field.
26 * arc.h (arc_ext_opcodes): Declare as extern.
27 (arc_ext_operands): Declare as extern.
28 * i860.h (i860_opcodes): Declare as const.
32 * tic4x.h: File reordering. Added enhanced opcodes.
36 * tic4x.h: Major rewrite of entire file. Define instruction
37 classes, and put each instruction into a class.
41 * tic4x.h: Added new opcodes and corrected some bugs. Add support
46 * cgen.h: Test __BFD_H_SEEN__ rather than BFD_VERSION_DATE.
54 * mips.h: Update comment for new opcodes.
55 (OP_MASK_VECBYTE, OP_SH_VECBYTE): New.
56 (OP_MASK_VECALIGN, OP_SH_VECALIGN): New.
57 (INSN_4111, INSN_4120, INSN_5400, INSN_5500): New.
58 (CPU_VR4120, CPU_VR5400, CPU_VR5500): New.
59 (OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags.
60 Don't match CPU_R4111 with INSN_4100.
66 * ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500
68 (PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR,
69 PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the
70 e500x2 Integer select, branch locking, performance monitor,
71 cache locking and machine check APUs, respectively.
72 (PPC_OPCODE_EFS): New opcode type for efs* instructions.
73 (PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions.
77 * m68hc11.h (M6812_OP_PAGE): Define to identify call operand.
78 (M68HC12_BANK_VIRT, M68HC12_BANK_MASK, M68HC12_BANK_BASE,
79 M68HC12_BANK_SHIFT, M68HC12_BANK_PAGE_MASK): Define for 68HC12
81 (M6811_OC1M5, M6811_OC1M4, M6811_MODF): Fix value.
85 * mips.h (INSN_MIPS16): New define.
89 * i386.h: Remove IgnoreSize from movsx and movzx.
93 * a29k.h: Replace CONST with const.
94 (CONST): Don't define.
95 * convex.h: Replace CONST with const.
96 (CONST): Don't define.
97 * dlx.h: Replace CONST with const.
98 * or32.h (CONST): Don't define.
102 * mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
103 (MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
104 (MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
105 (INSN_MDMX): New constants, for MDMX support.
106 (opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
114 * ia64.h: Use #include "" instead of <> for local header files.
119 * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
123 * h8300.h: Corrected defs of all control regs
128 * i386.h: Add intel mode cmpsd and movsd.
129 Put them before SSE2 insns, so that rep prefix works.
133 * mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D
135 (OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks
136 may be passed along with the ISA bitmask.
140 * pdp11.h: Add format codes for float instruction formats.
144 * ppc.h (PPC_OPCODE_POWER4, PPC_OPCODE_NOPOWER4): Define.
148 * i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands.
152 * i386.h (push,pop): Allow 16bit operands in 64bit mode.
154 (in, out): Disable 64bit operands.
155 (call, jmp): Avoid REX prefixes.
156 (jcxz): Prohibit in 64bit mode
157 (jrcxz, loop): Add 64bit variants.
158 (movq): Fix patterns.
159 (movmskps, pextrw, pinstrw): Add 64bit variants.
167 * cgen.h (CGEN_MAYBE_MULTI_IFLD): New structure.
168 (CGEN_OPERAND): Add CGEN_MAYBE_MULTI_IFLD field.
172 * h8300.h: Comment typo fix.
176 * ppc.h (PPC_OPCODE_BOOKE): BookE is not Motorola specific.
177 (PPC_OPCODE_BOOKE64): Likewise.
181 * hppa.h (call, ret): Move to end of table.
182 (addb, addib): PA2.0 variants should have been PA2.0W.
183 (ldw, ldh, ldb, stw, sth, stb, stwa): Reorder to keep disassembler
185 (fldw, fldd, fstw, fstd, bb): Likewise.
186 (short loads/stores): Tweak format specifier slightly to keep
188 (indexed loads/stores): Likewise.
189 (absolute loads/stores): Likewise.
193 * d10v.h (OPERAND_NOSP): New macro.
197 * d10v.h (OPERAND_SP): New macro.
201 * ppc.h (struct powerpc_operand <insert, extract>): Add dialect param.
205 * tic54x.h: Revise opcode layout; don't really need a separate
206 structure for parallel opcodes.
211 * i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to
216 * mips.h (OPCODE_IS_MEMBER): Remove extra space.
224 * mips.h (OPCODE_IS_MEMBER): Add a no-op term to the end
225 of the expression, to make source code merging easier.
229 * mips.h: Sort coprocessor instruction argument characters
230 in comment, add a few more words of description for "H".
234 * mips.h (INSN_SB1): New cpu-specific instruction bit.
235 (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1
240 * ppc.h (PPC_OPCODE_BOOKE64): Fix typo.
244 * ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_BOOKE64, PPC_OPCODE_403): New
245 opcode flags for BookE 32-bit, BookE 64-bit and PowerPC 403
246 instructions, respectively.
250 * v850.h: Remove spurious comment.
254 * h8300.h: Fix compile time warning messages
258 * alpha.h (struct alpha_operand): Pack elements into bitfields.
262 * mips.h: Remove CPU_MIPS32_4K.
266 * ppc.h (PPC_OPERAND_DS): Define.
270 * d30v.h: Fix declaration of reg_name_cnt.
272 * d10v.h: Fix declaration of d10v_reg_name_cnt.
274 * arc.h: Add prototypes from opcodes/arc-opc.c.
278 * mips.h (INSN_10000): Define.
279 (OPCODE_IS_MEMBER): Check for INSN_10000.
283 * ppc.h: Revert 2001-08-08.
287 * mips.h (INSN_GP32): Remove.
288 (OPCODE_IS_MEMBER): Remove gp32 parameter.
289 (M_MOVE): New macro identifier.
294 * ppc.h (struct powerpc_operand): New field `reloc'.
298 * mips.h (INSN_ISA_MASK): Nuke bits 12-15.
302 * cgen.h (CGEN_INSN): Add regex support.
303 (build_insn_regex): Declare.
307 * cgen.h (CGEN_MACH): Add insn_chunk_bitsize field.
308 (cgen_cpu_desc): Ditto.
312 * m88k.h: Clean up and reformat. Remove unused code.
316 * cgen.h (cgen_keyword): Add nonalpha_chars field.
320 * mips.h (CPU_R12000): Define.
324 * cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48.
328 * mips.h (INSN_ISA_MASK): Define.
332 * i386.h (i386_optab): Second operand of cvtps2dq is an xmm reg,
333 not an mmx reg. Swap xmm/mmx regs on both movdq2q and movq2dq,
334 and use InvMem as these insns must have register operands.
338 * i386.h (i386_optab): Move InvMem to first operand of pmovmskb
339 and pextrw to swap reg/rm assignments.
343 * cris.h (enum cris_insn_version_usage): Correct comment for
348 * i386.h (i386_optab): Correct entry for "movntdq". Add "punpcklqdq".
349 Add InvMem to first operand of "maskmovdqu".
353 * cris.h (ADD_PC_INCR_OPCODE): New macro.
357 * h8300.h: Fix formatting.
361 * i386.h (i386_optab): Add paddq, psubq.
365 * i386.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Define.
369 * m68k.h: new defines for Coldfire V4. Update mcf to know
378 * i386.h (i386_optab): SSE integer converison instructions have
379 64bit versions on x86-64.
383 * mips.h: Remove extraneous whitespace. Formating change to allow
384 for future contribution.
392 * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short.
393 (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES.
394 (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS.
398 * i386.h (i386_optab): Fix swapgs
402 * hppa.h: Describe new '<' and '>' operand types, and tidy
404 (pa_opcodes): Add entries for missing wide mode ldi,ldo,ldw,stw.
405 Remove duplicate "ldw j(s,b),x". Sort some entries.
409 * i386.h (i386_optab): Fix pusha and ret templates.
413 * arc.h (ARC_MACH_5, ARC_MACH_6, ARC_MACH_7, ARC_MACH_8): New
414 definitions for masking cpu type.
415 (arc_ext_operand_value) New structure for storing extended
417 (ARC_OPERAND_*) Flags for operand values.
421 * i386.h (pinsrw): Add.
423 (cvttpd2dq): Fix operands.
424 (cvttps2dq): Likewise.
425 (movq2q): Rename to movdq2q.
429 * i386.h: Correct movnti instruction.
433 * cgen.h (CGEN_SYNTAX_CHAR_TYPE): New typedef based on max number
434 of operands (unsigned char or unsigned short).
435 (CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE.
436 (CGEN_SYNTAX_CHAR): Changed to cast to unsigned char.
440 * i386.h (i386_optab): Make [sml]fence template to use immext field.
444 * i386.h (i386_optab): Fix 64bit pushf template; Add instructions
445 introduced by Pentium4
449 * i386.h (i386_optab): Add "rex*" instructions;
450 add swapgs; disable jmp/call far direct instructions for
451 64bit mode; add syscall and sysret; disable registers for 0xc6
452 template. Add 'q' suffixes to extendable instructions, disable
453 obsolete instructions, add new sign/zero extension ones.
454 (i386_regtab): Add extended registers.
456 (q_Suf, wlq_Suf, bwlq_Suf): New.
460 * i386.h (i386_optab): Replace "Imm" with "EncImm".
461 (i386_regtab): Add flags field.
465 * mips.h: Fix formatting.
469 mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete.
470 (OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old
471 OP_*_SYSCALL definitions.
472 (OP_SH_CODE19, OP_MASK_CODE19): Define, for use as
474 (MIPS operand specifier comments): Remove 'm', add 'U' and
475 'J', and update the meaning of 'B' so that it's more general.
477 * mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4,
478 INSN_ISA5): Renumber, redefine to mean the ISA at which the
479 instruction was added.
480 (INSN_ISA32): New constant.
481 (INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32):
482 Renumber to avoid new and/or renumbered INSN_* constants.
483 (INSN_MIPS32): Delete.
484 (ISA_UNKNOWN): New constant to indicate unknown ISA.
485 (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5,
486 ISA_MIPS32): New constants, defined to be the mask of INSN_*
487 constants available at that ISA level.
488 (CPU_UNKNOWN): New constant to indicate unknown CPU.
489 (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter,
490 define it with a unique value.
491 (OPCODE_IS_MEMBER): Update for new ISA membership-related
494 * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
497 * mips.h (CPU_SB1): New constant.
501 * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
502 Note that '3' is used for siam operand.
506 * ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP.
510 * mips.h: Use defines instead of hard-coded processor numbers.
511 (CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010,
512 CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650,
513 CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K,
514 CPU_4KC, CPU_4KM, CPU_4KP): Define..
515 (OPCODE_IS_MEMBER): Use new defines.
516 (OP_MASK_SEL, OP_SH_SEL): Define.
517 (OP_MASK_CODE20, OP_SH_CODE20): Define.
518 Add 'P' to used characters.
519 Use 'H' for coprocessor select field.
520 Use 'm' for 20 bit breakpoint code.
521 Document new arg characters and add to used characters.
522 (INSN_MIPS32): New define for MIPS32 extensions.
523 (OPCODE_IS_MEMBER): Recognize MIPS32 instructions.
527 * hppa.h: Mention cz completer.
531 * ia64.h (IA64_OPCODE_POSTINC): New.
535 * i386.h: Swap the Intel syntax "movsx"/"movzx" due to the
540 * i860.h: Small formatting adjustments.
544 * avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros.
545 Move related opcodes closer to each other.
546 Minor changes in comments, list undefined opcodes.
550 * cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned.
554 * i860.h (btne, bte, bla): Changed these opcodes
555 to use sbroff ('r') instead of split16 ('s').
556 (J, K, L, M): New operand types for 16-bit aligned fields.
557 (ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to
558 use I, J, K, L, M instead of just I.
559 (T, U): New operand types for split 16-bit aligned fields.
560 (st.x): Changed these opcodes to use S, T, U instead of just S.
561 (andh, andnoth, orh, xorh): Deleted 3-register forms as they do not
563 (pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860.
564 (pfeq.ss, pfeq.dd): New opcodes.
565 (st.s): Fixed incorrect mask bits.
566 (fmlow): Fixed incorrect mask bits.
567 (fzchkl, pfzchkl): Fixed incorrect mask bits.
568 (faddz, pfaddz): Fixed incorrect mask bits.
569 (form, pform): Fixed incorrect mask bits.
570 (pfld.l): Fixed incorrect mask bits.
571 (fst.q): Fixed incorrect mask bits.
572 (all floating point opcodes): Fixed incorrect mask bits for
573 handling of dual bit.
581 * avr.h (AVR_ISA_WRAP): Remove, now assumed if not AVR_ISA_MEGA.
582 (AVR_ISA_ESPM): Remove, because ESPM removed in databook update.
583 (AVR_ISA_85xx): Remove, all uses changed back to AVR_ISA_2xxx.
584 (AVR_ISA_M83): Define for ATmega83, ATmega85.
585 (espm): Remove, because ESPM removed in databook update.
586 (eicall, eijmp): Move to the end of opcode table.
590 * m68hc11.h: New file for support of Motorola 68hc11.
594 * avr.h: clr,lsl,rol, ... moved after add,adc, ...
598 * avr.h: New file with AVR opcodes.
602 * d10v.h: added ALONE attribute for d10v_opcode.exec_type.
606 * i386.h: Allow d suffix on iret, and add DefaultSize modifier.
610 * i386.h: Use sl_FP, not sl_Suf for fild.
614 * cgen.h (CGEN_MAX_SYNTAX_BYTES): Increase to 32. Check that
615 it exceeds CGEN_ACTUAL_MAX_SYNTAX_BYTES, if set.
616 (CGEN_MAX_IFMT_OPERANDS): Increase to 16. Check that it exceeds
617 CGEN_ACTUAL_MAX_IFMT_OPERANDS, if set.
621 * i386.h (i386_optab): Cpu686 for sysenter,sysexit,fxsave,fxrestore.
626 * i386.h (i386_optab): Add cpu_flags for all instructions.
631 * i386.h (wld_Suf): Define. Use on pushf, popf, pusha, popa.
639 * ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit.
640 (PPC_OPERAND_VR): New operand flag for vector registers.
644 * h8300.h (EOP): Add missing initializer.
648 * hppa.h (pa_opcodes): New opcodes for PA2.0 wide mode
649 forms of ld/st{b,h,w,d} and fld/fst{w,d} (16-bit displacements).
650 New operand types l,y,&,fe,fE,fx added to support above forms.
651 (pa_opcodes): Replaced usage of 'x' as source/target for
652 floating point double-word loads/stores with 'fx'.
663 * d30v.h (SHORT_A1): Fix value.
664 (SHORT_AR): Renumber so that it is at the end of the list of short
665 instructions, not the end of the list of long instructions.
669 * i386.h: (UNIXWARE_COMPAT): Rename to SYSV386_COMPAT as the
670 problem isn't really specific to Unixware.
671 (OLDGCC_COMPAT): Define.
672 (i386_optab): If !OLDGCC_COMPAT, don't handle fsubp etc. with
674 Fix lots of comments.
679 (SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated.
680 (SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated.
681 (SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated.
682 (SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated.
683 (SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated.
684 (LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated.
685 (LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated.
689 * i386.h (fild, fistp): Change intel d_Suf form to fildd and
690 fistpd without suffix.
694 * cgen.h (cgen_cpu_desc): Rename field 'flags' to
695 'signed_overflow_ok_p'.
696 Delete prototypes for cgen_set_flags() and cgen_get_flags().
700 * cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
701 (CGEN_CPU_TABLE): flags: new field.
702 Add prototypes for new functions.
706 * i386.h: Add some more UNIXWARE_COMPAT comments.
714 * d30v.h (FLAG_NOT_WITH_ADDSUBppp): Redefined as operation
715 cannot be combined in parallel with ADD/SUBppp.
719 * mips.h: (OPCODE_IS_MEMBER): Add comment.
723 * mips.h (OPCODE_IS_MEMBER): Add gp32 arg, which determines
724 whether synthetic opcodes (e.g. move) generate 32-bit or 64-bit
729 * i386.h: Qualify intel mode far call and jmp with x_Suf.
733 * i386.h: Add JumpAbsolute qualifier to all non-intel mode
734 indirect jumps and calls. Add FF/3 call for intel mode.
738 * mn10300.h: Add new operand types. Add new instruction formats.
742 * hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb"
747 * mips.h (INSN_ISA5): New.
751 * mips.h (OPCODE_IS_MEMBER): New.
755 * d30v.h (SHORT_AR): Define.
759 * alpha.h (alpha_num_opcodes): Convert to unsigned.
760 (alpha_num_operands): Ditto.
764 * hppa.h (pa_opcodes): Add load and store cache control to
765 instructions. Add ordered access load and store.
767 * hppa.h (pa_opcode): Add new entries for addb and addib.
769 * hppa.h (pa_opcodes): Fix cmpb and cmpib entries.
771 * hppa.h (pa_opcodes): Add entries for cmpb and cmpib.
775 * d10v.h: Add flag RESTRICTED_NUM3 for imm3 operands.
779 * hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve"
780 and "be" using completer prefixes.
782 * hppa.h (pa_opcodes): Add initializers to silence compiler.
784 * hppa.h: Update comments about character usage.
788 * hppa.h (pa_opcodes): Fix minor thinkos introduced while cleaning
789 up the new fstw & bve instructions.
793 * hppa.h (pa_opcodes): Add remaining PA2.0 integer load/store
796 * hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions.
798 * hppa.h (pa_opcodes): Add long offset double word load/store
801 * hppa.h (pa_opcodes): Add FLAG_STRICT variants of FP loads and
804 * hppa.h (pa_opcodes): Handle PA2.0 fcnv, fcmp and ftest insns.
806 * hppa.h (pa_opcodes): Finish support for PA2.0 "b" instructions.
808 * hppa.h (pa_opcodes): Handle PA2.0 "bve" instructions.
810 * hppa.h (pa_opcodes): Add new syntax "be" instructions.
812 * hppa.h (pa_opcodes): Note use of 'M' and 'L'.
814 * hppa.h (pa_opcodes): Add support for "b,l".
816 * hppa.h (pa_opcodes): Add support for "b,gate".
820 * hppa.h (pa_opcodes): Use 'fX' for first register operand
823 * hppa.h (pa_opcodes): Fix mask for probe and probei.
825 * hppa.h (pa_opcodes): Fix mask for depwi.
829 * hppa.h (pa_opcodes): Add "addil" variant which has the %r1 as
830 an explicit output argument.
834 * hppa.h: Add strict variants of PA1.0/PA1.1 loads and stores.
835 Add a few PA2.0 loads and store variants.
843 * i386.h (i386_regtab): Move %st to top of table, and split off
844 other fp reg entries.
845 (i386_float_regtab): To here.
849 * hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args
852 * hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi.
855 * hppa.h: Document new completers and args.
856 * hppa.h (pa_opcodes): Add 64 bit patterns and pa2.0 syntax for uxor,
857 uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe. Add pa2.0
858 extensions for ssm, rsm, pdtlb, pitlb. Add performance instructions
861 * hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl,
862 hshr, hsub, mixh, mixw, permh.
864 * hppa.h (pa_opcodes): Change completers in instructions to
867 * hppa.h (pa_opcodes): Add popbts, new forms of bb, havg,
868 hshladd, hshradd, shrpd, and shrpw instructions. Update arg comments.
870 * hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg,
871 fnegabs to use 'I' instead of 'F'.
875 * i386.h: Add AMD athlon instructions, pfnacc, pfpnacc, pswapd.
876 Document pf2iw and pi2fw as athlon insns. Remove pswapw.
877 Alphabetically sort PIII insns.
881 * cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
885 * hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and,
886 and andcm. Add 32 and 64 bit version of cmpclr, cmpiclr.
888 * hppa.h: Document 64 bit condition completers.
892 * hppa.h (pa_opcodes): Change condition args to use '?' prefix.
896 * i386.h (i386_optab): Add DefaultSize modifier to all insns
897 that implicitly modify %esp. #undef d_Suf, x_suf, sld_suf,
898 sldx_suf, bwld_Suf, d_FP, x_FP, sld_FP, sldx_FP at end of table.
903 * hppa.h (pa_opcodes): Add "pushnom" and "pushbts".
905 * hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT.
907 * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd,
908 and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'.
912 * i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw insns.
916 * hppa.h (struct pa_opcode): Add new field "flags".
917 (FLAGS_STRICT): Define.
922 * hppa.h (pa_opcodes): Add pa2.0 clrbts instruction.
924 * hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions.
928 * i386.h: Allow `l' suffix on bswap. Allow `w' suffix on arpl,
929 lldt, lmsw, ltr, str, verr, verw. Add FP flag to fcmov*. Add FP
930 flag to fcomi and friends.
934 * hppa.h (pa_opcodes): Move integer arithmetic instructions after
935 integer logical instructions.
939 * m68k.h: Document new formats `E', `G', `H' and new places `N',
942 * m68k.h: Define mcf5206e, mcf5307, mcf. Document new format `u'
943 and new places `m', `M', `h'.
947 * hppa.h (pa_opcodes): Add several processor specific system
952 * hppa.h (pa_opcodes): Add second entry for "comb", "comib",
953 "addb", and "addib" to be used by the disassembler.
957 * i386.h (ReverseModrm): Remove all occurences.
958 (InvMem): Add to control/debug/test mov insns, movhlps, movlhps,
959 movmskps, pextrw, pmovmskb, maskmovq.
960 Change NoSuf to FP on all MMX, XMM and AMD insns as these all
961 ignore the data size prefix.
963 * i386.h (i386_optab, i386_regtab): Add support for PIII SIMD.
968 * ppc.h (PPC_OPCODE_64_BRIDGE): New.
972 * cgen.h (CGEN_ATTR): Delete member num_nonbools.
973 (CGEN_ATTR_TYPE): Update.
974 (CGEN_ATTR_MASK): Number booleans starting at 0.
975 (CGEN_ATTR_VALUE): Update.
976 (CGEN_INSN_ATTR): Update.
980 * hppa.h (fmpyfadd, fmpynfadd, fneg, fnegabs): New PA2.0
985 * hppa.h (bb, bvb): Tweak opcode/mask.
990 * cgen.h (CGEN_ISA,CGEN_MACH): New typedefs.
991 (struct cgen_cpu_desc): Rename member mach to machs. New member isas.
992 New members word_bitsize,default_insn_bitsize,base_insn-bitsize,
993 min_insn_bitsize,max_insn_bitsize,isa_table,mach_table,rebuild_tables.
994 Delete member max_insn_size.
995 (enum cgen_cpu_open_arg): New enum.
996 (cpu_open): Update prototype.
997 (cpu_open_1): Declare.
998 (cgen_set_cpu): Delete.
1002 * cgen.h (CGEN_HW_TABLE): Delete `num_init_entries' member.
1003 (CGEN_OPERAND_NIL): New macro.
1004 (CGEN_OPERAND): New member `type'.
1005 (@arch@_cgen_operand_table): Delete decl.
1006 (CGEN_OPERAND_INDEX,CGEN_OPERAND_TYPE,CGEN_OPERAND_ENTRY): Delete.
1007 (CGEN_OPERAND_TABLE): New struct.
1008 (cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): Declare.
1009 (CGEN_OPINST): Pointer to operand table entry replaced with enum.
1010 (CGEN_CPU_TABLE): New member `isa'. Change member `operand_table',
1011 now a CGEN_OPERAND_TABLE. Add CGEN_CPU_DESC arg to
1012 {get,set}_{int,vma}_operand.
1013 (@arch@_cgen_cpu_open): New arg `isa'.
1014 (cgen_set_cpu): Ditto.
1018 * i386.h: Fill in cmov and fcmov alternates. Add fcomi short forms.
1022 * cgen.h (enum cgen_asm_type): Add CGEN_ASM_NONE.
1023 (CGEN_HW_ENTRY): Delete member `next'. Change type of `type' to
1025 (CGEN_HW_TABLE): New struct.
1026 (hw_table): Delete declaration.
1027 (CGEN_OPERAND): Change member hw to hw_type, change type from pointer
1028 to table entry to enum.
1029 (CGEN_OPINST): Ditto.
1030 (CGEN_CPU_TABLE): Change member hw_list to hw_table.
1034 * alpha.h (AXP_OPCODE_EV6): New.
1035 (AXP_OPCODE_NOPAL): Include it.
1039 * cgen.h (CGEN_CPU_DESC): Renamed from CGEN_OPCODE_DESC.
1040 All uses updated. New members int_insn_p, max_insn_size,
1041 parse_operand,insert_operand,extract_operand,print_operand,
1042 sizeof_fields,set_fields_bitsize,get_int_operand,set_int_operand,
1043 get_vma_operand,set_vma_operand,parse_handlers,insert_handlers,
1044 extract_handlers,print_handlers.
1045 (CGEN_ATTR): Change type of num_nonbools to unsigned int.
1046 (CGEN_ATTR_BOOL_OFFSET): New macro.
1047 (CGEN_ATTR_MASK): Subtract it to compute bit number.
1048 (CGEN_ATTR_VALUE): Redo bool/nonbool attr calculation.
1049 (cgen_opcode_handler): Renamed from cgen_base.
1050 (CGEN_HW_ATTR_VALUE): Renamed from CGEN_HW_ATTR, all uses updated.
1051 (CGEN_OPERAND_ATTR_VALUE): Renamed from CGEN_OPERAND_ATTR,
1053 (CGEN_OPERAND_INDEX): Rewrite to use table entry, not global.
1054 (enum cgen_opinst_type): Renamed from cgen_operand_instance_type.
1055 (CGEN_IFLD_ATTR_VALUE): Renamed from CGEN_IFLD_ATTR, all uses updated.
1056 (CGEN_OPCODE,CGEN_IBASE): New types.
1057 (CGEN_INSN): Rewrite.
1058 (CGEN_{ASM,DIS}_HASH*): Delete.
1059 (init_opcode_table,init_ibld_table): Declare.
1060 (CGEN_INSN_ATTR): New type.
1064 * i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define.
1065 (x_FP, d_FP, dls_FP, sldx_FP): Define.
1066 Change *Suf definitions to include x and d suffixes.
1067 (movsx): Use w_Suf and b_Suf.
1069 (movs): Use bwld_Suf.
1070 (fld): Change ordering. Use sld_FP.
1071 (fild): Add Intel Syntax equivalent of fildq.
1074 (fstp): Use sld_FP. Add x_FP version.
1075 (fistp): LLongMem version for Intel Syntax.
1076 (fcom, fcomp): Use sld_FP.
1077 (fadd, fiadd, fsub): Use sld_FP.
1078 (fsubr): Use sld_FP.
1079 (fmul, fimul, fdvi, fidiv, fdivr): Use sld_FP.
1083 * cgen.h (enum cgen_mode): Add CGEN_MODE_TARGET_MAX, CGEN_MODE_INT,
1088 * hppa.h (bv): Fix mask.
1092 * cgen.h (CGEN_ATTR_VALUE_TYPE): New typedef.
1093 (CGEN_ATTR): Use it.
1094 (CGEN_ATTR_TYPE,CGEN_ATTR_ENTRY): Ditto.
1095 (CGEN_ATTR_TABLE): New member dfault.
1099 * mips.h (MIPS16_INSN_BRANCH): New.
1103 The following is part of a change made by Edith Epstein
1105 changes by HP; HP did not create ChangeLog entries.
1107 * hppa.h (completer_chars): list of chars to not put a space
1112 * i386.h (i386_optab): Permit w suffix on processor control and
1113 status word instructions.
1117 * cgen.h (struct cgen_hw_entry): Delete const on attrs member.
1118 (struct cgen_keyword_entry): Ditto.
1119 (struct cgen_operand): Ditto.
1120 (CGEN_IFLD): New typedef, with associated access macros.
1121 (CGEN_IFMT): New typedef, with associated access macros.
1122 (CGEN_IFMT): Renamed from CGEN_FORMAT. New member `iflds'.
1123 (CGEN_IVALUE): New typedef.
1124 (struct cgen_insn): Delete const on syntax,attrs members.
1125 `format' now points to format data. Type of `value' is now
1127 (struct cgen_opcode_table): New member ifld_table.
1131 * cgen.h (cgen_extract_fn): Update type of `base_insn' arg.
1132 (CGEN_OPERAND_INSTANCE): New member `attrs'.
1133 (CGEN_OPERAND_INSTANCE_{ATTRS,ATTR}): New macros.
1134 (cgen_dis_lookup_insn): Update type of `base_insn' arg.
1135 (cgen_opcode_table): Update type of dis_hash fn.
1136 (extract_operand): Update type of `insn_value' arg.
1140 * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Delete.
1144 * mips.h (INSN_MULT): Added.
1148 * i386.h (MAX_MNEM_SIZE): Rename from MAX_OPCODE_SIZE.
1152 * cgen.h (CGEN_INSN_INT): New typedef.
1153 (CGEN_INT_INSN_P): Renamed from CGEN_INT_INSN.
1154 (CGEN_INSN_BYTES): Renamed from cgen_insn_t.
1155 (CGEN_INSN_BYTES_PTR): New typedef.
1156 (CGEN_EXTRACT_INFO): New typedef.
1157 (cgen_insert_fn,cgen_extract_fn): Update.
1158 (cgen_opcode_table): New member `insn_endian'.
1159 (assemble_insn,lookup_insn,lookup_get_insn_operands): Update.
1160 (insert_operand,extract_operand): Update.
1161 (cgen_get_insn_value,cgen_put_insn_value): Add prototypes.
1165 * cgen.h (CGEN_ATTR_BOOLS): New macro.
1166 (struct CGEN_HW_ENTRY): New member `attrs'.
1167 (CGEN_HW_ATTR): New macro.
1168 (struct CGEN_OPERAND_INSTANCE): New member `name'.
1169 (CGEN_INSN_INVALID_P): New macro.
1173 * hppa.h: Add "fid".
1178 * i386.h (i386_optab): Add AMD 3DNow! instructions.
1179 (AMD_3DNOW_OPCODE): Define.
1183 * d30v.h (EITHER_BUT_PREFER_MU): Define.
1187 * cgen.h (cgen_insn): #if 0 out element `cdx'.
1191 Move all global state data into opcode table struct, and treat
1192 opcode table as something that is "opened/closed".
1193 * cgen.h (CGEN_OPCODE_DESC): New type.
1194 (all fns): New first arg of opcode table descriptor.
1195 (cgen_set_parse_operand_fn): Add prototype.
1196 (cgen_current_machine,cgen_current_endian): Delete.
1197 (CGEN_OPCODE_TABLE): New members mach,endian,operand_table,
1198 parse_operand_fn,asm_hash_table,asm_hash_table_entries,
1199 dis_hash_table,dis_hash_table_entries.
1200 (opcode_open,opcode_close): Add prototypes.
1202 * cgen.h (cgen_insn): New element `cdx'.
1206 * d30v.h (FLAG_LKR): New flag for "left-kills-right" instructions.
1210 * mn10300.h: Add "no_match_operands" field for instructions.
1211 (MN10300_MAX_OPERANDS): Define.
1215 * cgen.h (cgen_macro_insn_count): Declare.
1219 * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Define.
1220 (cgen_insert_fn,cgen_extract_fn): New arg `pc'.
1221 (get_operand,put_operand): Replaced with get_{int,vma}_operand,
1222 set_{int,vma}_operand.
1226 * mn10300.h: Add "machine" field for instructions.
1227 (MN103, AM30): Define machine types.
1231 * i386.h: Use FP, not sl_Suf, for fxsave and fxrstor.
1235 * i386.h: Add support for fxsave, fxrstor, sysenter and sysexit.
1239 * i386.h (i386_optab): Add general form of aad and aam. Add ud2a
1241 (i386_regtab): Allow cr0..7, db0..7, dr0..7, tr0..7, not just
1242 those that happen to be implemented on pentiums.
1246 * i386.h: Change occurences of Data16 to Size16, Data32 to Size32,
1247 IgnoreDataSize to IgnoreSize. Flag address and data size prefixes
1248 with Size16|IgnoreSize or Size32|IgnoreSize.
1252 * i386.h (REPNE): Rename to REPNE_PREFIX_OPCODE.
1253 (REPE): Rename to REPE_PREFIX_OPCODE.
1254 (i386_regtab_end): Remove.
1255 (i386_prefixtab, i386_prefixtab_end): Remove.
1256 (i386_optab): Use NULL as sentinel rather than "" to suit rewrite
1258 (MAX_OPCODE_SIZE): Define.
1259 (i386_optab_end): Remove.
1261 (sl_FP): Use sl_Suf.
1263 * i386.h (i386_optab): Allow 16 bit displacement for `mov
1264 mem,acc'. Combine 16 and 32 bit forms of various insns. Allow 16
1265 bit form of ljmp. Add IsPrefix modifier to prefixes. Add addr32,
1266 data32, dword, and adword prefixes.
1267 (i386_regtab): Add BaseIndex modifier to valid 16 bit base/index
1272 * i386.h (i386_regtab): Remove BaseIndex modifier from esp.
1274 * i386.h: Allow `l' suffix on fld, fst, fstp, fcom, fcomp with
1275 register operands, because this is a common idiom. Flag them with
1276 a warning. Allow illegal faddp, fsubp, fsubrp, fmulp, fdivp,
1277 fdivrp because gcc erroneously generates them. Also flag with a
1280 * i386.h: Add suffix modifiers to most insns, and tighter operand
1281 checks in some cases. Fix a number of UnixWare compatibility
1282 issues with float insns. Merge some floating point opcodes, using
1283 new FloatMF modifier.
1284 (WORD_PREFIX_OPCODE): Rename to DATA_PREFIX_OPCODE for
1287 * i386.h: Change occurence of ShortformW to W|ShortForm. Add
1288 IgnoreDataSize where appropriate.
1292 * i386.h: (one_byte_segment_defaults): Remove.
1293 (two_byte_segment_defaults): Remove.
1294 (i386_regtab): Add BaseIndex to 32 bit regs reg_type.
1298 * cgen.h (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup.
1299 (cgen_hw_lookup_by_num): Declare.
1303 * mips.h (OP_{SH,MASK}_CODE2): Added "q" operand format for lower
1304 ten bits of MIPS ISA1 "break" instruction, and for "sdbbp"
1308 * cgen.h (cgen_asm_init_parse): Delete.
1309 (cgen_save_fixups,cgen_restore_fixups,cgen_swap_fixups): Delete.
1310 (cgen_asm_record_register,cgen_asm_finish_insn): Delete.
1314 * cgen.h (CGEN_ATTR_TYPE): Delete `const', moved to uses.
1315 (cgen_asm_finish_insn): Update prototype.
1316 (cgen_insn): New members num, data.
1317 (CGEN_INSN_TABLE): Members asm_hash, asm_hash_table_size,
1318 dis_hash, dis_hash_table_size moved to ...
1319 (CGEN_OPCODE_TABLE). Here. Renamed from CGEN_OPCODE_DATA.
1320 All uses updated. New members asm_hash_p, dis_hash_p.
1321 (CGEN_MINSN_EXPANSION): New struct.
1322 (cgen_expand_macro_insn): Declare.
1323 (cgen_macro_insn_count): Declare.
1324 (get_insn_operands): Update prototype.
1325 (lookup_get_insn_operands): Declare.
1329 * i386.h (i386_optab): Change iclrKludge and imulKludge to
1330 regKludge. Add operands types for string instructions.
1334 * i386.h (X): Renamed from `Z_' to preserve formatting of opcode
1339 * i386.h (Z_): Renamed from `_' to avoid clash with common alias
1344 * i386.h: Remove NoModrm flag from all insns: it's never checked.
1345 Add IsString flag to string instructions.
1346 (IS_STRING): Don't define.
1347 (LOCK_PREFIX_OPCODE, CS_PREFIX_OPCODE, DS_PREFIX_OPCODE): Define.
1348 (ES_PREFIX_OPCODE, FS_PREFIX_OPCODE, GS_PREFIX_OPCODE): Define.
1349 (SS_PREFIX_OPCODE): Define.
1353 * i386.h: Revert March 24 patch; no more LinearAddress.
1357 * i386.h (i386_optab): Remove fwait (9b) from all floating point
1358 instructions, and instead add FWait opcode modifier. Add short
1359 form of fldenv and fstenv.
1360 (FWAIT_OPCODE): Define.
1362 * i386.h (i386_optab): Change second operand constraint of `mov
1363 sreg,reg|mem' instruction from Reg16|Mem to WordReg|WordMem to
1364 allow legal instructions such as `movl %gs,%esi'
1368 * h8300.h: Various changes to fully bracket initializers.
1372 * i386.h: Set LinearAddress for lidt and lgdt.
1376 * cgen.h (CGEN_BOOL_ATTR): New macro.
1380 * d30v.h (FLAG_DELAY): New flag for delayed branches/jumps.
1384 * cgen.h (CGEN_CAT3): Delete. Use CONCAT3 now.
1385 (cgen_insn): Record syntax and format entries here, rather than
1390 * cgen.h (CGEN_SYNTAX_MAKE_FIELD): New macro.
1394 * cgen.h (cgen_insert_fn): Change type of result to const char *.
1395 (cgen_parse_{signed,unsigned}_integer): Delete min,max arguments.
1396 (CGEN_{INSN,KEYWORD,OPERAND}_NBOOL_ATTRS): Renamed from ..._MAX_ATTRS.
1400 * cgen.h (lookup_insn): New argument alias_p.
1404 Fix rac to accept only a0:
1405 * d10v.h (OPERAND_ACC): Split into:
1406 (OPERAND_ACC0, OPERAND_ACC1) .
1407 (OPERAND_GPR): Define.
1411 * cgen.h (CGEN_FIELDS): Define here.
1412 (CGEN_HW_ENTRY): New member `type'.
1413 (hw_list): Delete decl.
1414 (enum cgen_mode): Declare.
1415 (CGEN_OPERAND): New member `hw'.
1416 (enum cgen_operand_instance_type): Declare.
1417 (CGEN_OPERAND_INSTANCE): New type.
1418 (CGEN_INSN): New member `operands'.
1419 (CGEN_OPCODE_DATA): Make hw_list const.
1420 (get_insn_operands,lookup_insn): Add prototypes for.
1424 * cgen.h (CGEN_INSN_MAX_ATTRS): Renamed from CGEN_MAX_INSN_ATTRS.
1425 (CGEN_HW_ENTRY): Move `next' entry to end of struct.
1426 (CGEN_KEYWORD_MAX_ATTRS): Renamed from CGEN_MAX_KEYWORD_ATTRS.
1427 (CGEN_OPERAND_MAX_ATTRS): Renamed from CGEN_MAX_OPERAND_ATTRS.
1431 * cgen.h: Correct typo in comment end marker.
1435 * tic30.h: New file.
1439 * cgen.h: Add prototypes for cgen_save_fixups(),
1440 cgen_restore_fixups(), and cgen_swap_fixups(). Change prototype
1441 of cgen_asm_finish_insn() to return a char *.
1445 * cgen.h: Formatting changes to improve readability.
1449 * cgen.h (*): Clean up pass over `struct foo' usage.
1450 (CGEN_ATTR): Make unsigned char.
1451 (CGEN_ATTR_TYPE): Update.
1452 (CGEN_ATTR_{ENTRY,TABLE}): New types.
1453 (cgen_base): Move member `attrs' to cgen_insn.
1454 (CGEN_KEYWORD): New member `null_entry'.
1455 (CGEN_{SYNTAX,FORMAT}): New types.
1456 (cgen_insn): Format and syntax separated from each other.
1460 * d30v.h (d30v_opcode): Reorder flags somewhat, add new flags for
1461 2 word load/store, ADDppp/SUBppp, 16/32 bit multiply. Make
1462 flags_{used,set} long.
1463 (d30v_operand): Make flags field long.
1467 * m68k.h: Fix comment describing operand types.
1471 * d30v.h (SHORT_CMPU): Add case for cmpu instruction, and move
1472 everything else after down.
1476 * d10v.h (OPERAND_FLAG): Split into:
1477 (OPERAND_FFLAG, OPERAND_CFLAG) .
1481 * mips.h (struct mips_opcode): Changed comments to reflect new
1486 * mips.h: Added to comments a quick-ref list of all assigned
1487 operand type characters.
1488 (OP_{MASK,SH}_PERFREG): New macros.
1492 * sparc.h: Add '_' and '/' for v9a asr's.
1497 * h8300.h: Bit ops with absolute addresses not in the 8 bit
1498 area are not available in the base model (H8/300).
1502 * m68k.h: Remove documentation of ` operand specifier.
1506 * m68k.h: Document q and v operand specifiers.
1510 * v850.h (struct v850_opcode): Add processors field.
1511 (PROCESSOR_V850, PROCESSOR_ALL): New bit constants.
1512 (PROCESSOR_V850E, PROCESSOR_NOT_V850): New bit constants.
1513 (PROCESSOR_V850EA): New bit constants.
1517 Merge changes from Martin Hunt:
1519 * d30v.h: Allow up to 64 control registers. Add
1522 * d30v.h (LONG_Db): New form for delayed branches.
1524 * d30v.h: (LONG_Db): New form for repeati.
1526 * d30v.h (SHORT_D2B): New form.
1528 * d30v.h (SHORT_A2): New form.
1530 * d30v.h (OPERAND_2REG): Add new operand to indicate 2
1531 registers are used. Needed for VLIW optimization.
1535 * cgen.h: Move assembler interface section
1536 up so cgen_parse_operand_result is defined for cgen_parse_address.
1537 (cgen_parse_address): Update prototype.
1541 * v850.h (V850_OPREAND_ADJUST_SHORT_MEMORY): Removed.
1545 * i386.h (two_byte_segment_defaults): Correct base register 5 in
1546 modes 1 and 2 to be ss rather than ds. From Gabriel Paubert
1549 * i386.h: Set ud2 to 0x0f0b. From Gabriel Paubert
1552 * i386.h: Comment fixes for ficom[p]?{s,l} from Gabriel Paubert
1555 * i386.h (JUMP_ON_CX_ZERO): Uncomment (define again).
1556 (JUMP_ON_ECX_ZERO): Remove commented out macro.
1560 * v850.h (V850_NOT_R0): New flag.
1564 * v850.h (struct v850_opcode): Remove flags field.
1568 * v850.h (struct v850_opcode): Add flags field.
1569 (struct v850_operand): Extend meaning of 'bits' and 'shift'
1571 (V850E_INSTRUCTION, V850EA_INSTRUCTION): New flags.
1572 (V850E_PUSH_POP, V850E_IMMEDIATE16, V850E_IMMEDIATE32): New flags.
1580 * sparc.h (sparc_opcodes): Declare as const.
1584 * mips.h (FP_S, FP_D): Define. Bitmasks indicating if an insn
1585 uses single or double precision floating point resources.
1586 (INSN_NO_ISA, INSN_ISA1): Define.
1587 (cpu specific INSN macros): Tweak into bitmasks outside the range
1592 * i386.h: Fix pand opcode.
1596 * mips.h: Widen INSN_ISA and move it to a more convenient
1597 bit position. Add INSN_3900.
1601 * mips.h (struct mips_opcode): added new field membership.
1605 * i386.h (movd): only Reg32 is allowed.
1607 * i386.h: add fcomp and ud2. From Wayne Scott
1612 * i386.h: Add MMX instructions.
1616 * i386.h: Remove W modifier from conditional move instructions.
1620 * i386.h: Change the opcodes for fsubp, fsubrp, fdivp, and fdivrp
1621 with no arguments to match that generated by the UnixWare
1626 * cgen.h (<cpu>_cgen_assemble_insn): New arg for errmsg.
1627 (cgen_parse_operand_fn): Declare.
1628 (cgen_init_parse_operand): Declare.
1629 (cgen_parse_operand): Renamed from cgen_asm_parse_operand,
1630 new argument `want'.
1631 (enum cgen_parse_operand_result): Renamed from cgen_asm_result.
1632 (enum cgen_parse_operand_type): New enum.
1636 * i386.h: Revert last patch for the NON_BROKEN_OPCODES cases.
1644 * i386.h: Correct opcode values for fsubp, fsubrp, fdivp, and
1649 * v850.h (extract): Make unsigned.
1657 * i386.h: Change DW to W for cmpxchg and xadd, since they don't
1658 take a direction bit.
1662 * sparc.h (sparc_opcode_lookup_arch): Use full prototype.
1666 * sparc.h: Include <ansidecl.h>. Update function declarations to
1667 use prototypes, and to use const when appropriate.
1671 * mn10300.h (MN10300_OPERAND_RELAX): Define.
1675 * d10v.h: Change pre_defined_registers to
1676 d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt.
1680 * mips.h: Add macros for cop0, cop1 cop2 and cop3.
1681 Change mips_opcodes from const array to a pointer,
1682 and change bfd_mips_num_opcodes from const int to int,
1683 so that we can increase the size of the mips opcodes table
1688 * d30v.h (FLAG_X): Remove unused flag.
1696 * tic80.h (PDS_NAME): Macro to access name field of predefined symbols.
1697 (PDS_VALUE): Macro to access value field of predefined symbols.
1698 (tic80_next_predefined_symbol): Add prototype.
1702 * tic80.h (tic80_symbol_to_value): Change prototype to match
1703 change in function, added class parameter.
1707 * tic80.h (TIC80_OPERAND_ENDMASK): Add for flagging TIc80
1708 endmask fields, which are somewhat weird in that 0 and 32 are
1709 treated exactly the same.
1713 * tic80.h: Change all the OPERAND defines to use the form (1 << X)
1714 rather than a constant that is 2**X. Reorder them to put bits for
1715 operands that have symbolic names in the upper bits, so they can
1716 be packed into an int where the lower bits contain the value that
1717 corresponds to that symbolic name.
1718 (predefined_symbo): Add struct.
1719 (tic80_predefined_symbols): Declare array of translations.
1720 (tic80_num_predefined_symbols): Declare size of that array.
1721 (tic80_value_to_symbol): Declare function.
1722 (tic80_symbol_to_value): Declare function.
1726 * mn10200.h (MN10200_OPERAND_RELAX): Define.
1730 * tic80.h (TIC80_NO_R0_DEST): Add for opcodes where r0 cannot
1731 be the destination register.
1735 * tic80.h (struct tic80_opcode): Change "format" field to "flags".
1736 (FMT_UNUSED, FMT_SI, FMT_LI, FMT_REG): Delete.
1737 (TIC80_VECTOR): Define a flag bit for the flags. This one means
1738 that the opcode can have two vector instructions in a single
1739 32 bit word and we have to encode/decode both.
1743 * tic80.h (TIC80_OPERAND_PCREL): Renamed from
1744 TIC80_OPERAND_RELATIVE for PC relative.
1745 (TIC80_OPERAND_BASEREL): New flag bit for register
1750 * tic80.h (TIC80_OPERAND_FLOAT): Add for floating point operands.
1754 * tic80.h (TIC80_OPERAND_SCALED): Operand may have optional
1755 ":s" modifier for scaling.
1759 * tic80.h (TIC80_OPERAND_M_SI): Add operand modifier for ":m".
1760 (TIC80_OPERAND_M_LI): Ditto
1764 * tic80.h (TIC80_OPERAND_BITNUM): Renamed from TIC80_OPERAND_CC_SZ.
1765 (TIC80_OPERAND_CC): New define for condition code operand.
1766 (TIC80_OPERAND_CR): New define for control register operand.
1770 * tic80.h (struct tic80_opcode): Name changed.
1771 (struct tic80_opcode): Remove format field.
1772 (struct tic80_operand): Add insertion and extraction functions.
1773 (TIC80_OPERAND_*): Remove old bogus values, start adding new
1779 * v850.h (V850_OPERAND_ADJUST_SHORT_MEMORY): New flag to adjust
1780 type IV instruction offsets.
1784 * tic80.h: New file.
1788 * mn10200.h (MN10200_OPERAND_NOCHECK): Define.
1792 * mn10200.h: Fix comment, mn10200_operand not powerpc_operand.
1793 * mn10300.h: Fix comment, mn10300_operand not powerpc_operand.
1794 * v850.h: Fix comment, v850_operand not powerpc_operand.
1798 * mn10200.h: Flesh out structures and definitions needed by
1799 the mn10200 assembler & disassembler.
1803 * mips.h: Add mips16 definitions.
1807 * m68k.h: Document new <, >, m, n, o and p operand specifiers.
1811 * mn10300.h (MN10300_OPERAND_PCREL): Define.
1812 (MN10300_OPERAND_MEMADDR): Define.
1816 * mn10300.h (MN10300_OPERAND_REG_LIST): Define.
1820 * mn10300.h (MN10300_OPERAND_SPLIT): Define.
1824 * mn10300.h (MN10300_OPERAND_EXTENDED): Define.
1828 * mn10300.h (MN10300_OPERAND_REPEATED): Define.
1832 * alpha.h: Don't include "bfd.h"; private relocation types are now
1833 negative to minimize problems with shared libraries. Organize
1834 instruction subsets by AMASK extensions and PALcode
1836 (struct alpha_operand): Move flags slot for better packing.
1840 * v850.h (V850_OPERAND_RELAX): New operand flag.
1844 * mn10300.h (FMT_*): Move operand format definitions
1849 * mn10300.h (MN10300_OPERAND_PAREN): Define.
1853 * mn10300.h (mn10300_opcode): Add "format" field.
1854 (MN10300_OPERAND_*): Define.
1858 * mn10x00.h: Delete.
1859 * mn10200.h, mn10300.h: New files.
1863 * mn10x00.h: New file.
1867 * v850.h: Add new flag to indicate this instruction uses a PC
1872 * h8300.h (stmac): Add missing instruction.
1876 * v850.h (v850_opcode): Remove "size" field. Add "memop"
1881 * v850.h (V850_OPERAND_EP): Define.
1883 * v850.h (v850_opcode): Add size field.
1887 * v850.h (v850_operands): Add insert and extract fields, pointers
1888 to functions used to handle unusual operand encoding.
1889 (V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC,
1890 V850_OPERAND_SIGNED): Defined.
1894 * v850.h (v850_operands): Add flags field.
1895 (OPERAND_REG, OPERAND_NUM): Defined.
1903 * mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM,
1904 OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC,
1905 OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT,
1906 OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE,
1907 OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT):
1912 * hppa.h (pitlb, pitlbe, iitlba, iitlbp, fic, fice): Accept
1913 a 3 bit space id instead of a 2 bit space id.
1917 * d10v.h: Add some additional defines to support the
1918 assembler in determining which operations can be done in parallel.
1922 * h8300.h (SN): Define.
1923 (eepmov.b): Renamed from "eepmov"
1924 (nop, bpt, rte, rts, sleep, clrmac): These have no size associated
1929 * d10v.h (OPERAND_SHIFT): New operand flag.
1933 * d10v.h: Changes for divs, parallel-only instructions, and
1938 * d10v.h (pd_reg): Define. Putting the definition here allows
1939 the assembler and disassembler to share the same struct.
1943 * i960.h (i960_opcodes): "halt" takes an argument. From Stephen
1952 * h8300.h (band, bclr): Force high bit of immediate nibble to zero.
1956 * m68k.h (mcf5200): New macro.
1957 Document names of coldfire control registers.
1961 * h8300.h (SRC_IN_DST): Define.
1963 * h8300.h (UNOP3): Mark the register operand in this insn
1964 as a source operand, not a destination operand.
1965 (SHIFT_2, SHIFT_IMM): Remove. Eliminate all references.
1966 (UNOP3): Change SHIFT_IMM to IMM for H8/S bitops. Mark
1967 register operand with SRC_IN_DST.
1971 * alpha.h: New file.
1975 * rs6k.h: Remove obsolete file.
1979 * i386.h: Correct opcode values for faddp, fsubp, fsubrp, fmulp,
1980 fdivp, and fdivrp. Add ffreep.
1984 * h8300.h: Reorder various #defines for readability.
1985 (ABS32SRC, ABS32DST, DSP32LIST, ABS32LIST, A32LIST): Define.
1986 (BITOP): Accept additional (unused) argument. All callers changed.
1989 (ldc, stc, movb, movw, movl): Use 32bit offsets and absolutes.
1991 * h8300.h (EXR, SHIFT_2, MACREG, SHIFT_IMM, RDINC): Define.
1992 (O_TAS, O_CLRMAC, O_LDMAC, O_MAC, O_LDM, O_STM): Define.
1993 (BITOP, EBITOP): Handle new H8/S addressing modes for
1995 (UNOP3): Handle new shift/rotate insns on the H8/S.
1996 (insns using exr): New instructions.
1997 (tas, mac, ldmac, clrmac, ldm, stm): New instructions.
2001 * h8300.h (add.l): Undo Apr 5th change. The manual I had
2006 * h8300.h (START): Remove.
2007 (MEMRELAX): Define. Mark absolute memory operands in mov.b, mov.w
2008 and mov.l insns that can be relaxed.
2012 * i386.h: Remove Abs32 from lcall.
2016 * sparc.h (SPARC_OPCODE_ARCH_V9_P): New macro.
2017 (SLCPOP): New macro.
2018 Mark X,Y opcode letters as in use.
2022 * sparc.h (F_FLOAT, F_FBR): Define.
2026 * h8300.h (ABS8MEM): Renamed from ABSMOV. Remove ABSMOV
2028 (ABS8SRC,ABS8DST): Add ABS8MEM.
2029 (add.l): Fix reg+reg variant.
2030 (eepmov.w): Renamed from eepmovw.
2031 (ldc,stc): Fix many cases.
2035 * sparc.h (SPARC_OPCODE_ARCH_MASK): New macro.
2039 * sparc.h (O): Mark operand letter as in use.
2043 * sparc.h (sparc_{encode,decode}_sparclet_cpreg): Declare.
2044 Mark operand letters uU as in use.
2048 * sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_SPARCLET.
2049 (sparc_opcode_arch): Delete member `conflicts'. Add `supported'.
2050 (SPARC_OPCODE_SUPPORTED): New macro.
2051 (SPARC_OPCODE_CONFLICT_P): Rewrite.
2056 * sparc.h (sparc_opcode_lookup_arch) Make return type in
2057 declaration consistent with return type in definition.
2061 * i386.h (i386_optab): Remove Data32 from pushf and popf.
2065 * i386.h (i386_regtab): Add 80486 test registers.
2069 * i960.h (I_HX): Define.
2070 (i960_opcodes): Add HX instruction.
2074 * i386.h: Fix waiting forms of finit, fstenv, fsave, fstsw, fstcw,
2079 * sparc.h (enum sparc_opcode_arch_val): Replaces sparc_architecture.
2080 (SPARC_OPCODE_CONFLICT_P): Renamed from ARCHITECTURES_CONFLICT_P.
2081 (bfd_* defines): Delete.
2082 (sparc_opcode_archs): Replaces architecture_pname.
2083 (sparc_opcode_lookup_arch): Declare.
2084 (NUMOPCODES): Delete.
2088 * sparc.h (enum sparc_architecture): Add v9a.
2089 (ARCHITECTURES_CONFLICT_P): Update.
2093 * i386.h: Added Pentium Pro instructions.
2097 * m68k.h: Document new 'W' operand place.
2101 * hppa.h: Add lci and syncdma instructions.
2105 * mips.h: Added INSN_4100 flag to mark NEC VR4100 specific
2110 * ppc.h (PPC_OPCODE_{COMMON,ANY}): New opcode flags for
2111 assembler's -mcom and -many switches.
2115 * i386.h: Fix cmpxchg8b extension opcode description.
2119 * i386.h: Add Pentium instructions wrmsr, rdtsc, rdmsr, cmpxchg8b,
2124 * m68k.h: Change comment: split type P into types 0, 1 and 2.
2128 * sparc.h (sparc_{encode,decode}_prefetch): Declare.
2132 * sparc.h (sparc_{encode,decode}_{asi,membar}): Declare.
2136 * m68kmri.h: Remove.
2138 * m68k.h: Move tables into opcodes/m68k-opc.c, leaving just the
2139 declarations. Remove F_ALIAS and flag field of struct
2140 m68k_opcode. Change arch field of struct m68k_opcode to unsigned
2141 int. Make name and args fields of struct m68k_opcode const.
2145 * sparc.h (F_NOTV9): Define.
2149 * mips.h (INSN_4010): Define.
2153 * m68k.h (TBL1): Reverse sense of "round" argument in result.
2156 * m68k.h: Fix argument descriptions of coprocessor
2157 instructions to allow only alterable operands where appropriate.
2158 [!NO_DEFAULT_SIZES]: An omitted size defaults to `w'.
2159 (m68k_opcode_aliases): Add more aliases.
2163 * m68k.h: Added explcitly short-sized conditional branches, and a
2164 bunch of aliases (fmov*, ftest*, tdivul) to support gcc's
2165 svr4-based configurations.
2170 * i386.h: added missing Data16/Data32 flags to a few instructions.
2174 * mips.h (OP_MASK_FR, OP_SH_FR): Define.
2175 (OP_MASK_BCC, OP_SH_BCC): Define.
2176 (OP_MASK_PREFX, OP_SH_PREFX): Define.
2177 (OP_MASK_CCC, OP_SH_CCC): Define.
2178 (INSN_READ_FPR_R): Define.
2183 * m68k.h (enum m68k_architecture): Deleted.
2184 (struct m68k_opcode_alias): New type.
2185 (m68k_opcodes): Now const. Deleted opcode aliases with exactly
2186 matching constraints, values and flags. As a side effect of this,
2187 the MOTOROLA_SYNTAX_ONLY and MIT_SYNTAX_ONLY macros, which so far
2188 as I know were never used, now may need re-examining.
2189 (numopcodes): Now const.
2190 (m68k_opcode_aliases, numaliases): New variables.
2192 [DONT_DEFINE_TABLE]: Declare numopcodes, numaliases, and
2193 m68k_opcode_aliases; update declaration of m68k_opcodes.
2197 * hppa.h (delay_type): Delete unused enumeration.
2198 (pa_opcode): Replace unused delayed field with an architecture
2200 (pa_opcodes): Mark each instruction as either PA1.0 or PA1.1.
2204 * mips.h (INSN_ISA4): Define.
2208 * mips.h (M_DLA_AB, M_DLI): Define.
2212 * hppa.h (fstwx): Fix single-bit error.
2216 * mips.h (M_ULD, M_ULD_A, M_USD, M_USD_A): Define.
2220 * i386.h: added cpuid instruction , and dr[0-7] aliases for the
2227 * i386.h (MOV_AX_DISP32): New macro.
2228 (i386_optab): Added Data16 and Data32 as needed. Added "w" forms
2229 of several call/return instructions.
2230 (ADDR_PREFIX_OPCODE): New macro.
2236 * vax.h (struct vot_wot, field `args'): Make it pointer to const
2238 (struct vot, field `name'): ditto.
2242 * vax.h: Supply and properly group all values in end sentinel.
2246 * mips.h (INSN_ISA, INSN_4650): Define.
2250 * a29k.h: Add operand type 'I' for `inv' and `iretinv'. On
2251 systems with a separate instruction and data cache, such as the
2252 29040, these instructions take an optional argument.
2256 * mips.h (INSN_STORE_MEMORY): Correct value to not conflict with
2261 * mips.h (INSN_STORE_MEMORY): Define.
2265 * sparc.h: Document new operand type 'x'.
2269 * i960.h (I_CX2): New instruction category. It includes
2270 instructions available on Cx and Jx processors.
2271 (I_JX): New instruction category, for JX-only instructions.
2272 (i960_opcodes): Put eshro and sysctl in I_CX2 category. Added
2273 Jx-only instructions, in I_JX category.
2277 * ns32k.h (endop): Made pointer const too.
2281 * ns32k.h: Drop Q operand type as there is no correct use
2282 for it. Add I and Z operand types which allow better checking.
2286 * h8300.h (xor.l) :fix bit pattern.
2287 (L_2): New size of operand.
2292 * m68k.h: Move "trap" before "tpcc" to change disassembly.
2296 * sparc.h: Include v9 definitions.
2300 * m68k.h (m68060): Defined.
2301 (m68040up, mfloat, mmmu): Include it.
2302 (struct m68k_opcode): Widen `arch' field.
2303 (m68k_opcodes): Updated for M68060. Removed comments that were
2304 instructions commented out by "JF" years ago.
2308 * m68k.h (struct m68k_opcode): Shorten `arch' field to 8 bits, and
2309 add a one-bit `flags' field.
2310 (F_ALIAS): New macro.
2314 * h8300.h (dec, inc): Get encoding right.
2318 * ppc.h (struct powerpc_operand): Removed signedp field; just use
2320 (PPC_OPERAND_SIGNED): Define.
2321 (PPC_OPERAND_SIGNOPT): Define.
2325 * i386.h (IS_JUMP_ON_ECX_ZERO, "jcxz" pattern): Operand size
2330 * i386.h: Reverse last change. It'll be handled in gas instead.
2334 * i386.h (sar): Disabled the two-operand Imm1 form, since it was
2335 slower on the 486 and used the implicit shift count despite the
2336 explicit operand. The one-operand form is still available to get
2337 the shorter form with the implicit shift count.
2341 * hppa.h: Fix typo in fstws arg string.
2345 * ppc.h (struct powerpc_opcode): Make operands field unsigned.
2349 * ppc.h (PPC_OPCODE_601): Define.
2353 * hppa.h (addb): Use '@' for addb and addib pseudo ops.
2354 (so we can determine valid completers for both addb and addb[tf].)
2356 * hppa.h (xmpyu): No floating point format specifier for the
2361 * ppc.h (PPC_OPERAND_NEXT): Define.
2362 (PPC_OPERAND_NEGATIVE): Change value to make room for above.
2363 (struct powerpc_macro): Define.
2364 (powerpc_macros, powerpc_num_macros): Declare.
2368 * ppc.h: New file. Header file for PowerPC opcode table.
2372 * hppa.h: More minor template fixes for sfu and copr (to allow
2373 for easier disassembly).
2375 * hppa.h: Fix templates for all the sfu and copr instructions.
2379 * i386.h (push): Permit Imm16 operand too.
2383 * h8300.h (andc): Exists in base arch.
2388 * hppa.h: #undef NONE to avoid conflict with hiux include files.
2392 * hppa.h: Add FP quadword store instructions.
2396 * mips.h: (M_J_A): Added.
2401 * mips.h (OP_MASK_CACHE, OP_SH_CACHE): Define. From Ted Lemon
2406 * hppa.h: Immediate field in probei instructions is unsigned,
2407 not low-sign extended.
2411 * m88k.h (RRI10MASK): Change from 0xfc00ffe0 to 0xfc00fc00.
2415 * i386.h: Add "fxch" without operand.
2419 * mips.h (M_JAL_1, M_JAL_2, M_JAL_A): Added.
2423 * hppa.h: Add gfw and gfr to the opcode table.
2427 * m88k.h: extended to handle m88110.
2431 * hppa.h (be, ble): Use operand type 'z' to denote absolute branch
2436 * i960.h (i960_opcodes): Properly bracket initializers.
2440 * m88k.h (BOFLAG): rewrite to avoid nested comment.
2444 * m68k.h (two): Protect second argument with parentheses.
2448 * i386.h (i386_optab): Added new instruction "rsm" (for i386sl).
2449 Deleted old in/out instructions in "#if 0" section.
2453 * i386.h (i386_optab): Properly bracket initializers.
2457 * hppa.h (pa_opcode): Use '|' for movb and movib insns. (From
2462 * i386.h (lcall): Accept Imm32 operand also.
2466 * mips.h (M_ABSU): Removed (absolute value of unsigned number??).
2471 * mips.h (INSN_*): Changed values. Removed unused definitions.
2472 Added INSN_COND_BRANCH_LIKELY, INSN_ISA2 and INSN_ISA3. Split
2473 INSN_LOAD_DELAY into INSN_LOAD_MEMORY_DELAY and
2474 INSN_LOAD_COPROC_DELAY. Split INSN_COPROC_DELAY into
2475 INSN_COPROC_MOVE_DELAY and INSN_COPROC_MEMORY_DELAY.
2476 (M_*): Added new values for r6000 and r4000 macros.
2477 (ANY_DELAY): Removed.
2481 * mips.h: Added M_LI_S and M_LI_SS.
2485 * h8300.h: Get some rare mov.bs correct.
2489 * sparc.h: Don't define const ourself; rely on ansidecl.h having
2494 * sparc.h (F_JSR, F_UNBR, F_CONDBR): Add new flags to mark
2495 jump instructions, for use in disassemblers.
2499 * m88k.h: Make bitfields just unsigned, not unsigned long or
2504 * hppa.h: New argument type 'y'. Use in various float instructions.
2508 * hppa.h (break): First immediate field is unsigned.
2510 * hppa.h: Add rfir instruction.
2514 * mips.h: Split the actual table out into ../../opcodes/mips-opc.c.
2518 * mips.h: Reworked the hazard information somewhat, and fixed some
2519 bugs in the instruction hazard descriptions.
2523 * m88k.h: Corrected a couple of opcodes.
2527 * mips.h: Replaced with version from Ralph Campbell and OSF. The
2528 new version includes instruction hazard information, but is
2529 otherwise reasonably similar.
2533 * h8300.h: Fix typo in UNOP3 (affected sh[al][lr].l).
2538 * hppa.h: Clean up some of the OLD_TABLE, non-OLD_TABLE braindamage.
2539 Make the tables be the same for the following instructions:
2540 "bb", "addb[tf]", "addib[tf]", "add", "add[loc]", "addco",
2541 "sh[123]add", "sh[123]add[lo]", "sub", "sub[obt]", "sub[bt]o",
2542 "ds", "comclr", "addi", "addi[ot]", "addito", "subi", "subio",
2543 "comiclr", "fadd", "fsub", "fmpy", "fdiv", "fsqrt", "fabs",
2544 "frnd", "fcpy", "fcnvff", "fcnvxf", "fcnvfx", "fcnvfxt",
2545 "fcmp", and "ftest".
2547 * hppa.h: Make new and old tables the same for "break", "mtctl",
2548 "mfctl", "bb", "ssm", "rsm", "xmpyu", "fmpyadd", "fmpysub".
2549 Fix typo in last patch. Collapse several #ifdefs into a
2552 * hppa.h: Delete remaining OLD_TABLE code. Bring some
2553 of the comments up-to-date.
2555 * hppa.h: Update "free list" of letters and update
2556 comments describing each letter's function.
2560 * h8300.h: Lots of little fixes for the h8/300h.
2564 Support for H8/300-H
2565 * h8300.h: Lots of new opcodes.
2569 * h8300.h: checkpoint, includes H8/300-H opcodes.
2574 * hppa.h: Rework single precision FP
2575 instructions so that they correctly disassemble code
2580 * i386.h (i386_optab, mov pattern): Remove Mem16 restriction from
2581 mov to allow instructions like mov ss,xyz(ecx) to assemble.
2585 * hppa.h: Use new version from Utah if OLD_TABLE isn't defined;
2586 gdb will define it for now.
2590 * sparc.h: Don't end enumerator list with comma.
2595 * mips.h (OP_MASK_COPZ, OP_SH_COPZ): Define.
2596 ("bc2t"): Correct typo.
2597 ("[ls]wc[023]"): Use T rather than t.
2598 ("c[0123]"): Define general coprocessor instructions.
2602 * m68k.h: Move split point for gcc compilation more towards
2607 * rs6k.h: Clean up instructions for primary opcode 19 (many were
2608 simply wrong, ics, rfi, & rfsvc were missing).
2609 Add "a" to opr_ext for "bb". Doc fix.
2614 * mips.h: Add casts, to suppress warnings about shifting too much.
2615 * m68k.h: Document the placement code '9'.
2619 * m68k.h (BREAK_UP_BIG_DECL, AND_OTHER_PART): Add kludge which
2620 allows callers to break up the large initialized struct full of
2621 opcodes into two half-sized ones. This permits GCC to compile
2622 this module, since it takes exponential space for initializers.
2623 (numopcodes, endop): Revise to use AND_OTHER_PART in size calcs.
2627 * a29k.h: Remove RCS crud, update GPL to v2, update copyrights.
2628 * convex.h: Added, from GDB's convx-opcode.h. Added CONST to all
2629 initialized structs in it.
2634 * m88k.h (PMEM): Avoid previous definition from <sys/param.h>.
2635 (AND): Change to AND_ to avoid ansidecl.h `AND' conflict.
2639 * mips.h: document "i" and "j" operands correctly.
2643 * mips.h: Removed endianness dependency.
2647 * h8300.h: include info on number of cycles per instruction.
2649 Mon Dec 21 21:29:08 1992 Stu Grossman (grossman at cygnus.com)
2651 * hppa.h: Move handy aliases to the front. Fix masks for extract
2652 and deposit instructions.
2656 * i386.h: accept shld and shrd both with and without the shift
2657 count argument, which is always %cl.
2659 Fri Nov 27 17:13:18 1992 Ken Raeburn (raeburn at cygnus.com)
2661 * i386.h (i386_optab_end, i386_regtab_end): Now const.
2662 (one_byte_segment_defaults, two_byte_segment_defaults,
2663 i386_prefixtab_end): Ditto.
2667 * vax.h (bb*): Use "v" (bitfield type), not "a" (address operand)
2672 * m68k.h: Define FIXED_SIZE_BRANCH, so bsr and bra instructions
2673 always use 16-bit offsets. Makes calculated-size jump tables
2678 * i386.h: Fix one-operand forms of in* and out* patterns.
2682 * m68k.h: Added CPU32 support.
2686 * mips.h (break): Disassemble the argument. Patch from
2691 * m68k.h: merged Motorola and MIT syntax.
2695 * m68k.h (pmove): make the tests less strict, the 68k book is
2700 * m68k.h (m68ec030): Defined as alias for 68030.
2701 (m68k_opcodes): New type characters "3" for 68030 MMU regs and "t"
2702 for immediate 0-7 added. Set up some opcodes (ptest, bkpt) to use
2703 them. Tightened description of "fmovex" to distinguish it from
2704 some "pmove" encodings. Added "pmove" for 68030 MMU regs, cleaned
2705 up descriptions that claimed versions were available for chips not
2706 supporting them. Added "pmovefd".
2710 * m68k.h: fix where the . goes in divull
2714 * m68k.h: the cas2 instruction is supposed to be written with
2715 indirection on the last two operands, which can be either data or
2716 address registers. Added a new operand type 'r' which accepts
2717 either register type. Added new cases for cas2l and cas2w which
2718 use them. Corrected masks for cas2 which failed to recognize use
2719 of address register.
2723 * m68k.h: Merged in patches (mostly m68040-specific) from
2726 * m68k.h: Merged m68kmri.h and m68k.h (using the former as a
2727 base). Also cleaned up duplicates, re-ordered instructions for
2728 the sake of dis-assembling (so aliases come after standard names).
2729 * m68kmri.h: Now just defines some macros, and #includes m68k.h.
2733 * m68kmri.h: added various opcodes. Moved jbxx to bxxes. Filled in
2738 * sparc.h: Moved tables to BFD library.
2740 * i386.h (i386_optab): Add fildq, fistpq aliases used by gcc.
2744 * h8300.h: Finish filling in all the holes in the opcode table,
2745 so that the Lucid C compiler can digest this as well...
2747 Fri Jun 26 21:27:17 1992 John Gilmore (gnu at cygnus.com)
2749 * i386.h: Add setc, setnc, addr16, data16, repz, repnz aliases.
2750 Fix opcodes on various sizes of fild/fist instructions
2751 (16bit=no suffix, 32bit="l" suffix, 64bit="ll" suffix).
2752 Use tabs to indent for comments. Fixes suggested by Minh Tran-Le.
2754 Thu Jun 25 16:13:26 1992 Stu Grossman (grossman at cygnus.com)
2756 * h8300.h: Fill in all the holes in the opcode table so that the
2757 losing HPUX C compiler can digest this...
2759 Thu Jun 11 12:15:25 1992 John Gilmore (gnu at cygnus.com)
2761 * mips.h: Fix decoding of coprocessor instructions, somewhat.
2766 * sparc.h: Add new architecture variant sparclite; add its scan
2767 and divscc opcodes. Define ARCHITECTURES_CONFLICT_P macro.
2771 * mips.h: Add some more opcode synonyms (from Frank Yellin,
2776 * rs6k.h: New version from IBM (Metin).
2780 * rs6k.h: Fix incorrect extended opcode for instructions `fm'
2783 Tue Apr 7 13:38:47 1992 Stu Grossman (grossman at cygnus.com)
2785 * rs6k.h: Move from ../../gdb/rs6k-opcode.h.
2789 * m68k.h (one, two): Cast macro args to unsigned to suppress
2790 complaints from compiler and lint about integer overflow during
2793 Sun Mar 29 12:22:08 1992 John Gilmore (gnu at cygnus.com)
2795 * sparc.h (OP): Avoid signed overflow when shifting to high order bit.
2797 Fri Mar 6 00:22:38 1992 John Gilmore (gnu at cygnus.com)
2799 * mips.h: Make bitfield layout depend on the HOST compiler,
2800 not on the TARGET system.
2804 * i386.h: added inb, inw, outb, outw opcodes, added att syntax for
2805 scmp, slod, smov, ssca, ssto. Curtesy Minh Tran-Le
2808 Thu Jan 30 07:31:44 1992 Steve Chamberlain (sac at rtl.cygnus.com)
2810 * h8300.h: turned op_type enum into #define list
2812 Thu Jan 30 01:07:24 1992 John Gilmore (gnu at cygnus.com)
2814 * sparc.h: Remove "cypress" architecture. Remove "fitox" and
2815 similar instructions -- they've been renamed to "fitoq", etc.
2816 REALLY fix tsubcctv. Fix "fcmpeq" and "fcmpq" which had wrong
2817 number of arguments.
2818 * h8300.h: Remove extra ; which produces compiler warning.
2820 Tue Jan 28 22:59:22 1992 Stu Grossman (grossman at cygnus.com)
2822 * sparc.h: fix opcode for tsubcctv.
2824 Tue Jan 7 17:19:39 1992 K. Richard Pixley (rich at cygnus.com)
2826 * sparc.h: fba and cba are now aliases for fb and cb respectively.
2828 Fri Dec 27 10:55:50 1991 Per Bothner (bothner at cygnus.com)
2830 * sparc.h (nop): Made the 'lose' field be even tighter,
2831 so only a standard 'nop' is disassembled as a nop.
2833 Sun Dec 22 12:18:18 1991 Michael Tiemann (tiemann at cygnus.com)
2835 * sparc.h (nop): Add RD_GO to `lose' so that only %g0 in dest is
2836 disassembled as a nop.
2838 Wed Dec 18 17:19:44 1991 Stu Grossman (grossman at cygnus.com)
2840 * m68k.h, sparc.h: ANSIfy enums.
2842 Tue Dec 10 00:22:20 1991 K. Richard Pixley (rich at rtl.cygnus.com)
2844 * sparc.h: fix a typo.
2846 Sat Nov 30 20:40:51 1991 Steve Chamberlain (sac at rtl.cygnus.com)
2848 * a29k.h, arm.h, h8300.h, i386.h, i860.h, i960.h , m68k.h,
2849 m88k.h, mips.h , np1.h, ns32k.h, pn.h, pyr.h, sparc.h, tahoe.h,
2850 vax.h: Renamed from ../<foo>-opcode.h.
2854 version-control: never