3 * tic54x-dis.c (sprint_mmr): Adjust.
4 * tic54x-opc.c: Likewise.
8 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
12 * ppc-opc.c: Formatting.
14 (powerpc_opcodes <subis>): Use NSISIGNOPT.
18 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
19 replacing references to `micromips_ase' throughout.
20 (_print_insn_mips): Don't use file-level microMIPS annotation to
21 determine the disassembly mode with the symbol table.
25 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
29 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
31 * mips-opc.c (D34): New macro.
32 (mips_builtin_opcodes): Define bposge32c for DSPr3.
36 * i386-dis.c (prefix_table): Add RDPID instruction.
37 * i386-gen.c (cpu_flag_init): Add RDPID flag.
38 (cpu_flags): Add RDPID bitfield.
39 * i386-opc.h (enum): Add RDPID element.
40 (i386_cpu_flags): Add RDPID field.
41 * i386-opc.tbl: Add RDPID instruction.
42 * i386-init.h: Regenerate.
43 * i386-tbl.h: Regenerate.
47 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
48 branch type of a symbol.
49 (print_insn): Likewise.
53 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
54 Mainline Security Extensions instructions.
55 (thumb_opcodes): Add entries for narrow ARMv8-M Security
56 Extensions instructions.
57 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
59 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
64 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
68 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
69 (arcExtMap_genOpcode): Likewise.
70 * arc-opc.c (arg_32bit_rc): Define new variable.
71 (arg_32bit_u6): Likewise.
72 (arg_32bit_limm): Likewise.
76 * aarch64-gen.c (VERIFIER): Define.
77 * aarch64-opc.c (VERIFIER): Define.
78 (verify_ldpsw): Use static linkage.
79 * aarch64-opc.h (verify_ldpsw): Remove.
80 * aarch64-tbl.h: Use VERIFIER for verifiers.
85 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
86 * aarch64-opc.c (verify_ldpsw): New function.
87 * aarch64-opc.h (verify_ldpsw): New prototype.
88 * aarch64-tbl.h: Add initialiser for verifier field.
89 (LDPSW): Set verifier to verify_ldpsw.
95 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
96 smaller than address size.
100 * alpha-dis.c: Regenerate.
101 * crx-dis.c: Likewise.
102 * disassemble.c: Likewise.
103 * epiphany-opc.c: Likewise.
104 * fr30-opc.c: Likewise.
105 * frv-opc.c: Likewise.
106 * ip2k-opc.c: Likewise.
107 * iq2000-opc.c: Likewise.
108 * lm32-opc.c: Likewise.
109 * lm32-opinst.c: Likewise.
110 * m32c-opc.c: Likewise.
111 * m32r-opc.c: Likewise.
112 * m32r-opinst.c: Likewise.
113 * mep-opc.c: Likewise.
114 * mt-opc.c: Likewise.
115 * or1k-opc.c: Likewise.
116 * or1k-opinst.c: Likewise.
117 * tic80-opc.c: Likewise.
118 * xc16x-opc.c: Likewise.
119 * xstormy16-opc.c: Likewise.
123 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
124 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
125 calcsd, and calcxd instructions.
126 * arc-opc.c (insert_nps_bitop_size): Delete.
127 (extract_nps_bitop_size): Delete.
128 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
129 (extract_nps_qcmp_m3): Define.
130 (extract_nps_qcmp_m2): Define.
131 (extract_nps_qcmp_m1): Define.
132 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
133 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
134 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
135 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
136 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
141 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
145 * Makefile.in: Regenerated with automake 1.11.6.
146 * aclocal.m4: Likewise.
150 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
152 * arc-opc.c (insert_nps_cmem_uimm16): New function.
153 (extract_nps_cmem_uimm16): New function.
154 (arc_operands): Add NPS_XLDST_UIMM16 operand.
158 * arc-dis.c (arc_insn_length): New function.
159 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
160 (find_format): Change insnLen parameter to unsigned.
165 * v850-opc.c (v850_opcodes): Correct masks for long versions of
166 the LD.B and LD.BU instructions.
170 * arc-dis.c (find_format): Check for extension flags.
171 (print_flags): New function.
172 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
174 * arc-ext.c (arcExtMap_coreRegName): Use
175 LAST_EXTENSION_CORE_REGISTER.
176 (arcExtMap_coreReadWrite): Likewise.
177 (dump_ARC_extmap): Update printing.
178 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
179 (arc_aux_regs): Add cpu field.
180 * arc-regs.h: Add cpu field, lower case name aux registers.
184 * arc-tbl.h: Add rtsc, sleep with no arguments.
188 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
190 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
191 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
192 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
193 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
194 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
195 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
196 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
197 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
198 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
199 (arc_opcode arc_opcodes): Null terminate the array.
200 (arc_num_opcodes): Remove.
201 * arc-ext.h (INSERT_XOP): Define.
202 (extInstruction_t): Likewise.
203 (arcExtMap_instName): Delete.
204 (arcExtMap_insn): New function.
205 (arcExtMap_genOpcode): Likewise.
206 * arc-ext.c (ExtInstruction): Remove.
207 (create_map): Zero initialize instruction fields.
208 (arcExtMap_instName): Remove.
209 (arcExtMap_insn): New function.
210 (dump_ARC_extmap): More info while debuging.
211 (arcExtMap_genOpcode): New function.
212 * arc-dis.c (find_format): New function.
213 (print_insn_arc): Use find_format.
214 (arc_get_disassembler): Enable dump_ARC_extmap only when
219 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
220 instruction bits out.
224 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
225 * arc-opc.c (arc_flag_operands): Add new flags.
226 (arc_flag_classes): Add new classes.
230 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
234 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
235 encode1, rflt, crc16, and crc32 instructions.
236 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
237 (arc_flag_classes): Add C_NPS_R.
238 (insert_nps_bitop_size_2b): New function.
239 (extract_nps_bitop_size_2b): Likewise.
240 (insert_nps_bitop_uimm8): Likewise.
241 (extract_nps_bitop_uimm8): Likewise.
242 (arc_operands): Add new operand entries.
246 * arc-regs.h: Add a new subclass field. Add double assist
247 accumulator register values.
248 * arc-tbl.h: Use DPA subclass to mark the double assist
249 instructions. Use DPX/SPX subclas to mark the FPX instructions.
250 * arc-opc.c (RSP): Define instead of SP.
251 (arc_aux_regs): Add the subclass field.
255 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
259 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
264 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
265 issues. No functional changes.
269 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
270 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
271 (RTT): Remove duplicate.
272 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
273 (PCT_CONFIG*): Remove.
274 (D1L, D1H, D2H, D2L): Define.
278 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
282 * arc-tbl.h (invld07): Remove.
283 * arc-ext-tbl.h: New file.
284 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
285 * arc-opc.c (arc_opcodes): Add ext-tbl include.
289 Fix -Wstack-usage warnings.
290 * aarch64-dis.c (print_operands): Substitute size.
291 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
295 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
296 to get a proper diagnostic when an invalid ASR register is used.
300 * configure: Regenerate.
304 * arc-nps400-tbl.h: New file.
305 * arc-opc.c: Add top level comment.
306 (insert_nps_3bit_dst): New function.
307 (extract_nps_3bit_dst): New function.
308 (insert_nps_3bit_src2): New function.
309 (extract_nps_3bit_src2): New function.
310 (insert_nps_bitop_size): New function.
311 (extract_nps_bitop_size): New function.
312 (arc_flag_operands): Add nps400 entries.
313 (arc_flag_classes): Add nps400 entries.
314 (arc_operands): Add nps400 entries.
315 (arc_opcodes): Add nps400 include.
319 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
320 the new class enum values.
324 * arc-dis.c (print_insn_arc): Handle nps400.
328 * arc-opc.c (BASE): Delete.
333 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
334 of MOV insn that aliases an ORR insn.
338 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
342 * mcore-opc.h: Add const qualifiers.
343 * microblaze-opc.h (struct op_code_struct): Likewise.
344 * sh-opc.h: Likewise.
345 * tic4x-dis.c (tic4x_print_indirect): Likewise.
346 (tic4x_print_op): Likewise.
350 * or1k-desc.h: Regenerate.
351 * fr30-ibld.c: Regenerate.
352 * rl78-decode.c: Regenerate.
357 * rl78-dis.c (print_insn_rl78_common): Fix typo.
361 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
362 (print_insn_coprocessor): Support fp16 instructions.
366 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
371 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
372 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
376 * i386-dis.c (print_insn): Parenthesize expression to prevent
383 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
389 * msp430-dis.c (print_insn_msp430): Add a special case for
390 decoding an RRC instruction with the ZC bit set in the extension
395 * cgen-ibld.in (insert_normal): Rework calculation of shift.
396 * epiphany-ibld.c: Regenerate.
397 * fr30-ibld.c: Regenerate.
398 * frv-ibld.c: Regenerate.
399 * ip2k-ibld.c: Regenerate.
400 * iq2000-ibld.c: Regenerate.
401 * lm32-ibld.c: Regenerate.
402 * m32c-ibld.c: Regenerate.
403 * m32r-ibld.c: Regenerate.
404 * mep-ibld.c: Regenerate.
405 * mt-ibld.c: Regenerate.
406 * or1k-ibld.c: Regenerate.
407 * xc16x-ibld.c: Regenerate.
408 * xstormy16-ibld.c: Regenerate.
412 * epiphany-dis.c: Regenerated from latest cpu files.
416 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
421 * arm-dis.c (mapping_symbol_for_insn): New function.
422 (find_ifthen_state): Call mapping_symbol_for_insn().
426 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
427 of MSR UAO immediate operand.
431 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
436 * configure: Regenerate.
440 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
441 instructions that can support stack pointer operations.
442 * rl78-decode.c: Regenerate.
443 * rl78-dis.c: Fix display of stack pointer in MOVW based
448 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
449 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
450 erxtatus_el1 and erxaddr_el1.
454 * arm-dis.c (arm_opcodes): Add "esb".
455 (thumb_opcodes): Likewise.
459 * ppc-opc.c <xscmpnedp>: Delete.
460 <xvcmpnedp>: Likewise.
461 <xvcmpnedp.>: Likewise.
462 <xvcmpnesp>: Likewise.
463 <xvcmpnesp.>: Likewise.
468 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
473 Update year range in copyright notice of all files.
475 For older changes see ChangeLog-2015
477 Copyright (C) 2016 Free Software Foundation, Inc.
479 Copying and distribution of this file, with or without modification,
480 are permitted in any medium without royalty provided the copyright
481 notice and this notice are preserved.
487 version-control: never