3 * mips-opc.c: R3900s can support all branch likely INSN_MACROs where
4 the corresponding non-likely insn is in MIPS I.
8 * mcore-dis.c: Fix formatting.
9 * mips-dis.c: Likewise.
11 * z8k-dis.c: Likewise.
15 * cgen-ibld.in (extract_normal): Match type of VALUE and MASK
16 to *VALUEP. Regenerate all cgen files.
20 * mips-dis.c (print_insn_mips): Remove OPCODE_IS_MEMBER's gp32
22 * mips-opc.c (G6): Undefine.
23 (mips_builtin_opcodes): Remove gp32 entry for "move". Add macro
24 as the first "move" alternative.
28 * configure.in: Add -Wstrict-prototypes and -Wmissing-prototypes
30 * configure: Regenerate.
34 * ppc-opc.c: Revert 2001-08-08.
38 * dis-buf.c (generic_strcat_address): Add missing prototype.
39 #if 0 the functions as it is unused.
44 * ppc-opc.c: Include "bfd.h".
45 (powerpc_operands): Add new field for reloc type.
49 * mips-dis.c (print_insn_arg): Don't use software integer registers
50 for coprocessor registers.
51 (get_mips_isa): Removed.
52 (is_newabi): New function, checks if NewABI is used.
53 (_print_insn_mips): Get distinction between old ABI and new ABI right.
57 * z8kgen.c: Fixed indentation of opt[] array. Include stdio.h to
58 get stderr definition.
59 (internal, gas): Removed warnings.
60 (gas): Create a correct final entry for created array.
61 * z8k-opc.h: Recreated with new z8kgen.
65 * i386-dis.c: Fix formatting.
69 * i386-dis.c: Change formatting conventions for architecture
70 i386:intel to better match the format of various intel i386
71 assemblers, like nasm, tasm or masm.
75 * Makefile.am: Update dependencies with "make dep-am".
76 * Makefile.in: Regenerate
80 * alpha-dis.c: Fix formatting.
81 * cris-dis.c: Likewise.
82 * d10v-dis.c: Likewise.
83 * d30v-dis.c: Likewise.
84 * m10300-dis.c: Likewise.
85 * tic54x-dis.c: Likewise.
89 * m68k-dis.c: Fix formatting.
91 * s390-dis.c: Likewise.
92 * z8k-dis.c: Likewise.
96 * mips-opc.c (mips_builtin_opcodes): Sort c.le.s and c.lt.s
97 into the rest of the surrounding definitions.
101 * i386-dis.c (grps): Print l or w suffix, and require mem modrm
102 for lgdt, lidt, sgdt, sidt.
106 * arm-dis.c (print_insn_arm): Use decimal for offsets in LDR/STR.
110 * cgen-asm.in: Include "xregex.h" always to enable the libiberty
112 (@arch@_cgen_build_insn_regex): New routine from Graydon.
113 (@arch@_cgen_assemble_insn): Add Graydon's code to use regex
114 to verify if it is worth parsing the insn as insn "x". Also update
115 error message when insn is not a recognized format of the insn vs
116 when the insn is completely unrecognized.
120 * cgen-dis.in (print_insn): Use cgen_get_insn_value instead of
122 * cgen-opc.c (cgen_get_insn_value, cgen_put_insn_value): Respect
123 non-zero CGEN_CPU_DESC->insn_chunk_bitsize.
127 * i386-dis.c (set_op): Handle 64 bit and 32 bit mode.
128 (OP_J): Use bfd_vma for mask to work properly with 64 bits.
129 (op_address,op_riprel): Use bfd_vma to handle 64 bits.
133 * Makefile.am (CPUDIR): Define.
134 (stamp-m32r): Update dependencies.
136 (stamp-openrisc): Ditto.
137 * Makefile.in: Regenerate.
141 * ppc-opc.c: Fix encoding of 'clf' instruction.
145 * cgen-ibld.in (insert_normal): Support CGEN_IFLD_SIGN_OPT.
149 * cgen-asm.c (cgen_parse_keyword): Allow any first character.
150 * cgen-opc.c (cgen_keyword_add): Ignore special first
151 character when building nonalpha_chars field.
155 * m88k-dis.c: Format to conform to GNU coding standards.
159 * disassemble.c (disassembler_usage): Add unused attribute.
163 * mips-opc.c: Move prefx to start of the table.
167 * arc-opc.c (insert_st_syntax): Fix over-optimisation of ST
172 * m68k-opc.c: Add wdebug instruction.
176 * m10300-opc.c (mn10300_opcodes): Change opcode for AM33 subc.
180 * cgen-asm.c (cgen_parse_keyword): When looking for the
181 boundaries of a keyword, allow any special characters
182 that are actually in one of the allowed keyword.
183 * cgen-opc.c (cgen_keyword_add): Add any special characters
184 to the nonalpha_chars field.
188 * s390-opc.c: Add lgh instruction.
189 * s390-opc.txt: Likewise.
193 * i386-dis.c: Group function prototypes in one place.
194 (FLOATCODE): Redefine as 1.
195 (USE_GROUPS): Redefine as 2.
196 (USE_PREFIX_USER_TABLE): Redefine as 3.
197 (X86_64_SPECIAL): Define as 4.
198 (GRP1b..GRPAMD): Move USE_GROUPS to bytecode1, index to bytecode2.
199 (PREGRP0..PREGRP26): Similarly with USE_PREFIX_USER_TABLE.
200 (dis386_att, dis386_intel, disx86_64_att, disx86_64_intel): Delete.
201 (dis386): New table combining above four tables.
202 (dis386_twobyte_att, dis386_twobyte_intel): Delete.
203 (dis386_twobyte): New table combining above two tables.
204 (x86_64_table): New table to handle x86_64.
206 (float_mem_att, float_mem_intel): Delet.
207 (float_mem): New table combining above two tables.
208 (print_insn_i386): Modify for above.
210 (putop): Handle '{', '|' and '}' to select alternative mnemonics.
211 Return 0 on success, 1 if no valid alternative.
212 (putop <case 'F'>, <case 'H'>): Print nothing for intel_syntax.
213 (putop <case 'T'>): Move to case 'U', and share case 'Q' code.
214 (putop <case 'I'>): Move to case 'T', and share case 'P' code.
215 (OP_REG <case rAX_reg .. rDI_reg>): Handle as for eAX_reg .. eDI_reg
217 (OP_I <case q_mode>): Handle as for v_mode if not 64-bit mode.
218 (OP_I64): If not 64-bit mode, call OP_I.
219 OP_OFF64): If not 64-bit mode, call OP_OFF.
220 (OP_ST, OP_STi, OP_SEG, OP_DIR, OP_OFF, OP_OFF64, OP_MMX): Rename
221 'ignore'/'ignored' to 'bytemode'.
225 * configure.in: Sort 'ta' case statement.
226 * configure: Regenerate.
228 * i386-dis.c (dis386_att): Add 'H' to conditional branch and
230 (disx86_64_att): Likewise.
231 (dis386_twobyte_att): Likewise.
232 (print_insn_i386): Don't print branch hints as a prefix.
233 (putop): 'H' macro prints branch hints.
234 (get64): Kill compile warnings.
238 * sh-opc.h (sh_table): Don't use empty initializers.
242 * z8k-dis.c: Fix formatting.
243 (unpack_instr): Remove unused cases in switch statement. Add
244 safety abort() in default case.
245 (unparse_instr): Add safety abort() in default case.
249 * m68k-dis.c (print_insn_m68k): Fix typo.
250 * m68k-opc.c (m68k_opcodes): Correct allowed operands for
251 mcf (ColdFire) div, rem and moveb instructions.
255 * i386-dis.c (cond_jump_flag, loop_jcxz_flag): Define.
256 (cond_jump_mode, loop_jcxz_mode): Define.
257 (dis386_att): Add cond_jump_flag and loop_jcxz_flag as
258 appropriate, and 'F' suffix to loop insns.
259 (disx86_64_att): Likewise.
260 (dis386_twobyte_att): Likewise.
261 (print_insn_i386): Don't output addr prefix for loop, jcxz insns.
262 Output data size prefix for long conditional jumps. Output cs and
264 (putop): Handle 'F', and mark PREFIX_ADDR used for case 'E'.
265 (OP_J): Don't make PREFIX_DATA used.
269 * sh-opc.h (sh_table): Complete last element entry to avoid
274 * mips-dis.c (mips_isa_type): Add MIPS r12k support.
278 * arc-opc.c: Whitespace changes.
282 * cris-opc.c (cris_spec_regs): Add missing initializer field for
287 * cgen-dis.in (extract_normal): Complete support for min<base case.
291 * mips-dis.c (INSNLEN): Rename MAXLEN.
292 (std_reg_names): Replace by mips32_reg_names and mips64_reg_names.
293 (print_insn_arg): Remove $ prefix of register names.
294 (set_mips_isa_type): Remove.
295 (mips_isa_type): New function.
296 (get_mips_isa): New Function.
297 (print_insn_mips): Rename _print_insn_mips.
298 (_print_insn_mips): New function, contains code which was
299 duplicated in print_insn_big_mips and print_insn_little_mips.
300 (print_insn_big_mips): Moved code to _print_insn_mips.
301 (print_insn_little_mips): Likewise.
302 (print_mips16_insn_arg): Remove $ prefix of register names.
303 Print error message before abort.
307 * ppc-opc.c (powerpc_opcodes): Fixed extended opcode field of
308 simplified mnemonics used for setting PPC750-specific special
313 * i386-dis.c (print_insn_i386): Always set `mod', `reg' and
318 * arc-opc.c (arc_reg_names): Correct attribute for lp_count
319 register to r/w. Formatting fixes throughout file.
323 * i386-dis.c (prefix_user_table): Correct movq2dq, movdq2q, and
325 (twobyte_has_modrm): Update table.
326 (need_modrm): Give it file scope.
327 (MODRM_CHECK): Define.
328 (dofloat): Use MODRM_CHECK.
335 * cgen-dis.in (default_print_insn): Tolerate min<base instructions
336 even at end of a section.
337 * cgen-ibld.in (extract_normal): Tolerate min!=base!=max instructions
338 by ignoring precariously-unpacked insn_value in favor of raw buffer.
342 * disassemble.c (disassembler_usage): Remove unused attribute.
346 * m32r-dis.c, -asm.c, -ibld.c: Regenerated with disassembler fixes.
350 * cgen-dis.in (print_insn): Remove call to read_insn. Instead,
351 assume incoming buffer already has the base insn loaded. Handle
352 smaller-than-base instructions for variable-length case.
356 * i386-dis.c (Ev, Ed): Remove duplicate define.
359 (OP_XS): New function.
360 (dis386_twobyte_att): Correct pinsrw, pextrw, pmovmskb, and
362 (dis386_twobyte_intel): Likewise.
363 (prefix_user_table): Use MS for maskmovq operand.
367 * Makefile.am: Add OpenRISC target.
368 * Makefile.in: Regenerated.
370 * disassemble.c (disassembler): Recognize the OpenRISC disassembly.
372 * configure.in (bfd_openrisc_arch): Add target.
373 * configure: Regenerated.
375 * openrisc-asm.c: New file.
376 * openrisc-desc.c: Likewise.
377 * openrisc-desc.h: Likewise.
378 * openrisc-dis.c: Likewise.
379 * openrisc-ibld.c: Likewise.
380 * openrisc-opc.c: Likewise.
381 * openrisc-opc.h: Likewise.
385 * z8k-dis.c: add names of control registers (ctrl_names);
386 (seg_length): provides instruction length fixup for segmented
387 mode; (unpack_instr): correctly handle ARG_DISP16, ARG_DISP12,
388 CLASS_0DISP7, CLASS_1DISP7, CLASS_DISP8 and CLASS_PR cases;
389 (unparse_intr): handle CLASS_PR, print addresses without '#'
390 * z8k-opc.h: re-created with new z8kgen
391 * z8kgen.c: merged in fixes which were in existing z8k-opc.h; new
392 entries for ldctl/ldctlb instruction
396 * i386-dis.c: Add ffreep instruction.
400 * ppc-opc.c (insert_mbe): Shift mask initializer as long.
404 * i386-dis.c (PREGRP25): Define.
405 (dis386_twobyte_att): Use here in place of "movntq" entry.
406 (dis386_twobyte_intel): Likewise.
407 (prefix_user_table): Add PREGRP25 entry for "movntq" and "movntdq".
409 (dis386_twobyte_att): Use here.
410 (dis386_twobyte_intel): Likewise.
411 (prefix_user_table): Add PREGRP26 entry for "punpcklqdq".
412 (prefix_user_table <maskmovdqu>): XM operand, not MX.
413 (prefix_user_table): Cosmetic changes to "bad" entries.
417 * mips-opc.c: Remove extraneous whitespace.
418 * mips-dis.c: Remove extraneous whitespace.
422 * cgen-asm.in (@arch@_cgen_assemble_insn): Move tmp_errmsg
423 declaration inside CGEN_VERBOSE_ASSEMBLER_ERRORS conditional.
424 * cgen-ibld.in (put_insn_int_value): Mark cd parameter as unused
425 to allay a compiler warning.
429 * i386-dis.c (dis386_twobyte_att): Add entries for paddq, psubq.
430 (dis386_twobyte_intel): Likewise.
431 (twobyte_has_modrm): Set entry for paddq, psubq.
435 * cgen-dis.in (print_insn_@arch@): Add support for target machine
436 determination via CGEN_COMPUTE_MACH.
437 * fr30-desc.c: Regenerate.
438 * fr30-dis.c: Regenerate.
439 * fr30-opc.h: Regenerate.
440 * m32r-desc.c: Regenerate.
441 * m32r-dis.c: Regenerate.
442 * m32r-opc.h: Regenerate.
443 * m32r-opinst.c: Regenerate.
447 * configure.in: Remove the redundent AC_ARG_PROGRAM.
448 * configure: Rebuild.
452 * ia64-gen.c (fetch_insn_class): If xsect, then ignore comment and
453 notestr if larger than xsect.
454 (in_class): Handle format M5.
455 * ia64-asmtab.c: Regnerate.
459 * vax-dis.c (print_insn_vax): Only fetch two bytes if the info buffer
460 has more than one byte left to read.
464 * s390-opc.c: Add new opcodes. Smooth out formatting.
465 * s390-opc.txt: Add new opcodes.
469 * arm-dis.c (print_insn_thumb): Compute destination address
470 of BLX(1) instruction by taking bit 1 from PC and not from bit
475 * m68k-dis.c (print_insn_m68k): Recognize Coldfire CPUs
476 so command line switches will work.
480 * fr30-asm.c: Regenerate.
481 * fr30-desc.c: Regenerate.
482 * fr30-desc.h: Regenerate.
483 * fr30-dis.c: Regenerate.
484 * fr30-ibld.c: Regenerate.
485 * fr30-opc.c: Regenerate.
486 * fr30-opc.h: Regenerate.
487 * m32r-asm.c: Regenerate.
488 * m32r-desc.c: Regenerate.
489 * m32r-desc.h: Regenerate.
490 * m32r-dis.c: Regenerate.
491 * m32r-ibld.c: Regenerate.
492 * m32r-opc.c: Regenerate.
493 * m32r-opc.h: Regenerate.
494 * m32r-opinst.c: Regenerate.
498 * m68k-opc.c: fix cpushl according to Motorola. Enable
499 bunch of instructions for Coldfire 5407 and add all new.
503 * configure.in (BFD_VERSION): Do without grep.
504 * configure: Regenerate.
505 * Makefile.am: Run "make dep-am".
506 * Makefile.in: Regenerate.
510 * ia64-opc-a.c: Add missing pseudo-ops for "cmp" and "cmp4".
511 * ia64-asmtab.c: Regenerate.
515 * ia64-opc-d.c (ia64_opcodes_d): Break the "add" pattern into two
516 separate variants: one for IMM22 and the other for IMM14.
517 * ia64-asmtab.c: Regenerate.
521 * cgen-opc.c (cgen_get_insn_value): Add missing `return'.
525 * Makefile.am (ia64-ic.tbl): Remove the target.
526 (ia64-raw.tbl): Likewise.
527 (ia64-waw.tbl): Likewise.
528 (ia64-war.tbl): Likewise.
529 (ia64-asmtab.c): Generate it in the source directory.
530 * Makefile.in: Regenerated.
534 * Makefile.am: Add PDP-11 target.
535 * configure.in: Likewise.
536 * disassemble.c: Likewise.
537 * pdp11-dis.c: New file.
538 * pdp11-opc.c: New file.
542 * ia64-ic.tbl: Update from Intel. Add setf to fr-writers.
543 * ia64-asmtab.c: Regenerate.
547 * i386-dis.c (prefix_user_t): Add 'Y' to SSE ineger converison
553 * mips-dis.c (print_insn_arg): Use top four bits of the address of
554 the following instruction not of the jump itself for the jump
556 (print_mips16_insn_arg): Likewise.
560 * Makefile.am (stamp-lib): ranlib the libopcodes.a in the build
562 * Makefile.in: Regenerate.
566 * Makefile.am: Add linux target for S/390.
567 * Makefile.in: Likewise.
568 * configure.in: Likewise.
569 * disassemble.c: Likewise.
570 * s390-dis.c: New file.
571 * s390-mkopc.c: New file.
572 * s390-opc.c: New file.
573 * s390-opc.txt: New file.
577 * ia64-asmtab.c: Revert 2000-12-16 change.
581 * fr30-desc.h: Regenerate with CGEN_MAX_SYNTAX_ELEMENTS.
582 * m32r-desc.h: Regenerate.
586 * i386-dis.c (dis386_att, grps): Use 'T' for push/pop
587 (putop): Handle 'T', alphabetize order, fix 'I' handling in Intel syntax
591 * hppa-dis.c (print_insn_hppa): Handle '>' and '<' arg types.
595 * disassemble.c: Remove spurious white space.
599 * i386-dis.c (dis386_att, disx86_64_att): Fix ret, lret and iret
604 * configure.in: Add arc-ext.lo for bfd_arc_arch selection.
605 * Makefile.am (C_FILES): Add arc-ext.c.
606 (ALL_MACHINES) Add arc-ext.lo.
607 (INCLUDES) Add opcode directory to list.
608 New dependency entry for arc-ext.lo.
609 * disassemble.c (disassembler): Correct call to
610 arc_get_disassembler.
611 * arc-opc.c: New update for ARC, including full base
612 instructions for ARC variants.
613 * arc-dis.h, arc-dis.c: New update for ARC, including
614 extensibility functionality.
615 * arc-ext.h, arc-ext.c: New files for handling extensibility.
619 * i386-dis.c (PREGRP15 - PREGRP24): New.
620 (dis386_twobyt): Add SSE2 instructions.
621 (twobyte_uses_SSE_prefix: Rename from ... ; add new SSE instructions.
622 (twobyte_uses_f3_prefix): ... this one.
623 (grps): Add SSE instructions.
624 (prefix_user_table): Add two new slots; add SSE2 instructions.
625 (print_insn_i386): Rename uses_f3_prefix to uses_SSE_prefix;
626 Handle the REPNZ and Data16 prefixes as well; do proper lookup
627 to prefix_user_table.
628 (OP_E): Accept mfence and lfence as well.
629 (OP_MMX): Data16 prefix turns MMX to SSE; support REX extensions.
630 (OP_XMM): Support REX extensions.
636 * arm-dis.c (print_insn): Set pc to zero for instructions with
637 a reloc associated with them.
641 * cgen-asm.in (parse_insn_normal): Changed syn to be
642 CGEN_SYNTAX_CHAR_TYPE. Changed all references to *syn
643 as character to use CGEN_SYNTAX_CHAR macro and all comparisons
644 to '\0' to use 0 instead.
645 * cgen-dis.in (print_insn_normal): Ditto.
646 * cgen-ibld.in (insert_insn_normal, extract_insn_normal): Ditto.
650 * i386-dis.c: Add x86_64 support.
651 (rex): New static variable.
652 (REX_MODE64, REX_EXTX, REX_EXTY, REX_EXTZ): New constants.
653 (USED_REX): New macro.
654 (Ev, Ed, Rm, Iq, Iv64, Cm, Dm, Rm*, Ob64, Ov64): New macros.
655 (OP_I64, OP_OFF64, OP_IMREG): New functions.
656 (OP_REG, OP_OFF): Declare.
657 (get64, get32, get32s): New functions.
658 (r??_reg): New constants.
659 (dis386_att): Change templates of instruction implicitly promoted
660 to 64bit; change e?? to RMe?? for unwind RM byte instructions.
662 (dis386_intel): Likewise.
663 (dixx86_64_att): New table based on dis386_att.
664 (dixx86_64_intel): New table based on dis386_intel.
665 (names64, names8rex): New global variable.
666 (names32, names16): Add extended registers.
667 (prefix_user_t): Recognize rex prefixes.
668 (prefix_name): Print REX prefixes nicely.
669 (op_riprel): New global variable.
670 (start_pc): Set type to bfd_vma.
671 (print_insn_i386): Detect the 64bit mode and use proper table;
672 move ckprefix after initializing the buffer; output unused rex prefixes;
673 output information about target of RIP relative addresses.
674 (putop): Support 'O' and 'I'. Update handling of "P', 'Q', 'R' and 'S';
675 (print_operand_value): New function.
676 (OP_E, OP_G, OP_REG, OP_I, OP_J, OP_DIR, OP_OFF, OP_D): Add support for
677 REX prefix and new modes.
678 (get64, get32s): New.
679 (get32): Return bfd_signed_vma type.
680 (set_op): Initialize the op_riprel.
681 * disassemble.c (disassembler): Recognize the x86-64 disassembly.
685 cgen-dis.in (read_insn): Use bfd_get_bits()
689 * cgen-dis.c (hash_insn_array): Use bfd_put_bits().
690 (hash_insn_list): Likewise
691 * cgen-ibld.in (insert_1): Use bfd_put_bits() and bfd_get_bits().
692 (extract_1): Use bfd_get_bits().
693 (extract_normal): Apply sign extension to both extraction
695 * cgen-opc.c (cgen_get_insn_value): Use bfd_get_bits()
696 (cgen_put_insn_value): Use bfd_put_bits()
700 * cgen-asm.in (parse_insn_normal): Print better error message for
701 instructions with missing operands.
705 * cgen-opc.c: Include alloca.h if HAVE_ALLOCA_H is defined.
709 * Makefile.in: Regenerate.
710 * aclocal.m4: Regenerate.
711 * config.in: Regenerate.
712 * configure.in: Add spacing.
713 * configure: Regenerate.
714 * ia64-asmtab.c: Regenerate.
715 * po/opcodes.pot: Regenerate.
719 * cgen-asm.in (@arch@_cgen_assemble_insn): Prefer printing insert-time
720 error messages over later parse-time ones.
724 * ia64-dis.c (print_insn_ia64): Cast away const on ia64_free_opcode
726 * ia64-gen.c (insert_deplist): Cast sizeof result to int.
727 (print_dependency_table): Print NULL if semantics field not set.
728 (insert_opcode_dependencies): Mark cmp parameter as unused.
729 (print_main_table): Use fprintf_vma to print long long fields.
730 (main): Mark argv paramter as unused. Convert to old style definition.
731 * ia64-opc.c (ia64_find_dependency): Cast sizeof result to int.
732 * ia64-asmtab.c: Regnerate.
736 * m32r-dis.c (print_insn): Prevent re-read of instruction from
739 * fr30-dis.c: Regenerate.
743 * configure.in: Add arc-ext.lo for bfd_arc_arch selection.
744 * Makefile.am (C_FILES): Add arc-ext.c.
745 (ALL_MACHINES) Add arc-ext.lo.
746 (INCLUDES) Add opcode directory to list.
747 New dependency entry for arc-ext.lo.
748 * disassemble.c (disassembler): Correct call to
749 arc_get_disassembler.
750 * arc-opc.c: New update for ARC, including full base
751 instructions for ARC variants.
752 * arc-dis.h, arc-dis.c: New update for ARC, including
753 extensibility functionality.
754 * arc-ext.h, arc-ext.c: New files for handling extensibility.
758 * mips-opc.c (mips_builtin_opcodes): Use the WR_HILO, RD_HILO,
759 MOD_HILO, and MOD_LO macros.
761 * mips-opc.c (M1, M2): Delete.
762 (mips_builtin_opcodes): Remove all uses of M1.
764 * mips-opc.c (mips_builtin_opcodes): Make the dmfc2 and dmtc2
765 instructions take "G" format second operands and use the
767 There are mfc3 and mtc3 opcodes, so add dmfc3 and dmtc3 opcodes to
769 Delete "sel" code operands from mfc1 and mtc1.
770 Add MIPS64 opcode changes (dclo, dclz), and "sel" code variants
776 * mips-opc.c (mips_builtin_opcodes): Finish additions
777 for MIPS32 support, and clean up existing entries for
778 aesthetics, consistency with the MIPS32 ISA, and
779 with consistency the rest of the table.
783 * mips16-opc.c (mips16_opcodes): Add initialiser for membership
788 mips-dis.c (print_insn_arg): Handle new 'U' and 'J' argument
789 specifiers. Update 'B' for new constant names, and remove
791 mips-opc.c (mips_builtin_opcodes): Place "pref" and "ssnop"
792 near the top of the array, so they are disassembled properly.
793 Enable "ssnop" for MIPS32. Add "break" variant with 20 bit
794 code for MIPS32. Update "clo" and "clz" to use 'U' operand
795 specifier. Add 'H' format specifier variants for "mfc1,"
796 "mfc2," "mfc3," "mtc1," "mtc2," and "mtc3" for MIPS32. Update
797 MIPS32 "sdbbp" to use 'B' operand specifier. Add MIPS32
798 "wait" variant which uses 'J' operand specifier.
800 * mips-dis.c (set_mips_isa_type): Update to use
801 CPU_UNKNOWN and ISA_* constants. Add bfd_mach_mips32 case.
802 Replace bfd_mach_mips4K with bfd_mach_mips32_4k case.
803 * mips-opc.c (I32): New constant for instructions added in
806 (mips_builtin_opcodes) Replace all uses of P4 with I32.
808 * mips-dis.c (set_mips_isa_type): Add cases for
809 bfd_mach_mips5 and bfd_mach_mips64.
810 * mips-opc.c (I64): New definitions.
812 * mips-dis.c (set_mips_isa_type): Add case for
817 * sh-dis.c (print_insn_ddt): Make insn_x, insn_y unsigned.
818 (print_insn_ppi): Make nib1, nib2, nib3 unsigned.
819 Initialize variable dc to NULL.
820 (print_insn_shx): Remove unused label d_reg_n.
824 * arm-opc.h: Add new opcode formatting parameter 'B'.
825 (arm_opcodes): Add XScale, v5, and v5te instructions.
826 (thumb_opcodes): Add v5t instructions.
828 * arm-dis.c (print_insn_arm): Handle new 'B' format
830 (print_insn_thumb): Decode BLX(1) instruction.
834 * mips-opc.c: Fix file header comment.
838 * cris-dis.c (cris_get_disassembler): If abfd is NULL, return
839 print_insn_cris_with_register_prefix.
843 * sh-opc.h: The operand of `mov.w r0, (<disp>,GBR)' is IMM1, not 0.
847 * cgen-dis.in (print_insn): All insns which can fit into insn_value
848 must be loaded there in their entirety.
852 * sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs.
853 (compute_arch_mask): Add v8plusb and v9b machines.
854 (print_insn_sparc): siam mode decoding, accept ASRs up to 25.
855 * sparc-opc.c: Support for Cheetah instruction set.
856 (prefetch_table): Add #invalidate.
860 * mcore-dis.c (imsk): Change mask for OC to 0xFE00.
864 * fr30-desc.h: Regenerate.
865 * m32r-desc.h: Regenerate.
866 * m32r-ibld.c: Regenerate.
870 * ia64-ic.tbl: Update from Intel.
871 * ia64-asmtab.c: Regenerate.
875 * ia64-gen.c: Convert C++-style comments to C-style comments.
876 * tic54x-dis.c: Likewise.
880 Changes to add dollar prefix to registers for files where user symbols
881 don't have a leading underscore. Fix formatting.
882 * cris-dis.c (REGISTER_PREFIX_CHAR): New.
883 (format_reg): Add parameter with_reg_prefix. All callers changed.
884 (print_with_operands): Ditto.
885 (print_insn_cris_generic): Renamed from print_insn_cris, add
886 parameter with_reg_prefix.
887 (print_insn_cris_with_register_prefix,
888 print_insn_cris_without_register_prefix, cris_get_disassembler):
890 * disassemble.c (disassembler) [ARCH_cris]: Call cris_get_disassembler.
894 * ia64-opc-f.c (ia64_opcodes_f): Add fpcmp pseudo-ops for
895 gt, ge, ngt, and nge.
896 * ia64-asmtab.c: Regenerate.
898 * ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change.
899 * ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP.
900 (lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62".
901 * ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update.
902 * ia64-asmtab.c: Regnerate.
906 * mips-opc.c (mips_builtin_opcodes): Support cache instruction on 4K cores.
907 Add mfc0 and mtc0 with sub-selection values.
908 Add clo and clz opcodes.
909 Add msub and msubu instructions for MIPS32.
910 Add madd/maddu aliases for mad/madu for MIPS32.
911 Support wait, deret, eret, movn, pref for MIPS32.
912 Support tlbp, tlbr, tlbwi, tlbwr.
915 * mips-dis.c (print_insn_arg): Print sdbbp 'm' args.
916 (print_insn_arg): Handle 'H' args.
917 (set_mips_isa_type): Recognize 4K.
918 Use CPU_* defines instead of hardcoded numbers.
922 * d30v-opc.c (d30v_operand_t): New operand type Rb2.
923 (d30v_format_tab): Use Rb2 for modinc and moddec.
927 * d30v-opc.c (d30v_format_tab): Use format Ra for
932 * configure: Rebuilt with new libtool.m4.
936 * configure: Regenerate.
937 * po/opcodes.pot: Regenerate.
941 * acinclude.m4: Include libtool and gettext macros from the
943 * aclocal.m4, configure: Rebuilt.
947 * tic80-dis.c: Fix formatting.
951 * w65-dis.c: Fix formatting.
955 * ppc-opc.c: Add XTLB macro for a few PPC 4xx extended mnemonics.
956 (powerpc_opcodes): Add table entries for PPC 405 instructions.
957 Changed rfci, icbt, mfdcr, dccci, mtdcr, iccci from PPC to PPC403
958 instructions. Added extended mnemonic mftbl as defined in the
959 405GP manual for all PPCs.
963 * ia64-dis.c (print_insn_ia64): Add failed label after ia64_free_opcode
964 call. Change last goto to use failed instead of done.
968 * cgen-ibld.in (cgen_put_insn_int_value): New function.
969 (insert_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P.
970 (insert_insn_normal): Use cgen_put_insn_int_value with CGEN_INT_INSN_P.
971 (extract_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P.
972 * cgen-dis.in (read_insn): New static function.
973 (print_insn): Use read_insn to read the insn into the buffer and set
975 (print_insn): in CGEN_INT_INSN_P, make sure that the entire insn is
977 * fr30-asm.c: Regenerated.
978 * fr30-desc.c: Regenerated.
979 * fr30-desc.h: Regenerated.
980 * fr30-dis.c: Regenerated.
981 * fr30-ibld.c: Regenerated.
982 * fr30-opc.c: Regenerated.
983 * fr30-opc.h: Regenerated.
984 * m32r-asm.c: Regenerated.
985 * m32r-desc.c: Regenerated.
986 * m32r-desc.h: Regenerated.
987 * m32r-dis.c: Regenerated.
988 * m32r-ibld.c: Regenerated.
989 * m32r-opc.c: Regenerated.
993 * tic30-dis.c: Fix formatting.
997 * sh-dis.c: Fix formatting.
1001 * ppc-opc.c (powerpc_opcodes): Add rfid, mtsrd, mtsrdin, mtmsrd.
1005 * z8k-dis.c: Fix formatting.
1009 * ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete
1010 break, mov-immediate, nop.
1011 * ia64-opc-f.c: Delete fpsub instructions.
1012 * ia64-opc-m.c: Add POSTINC to all instructions with postincrement
1013 address operand. Rewrite using macros to avoid long lines.
1014 * ia64-opc.h (POSTINC): Define.
1015 * ia64-asmtab.c: Regenerate.
1019 * ia64-ic.tbl: Add missing entries.
1023 * i860-dis.c (print_br_address): Change third argument from int
1028 * ia64-dis.c (print_insn_ia64): Get byte skip count correct
1029 for MLI templates. Handle IA64_OPND_TGT64.
1033 * cgen-dis.in, cgen-asm.in, cgen-ibld.in: New files.
1034 * cgen.sh: Likewise.
1038 * ia64-dis.c (print_insn_ia64): Call ia64_free_opcode at end.
1042 * avr-dis.c (avr_operand): Use PARAMS macro in declaration.
1043 Change return type from void to int. Check the combination
1044 of operands, return 1 if valid. Fix to avoid BUF overflow.
1045 Report undefined combinations of operands in COMMENT.
1046 Report internal errors to stderr. Output the adiw/sbiw
1047 constant operand in both decimal and hex.
1048 (print_insn_avr): Disassemble ldd/std with displacement of 0
1049 as ld/st. Check avr_operand () return value, handle invalid
1050 combinations of operands like unknown opcodes.
1054 * Makefile.am (CGEN, CGENDEPS, CGENDIR, CGENFLAGS): New.
1055 (run-cgen, stamp-m32r, stamp-fr30): New targets.
1056 * Makefile.in: Regenerate.
1057 * configure.in: Add --enable-cgen-maint option.
1058 * configure: Regenerate.
1062 * cgen-opc.c (cgen_hw_lookup_by_name): 'i' is now unsigned.
1063 (cgen_hw_lookup_by_num): Ditto.
1064 (cgen_operand_lookup_by_name): Ditto.
1065 (print_address): Ditto.
1066 (print_keyword): Ditto.
1067 * cgen-dis.c (hash_insn_array): Mark unused parameters with
1069 * cgen-asm.c (hash_insn_array): Mark unused parameters with
1071 (cgen_parse_keyword): Ditto.
1075 * i860-dis.c: New file.
1076 (print_insn_i860): New function.
1077 (print_br_address): New function.
1078 (sign_extend): New function.
1079 (BITWISE_OP): New macro.
1080 (I860_REG_PREFIX): New macro.
1081 (grnames, frnames, crnames): New structures.
1083 * disassemble.c (ARCH_i860): Define.
1084 (disassembler): Add check for bfd_arch_i860 to set disassemble
1085 function to print_insn_i860.
1087 * Makefile.in (CFILES): Added i860-dis.c.
1088 (ALL_MACHINES): Added i860-dis.lo.
1089 (i860-dis.lo): New dependences.
1091 * configure.in: New bits for bfd_i860_arch.
1093 * configure: Regenerated.
1097 * Makefile.am (CFILES): Add cris-dis.c and cris-opc.c.
1098 (ALL_MACHINES): Add cris-dis.lo and cris-opc.lo.
1099 (cris-dis.lo, cris-opc.lo): New rules.
1100 * Makefile.in: Rebuild.
1101 * configure.in (bfd_cris_arch): New target.
1102 * configure: Rebuild.
1103 * disassemble.c (ARCH_cris): Define.
1104 (disassembler): Support ARCH_cris.
1105 * cris-dis.c, cris-opc.c: New files.
1106 * po/POTFILES.in, po/opcodes.pot: Regenerate.
1110 * sparc-opc.c (sparc_opcodes): popc has 0 in rs1, not rs2.
1115 * ppc-opc.c (powerpc_opcodes): Correct suffix for vslw.
1120 * hppa-dis.c (fput_reg, fput_fp_reg, fput_fp_reg_r, fput_creg,
1121 fput_const, extract_3, extract_5_load, extract_5_store,
1122 extract_5r_store, extract_5R_store, extract_10U_store,
1123 extract_5Q_store, extract_11, extract_14, extract_16, extract_21,
1124 extract_12, extract_17, extract_22): Prototype.
1125 (print_insn_hppa): Rename inner block opcode -> opc to avoid
1126 shadowing outer block.
1135 * arm-dis.c (print_insn_arm): Output combinations of PSR flags.
1139 * avr-dis.c (avr_operand): Change _ () to _() around all strings
1140 marked for translation (exception from the usual coding style).
1141 (print_insn_avr): Initialize insn2 to avoid warnings.
1145 * h8300-dis.c (bfd_h8_disassemble): Improve readability.
1146 * h8500-dis.c: Fix formatting.
1150 * Makefile.am (DEP): Fix 2000-06-22. grep after running dep.sed
1151 (CLEANFILES): Add DEPA.
1152 * Makefile.in: Regenerate.
1156 * arm-dis.c (regnames): Add an additional register set to match
1157 the set used by GCC. Make it the default.
1161 * Makefile.am (DEP): grep for leading `/' in DEP1, and fail if we
1163 * Makefile.in: Regenerate.
1167 * Makefile.am: Rebuild dependency.
1168 * Makefile.in: Rebuild.
1172 * Makefile.in, configure: regenerate
1173 * disassemble.c (disassembler): Recognize ARCH_m68hc12,
1175 * m68hc11-dis.c (read_memory, print_insn, print_insn_m68hc12):
1177 * configure.in: Recognize m68hc12 and m68hc11.
1178 * m68hc11-dis.c, m68hc11-opc.c: New files for support of m68hc1x
1179 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
1180 and opcode generation for m68hc11 and m68hc12.
1184 * disassemble.c (disassembler): Refer to the PowerPC 620 using
1185 bfd_mach_ppc_620 instead of 620.
1189 * h8300-dis.c: Fix formatting.
1190 (bfd_h8_disassemble): Distinguish adds/subs, inc/dec.[wl]
1195 * avr-dis.c (avr_operand): Bugfix for jmp/call address.
1199 * avr-dis.c: completely rewritten.
1203 * h8300-dis.c: Follow the GNU coding style.
1204 (bfd_h8_disassemble) Fix a typo.
1208 * h8300-dis.c (bfd_h8_disassemble_init): Fix a typo.
1209 (bfd_h8_disassemble): Distinguish the operand size of inc/dev.[wl]
1210 correctly. Fix a typo.
1214 * opintl.h (_(String)): Explain why dgettext is used instead of
1219 * opintl.h (gettext, dgettext, dcgettext, textdomain,
1220 bindtextdomain): Replace defines with those from intl/libgettext.h
1221 to quieten gcc warnings.
1225 * Makefile.am: Update dependencies with "make dep-am"
1226 * Makefile.in: Regenerate.
1230 * m10300-dis.c (disassemble): Don't assume 32-bit longs when
1231 sign-extending operands.
1235 * d10v-opc.c (d10v_opcodes): add ALONE tag to all short branches
1240 * Makefile.am (LIBIBERTY): Define.
1244 * mips-dis.c (REGISTER_NAMES): Rename to STD_REGISTER_NAMES.
1245 (STD_REGISTER_NAMES): New name for REGISTER_NAMES.
1246 (reg_names): Rename to std_reg_names. Change it to a char **
1248 (std_reg_names): New name for reg_names.
1249 (set_mips_isa_type): Set reg_names to point to std_reg_names by
1254 * fr30-desc.h: Partially regenerated to account for changed
1255 CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros.
1256 * m32r-desc.h: Ditto.
1260 * arm-opc.h: Use upper case for flasg in MSR and MRS
1261 instructions. Allow any bit to be set in the field_mask of
1262 the MSR instruction.
1264 * arm-dis.c (print_insn_arm): Decode _x and _s bits of the
1265 field_mask of an MSR instruction.
1269 * arm-opc.h: Disassembly of thumb ldsb/ldsh
1270 instructions changed to ldrsb/ldrsh.
1274 * mips-dis.c (print_insn_arg): Don't mask top 32 bits of 64-bit
1275 target addresses for 'jal' and 'j'.
1279 * ppc-opc.c (powerpc_opcodes): Make the predicted-branch opcodes
1280 also available in common mode when powerpc syntax is being used.
1284 * m68k-dis.c (dummy_printer): Add ATTRIBUTE_UNUSED to args.
1285 (dummy_print_address): Ditto.
1289 * tic54x-opc.c: New.
1290 * tic54x-dis.c: New.
1291 * disassemble.c (disassembler): Add ARCH_tic54x.
1292 * configure.in: Added tic54x target.
1294 * Makefile.am: Add tic54x dependencies.
1295 * Makefile.in: Ditto.
1299 * ppc-opc.c (VA, VB, VC, VD, VS, SIMM, UIMM, SHB): New macros, for
1300 vector unit operands.
1301 (VX, VX_MASK, VXA, VXA_MASK, VXR, VXR_MASK): New macros, for vector
1302 unit instruction formats.
1303 (PPCVEC): New macro, mask for vector instructions.
1304 (powerpc_operands): Add table entries for above operand types.
1305 (powerpc_opcodes): Add table entries for vector instructions.
1307 * ppc-dis.c (print_insn_big_powerpc): Add PPC_OPCODE_ALTIVEC to mask.
1308 (print_insn_little_powerpc): Likewise.
1309 (print_insn_powerpc): Prepend 'v' when printing vector registers.
1313 * configure.in: Add bfd_powerpc_64_arch.
1314 * disassemble.c (disassembler): Use print_insn_big_powerpc for
1319 * fr30-desc.c (fr30_cgen_cpu_open): Initialise signed_overflow
1324 * avr-dis.c (reg_fmul_d): New. Extract destination register from
1326 (reg_fmul_r): New. Extract source register from FMUL instruction.
1327 (reg_muls_d): New. Extract destination register from MULS instruction.
1328 (reg_muls_r): New. Extract source register from MULS instruction.
1329 (reg_movw_d): New. Extract destination register from MOVW instruction.
1330 (reg_movw_r): New. Extract source register from MOVW instruction.
1331 (print_insn_avr): Handle MOVW, MULS, MULSU, FMUL, FMULS, FMULSU,
1332 EICALL, EIJMP, LPM r,Z, ELPM r,Z, SPM, ESPM instructions.
1336 * ia64-gen.c (general): Add an ordered table of primary
1337 opcode names, as well as priority fields to disassembly data
1338 structures to enforce a preferred disassembly format based on the
1339 ordering of the opcode tables.
1340 (load_insn_classes): Show a useful message if IC tables are missing.
1341 (load_depfile): Ditto.
1342 * ia64-asmtab.h (struct ia64_dis_names ): Add priority flag to
1343 distinguish preferred disassembly.
1344 * ia64-opc-f.c: Reorder some insn for preferred disassembly
1345 format. Fix incorrect flag on fma.s/fma.s.s0.
1346 * ia64-opc.c: Scan *all* disassembly matches and use the one with
1347 the highest priority.
1348 * ia64-opc-b.c: Use more abbreviations.
1349 * ia64-asmtab.c: Regenerate.
1353 * hppa-dis.c (extract_16): New function.
1354 (print_insn_hppa): Fix incorrect handling of 'fe'. Added handling of
1355 new operand types l,y,&,fe,fE,fx.
1363 * Makefile.am (HFILES): Add ia64-asmtab.h, ia64-opc.h.
1364 (CFILES): Add ia64-dis.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c,
1365 ia64-opc-i.c, ia64-opc-m.c, ia64-opc-d.c, ia64-opc.c, ia64-gen.c,
1367 (ALL_MACHINES): Add ia64-dis.lo, ia64-opc.lo.
1368 (ia64-ic.tbl, ia64-raw.tbl, ia64-waw.tbl, ia64-war.tbl, ia64-gen,
1369 ia64-gen.o, ia64-asmtab.c, ia64-dis.lo, ia64-opc.lo): New rules.
1370 * Makefile.in: Rebuild.
1371 * configure Rebuild.
1372 * configure.in (bfd_ia64_arch): New target.
1373 * disassemble.c (ARCH_ia64): Define.
1374 (disassembler): Support ARCH_ia64.
1375 * ia64-asmtab.c, ia64-asmtab.h, ia64-dis.c, ia64-gen.c ia64-ic.tbl,
1376 ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c ia64-opc-f.c, ia64-opc-i.c,
1377 ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl,
1378 ia64-war.tbl, ia64-waw.tbl: New files.
1382 * m10300-dis.c (HAVE_AM30, HAVE_AM33): Define.
1383 (disassemble): Use them.
1387 * sysdep.h: Include "ansidecl.h" not <ansidecl.h>
1388 * Makefile.am: Update dependencies.
1389 * Makefile.in: Regenerate.
1393 * a29k-dis.c, alpha-dis.c, alpha-opc.c, arc-dis.c, arc-opc.c,
1394 avr-dis.c, d10v-dis.c, d10v-opc.c, d30v-dis.c, d30v-opc.c,
1395 disassemble.c, h8300-dis.c, h8500-dis.c, hppa-dis.c, i370-dis.c,
1396 i370-opc.c, i960-dis.c, m10200-dis.c, m10200-opc.c, m10300-dis.c,
1397 m10300-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c, mcore-dis.c,
1398 mips-dis.c, mips-opc.c, mips16-opc.c, pj-dis.c, pj-opc.c,
1399 ppc-dis.c, ppc-opc.c, sh-dis.c, sparc-dis.c, sparc-opc.c,
1400 tic80-dis.c, tic80-opc.c, v850-dis.c, v850-opc.c, vax-dis.c,
1401 w65-dis.c, z8k-dis.c, z8kgen.c: Include sysdep.h. Remove
1402 ansidecl.h as sysdep.h includes it.
1406 * configure.in (WARN_CFLAGS): Set to -W -Wall by default. Add
1407 --enable-build-warnings option.
1408 * Makefile.am (AM_CFLAGS, WARN_CFLAGS): Add definitions.
1409 * Makefile.in, configure: Re-generate.
1413 * sh-opc.h (sh_table): Use A_DISP_PC / PCRELIMM_8BY2 for ldre & ldrs.
1414 stc GBR,@-<REG_N> is available for arch_sh1_up.
1415 Group parallel processing insn with identical mnemonics together.
1416 Make three-operand psha / pshl come first.
1420 * sh-opc.h (sh_nibble_type): Remove DISP_8 and DISP_4.
1421 Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT.
1422 (sh_arg_type): Add A_PC.
1423 (sh_table): Update entries using immediates. Add repeat.
1424 * sh-dis.c (print_insn_shx): Remove DISP_8 and DISP_4.
1425 Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT.
1429 * po/opcodes.pot: Regenerate.
1431 * Makefile.am (MKDEP): Use gcc -MM rather than mkdep.
1432 (DEP): Quote when passing vars to sub-make. Add warning message
1434 (DEP1): Rewrite for "gcc -MM".
1435 (CLEANFILES): Add DEP2.
1436 Update dependencies.
1437 * Makefile.in: Regenerate.
1441 * avr-dis.c: Syntax cleanup.
1442 (add0fff): Print the pc relative address as a signed number.
1443 (add03f8): Likewise.
1447 * disassemble.c (disassembler_usage): Don't use a prototype. Mark
1448 the parameter ATTRIBUTE_UNUSED.
1449 * ppc-opc.c: Add ATTRIBUTE_UNUSED as needed.
1453 * m10300-opc.c: SP-based offsets are always unsigned.
1457 * arm-opc.h (thumb_opcodes): Disassemble 0xde.. to "bal"
1458 [branch always] instead of "undefined".
1462 * d30v-opc.c (d30v_format_table): Move SHORT_AR to end of list of
1463 short instructions, from end of list of long instructions.
1467 * Makefile.am (CFILES): Add avr-dis.c.
1468 (ALL_MACHINES): Add avr-dis.lo.
1472 * avr-dis.c (add0fff, add03f8): Don't use structure bitfields to
1474 (print_insn_avr): Call function via pointer in K&R compatible way.
1475 (dispLDD, regPP, reg50, reg104, reg40, reg20w, lit404, lit204,
1476 add0fff, add03f8): Convert to old style function declaration and
1478 (avrdis_opcode): Add prototype.
1482 * avr-dis.c: New file. AVR disassembler.
1483 * configure.in (bfd_avr_arch): New architecture support.
1484 * disassemble.c: Likewise.
1485 * configure: Regenerate.
1489 * sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement.
1493 * d30v-dis.c (print_insn): Remove d*i hacks. Use per-operand
1494 flag to determine if operand is pc-relative.
1496 (d30v_format_table):
1497 (REL6S3): Renamed from IMM6S3.
1498 Added flag OPERAND_PCREL.
1499 (REL12S3, REL18S3, REL32): Split from IMM12S3, IMM18S3, REL32, with
1500 added flag OPERAND_PCREL.
1501 (IMM12S3U): Replaced with REL12S3.
1502 (SHORT_D2, LONG_D): Delay target is pc-relative.
1503 (SHORT_B2r, SHORT_B3r, SHORT_B3br, SHORT_D2r, LONG_Ur, LONG_2r):
1504 Split from SHORT_B2, SHORT_D2, SHORT_B3b, SHORT_D2, LONG_U, LONG_2r,
1505 using the REL* operands.
1506 (LONG_2br, LONG_Dr): Likewise, from LONG_2b, LONG_D.
1507 (SHORT_D1r, SHORT_D2Br, LONG_Dbr): Renamed from SHORT_D1, SHORT_D2B,
1508 LONG_Db, using REL* operands.
1509 (SHORT_U, SHORT_A5S): Removed stray alternatives.
1510 (d30v_opcode_table): Use new *r formats.
1514 * m32r-desc.c (m32r_cgen_cpu_open): Replace 'flags' with
1515 'signed_overflow_ok_p'.
1519 * Makefile.am (stamp-lib): Use $(LIBTOOL) --config to get the
1520 name of the libtool directory.
1521 * Makefile.in: Rebuild.
1525 * cgen-opc.c (cgen_set_signed_overflow_ok): New function.
1526 (cgen_clear_signed_overflow_ok): New function.
1527 (cgen_signed_overflow_ok_p): New function.
1531 * m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c,
1532 m32r-ibld.c, m32r-opc.h: Rebuild.
1536 * i370-dis.c, i370-opc.c: New.
1538 * disassemble.c (ARCH_i370): Define.
1539 (disassembler): Handle it.
1541 * Makefile.am: Add support for Linux/IBM 370.
1542 * configure.in: Likewise.
1544 * Makefile.in: Regenerate.
1545 * configure: Likewise.
1549 * d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp to
1550 ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel
1555 * mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER:
1557 * mips-opc.c (G6): New define.
1558 (mips_builtin_op): Add "move" definition for -gp32.
1563 * ppc-opc.c: Correct dcread--it takes 3 arguments, not 2.
1567 * dis-buf.c (buffer_read_memory): Change `length' param and all int
1572 * sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions.
1573 (print_insn_ppi): Likewise.
1574 (print_insn_shx): Use info->mach to select appropriate insn set.
1575 Add support for sh-dsp. Remove FD_REG_N support.
1576 * sh-opc.h (sh_nibble_type): Add new values for sh-dsp support.
1577 (sh_arg_type): Likewise. Remove FD_REG_N.
1578 (sh_dsp_reg_nums): New enum.
1579 (arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros.
1580 (arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise.
1581 (arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise.
1582 (arch_sh3_dsp_up): Likewise.
1583 (sh_opcode_info): New field: arch.
1584 (sh_table): Split up insn with FD_REG_N into ones with F_REG_N and
1585 D_REG_N. Fill in arch field. Add sh-dsp insns.
1589 * arm-dis.c: Change flavor name from atpcs-special to
1590 special-atpcs to prevent name conflict in gdb.
1591 (get_arm_regname_num_options, set_arm_regname_option,
1592 get_arm_regnames): New functions. API to access the several
1593 flavor of register names. Note: Used by gdb.
1594 (print_insn_thumb): Use the register name entry from the currently
1595 selected flavor for LR and PC.
1599 * mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR
1601 (mcore_table): Add "idly4", "psrclr", "psrset", "mulsh" and
1602 "mulsh.h" instructions.
1603 * mcore-dis.c (imsk array): Add masks for MULSH and OPSR
1605 (print_insn_mcore): Add support for little endian targets.
1606 Add support for MULSH and OPSR classes.
1610 * arm-dis.c (parse_arm_diassembler_option): Rename again.
1611 Previous delat did not take.
1615 * dis-buf.c (buffer_read_memory): Use octets_per_byte field
1616 to adjust target address bounds checking and calculate the
1617 appropriate octet offset into data.
1621 * arm-dis.c: (parse_disassembler_option): Rename to
1622 parse_arm_disassembler_option and allow to be exported.
1624 * disassemble.c (disassembler_usage): New function: Print out any
1625 target specific disassembler options.
1626 Call arm_disassembler_options() if the ARM architecture is being
1629 * arm-dis.c (NUM_ELEM): Define this macro if not already
1631 (arm_regname): New struct type for ARM register names.
1632 (arm_toggle_regnames): Delete.
1633 (parse_disassembler_option): Use register name structure.
1634 (print_insn): New function: Combines duplicate code found in
1635 print_insn_big_arm and print_insn_little_arm.
1636 (print_insn_big_arm): Call print_insn.
1637 (print_insn_little_arm): Call print_insn.
1638 (print_arm_disassembler_options): Display list of supported,
1639 ARM specific disassembler options.
1643 * arm-dis.c (printf_insn_big_arm): Treat ELF symbols with the
1644 ARM_STT_16BIT flag as Thumb code symbols.
1646 * arm-dis.c (printf_insn_little_arm): Ditto.
1650 * arm-dis.c (printf_insn_thumb): Prevent double dumping
1651 of raw thumb instructions.
1655 * mcore-opc.h (mcore_table): Add "add" as an alias for "addu".
1659 * arm-dis.c (streq): New macro.
1660 (strneq): New macro.
1661 (force_thumb): ew local variable.
1662 (parse_disassembler_option): New function: Parse a single, ARM
1663 specific disassembler command line switch.
1664 (parse_disassembler_option): Call parse_disassembler_option to
1665 parse individual command line switches.
1666 (print_insn_big_arm): Check force_thumb.
1667 (print_insn_little_arm): Check force_thumb.
1669 For older changes see ChangeLog-9899
1675 version-control: never