1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2018 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
57 typedef arelent, howto manager, Relocations, Relocations
62 This is the structure of a relocation entry:
66 .typedef enum bfd_reloc_status
68 . {* No errors detected. Note - the value 2 is used so that it
69 . will not be mistaken for the boolean TRUE or FALSE values. *}
72 . {* The relocation was performed, but there was an overflow. *}
75 . {* The address to relocate was not within the section supplied. *}
76 . bfd_reloc_outofrange,
78 . {* Used by special functions. *}
81 . {* Unsupported relocation size requested. *}
82 . bfd_reloc_notsupported,
87 . {* The symbol to relocate against was undefined. *}
88 . bfd_reloc_undefined,
90 . {* The relocation was performed, but may not be ok. If this type is
91 . returned, the error_message argument to bfd_perform_relocation
95 . bfd_reloc_status_type;
98 .typedef struct reloc_cache_entry
100 . {* A pointer into the canonical table of pointers. *}
101 . struct bfd_symbol **sym_ptr_ptr;
103 . {* offset in section. *}
104 . bfd_size_type address;
106 . {* addend for relocation value. *}
109 . {* Pointer to how to perform the required relocation. *}
110 . reloc_howto_type *howto;
120 Here is a description of each of the fields within an <<arelent>>:
124 The symbol table pointer points to a pointer to the symbol
125 associated with the relocation request. It is the pointer
126 into the table returned by the back end's
127 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
128 referenced through a pointer to a pointer so that tools like
129 the linker can fix up all the symbols of the same name by
130 modifying only one pointer. The relocation routine looks in
131 the symbol and uses the base of the section the symbol is
132 attached to and the value of the symbol as the initial
133 relocation offset. If the symbol pointer is zero, then the
134 section provided is looked up.
138 The <<address>> field gives the offset in bytes from the base of
139 the section data which owns the relocation record to the first
140 byte of relocatable information. The actual data relocated
141 will be relative to this point; for example, a relocation
142 type which modifies the bottom two bytes of a four byte word
143 would not touch the first byte pointed to in a big endian
148 The <<addend>> is a value provided by the back end to be added (!)
149 to the relocation offset. Its interpretation is dependent upon
150 the howto. For example, on the 68k the code:
155 | return foo[0x12345678];
158 Could be compiled into:
161 | moveb @@#12345678,d0
166 This could create a reloc pointing to <<foo>>, but leave the
167 offset in the data, something like:
169 |RELOCATION RECORDS FOR [.text]:
173 |00000000 4e56 fffc ; linkw fp,#-4
174 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
175 |0000000a 49c0 ; extbl d0
176 |0000000c 4e5e ; unlk fp
179 Using coff and an 88k, some instructions don't have enough
180 space in them to represent the full address range, and
181 pointers have to be loaded in two parts. So you'd get something like:
183 | or.u r13,r0,hi16(_foo+0x12345678)
184 | ld.b r2,r13,lo16(_foo+0x12345678)
187 This should create two relocs, both pointing to <<_foo>>, and with
188 0x12340000 in their addend field. The data would consist of:
190 |RELOCATION RECORDS FOR [.text]:
192 |00000002 HVRT16 _foo+0x12340000
193 |00000006 LVRT16 _foo+0x12340000
195 |00000000 5da05678 ; or.u r13,r0,0x5678
196 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
197 |00000008 f400c001 ; jmp r1
199 The relocation routine digs out the value from the data, adds
200 it to the addend to get the original offset, and then adds the
201 value of <<_foo>>. Note that all 32 bits have to be kept around
202 somewhere, to cope with carry from bit 15 to bit 16.
204 One further example is the sparc and the a.out format. The
205 sparc has a similar problem to the 88k, in that some
206 instructions don't have room for an entire offset, but on the
207 sparc the parts are created in odd sized lumps. The designers of
208 the a.out format chose to not use the data within the section
209 for storing part of the offset; all the offset is kept within
210 the reloc. Anything in the data should be ignored.
213 | sethi %hi(_foo+0x12345678),%g2
214 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
218 Both relocs contain a pointer to <<foo>>, and the offsets
221 |RELOCATION RECORDS FOR [.text]:
223 |00000004 HI22 _foo+0x12345678
224 |00000008 LO10 _foo+0x12345678
226 |00000000 9de3bf90 ; save %sp,-112,%sp
227 |00000004 05000000 ; sethi %hi(_foo+0),%g2
228 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
229 |0000000c 81c7e008 ; ret
230 |00000010 81e80000 ; restore
234 The <<howto>> field can be imagined as a
235 relocation instruction. It is a pointer to a structure which
236 contains information on what to do with all of the other
237 information in the reloc record and data section. A back end
238 would normally have a relocation instruction set and turn
239 relocations into pointers to the correct structure on input -
240 but it would be possible to create each howto field on demand.
246 <<enum complain_overflow>>
248 Indicates what sort of overflow checking should be done when
249 performing a relocation.
253 .enum complain_overflow
255 . {* Do not complain on overflow. *}
256 . complain_overflow_dont,
258 . {* Complain if the value overflows when considered as a signed
259 . number one bit larger than the field. ie. A bitfield of N bits
260 . is allowed to represent -2**n to 2**n-1. *}
261 . complain_overflow_bitfield,
263 . {* Complain if the value overflows when considered as a signed
265 . complain_overflow_signed,
267 . {* Complain if the value overflows when considered as an
268 . unsigned number. *}
269 . complain_overflow_unsigned
278 The <<reloc_howto_type>> is a structure which contains all the
279 information that libbfd needs to know to tie up a back end's data.
282 .struct bfd_symbol; {* Forward declaration. *}
284 .struct reloc_howto_struct
286 . {* The type field has mainly a documentary use - the back end can
287 . do what it wants with it, though normally the back end's
288 . external idea of what a reloc number is stored
289 . in this field. For example, a PC relative word relocation
290 . in a coff environment has the type 023 - because that's
291 . what the outside world calls a R_PCRWORD reloc. *}
294 . {* The value the final relocation is shifted right by. This drops
295 . unwanted data from the relocation. *}
296 . unsigned int rightshift;
298 . {* The size of the item to be relocated. This is *not* a
299 . power-of-two measure. To get the number of bytes operated
300 . on by a type of relocation, use bfd_get_reloc_size. *}
303 . {* The number of bits in the item to be relocated. This is used
304 . when doing overflow checking. *}
305 . unsigned int bitsize;
307 . {* The relocation is relative to the field being relocated. *}
308 . bfd_boolean pc_relative;
310 . {* The bit position of the reloc value in the destination.
311 . The relocated value is left shifted by this amount. *}
312 . unsigned int bitpos;
314 . {* What type of overflow error should be checked for when
316 . enum complain_overflow complain_on_overflow;
318 . {* If this field is non null, then the supplied function is
319 . called rather than the normal function. This allows really
320 . strange relocation methods to be accommodated. *}
321 . bfd_reloc_status_type (*special_function)
322 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
325 . {* The textual name of the relocation type. *}
328 . {* Some formats record a relocation addend in the section contents
329 . rather than with the relocation. For ELF formats this is the
330 . distinction between USE_REL and USE_RELA (though the code checks
331 . for USE_REL == 1/0). The value of this field is TRUE if the
332 . addend is recorded with the section contents; when performing a
333 . partial link (ld -r) the section contents (the data) will be
334 . modified. The value of this field is FALSE if addends are
335 . recorded with the relocation (in arelent.addend); when performing
336 . a partial link the relocation will be modified.
337 . All relocations for all ELF USE_RELA targets should set this field
338 . to FALSE (values of TRUE should be looked on with suspicion).
339 . However, the converse is not true: not all relocations of all ELF
340 . USE_REL targets set this field to TRUE. Why this is so is peculiar
341 . to each particular target. For relocs that aren't used in partial
342 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
343 . bfd_boolean partial_inplace;
345 . {* src_mask selects the part of the instruction (or data) to be used
346 . in the relocation sum. If the target relocations don't have an
347 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
348 . dst_mask to extract the addend from the section contents. If
349 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
350 . field should be zero. Non-zero values for ELF USE_RELA targets are
351 . bogus as in those cases the value in the dst_mask part of the
352 . section contents should be treated as garbage. *}
355 . {* dst_mask selects which parts of the instruction (or data) are
356 . replaced with a relocated value. *}
359 . {* When some formats create PC relative instructions, they leave
360 . the value of the pc of the place being relocated in the offset
361 . slot of the instruction, so that a PC relative relocation can
362 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
363 . Some formats leave the displacement part of an instruction
364 . empty (e.g., ELF); this flag signals the fact. *}
365 . bfd_boolean pcrel_offset;
375 The HOWTO define is horrible and will go away.
377 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
378 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
381 And will be replaced with the totally magic way. But for the
382 moment, we are compatible, so do it this way.
384 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
385 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
386 . NAME, FALSE, 0, 0, IN)
390 This is used to fill in an empty howto entry in an array.
392 .#define EMPTY_HOWTO(C) \
393 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
394 . NULL, FALSE, 0, 0, FALSE)
398 Helper routine to turn a symbol into a relocation value.
400 .#define HOWTO_PREPARE(relocation, symbol) \
402 . if (symbol != NULL) \
404 . if (bfd_is_com_section (symbol->section)) \
410 . relocation = symbol->value; \
422 unsigned int bfd_get_reloc_size (reloc_howto_type *);
425 For a reloc_howto_type that operates on a fixed number of bytes,
426 this returns the number of bytes operated on.
430 bfd_get_reloc_size (reloc_howto_type *howto)
453 How relocs are tied together in an <<asection>>:
455 .typedef struct relent_chain
458 . struct relent_chain *next;
464 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
465 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
472 bfd_reloc_status_type bfd_check_overflow
473 (enum complain_overflow how,
474 unsigned int bitsize,
475 unsigned int rightshift,
476 unsigned int addrsize,
480 Perform overflow checking on @var{relocation} which has
481 @var{bitsize} significant bits and will be shifted right by
482 @var{rightshift} bits, on a machine with addresses containing
483 @var{addrsize} significant bits. The result is either of
484 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
488 bfd_reloc_status_type
489 bfd_check_overflow (enum complain_overflow how,
490 unsigned int bitsize,
491 unsigned int rightshift,
492 unsigned int addrsize,
495 bfd_vma fieldmask, addrmask, signmask, ss, a;
496 bfd_reloc_status_type flag = bfd_reloc_ok;
498 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
499 we'll be permissive: extra bits in the field mask will
500 automatically extend the address mask for purposes of the
502 fieldmask = N_ONES (bitsize);
503 signmask = ~fieldmask;
504 addrmask = N_ONES (addrsize) | (fieldmask << rightshift);
505 a = (relocation & addrmask) >> rightshift;
509 case complain_overflow_dont:
512 case complain_overflow_signed:
513 /* If any sign bits are set, all sign bits must be set. That
514 is, A must be a valid negative address after shifting. */
515 signmask = ~ (fieldmask >> 1);
518 case complain_overflow_bitfield:
519 /* Bitfields are sometimes signed, sometimes unsigned. We
520 explicitly allow an address wrap too, which means a bitfield
521 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
522 if the value has some, but not all, bits set outside the
525 if (ss != 0 && ss != ((addrmask >> rightshift) & signmask))
526 flag = bfd_reloc_overflow;
529 case complain_overflow_unsigned:
530 /* We have an overflow if the address does not fit in the field. */
531 if ((a & signmask) != 0)
532 flag = bfd_reloc_overflow;
544 bfd_reloc_offset_in_range
547 bfd_boolean bfd_reloc_offset_in_range
548 (reloc_howto_type *howto,
551 bfd_size_type offset);
554 Returns TRUE if the reloc described by @var{HOWTO} can be
555 applied at @var{OFFSET} octets in @var{SECTION}.
559 /* HOWTO describes a relocation, at offset OCTET. Return whether the
560 relocation field is within SECTION of ABFD. */
563 bfd_reloc_offset_in_range (reloc_howto_type *howto,
568 bfd_size_type octet_end = bfd_get_section_limit_octets (abfd, section);
569 bfd_size_type reloc_size = bfd_get_reloc_size (howto);
571 /* The reloc field must be contained entirely within the section.
572 Allow zero length fields (marker relocs or NONE relocs where no
573 relocation will be performed) at the end of the section. */
574 return octet <= octet_end && octet + reloc_size <= octet_end;
577 /* Read and return the section contents at DATA converted to a host
578 integer (bfd_vma). The number of bytes read is given by the HOWTO. */
581 read_reloc (bfd *abfd, bfd_byte *data, reloc_howto_type *howto)
586 return bfd_get_8 (abfd, data);
590 return bfd_get_16 (abfd, data);
594 return bfd_get_32 (abfd, data);
601 return bfd_get_64 (abfd, data);
605 return bfd_get_24 (abfd, data);
613 /* Convert VAL to target format and write to DATA. The number of
614 bytes written is given by the HOWTO. */
617 write_reloc (bfd *abfd, bfd_vma val, bfd_byte *data, reloc_howto_type *howto)
622 bfd_put_8 (abfd, val, data);
627 bfd_put_16 (abfd, val, data);
632 bfd_put_32 (abfd, val, data);
640 bfd_put_64 (abfd, val, data);
645 bfd_put_24 (abfd, val, data);
653 /* Apply RELOCATION value to target bytes at DATA, according to
657 apply_reloc (bfd *abfd, bfd_byte *data, reloc_howto_type *howto,
660 bfd_vma val = read_reloc (abfd, data, howto);
663 relocation = -relocation;
665 val = ((val & ~howto->dst_mask)
666 | (((val & howto->src_mask) + relocation) & howto->dst_mask));
668 write_reloc (abfd, val, data, howto);
673 bfd_perform_relocation
676 bfd_reloc_status_type bfd_perform_relocation
678 arelent *reloc_entry,
680 asection *input_section,
682 char **error_message);
685 If @var{output_bfd} is supplied to this function, the
686 generated image will be relocatable; the relocations are
687 copied to the output file after they have been changed to
688 reflect the new state of the world. There are two ways of
689 reflecting the results of partial linkage in an output file:
690 by modifying the output data in place, and by modifying the
691 relocation record. Some native formats (e.g., basic a.out and
692 basic coff) have no way of specifying an addend in the
693 relocation type, so the addend has to go in the output data.
694 This is no big deal since in these formats the output data
695 slot will always be big enough for the addend. Complex reloc
696 types with addends were invented to solve just this problem.
697 The @var{error_message} argument is set to an error message if
698 this return @code{bfd_reloc_dangerous}.
702 bfd_reloc_status_type
703 bfd_perform_relocation (bfd *abfd,
704 arelent *reloc_entry,
706 asection *input_section,
708 char **error_message)
711 bfd_reloc_status_type flag = bfd_reloc_ok;
712 bfd_size_type octets;
713 bfd_vma output_base = 0;
714 reloc_howto_type *howto = reloc_entry->howto;
715 asection *reloc_target_output_section;
718 symbol = *(reloc_entry->sym_ptr_ptr);
720 /* If we are not producing relocatable output, return an error if
721 the symbol is not defined. An undefined weak symbol is
722 considered to have a value of zero (SVR4 ABI, p. 4-27). */
723 if (bfd_is_und_section (symbol->section)
724 && (symbol->flags & BSF_WEAK) == 0
725 && output_bfd == NULL)
726 flag = bfd_reloc_undefined;
728 /* If there is a function supplied to handle this relocation type,
729 call it. It'll return `bfd_reloc_continue' if further processing
731 if (howto && howto->special_function)
733 bfd_reloc_status_type cont;
735 /* Note - we do not call bfd_reloc_offset_in_range here as the
736 reloc_entry->address field might actually be valid for the
737 backend concerned. It is up to the special_function itself
738 to call bfd_reloc_offset_in_range if needed. */
739 cont = howto->special_function (abfd, reloc_entry, symbol, data,
740 input_section, output_bfd,
742 if (cont != bfd_reloc_continue)
746 if (bfd_is_abs_section (symbol->section)
747 && output_bfd != NULL)
749 reloc_entry->address += input_section->output_offset;
753 /* PR 17512: file: 0f67f69d. */
755 return bfd_reloc_undefined;
757 /* Is the address of the relocation really within the section? */
758 octets = reloc_entry->address * bfd_octets_per_byte (abfd);
759 if (!bfd_reloc_offset_in_range (howto, abfd, input_section, octets))
760 return bfd_reloc_outofrange;
762 /* Work out which section the relocation is targeted at and the
763 initial relocation command value. */
765 /* Get symbol value. (Common symbols are special.) */
766 if (bfd_is_com_section (symbol->section))
769 relocation = symbol->value;
771 reloc_target_output_section = symbol->section->output_section;
773 /* Convert input-section-relative symbol value to absolute. */
774 if ((output_bfd && ! howto->partial_inplace)
775 || reloc_target_output_section == NULL)
778 output_base = reloc_target_output_section->vma;
780 relocation += output_base + symbol->section->output_offset;
782 /* Add in supplied addend. */
783 relocation += reloc_entry->addend;
785 /* Here the variable relocation holds the final address of the
786 symbol we are relocating against, plus any addend. */
788 if (howto->pc_relative)
790 /* This is a PC relative relocation. We want to set RELOCATION
791 to the distance between the address of the symbol and the
792 location. RELOCATION is already the address of the symbol.
794 We start by subtracting the address of the section containing
797 If pcrel_offset is set, we must further subtract the position
798 of the location within the section. Some targets arrange for
799 the addend to be the negative of the position of the location
800 within the section; for example, i386-aout does this. For
801 i386-aout, pcrel_offset is FALSE. Some other targets do not
802 include the position of the location; for example, ELF.
803 For those targets, pcrel_offset is TRUE.
805 If we are producing relocatable output, then we must ensure
806 that this reloc will be correctly computed when the final
807 relocation is done. If pcrel_offset is FALSE we want to wind
808 up with the negative of the location within the section,
809 which means we must adjust the existing addend by the change
810 in the location within the section. If pcrel_offset is TRUE
811 we do not want to adjust the existing addend at all.
813 FIXME: This seems logical to me, but for the case of
814 producing relocatable output it is not what the code
815 actually does. I don't want to change it, because it seems
816 far too likely that something will break. */
819 input_section->output_section->vma + input_section->output_offset;
821 if (howto->pcrel_offset)
822 relocation -= reloc_entry->address;
825 if (output_bfd != NULL)
827 if (! howto->partial_inplace)
829 /* This is a partial relocation, and we want to apply the relocation
830 to the reloc entry rather than the raw data. Modify the reloc
831 inplace to reflect what we now know. */
832 reloc_entry->addend = relocation;
833 reloc_entry->address += input_section->output_offset;
838 /* This is a partial relocation, but inplace, so modify the
841 If we've relocated with a symbol with a section, change
842 into a ref to the section belonging to the symbol. */
844 reloc_entry->address += input_section->output_offset;
847 if (abfd->xvec->flavour == bfd_target_coff_flavour
848 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
849 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
851 /* For m68k-coff, the addend was being subtracted twice during
852 relocation with -r. Removing the line below this comment
853 fixes that problem; see PR 2953.
855 However, Ian wrote the following, regarding removing the line below,
856 which explains why it is still enabled: --djm
858 If you put a patch like that into BFD you need to check all the COFF
859 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
860 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
861 problem in a different way. There may very well be a reason that the
862 code works as it does.
864 Hmmm. The first obvious point is that bfd_perform_relocation should
865 not have any tests that depend upon the flavour. It's seem like
866 entirely the wrong place for such a thing. The second obvious point
867 is that the current code ignores the reloc addend when producing
868 relocatable output for COFF. That's peculiar. In fact, I really
869 have no idea what the point of the line you want to remove is.
871 A typical COFF reloc subtracts the old value of the symbol and adds in
872 the new value to the location in the object file (if it's a pc
873 relative reloc it adds the difference between the symbol value and the
874 location). When relocating we need to preserve that property.
876 BFD handles this by setting the addend to the negative of the old
877 value of the symbol. Unfortunately it handles common symbols in a
878 non-standard way (it doesn't subtract the old value) but that's a
879 different story (we can't change it without losing backward
880 compatibility with old object files) (coff-i386 does subtract the old
881 value, to be compatible with existing coff-i386 targets, like SCO).
883 So everything works fine when not producing relocatable output. When
884 we are producing relocatable output, logically we should do exactly
885 what we do when not producing relocatable output. Therefore, your
886 patch is correct. In fact, it should probably always just set
887 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
888 add the value into the object file. This won't hurt the COFF code,
889 which doesn't use the addend; I'm not sure what it will do to other
890 formats (the thing to check for would be whether any formats both use
891 the addend and set partial_inplace).
893 When I wanted to make coff-i386 produce relocatable output, I ran
894 into the problem that you are running into: I wanted to remove that
895 line. Rather than risk it, I made the coff-i386 relocs use a special
896 function; it's coff_i386_reloc in coff-i386.c. The function
897 specifically adds the addend field into the object file, knowing that
898 bfd_perform_relocation is not going to. If you remove that line, then
899 coff-i386.c will wind up adding the addend field in twice. It's
900 trivial to fix; it just needs to be done.
902 The problem with removing the line is just that it may break some
903 working code. With BFD it's hard to be sure of anything. The right
904 way to deal with this is simply to build and test at least all the
905 supported COFF targets. It should be straightforward if time and disk
906 space consuming. For each target:
908 2) generate some executable, and link it using -r (I would
909 probably use paranoia.o and link against newlib/libc.a, which
910 for all the supported targets would be available in
911 /usr/cygnus/progressive/H-host/target/lib/libc.a).
912 3) make the change to reloc.c
913 4) rebuild the linker
915 6) if the resulting object files are the same, you have at least
917 7) if they are different you have to figure out which version is
920 relocation -= reloc_entry->addend;
921 reloc_entry->addend = 0;
925 reloc_entry->addend = relocation;
930 /* FIXME: This overflow checking is incomplete, because the value
931 might have overflowed before we get here. For a correct check we
932 need to compute the value in a size larger than bitsize, but we
933 can't reasonably do that for a reloc the same size as a host
935 FIXME: We should also do overflow checking on the result after
936 adding in the value contained in the object file. */
937 if (howto->complain_on_overflow != complain_overflow_dont
938 && flag == bfd_reloc_ok)
939 flag = bfd_check_overflow (howto->complain_on_overflow,
942 bfd_arch_bits_per_address (abfd),
945 /* Either we are relocating all the way, or we don't want to apply
946 the relocation to the reloc entry (probably because there isn't
947 any room in the output format to describe addends to relocs). */
949 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
950 (OSF version 1.3, compiler version 3.11). It miscompiles the
964 x <<= (unsigned long) s.i0;
968 printf ("succeeded (%lx)\n", x);
972 relocation >>= (bfd_vma) howto->rightshift;
974 /* Shift everything up to where it's going to be used. */
975 relocation <<= (bfd_vma) howto->bitpos;
977 /* Wait for the day when all have the mask in them. */
980 i instruction to be left alone
981 o offset within instruction
982 r relocation offset to apply
991 (( i i i i i o o o o o from bfd_get<size>
992 and S S S S S) to get the size offset we want
993 + r r r r r r r r r r) to get the final value to place
994 and D D D D D to chop to right size
995 -----------------------
998 ( i i i i i o o o o o from bfd_get<size>
999 and N N N N N ) get instruction
1000 -----------------------
1006 -----------------------
1007 = R R R R R R R R R R put into bfd_put<size>
1010 data = (bfd_byte *) data + octets;
1011 apply_reloc (abfd, data, howto, relocation);
1017 bfd_install_relocation
1020 bfd_reloc_status_type bfd_install_relocation
1022 arelent *reloc_entry,
1023 void *data, bfd_vma data_start,
1024 asection *input_section,
1025 char **error_message);
1028 This looks remarkably like <<bfd_perform_relocation>>, except it
1029 does not expect that the section contents have been filled in.
1030 I.e., it's suitable for use when creating, rather than applying
1033 For now, this function should be considered reserved for the
1037 bfd_reloc_status_type
1038 bfd_install_relocation (bfd *abfd,
1039 arelent *reloc_entry,
1041 bfd_vma data_start_offset,
1042 asection *input_section,
1043 char **error_message)
1046 bfd_reloc_status_type flag = bfd_reloc_ok;
1047 bfd_size_type octets;
1048 bfd_vma output_base = 0;
1049 reloc_howto_type *howto = reloc_entry->howto;
1050 asection *reloc_target_output_section;
1054 symbol = *(reloc_entry->sym_ptr_ptr);
1056 /* If there is a function supplied to handle this relocation type,
1057 call it. It'll return `bfd_reloc_continue' if further processing
1059 if (howto && howto->special_function)
1061 bfd_reloc_status_type cont;
1063 /* Note - we do not call bfd_reloc_offset_in_range here as the
1064 reloc_entry->address field might actually be valid for the
1065 backend concerned. It is up to the special_function itself
1066 to call bfd_reloc_offset_in_range if needed. */
1067 /* XXX - The special_function calls haven't been fixed up to deal
1068 with creating new relocations and section contents. */
1069 cont = howto->special_function (abfd, reloc_entry, symbol,
1070 /* XXX - Non-portable! */
1071 ((bfd_byte *) data_start
1072 - data_start_offset),
1073 input_section, abfd, error_message);
1074 if (cont != bfd_reloc_continue)
1078 if (bfd_is_abs_section (symbol->section))
1080 reloc_entry->address += input_section->output_offset;
1081 return bfd_reloc_ok;
1084 /* No need to check for howto != NULL if !bfd_is_abs_section as
1085 it will have been checked in `bfd_perform_relocation already'. */
1087 /* Is the address of the relocation really within the section? */
1088 octets = reloc_entry->address * bfd_octets_per_byte (abfd);
1089 if (!bfd_reloc_offset_in_range (howto, abfd, input_section, octets))
1090 return bfd_reloc_outofrange;
1092 /* Work out which section the relocation is targeted at and the
1093 initial relocation command value. */
1095 /* Get symbol value. (Common symbols are special.) */
1096 if (bfd_is_com_section (symbol->section))
1099 relocation = symbol->value;
1101 reloc_target_output_section = symbol->section->output_section;
1103 /* Convert input-section-relative symbol value to absolute. */
1104 if (! howto->partial_inplace)
1107 output_base = reloc_target_output_section->vma;
1109 relocation += output_base + symbol->section->output_offset;
1111 /* Add in supplied addend. */
1112 relocation += reloc_entry->addend;
1114 /* Here the variable relocation holds the final address of the
1115 symbol we are relocating against, plus any addend. */
1117 if (howto->pc_relative)
1119 /* This is a PC relative relocation. We want to set RELOCATION
1120 to the distance between the address of the symbol and the
1121 location. RELOCATION is already the address of the symbol.
1123 We start by subtracting the address of the section containing
1126 If pcrel_offset is set, we must further subtract the position
1127 of the location within the section. Some targets arrange for
1128 the addend to be the negative of the position of the location
1129 within the section; for example, i386-aout does this. For
1130 i386-aout, pcrel_offset is FALSE. Some other targets do not
1131 include the position of the location; for example, ELF.
1132 For those targets, pcrel_offset is TRUE.
1134 If we are producing relocatable output, then we must ensure
1135 that this reloc will be correctly computed when the final
1136 relocation is done. If pcrel_offset is FALSE we want to wind
1137 up with the negative of the location within the section,
1138 which means we must adjust the existing addend by the change
1139 in the location within the section. If pcrel_offset is TRUE
1140 we do not want to adjust the existing addend at all.
1142 FIXME: This seems logical to me, but for the case of
1143 producing relocatable output it is not what the code
1144 actually does. I don't want to change it, because it seems
1145 far too likely that something will break. */
1148 input_section->output_section->vma + input_section->output_offset;
1150 if (howto->pcrel_offset && howto->partial_inplace)
1151 relocation -= reloc_entry->address;
1154 if (! howto->partial_inplace)
1156 /* This is a partial relocation, and we want to apply the relocation
1157 to the reloc entry rather than the raw data. Modify the reloc
1158 inplace to reflect what we now know. */
1159 reloc_entry->addend = relocation;
1160 reloc_entry->address += input_section->output_offset;
1165 /* This is a partial relocation, but inplace, so modify the
1168 If we've relocated with a symbol with a section, change
1169 into a ref to the section belonging to the symbol. */
1170 reloc_entry->address += input_section->output_offset;
1173 if (abfd->xvec->flavour == bfd_target_coff_flavour
1174 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
1175 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
1178 /* For m68k-coff, the addend was being subtracted twice during
1179 relocation with -r. Removing the line below this comment
1180 fixes that problem; see PR 2953.
1182 However, Ian wrote the following, regarding removing the line below,
1183 which explains why it is still enabled: --djm
1185 If you put a patch like that into BFD you need to check all the COFF
1186 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1187 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1188 problem in a different way. There may very well be a reason that the
1189 code works as it does.
1191 Hmmm. The first obvious point is that bfd_install_relocation should
1192 not have any tests that depend upon the flavour. It's seem like
1193 entirely the wrong place for such a thing. The second obvious point
1194 is that the current code ignores the reloc addend when producing
1195 relocatable output for COFF. That's peculiar. In fact, I really
1196 have no idea what the point of the line you want to remove is.
1198 A typical COFF reloc subtracts the old value of the symbol and adds in
1199 the new value to the location in the object file (if it's a pc
1200 relative reloc it adds the difference between the symbol value and the
1201 location). When relocating we need to preserve that property.
1203 BFD handles this by setting the addend to the negative of the old
1204 value of the symbol. Unfortunately it handles common symbols in a
1205 non-standard way (it doesn't subtract the old value) but that's a
1206 different story (we can't change it without losing backward
1207 compatibility with old object files) (coff-i386 does subtract the old
1208 value, to be compatible with existing coff-i386 targets, like SCO).
1210 So everything works fine when not producing relocatable output. When
1211 we are producing relocatable output, logically we should do exactly
1212 what we do when not producing relocatable output. Therefore, your
1213 patch is correct. In fact, it should probably always just set
1214 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1215 add the value into the object file. This won't hurt the COFF code,
1216 which doesn't use the addend; I'm not sure what it will do to other
1217 formats (the thing to check for would be whether any formats both use
1218 the addend and set partial_inplace).
1220 When I wanted to make coff-i386 produce relocatable output, I ran
1221 into the problem that you are running into: I wanted to remove that
1222 line. Rather than risk it, I made the coff-i386 relocs use a special
1223 function; it's coff_i386_reloc in coff-i386.c. The function
1224 specifically adds the addend field into the object file, knowing that
1225 bfd_install_relocation is not going to. If you remove that line, then
1226 coff-i386.c will wind up adding the addend field in twice. It's
1227 trivial to fix; it just needs to be done.
1229 The problem with removing the line is just that it may break some
1230 working code. With BFD it's hard to be sure of anything. The right
1231 way to deal with this is simply to build and test at least all the
1232 supported COFF targets. It should be straightforward if time and disk
1233 space consuming. For each target:
1235 2) generate some executable, and link it using -r (I would
1236 probably use paranoia.o and link against newlib/libc.a, which
1237 for all the supported targets would be available in
1238 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1239 3) make the change to reloc.c
1240 4) rebuild the linker
1242 6) if the resulting object files are the same, you have at least
1244 7) if they are different you have to figure out which version is
1246 relocation -= reloc_entry->addend;
1247 /* FIXME: There should be no target specific code here... */
1248 if (strcmp (abfd->xvec->name, "coff-z8k") != 0)
1249 reloc_entry->addend = 0;
1253 reloc_entry->addend = relocation;
1257 /* FIXME: This overflow checking is incomplete, because the value
1258 might have overflowed before we get here. For a correct check we
1259 need to compute the value in a size larger than bitsize, but we
1260 can't reasonably do that for a reloc the same size as a host
1262 FIXME: We should also do overflow checking on the result after
1263 adding in the value contained in the object file. */
1264 if (howto->complain_on_overflow != complain_overflow_dont)
1265 flag = bfd_check_overflow (howto->complain_on_overflow,
1268 bfd_arch_bits_per_address (abfd),
1271 /* Either we are relocating all the way, or we don't want to apply
1272 the relocation to the reloc entry (probably because there isn't
1273 any room in the output format to describe addends to relocs). */
1275 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1276 (OSF version 1.3, compiler version 3.11). It miscompiles the
1290 x <<= (unsigned long) s.i0;
1292 printf ("failed\n");
1294 printf ("succeeded (%lx)\n", x);
1298 relocation >>= (bfd_vma) howto->rightshift;
1300 /* Shift everything up to where it's going to be used. */
1301 relocation <<= (bfd_vma) howto->bitpos;
1303 /* Wait for the day when all have the mask in them. */
1306 i instruction to be left alone
1307 o offset within instruction
1308 r relocation offset to apply
1317 (( i i i i i o o o o o from bfd_get<size>
1318 and S S S S S) to get the size offset we want
1319 + r r r r r r r r r r) to get the final value to place
1320 and D D D D D to chop to right size
1321 -----------------------
1324 ( i i i i i o o o o o from bfd_get<size>
1325 and N N N N N ) get instruction
1326 -----------------------
1332 -----------------------
1333 = R R R R R R R R R R put into bfd_put<size>
1336 data = (bfd_byte *) data_start + (octets - data_start_offset);
1337 apply_reloc (abfd, data, howto, relocation);
1341 /* This relocation routine is used by some of the backend linkers.
1342 They do not construct asymbol or arelent structures, so there is no
1343 reason for them to use bfd_perform_relocation. Also,
1344 bfd_perform_relocation is so hacked up it is easier to write a new
1345 function than to try to deal with it.
1347 This routine does a final relocation. Whether it is useful for a
1348 relocatable link depends upon how the object format defines
1351 FIXME: This routine ignores any special_function in the HOWTO,
1352 since the existing special_function values have been written for
1353 bfd_perform_relocation.
1355 HOWTO is the reloc howto information.
1356 INPUT_BFD is the BFD which the reloc applies to.
1357 INPUT_SECTION is the section which the reloc applies to.
1358 CONTENTS is the contents of the section.
1359 ADDRESS is the address of the reloc within INPUT_SECTION.
1360 VALUE is the value of the symbol the reloc refers to.
1361 ADDEND is the addend of the reloc. */
1363 bfd_reloc_status_type
1364 _bfd_final_link_relocate (reloc_howto_type *howto,
1366 asection *input_section,
1373 bfd_size_type octets = address * bfd_octets_per_byte (input_bfd);
1375 /* Sanity check the address. */
1376 if (!bfd_reloc_offset_in_range (howto, input_bfd, input_section, octets))
1377 return bfd_reloc_outofrange;
1379 /* This function assumes that we are dealing with a basic relocation
1380 against a symbol. We want to compute the value of the symbol to
1381 relocate to. This is just VALUE, the value of the symbol, plus
1382 ADDEND, any addend associated with the reloc. */
1383 relocation = value + addend;
1385 /* If the relocation is PC relative, we want to set RELOCATION to
1386 the distance between the symbol (currently in RELOCATION) and the
1387 location we are relocating. Some targets (e.g., i386-aout)
1388 arrange for the contents of the section to be the negative of the
1389 offset of the location within the section; for such targets
1390 pcrel_offset is FALSE. Other targets (e.g., ELF) simply leave
1391 the contents of the section as zero; for such targets
1392 pcrel_offset is TRUE. If pcrel_offset is FALSE we do not need to
1393 subtract out the offset of the location within the section (which
1394 is just ADDRESS). */
1395 if (howto->pc_relative)
1397 relocation -= (input_section->output_section->vma
1398 + input_section->output_offset);
1399 if (howto->pcrel_offset)
1400 relocation -= address;
1403 return _bfd_relocate_contents (howto, input_bfd, relocation,
1405 + address * bfd_octets_per_byte (input_bfd));
1408 /* Relocate a given location using a given value and howto. */
1410 bfd_reloc_status_type
1411 _bfd_relocate_contents (reloc_howto_type *howto,
1417 bfd_reloc_status_type flag;
1418 unsigned int rightshift = howto->rightshift;
1419 unsigned int bitpos = howto->bitpos;
1421 /* If the size is negative, negate RELOCATION. This isn't very
1423 if (howto->size < 0)
1424 relocation = -relocation;
1426 /* Get the value we are going to relocate. */
1427 x = read_reloc (input_bfd, location, howto);
1429 /* Check for overflow. FIXME: We may drop bits during the addition
1430 which we don't check for. We must either check at every single
1431 operation, which would be tedious, or we must do the computations
1432 in a type larger than bfd_vma, which would be inefficient. */
1433 flag = bfd_reloc_ok;
1434 if (howto->complain_on_overflow != complain_overflow_dont)
1436 bfd_vma addrmask, fieldmask, signmask, ss;
1439 /* Get the values to be added together. For signed and unsigned
1440 relocations, we assume that all values should be truncated to
1441 the size of an address. For bitfields, all the bits matter.
1442 See also bfd_check_overflow. */
1443 fieldmask = N_ONES (howto->bitsize);
1444 signmask = ~fieldmask;
1445 addrmask = (N_ONES (bfd_arch_bits_per_address (input_bfd))
1446 | (fieldmask << rightshift));
1447 a = (relocation & addrmask) >> rightshift;
1448 b = (x & howto->src_mask & addrmask) >> bitpos;
1449 addrmask >>= rightshift;
1451 switch (howto->complain_on_overflow)
1453 case complain_overflow_signed:
1454 /* If any sign bits are set, all sign bits must be set.
1455 That is, A must be a valid negative address after
1457 signmask = ~(fieldmask >> 1);
1460 case complain_overflow_bitfield:
1461 /* Much like the signed check, but for a field one bit
1462 wider. We allow a bitfield to represent numbers in the
1463 range -2**n to 2**n-1, where n is the number of bits in the
1464 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1465 can't overflow, which is exactly what we want. */
1467 if (ss != 0 && ss != (addrmask & signmask))
1468 flag = bfd_reloc_overflow;
1470 /* We only need this next bit of code if the sign bit of B
1471 is below the sign bit of A. This would only happen if
1472 SRC_MASK had fewer bits than BITSIZE. Note that if
1473 SRC_MASK has more bits than BITSIZE, we can get into
1474 trouble; we would need to verify that B is in range, as
1475 we do for A above. */
1476 ss = ((~howto->src_mask) >> 1) & howto->src_mask;
1479 /* Set all the bits above the sign bit. */
1482 /* Now we can do the addition. */
1485 /* See if the result has the correct sign. Bits above the
1486 sign bit are junk now; ignore them. If the sum is
1487 positive, make sure we did not have all negative inputs;
1488 if the sum is negative, make sure we did not have all
1489 positive inputs. The test below looks only at the sign
1490 bits, and it really just
1491 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1493 We mask with addrmask here to explicitly allow an address
1494 wrap-around. The Linux kernel relies on it, and it is
1495 the only way to write assembler code which can run when
1496 loaded at a location 0x80000000 away from the location at
1497 which it is linked. */
1498 if (((~(a ^ b)) & (a ^ sum)) & signmask & addrmask)
1499 flag = bfd_reloc_overflow;
1502 case complain_overflow_unsigned:
1503 /* Checking for an unsigned overflow is relatively easy:
1504 trim the addresses and add, and trim the result as well.
1505 Overflow is normally indicated when the result does not
1506 fit in the field. However, we also need to consider the
1507 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1508 input is 0x80000000, and bfd_vma is only 32 bits; then we
1509 will get sum == 0, but there is an overflow, since the
1510 inputs did not fit in the field. Instead of doing a
1511 separate test, we can check for this by or-ing in the
1512 operands when testing for the sum overflowing its final
1514 sum = (a + b) & addrmask;
1515 if ((a | b | sum) & signmask)
1516 flag = bfd_reloc_overflow;
1524 /* Put RELOCATION in the right bits. */
1525 relocation >>= (bfd_vma) rightshift;
1526 relocation <<= (bfd_vma) bitpos;
1528 /* Add RELOCATION to the right bits of X. */
1529 x = ((x & ~howto->dst_mask)
1530 | (((x & howto->src_mask) + relocation) & howto->dst_mask));
1532 /* Put the relocated value back in the object file. */
1533 write_reloc (input_bfd, x, location, howto);
1537 /* Clear a given location using a given howto, by applying a fixed relocation
1538 value and discarding any in-place addend. This is used for fixed-up
1539 relocations against discarded symbols, to make ignorable debug or unwind
1540 information more obvious. */
1543 _bfd_clear_contents (reloc_howto_type *howto,
1545 asection *input_section,
1550 /* Get the value we are going to relocate. */
1551 x = read_reloc (input_bfd, location, howto);
1553 /* Zero out the unwanted bits of X. */
1554 x &= ~howto->dst_mask;
1556 /* For a range list, use 1 instead of 0 as placeholder. 0
1557 would terminate the list, hiding any later entries. */
1558 if (strcmp (bfd_get_section_name (input_bfd, input_section),
1559 ".debug_ranges") == 0
1560 && (howto->dst_mask & 1) != 0)
1563 /* Put the relocated value back in the object file. */
1564 write_reloc (input_bfd, x, location, howto);
1570 howto manager, , typedef arelent, Relocations
1575 When an application wants to create a relocation, but doesn't
1576 know what the target machine might call it, it can find out by
1577 using this bit of code.
1586 The insides of a reloc code. The idea is that, eventually, there
1587 will be one enumerator for every type of relocation we ever do.
1588 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1589 return a howto pointer.
1591 This does mean that the application must determine the correct
1592 enumerator value; you can't get a howto pointer from a random set
1613 Basic absolute relocations of N bits.
1628 PC-relative relocations. Sometimes these are relative to the address
1629 of the relocation itself; sometimes they are relative to the start of
1630 the section containing the relocation. It depends on the specific target.
1635 Section relative relocations. Some targets need this for DWARF2.
1638 BFD_RELOC_32_GOT_PCREL
1640 BFD_RELOC_16_GOT_PCREL
1642 BFD_RELOC_8_GOT_PCREL
1648 BFD_RELOC_LO16_GOTOFF
1650 BFD_RELOC_HI16_GOTOFF
1652 BFD_RELOC_HI16_S_GOTOFF
1656 BFD_RELOC_64_PLT_PCREL
1658 BFD_RELOC_32_PLT_PCREL
1660 BFD_RELOC_24_PLT_PCREL
1662 BFD_RELOC_16_PLT_PCREL
1664 BFD_RELOC_8_PLT_PCREL
1672 BFD_RELOC_LO16_PLTOFF
1674 BFD_RELOC_HI16_PLTOFF
1676 BFD_RELOC_HI16_S_PLTOFF
1690 BFD_RELOC_68K_GLOB_DAT
1692 BFD_RELOC_68K_JMP_SLOT
1694 BFD_RELOC_68K_RELATIVE
1696 BFD_RELOC_68K_TLS_GD32
1698 BFD_RELOC_68K_TLS_GD16
1700 BFD_RELOC_68K_TLS_GD8
1702 BFD_RELOC_68K_TLS_LDM32
1704 BFD_RELOC_68K_TLS_LDM16
1706 BFD_RELOC_68K_TLS_LDM8
1708 BFD_RELOC_68K_TLS_LDO32
1710 BFD_RELOC_68K_TLS_LDO16
1712 BFD_RELOC_68K_TLS_LDO8
1714 BFD_RELOC_68K_TLS_IE32
1716 BFD_RELOC_68K_TLS_IE16
1718 BFD_RELOC_68K_TLS_IE8
1720 BFD_RELOC_68K_TLS_LE32
1722 BFD_RELOC_68K_TLS_LE16
1724 BFD_RELOC_68K_TLS_LE8
1726 Relocations used by 68K ELF.
1729 BFD_RELOC_32_BASEREL
1731 BFD_RELOC_16_BASEREL
1733 BFD_RELOC_LO16_BASEREL
1735 BFD_RELOC_HI16_BASEREL
1737 BFD_RELOC_HI16_S_BASEREL
1743 Linkage-table relative.
1748 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1751 BFD_RELOC_32_PCREL_S2
1753 BFD_RELOC_16_PCREL_S2
1755 BFD_RELOC_23_PCREL_S2
1757 These PC-relative relocations are stored as word displacements --
1758 i.e., byte displacements shifted right two bits. The 30-bit word
1759 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1760 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1761 signed 16-bit displacement is used on the MIPS, and the 23-bit
1762 displacement is used on the Alpha.
1769 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1770 the target word. These are used on the SPARC.
1777 For systems that allocate a Global Pointer register, these are
1778 displacements off that register. These relocation types are
1779 handled specially, because the value the register will have is
1780 decided relatively late.
1785 BFD_RELOC_SPARC_WDISP22
1791 BFD_RELOC_SPARC_GOT10
1793 BFD_RELOC_SPARC_GOT13
1795 BFD_RELOC_SPARC_GOT22
1797 BFD_RELOC_SPARC_PC10
1799 BFD_RELOC_SPARC_PC22
1801 BFD_RELOC_SPARC_WPLT30
1803 BFD_RELOC_SPARC_COPY
1805 BFD_RELOC_SPARC_GLOB_DAT
1807 BFD_RELOC_SPARC_JMP_SLOT
1809 BFD_RELOC_SPARC_RELATIVE
1811 BFD_RELOC_SPARC_UA16
1813 BFD_RELOC_SPARC_UA32
1815 BFD_RELOC_SPARC_UA64
1817 BFD_RELOC_SPARC_GOTDATA_HIX22
1819 BFD_RELOC_SPARC_GOTDATA_LOX10
1821 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1823 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1825 BFD_RELOC_SPARC_GOTDATA_OP
1827 BFD_RELOC_SPARC_JMP_IREL
1829 BFD_RELOC_SPARC_IRELATIVE
1831 SPARC ELF relocations. There is probably some overlap with other
1832 relocation types already defined.
1835 BFD_RELOC_SPARC_BASE13
1837 BFD_RELOC_SPARC_BASE22
1839 I think these are specific to SPARC a.out (e.g., Sun 4).
1849 BFD_RELOC_SPARC_OLO10
1851 BFD_RELOC_SPARC_HH22
1853 BFD_RELOC_SPARC_HM10
1855 BFD_RELOC_SPARC_LM22
1857 BFD_RELOC_SPARC_PC_HH22
1859 BFD_RELOC_SPARC_PC_HM10
1861 BFD_RELOC_SPARC_PC_LM22
1863 BFD_RELOC_SPARC_WDISP16
1865 BFD_RELOC_SPARC_WDISP19
1873 BFD_RELOC_SPARC_DISP64
1876 BFD_RELOC_SPARC_PLT32
1878 BFD_RELOC_SPARC_PLT64
1880 BFD_RELOC_SPARC_HIX22
1882 BFD_RELOC_SPARC_LOX10
1890 BFD_RELOC_SPARC_REGISTER
1894 BFD_RELOC_SPARC_SIZE32
1896 BFD_RELOC_SPARC_SIZE64
1898 BFD_RELOC_SPARC_WDISP10
1903 BFD_RELOC_SPARC_REV32
1905 SPARC little endian relocation
1907 BFD_RELOC_SPARC_TLS_GD_HI22
1909 BFD_RELOC_SPARC_TLS_GD_LO10
1911 BFD_RELOC_SPARC_TLS_GD_ADD
1913 BFD_RELOC_SPARC_TLS_GD_CALL
1915 BFD_RELOC_SPARC_TLS_LDM_HI22
1917 BFD_RELOC_SPARC_TLS_LDM_LO10
1919 BFD_RELOC_SPARC_TLS_LDM_ADD
1921 BFD_RELOC_SPARC_TLS_LDM_CALL
1923 BFD_RELOC_SPARC_TLS_LDO_HIX22
1925 BFD_RELOC_SPARC_TLS_LDO_LOX10
1927 BFD_RELOC_SPARC_TLS_LDO_ADD
1929 BFD_RELOC_SPARC_TLS_IE_HI22
1931 BFD_RELOC_SPARC_TLS_IE_LO10
1933 BFD_RELOC_SPARC_TLS_IE_LD
1935 BFD_RELOC_SPARC_TLS_IE_LDX
1937 BFD_RELOC_SPARC_TLS_IE_ADD
1939 BFD_RELOC_SPARC_TLS_LE_HIX22
1941 BFD_RELOC_SPARC_TLS_LE_LOX10
1943 BFD_RELOC_SPARC_TLS_DTPMOD32
1945 BFD_RELOC_SPARC_TLS_DTPMOD64
1947 BFD_RELOC_SPARC_TLS_DTPOFF32
1949 BFD_RELOC_SPARC_TLS_DTPOFF64
1951 BFD_RELOC_SPARC_TLS_TPOFF32
1953 BFD_RELOC_SPARC_TLS_TPOFF64
1955 SPARC TLS relocations
1964 BFD_RELOC_SPU_IMM10W
1968 BFD_RELOC_SPU_IMM16W
1972 BFD_RELOC_SPU_PCREL9a
1974 BFD_RELOC_SPU_PCREL9b
1976 BFD_RELOC_SPU_PCREL16
1986 BFD_RELOC_SPU_ADD_PIC
1991 BFD_RELOC_ALPHA_GPDISP_HI16
1993 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
1994 "addend" in some special way.
1995 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
1996 writing; when reading, it will be the absolute section symbol. The
1997 addend is the displacement in bytes of the "lda" instruction from
1998 the "ldah" instruction (which is at the address of this reloc).
2000 BFD_RELOC_ALPHA_GPDISP_LO16
2002 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2003 with GPDISP_HI16 relocs. The addend is ignored when writing the
2004 relocations out, and is filled in with the file's GP value on
2005 reading, for convenience.
2008 BFD_RELOC_ALPHA_GPDISP
2010 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2011 relocation except that there is no accompanying GPDISP_LO16
2015 BFD_RELOC_ALPHA_LITERAL
2017 BFD_RELOC_ALPHA_ELF_LITERAL
2019 BFD_RELOC_ALPHA_LITUSE
2021 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2022 the assembler turns it into a LDQ instruction to load the address of
2023 the symbol, and then fills in a register in the real instruction.
2025 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2026 section symbol. The addend is ignored when writing, but is filled
2027 in with the file's GP value on reading, for convenience, as with the
2030 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2031 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2032 but it generates output not based on the position within the .got
2033 section, but relative to the GP value chosen for the file during the
2036 The LITUSE reloc, on the instruction using the loaded address, gives
2037 information to the linker that it might be able to use to optimize
2038 away some literal section references. The symbol is ignored (read
2039 as the absolute section symbol), and the "addend" indicates the type
2040 of instruction using the register:
2041 1 - "memory" fmt insn
2042 2 - byte-manipulation (byte offset reg)
2043 3 - jsr (target of branch)
2046 BFD_RELOC_ALPHA_HINT
2048 The HINT relocation indicates a value that should be filled into the
2049 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2050 prediction logic which may be provided on some processors.
2053 BFD_RELOC_ALPHA_LINKAGE
2055 The LINKAGE relocation outputs a linkage pair in the object file,
2056 which is filled by the linker.
2059 BFD_RELOC_ALPHA_CODEADDR
2061 The CODEADDR relocation outputs a STO_CA in the object file,
2062 which is filled by the linker.
2065 BFD_RELOC_ALPHA_GPREL_HI16
2067 BFD_RELOC_ALPHA_GPREL_LO16
2069 The GPREL_HI/LO relocations together form a 32-bit offset from the
2073 BFD_RELOC_ALPHA_BRSGP
2075 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2076 share a common GP, and the target address is adjusted for
2077 STO_ALPHA_STD_GPLOAD.
2082 The NOP relocation outputs a NOP if the longword displacement
2083 between two procedure entry points is < 2^21.
2088 The BSR relocation outputs a BSR if the longword displacement
2089 between two procedure entry points is < 2^21.
2094 The LDA relocation outputs a LDA if the longword displacement
2095 between two procedure entry points is < 2^16.
2100 The BOH relocation outputs a BSR if the longword displacement
2101 between two procedure entry points is < 2^21, or else a hint.
2104 BFD_RELOC_ALPHA_TLSGD
2106 BFD_RELOC_ALPHA_TLSLDM
2108 BFD_RELOC_ALPHA_DTPMOD64
2110 BFD_RELOC_ALPHA_GOTDTPREL16
2112 BFD_RELOC_ALPHA_DTPREL64
2114 BFD_RELOC_ALPHA_DTPREL_HI16
2116 BFD_RELOC_ALPHA_DTPREL_LO16
2118 BFD_RELOC_ALPHA_DTPREL16
2120 BFD_RELOC_ALPHA_GOTTPREL16
2122 BFD_RELOC_ALPHA_TPREL64
2124 BFD_RELOC_ALPHA_TPREL_HI16
2126 BFD_RELOC_ALPHA_TPREL_LO16
2128 BFD_RELOC_ALPHA_TPREL16
2130 Alpha thread-local storage relocations.
2135 BFD_RELOC_MICROMIPS_JMP
2137 The MIPS jump instruction.
2140 BFD_RELOC_MIPS16_JMP
2142 The MIPS16 jump instruction.
2145 BFD_RELOC_MIPS16_GPREL
2147 MIPS16 GP relative reloc.
2152 High 16 bits of 32-bit value; simple reloc.
2157 High 16 bits of 32-bit value but the low 16 bits will be sign
2158 extended and added to form the final result. If the low 16
2159 bits form a negative number, we need to add one to the high value
2160 to compensate for the borrow when the low bits are added.
2168 BFD_RELOC_HI16_PCREL
2170 High 16 bits of 32-bit pc-relative value
2172 BFD_RELOC_HI16_S_PCREL
2174 High 16 bits of 32-bit pc-relative value, adjusted
2176 BFD_RELOC_LO16_PCREL
2178 Low 16 bits of pc-relative value
2181 BFD_RELOC_MIPS16_GOT16
2183 BFD_RELOC_MIPS16_CALL16
2185 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2186 16-bit immediate fields
2188 BFD_RELOC_MIPS16_HI16
2190 MIPS16 high 16 bits of 32-bit value.
2192 BFD_RELOC_MIPS16_HI16_S
2194 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2195 extended and added to form the final result. If the low 16
2196 bits form a negative number, we need to add one to the high value
2197 to compensate for the borrow when the low bits are added.
2199 BFD_RELOC_MIPS16_LO16
2204 BFD_RELOC_MIPS16_TLS_GD
2206 BFD_RELOC_MIPS16_TLS_LDM
2208 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2210 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2212 BFD_RELOC_MIPS16_TLS_GOTTPREL
2214 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2216 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2218 MIPS16 TLS relocations
2221 BFD_RELOC_MIPS_LITERAL
2223 BFD_RELOC_MICROMIPS_LITERAL
2225 Relocation against a MIPS literal section.
2228 BFD_RELOC_MICROMIPS_7_PCREL_S1
2230 BFD_RELOC_MICROMIPS_10_PCREL_S1
2232 BFD_RELOC_MICROMIPS_16_PCREL_S1
2234 microMIPS PC-relative relocations.
2237 BFD_RELOC_MIPS16_16_PCREL_S1
2239 MIPS16 PC-relative relocation.
2242 BFD_RELOC_MIPS_21_PCREL_S2
2244 BFD_RELOC_MIPS_26_PCREL_S2
2246 BFD_RELOC_MIPS_18_PCREL_S3
2248 BFD_RELOC_MIPS_19_PCREL_S2
2250 MIPS PC-relative relocations.
2253 BFD_RELOC_MICROMIPS_GPREL16
2255 BFD_RELOC_MICROMIPS_HI16
2257 BFD_RELOC_MICROMIPS_HI16_S
2259 BFD_RELOC_MICROMIPS_LO16
2261 microMIPS versions of generic BFD relocs.
2264 BFD_RELOC_MIPS_GOT16
2266 BFD_RELOC_MICROMIPS_GOT16
2268 BFD_RELOC_MIPS_CALL16
2270 BFD_RELOC_MICROMIPS_CALL16
2272 BFD_RELOC_MIPS_GOT_HI16
2274 BFD_RELOC_MICROMIPS_GOT_HI16
2276 BFD_RELOC_MIPS_GOT_LO16
2278 BFD_RELOC_MICROMIPS_GOT_LO16
2280 BFD_RELOC_MIPS_CALL_HI16
2282 BFD_RELOC_MICROMIPS_CALL_HI16
2284 BFD_RELOC_MIPS_CALL_LO16
2286 BFD_RELOC_MICROMIPS_CALL_LO16
2290 BFD_RELOC_MICROMIPS_SUB
2292 BFD_RELOC_MIPS_GOT_PAGE
2294 BFD_RELOC_MICROMIPS_GOT_PAGE
2296 BFD_RELOC_MIPS_GOT_OFST
2298 BFD_RELOC_MICROMIPS_GOT_OFST
2300 BFD_RELOC_MIPS_GOT_DISP
2302 BFD_RELOC_MICROMIPS_GOT_DISP
2304 BFD_RELOC_MIPS_SHIFT5
2306 BFD_RELOC_MIPS_SHIFT6
2308 BFD_RELOC_MIPS_INSERT_A
2310 BFD_RELOC_MIPS_INSERT_B
2312 BFD_RELOC_MIPS_DELETE
2314 BFD_RELOC_MIPS_HIGHEST
2316 BFD_RELOC_MICROMIPS_HIGHEST
2318 BFD_RELOC_MIPS_HIGHER
2320 BFD_RELOC_MICROMIPS_HIGHER
2322 BFD_RELOC_MIPS_SCN_DISP
2324 BFD_RELOC_MICROMIPS_SCN_DISP
2326 BFD_RELOC_MIPS_REL16
2328 BFD_RELOC_MIPS_RELGOT
2332 BFD_RELOC_MICROMIPS_JALR
2334 BFD_RELOC_MIPS_TLS_DTPMOD32
2336 BFD_RELOC_MIPS_TLS_DTPREL32
2338 BFD_RELOC_MIPS_TLS_DTPMOD64
2340 BFD_RELOC_MIPS_TLS_DTPREL64
2342 BFD_RELOC_MIPS_TLS_GD
2344 BFD_RELOC_MICROMIPS_TLS_GD
2346 BFD_RELOC_MIPS_TLS_LDM
2348 BFD_RELOC_MICROMIPS_TLS_LDM
2350 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2352 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2354 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2356 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2358 BFD_RELOC_MIPS_TLS_GOTTPREL
2360 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2362 BFD_RELOC_MIPS_TLS_TPREL32
2364 BFD_RELOC_MIPS_TLS_TPREL64
2366 BFD_RELOC_MIPS_TLS_TPREL_HI16
2368 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2370 BFD_RELOC_MIPS_TLS_TPREL_LO16
2372 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2376 MIPS ELF relocations.
2382 BFD_RELOC_MIPS_JUMP_SLOT
2384 MIPS ELF relocations (VxWorks and PLT extensions).
2388 BFD_RELOC_MOXIE_10_PCREL
2390 Moxie ELF relocations.
2402 BFD_RELOC_FT32_RELAX
2410 BFD_RELOC_FT32_DIFF32
2412 FT32 ELF relocations.
2416 BFD_RELOC_FRV_LABEL16
2418 BFD_RELOC_FRV_LABEL24
2424 BFD_RELOC_FRV_GPREL12
2426 BFD_RELOC_FRV_GPRELU12
2428 BFD_RELOC_FRV_GPREL32
2430 BFD_RELOC_FRV_GPRELHI
2432 BFD_RELOC_FRV_GPRELLO
2440 BFD_RELOC_FRV_FUNCDESC
2442 BFD_RELOC_FRV_FUNCDESC_GOT12
2444 BFD_RELOC_FRV_FUNCDESC_GOTHI
2446 BFD_RELOC_FRV_FUNCDESC_GOTLO
2448 BFD_RELOC_FRV_FUNCDESC_VALUE
2450 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2452 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2454 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2456 BFD_RELOC_FRV_GOTOFF12
2458 BFD_RELOC_FRV_GOTOFFHI
2460 BFD_RELOC_FRV_GOTOFFLO
2462 BFD_RELOC_FRV_GETTLSOFF
2464 BFD_RELOC_FRV_TLSDESC_VALUE
2466 BFD_RELOC_FRV_GOTTLSDESC12
2468 BFD_RELOC_FRV_GOTTLSDESCHI
2470 BFD_RELOC_FRV_GOTTLSDESCLO
2472 BFD_RELOC_FRV_TLSMOFF12
2474 BFD_RELOC_FRV_TLSMOFFHI
2476 BFD_RELOC_FRV_TLSMOFFLO
2478 BFD_RELOC_FRV_GOTTLSOFF12
2480 BFD_RELOC_FRV_GOTTLSOFFHI
2482 BFD_RELOC_FRV_GOTTLSOFFLO
2484 BFD_RELOC_FRV_TLSOFF
2486 BFD_RELOC_FRV_TLSDESC_RELAX
2488 BFD_RELOC_FRV_GETTLSOFF_RELAX
2490 BFD_RELOC_FRV_TLSOFF_RELAX
2492 BFD_RELOC_FRV_TLSMOFF
2494 Fujitsu Frv Relocations.
2498 BFD_RELOC_MN10300_GOTOFF24
2500 This is a 24bit GOT-relative reloc for the mn10300.
2502 BFD_RELOC_MN10300_GOT32
2504 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2507 BFD_RELOC_MN10300_GOT24
2509 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2512 BFD_RELOC_MN10300_GOT16
2514 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2517 BFD_RELOC_MN10300_COPY
2519 Copy symbol at runtime.
2521 BFD_RELOC_MN10300_GLOB_DAT
2525 BFD_RELOC_MN10300_JMP_SLOT
2529 BFD_RELOC_MN10300_RELATIVE
2531 Adjust by program base.
2533 BFD_RELOC_MN10300_SYM_DIFF
2535 Together with another reloc targeted at the same location,
2536 allows for a value that is the difference of two symbols
2537 in the same section.
2539 BFD_RELOC_MN10300_ALIGN
2541 The addend of this reloc is an alignment power that must
2542 be honoured at the offset's location, regardless of linker
2545 BFD_RELOC_MN10300_TLS_GD
2547 BFD_RELOC_MN10300_TLS_LD
2549 BFD_RELOC_MN10300_TLS_LDO
2551 BFD_RELOC_MN10300_TLS_GOTIE
2553 BFD_RELOC_MN10300_TLS_IE
2555 BFD_RELOC_MN10300_TLS_LE
2557 BFD_RELOC_MN10300_TLS_DTPMOD
2559 BFD_RELOC_MN10300_TLS_DTPOFF
2561 BFD_RELOC_MN10300_TLS_TPOFF
2563 Various TLS-related relocations.
2565 BFD_RELOC_MN10300_32_PCREL
2567 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2570 BFD_RELOC_MN10300_16_PCREL
2572 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2583 BFD_RELOC_386_GLOB_DAT
2585 BFD_RELOC_386_JUMP_SLOT
2587 BFD_RELOC_386_RELATIVE
2589 BFD_RELOC_386_GOTOFF
2593 BFD_RELOC_386_TLS_TPOFF
2595 BFD_RELOC_386_TLS_IE
2597 BFD_RELOC_386_TLS_GOTIE
2599 BFD_RELOC_386_TLS_LE
2601 BFD_RELOC_386_TLS_GD
2603 BFD_RELOC_386_TLS_LDM
2605 BFD_RELOC_386_TLS_LDO_32
2607 BFD_RELOC_386_TLS_IE_32
2609 BFD_RELOC_386_TLS_LE_32
2611 BFD_RELOC_386_TLS_DTPMOD32
2613 BFD_RELOC_386_TLS_DTPOFF32
2615 BFD_RELOC_386_TLS_TPOFF32
2617 BFD_RELOC_386_TLS_GOTDESC
2619 BFD_RELOC_386_TLS_DESC_CALL
2621 BFD_RELOC_386_TLS_DESC
2623 BFD_RELOC_386_IRELATIVE
2625 BFD_RELOC_386_GOT32X
2627 i386/elf relocations
2630 BFD_RELOC_X86_64_GOT32
2632 BFD_RELOC_X86_64_PLT32
2634 BFD_RELOC_X86_64_COPY
2636 BFD_RELOC_X86_64_GLOB_DAT
2638 BFD_RELOC_X86_64_JUMP_SLOT
2640 BFD_RELOC_X86_64_RELATIVE
2642 BFD_RELOC_X86_64_GOTPCREL
2644 BFD_RELOC_X86_64_32S
2646 BFD_RELOC_X86_64_DTPMOD64
2648 BFD_RELOC_X86_64_DTPOFF64
2650 BFD_RELOC_X86_64_TPOFF64
2652 BFD_RELOC_X86_64_TLSGD
2654 BFD_RELOC_X86_64_TLSLD
2656 BFD_RELOC_X86_64_DTPOFF32
2658 BFD_RELOC_X86_64_GOTTPOFF
2660 BFD_RELOC_X86_64_TPOFF32
2662 BFD_RELOC_X86_64_GOTOFF64
2664 BFD_RELOC_X86_64_GOTPC32
2666 BFD_RELOC_X86_64_GOT64
2668 BFD_RELOC_X86_64_GOTPCREL64
2670 BFD_RELOC_X86_64_GOTPC64
2672 BFD_RELOC_X86_64_GOTPLT64
2674 BFD_RELOC_X86_64_PLTOFF64
2676 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2678 BFD_RELOC_X86_64_TLSDESC_CALL
2680 BFD_RELOC_X86_64_TLSDESC
2682 BFD_RELOC_X86_64_IRELATIVE
2684 BFD_RELOC_X86_64_PC32_BND
2686 BFD_RELOC_X86_64_PLT32_BND
2688 BFD_RELOC_X86_64_GOTPCRELX
2690 BFD_RELOC_X86_64_REX_GOTPCRELX
2692 x86-64/elf relocations
2695 BFD_RELOC_NS32K_IMM_8
2697 BFD_RELOC_NS32K_IMM_16
2699 BFD_RELOC_NS32K_IMM_32
2701 BFD_RELOC_NS32K_IMM_8_PCREL
2703 BFD_RELOC_NS32K_IMM_16_PCREL
2705 BFD_RELOC_NS32K_IMM_32_PCREL
2707 BFD_RELOC_NS32K_DISP_8
2709 BFD_RELOC_NS32K_DISP_16
2711 BFD_RELOC_NS32K_DISP_32
2713 BFD_RELOC_NS32K_DISP_8_PCREL
2715 BFD_RELOC_NS32K_DISP_16_PCREL
2717 BFD_RELOC_NS32K_DISP_32_PCREL
2722 BFD_RELOC_PDP11_DISP_8_PCREL
2724 BFD_RELOC_PDP11_DISP_6_PCREL
2729 BFD_RELOC_PJ_CODE_HI16
2731 BFD_RELOC_PJ_CODE_LO16
2733 BFD_RELOC_PJ_CODE_DIR16
2735 BFD_RELOC_PJ_CODE_DIR32
2737 BFD_RELOC_PJ_CODE_REL16
2739 BFD_RELOC_PJ_CODE_REL32
2741 Picojava relocs. Not all of these appear in object files.
2752 BFD_RELOC_PPC_B16_BRTAKEN
2754 BFD_RELOC_PPC_B16_BRNTAKEN
2758 BFD_RELOC_PPC_BA16_BRTAKEN
2760 BFD_RELOC_PPC_BA16_BRNTAKEN
2764 BFD_RELOC_PPC_GLOB_DAT
2766 BFD_RELOC_PPC_JMP_SLOT
2768 BFD_RELOC_PPC_RELATIVE
2770 BFD_RELOC_PPC_LOCAL24PC
2772 BFD_RELOC_PPC_EMB_NADDR32
2774 BFD_RELOC_PPC_EMB_NADDR16
2776 BFD_RELOC_PPC_EMB_NADDR16_LO
2778 BFD_RELOC_PPC_EMB_NADDR16_HI
2780 BFD_RELOC_PPC_EMB_NADDR16_HA
2782 BFD_RELOC_PPC_EMB_SDAI16
2784 BFD_RELOC_PPC_EMB_SDA2I16
2786 BFD_RELOC_PPC_EMB_SDA2REL
2788 BFD_RELOC_PPC_EMB_SDA21
2790 BFD_RELOC_PPC_EMB_MRKREF
2792 BFD_RELOC_PPC_EMB_RELSEC16
2794 BFD_RELOC_PPC_EMB_RELST_LO
2796 BFD_RELOC_PPC_EMB_RELST_HI
2798 BFD_RELOC_PPC_EMB_RELST_HA
2800 BFD_RELOC_PPC_EMB_BIT_FLD
2802 BFD_RELOC_PPC_EMB_RELSDA
2804 BFD_RELOC_PPC_VLE_REL8
2806 BFD_RELOC_PPC_VLE_REL15
2808 BFD_RELOC_PPC_VLE_REL24
2810 BFD_RELOC_PPC_VLE_LO16A
2812 BFD_RELOC_PPC_VLE_LO16D
2814 BFD_RELOC_PPC_VLE_HI16A
2816 BFD_RELOC_PPC_VLE_HI16D
2818 BFD_RELOC_PPC_VLE_HA16A
2820 BFD_RELOC_PPC_VLE_HA16D
2822 BFD_RELOC_PPC_VLE_SDA21
2824 BFD_RELOC_PPC_VLE_SDA21_LO
2826 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2828 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2830 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2832 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2834 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2836 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2838 BFD_RELOC_PPC_16DX_HA
2840 BFD_RELOC_PPC_REL16DX_HA
2842 BFD_RELOC_PPC64_HIGHER
2844 BFD_RELOC_PPC64_HIGHER_S
2846 BFD_RELOC_PPC64_HIGHEST
2848 BFD_RELOC_PPC64_HIGHEST_S
2850 BFD_RELOC_PPC64_TOC16_LO
2852 BFD_RELOC_PPC64_TOC16_HI
2854 BFD_RELOC_PPC64_TOC16_HA
2858 BFD_RELOC_PPC64_PLTGOT16
2860 BFD_RELOC_PPC64_PLTGOT16_LO
2862 BFD_RELOC_PPC64_PLTGOT16_HI
2864 BFD_RELOC_PPC64_PLTGOT16_HA
2866 BFD_RELOC_PPC64_ADDR16_DS
2868 BFD_RELOC_PPC64_ADDR16_LO_DS
2870 BFD_RELOC_PPC64_GOT16_DS
2872 BFD_RELOC_PPC64_GOT16_LO_DS
2874 BFD_RELOC_PPC64_PLT16_LO_DS
2876 BFD_RELOC_PPC64_SECTOFF_DS
2878 BFD_RELOC_PPC64_SECTOFF_LO_DS
2880 BFD_RELOC_PPC64_TOC16_DS
2882 BFD_RELOC_PPC64_TOC16_LO_DS
2884 BFD_RELOC_PPC64_PLTGOT16_DS
2886 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2888 BFD_RELOC_PPC64_ADDR16_HIGH
2890 BFD_RELOC_PPC64_ADDR16_HIGHA
2892 BFD_RELOC_PPC64_ADDR64_LOCAL
2894 BFD_RELOC_PPC64_ENTRY
2896 BFD_RELOC_PPC64_REL24_NOTOC
2898 Power(rs6000) and PowerPC relocations.
2907 BFD_RELOC_PPC_DTPMOD
2909 BFD_RELOC_PPC_TPREL16
2911 BFD_RELOC_PPC_TPREL16_LO
2913 BFD_RELOC_PPC_TPREL16_HI
2915 BFD_RELOC_PPC_TPREL16_HA
2919 BFD_RELOC_PPC_DTPREL16
2921 BFD_RELOC_PPC_DTPREL16_LO
2923 BFD_RELOC_PPC_DTPREL16_HI
2925 BFD_RELOC_PPC_DTPREL16_HA
2927 BFD_RELOC_PPC_DTPREL
2929 BFD_RELOC_PPC_GOT_TLSGD16
2931 BFD_RELOC_PPC_GOT_TLSGD16_LO
2933 BFD_RELOC_PPC_GOT_TLSGD16_HI
2935 BFD_RELOC_PPC_GOT_TLSGD16_HA
2937 BFD_RELOC_PPC_GOT_TLSLD16
2939 BFD_RELOC_PPC_GOT_TLSLD16_LO
2941 BFD_RELOC_PPC_GOT_TLSLD16_HI
2943 BFD_RELOC_PPC_GOT_TLSLD16_HA
2945 BFD_RELOC_PPC_GOT_TPREL16
2947 BFD_RELOC_PPC_GOT_TPREL16_LO
2949 BFD_RELOC_PPC_GOT_TPREL16_HI
2951 BFD_RELOC_PPC_GOT_TPREL16_HA
2953 BFD_RELOC_PPC_GOT_DTPREL16
2955 BFD_RELOC_PPC_GOT_DTPREL16_LO
2957 BFD_RELOC_PPC_GOT_DTPREL16_HI
2959 BFD_RELOC_PPC_GOT_DTPREL16_HA
2961 BFD_RELOC_PPC64_TPREL16_DS
2963 BFD_RELOC_PPC64_TPREL16_LO_DS
2965 BFD_RELOC_PPC64_TPREL16_HIGHER
2967 BFD_RELOC_PPC64_TPREL16_HIGHERA
2969 BFD_RELOC_PPC64_TPREL16_HIGHEST
2971 BFD_RELOC_PPC64_TPREL16_HIGHESTA
2973 BFD_RELOC_PPC64_DTPREL16_DS
2975 BFD_RELOC_PPC64_DTPREL16_LO_DS
2977 BFD_RELOC_PPC64_DTPREL16_HIGHER
2979 BFD_RELOC_PPC64_DTPREL16_HIGHERA
2981 BFD_RELOC_PPC64_DTPREL16_HIGHEST
2983 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
2985 BFD_RELOC_PPC64_TPREL16_HIGH
2987 BFD_RELOC_PPC64_TPREL16_HIGHA
2989 BFD_RELOC_PPC64_DTPREL16_HIGH
2991 BFD_RELOC_PPC64_DTPREL16_HIGHA
2993 PowerPC and PowerPC64 thread-local storage relocations.
2998 IBM 370/390 relocations
3003 The type of reloc used to build a constructor table - at the moment
3004 probably a 32 bit wide absolute relocation, but the target can choose.
3005 It generally does map to one of the other relocation types.
3008 BFD_RELOC_ARM_PCREL_BRANCH
3010 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3011 not stored in the instruction.
3013 BFD_RELOC_ARM_PCREL_BLX
3015 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3016 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3017 field in the instruction.
3019 BFD_RELOC_THUMB_PCREL_BLX
3021 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3022 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3023 field in the instruction.
3025 BFD_RELOC_ARM_PCREL_CALL
3027 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3029 BFD_RELOC_ARM_PCREL_JUMP
3031 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3034 BFD_RELOC_THUMB_PCREL_BRANCH7
3036 BFD_RELOC_THUMB_PCREL_BRANCH9
3038 BFD_RELOC_THUMB_PCREL_BRANCH12
3040 BFD_RELOC_THUMB_PCREL_BRANCH20
3042 BFD_RELOC_THUMB_PCREL_BRANCH23
3044 BFD_RELOC_THUMB_PCREL_BRANCH25
3046 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3047 The lowest bit must be zero and is not stored in the instruction.
3048 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3049 "nn" one smaller in all cases. Note further that BRANCH23
3050 corresponds to R_ARM_THM_CALL.
3053 BFD_RELOC_ARM_OFFSET_IMM
3055 12-bit immediate offset, used in ARM-format ldr and str instructions.
3058 BFD_RELOC_ARM_THUMB_OFFSET
3060 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3063 BFD_RELOC_ARM_TARGET1
3065 Pc-relative or absolute relocation depending on target. Used for
3066 entries in .init_array sections.
3068 BFD_RELOC_ARM_ROSEGREL32
3070 Read-only segment base relative address.
3072 BFD_RELOC_ARM_SBREL32
3074 Data segment base relative address.
3076 BFD_RELOC_ARM_TARGET2
3078 This reloc is used for references to RTTI data from exception handling
3079 tables. The actual definition depends on the target. It may be a
3080 pc-relative or some form of GOT-indirect relocation.
3082 BFD_RELOC_ARM_PREL31
3084 31-bit PC relative address.
3090 BFD_RELOC_ARM_MOVW_PCREL
3092 BFD_RELOC_ARM_MOVT_PCREL
3094 BFD_RELOC_ARM_THUMB_MOVW
3096 BFD_RELOC_ARM_THUMB_MOVT
3098 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3100 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3102 Low and High halfword relocations for MOVW and MOVT instructions.
3105 BFD_RELOC_ARM_GOTFUNCDESC
3107 BFD_RELOC_ARM_GOTOFFFUNCDESC
3109 BFD_RELOC_ARM_FUNCDESC
3111 BFD_RELOC_ARM_FUNCDESC_VALUE
3113 BFD_RELOC_ARM_TLS_GD32_FDPIC
3115 BFD_RELOC_ARM_TLS_LDM32_FDPIC
3117 BFD_RELOC_ARM_TLS_IE32_FDPIC
3119 ARM FDPIC specific relocations.
3122 BFD_RELOC_ARM_JUMP_SLOT
3124 BFD_RELOC_ARM_GLOB_DAT
3130 BFD_RELOC_ARM_RELATIVE
3132 BFD_RELOC_ARM_GOTOFF
3136 BFD_RELOC_ARM_GOT_PREL
3138 Relocations for setting up GOTs and PLTs for shared libraries.
3141 BFD_RELOC_ARM_TLS_GD32
3143 BFD_RELOC_ARM_TLS_LDO32
3145 BFD_RELOC_ARM_TLS_LDM32
3147 BFD_RELOC_ARM_TLS_DTPOFF32
3149 BFD_RELOC_ARM_TLS_DTPMOD32
3151 BFD_RELOC_ARM_TLS_TPOFF32
3153 BFD_RELOC_ARM_TLS_IE32
3155 BFD_RELOC_ARM_TLS_LE32
3157 BFD_RELOC_ARM_TLS_GOTDESC
3159 BFD_RELOC_ARM_TLS_CALL
3161 BFD_RELOC_ARM_THM_TLS_CALL
3163 BFD_RELOC_ARM_TLS_DESCSEQ
3165 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3167 BFD_RELOC_ARM_TLS_DESC
3169 ARM thread-local storage relocations.
3172 BFD_RELOC_ARM_ALU_PC_G0_NC
3174 BFD_RELOC_ARM_ALU_PC_G0
3176 BFD_RELOC_ARM_ALU_PC_G1_NC
3178 BFD_RELOC_ARM_ALU_PC_G1
3180 BFD_RELOC_ARM_ALU_PC_G2
3182 BFD_RELOC_ARM_LDR_PC_G0
3184 BFD_RELOC_ARM_LDR_PC_G1
3186 BFD_RELOC_ARM_LDR_PC_G2
3188 BFD_RELOC_ARM_LDRS_PC_G0
3190 BFD_RELOC_ARM_LDRS_PC_G1
3192 BFD_RELOC_ARM_LDRS_PC_G2
3194 BFD_RELOC_ARM_LDC_PC_G0
3196 BFD_RELOC_ARM_LDC_PC_G1
3198 BFD_RELOC_ARM_LDC_PC_G2
3200 BFD_RELOC_ARM_ALU_SB_G0_NC
3202 BFD_RELOC_ARM_ALU_SB_G0
3204 BFD_RELOC_ARM_ALU_SB_G1_NC
3206 BFD_RELOC_ARM_ALU_SB_G1
3208 BFD_RELOC_ARM_ALU_SB_G2
3210 BFD_RELOC_ARM_LDR_SB_G0
3212 BFD_RELOC_ARM_LDR_SB_G1
3214 BFD_RELOC_ARM_LDR_SB_G2
3216 BFD_RELOC_ARM_LDRS_SB_G0
3218 BFD_RELOC_ARM_LDRS_SB_G1
3220 BFD_RELOC_ARM_LDRS_SB_G2
3222 BFD_RELOC_ARM_LDC_SB_G0
3224 BFD_RELOC_ARM_LDC_SB_G1
3226 BFD_RELOC_ARM_LDC_SB_G2
3228 ARM group relocations.
3233 Annotation of BX instructions.
3236 BFD_RELOC_ARM_IRELATIVE
3238 ARM support for STT_GNU_IFUNC.
3241 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3243 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3245 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3247 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3249 Thumb1 relocations to support execute-only code.
3252 BFD_RELOC_ARM_IMMEDIATE
3254 BFD_RELOC_ARM_ADRL_IMMEDIATE
3256 BFD_RELOC_ARM_T32_IMMEDIATE
3258 BFD_RELOC_ARM_T32_ADD_IMM
3260 BFD_RELOC_ARM_T32_IMM12
3262 BFD_RELOC_ARM_T32_ADD_PC12
3264 BFD_RELOC_ARM_SHIFT_IMM
3274 BFD_RELOC_ARM_CP_OFF_IMM
3276 BFD_RELOC_ARM_CP_OFF_IMM_S2
3278 BFD_RELOC_ARM_T32_CP_OFF_IMM
3280 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3282 BFD_RELOC_ARM_ADR_IMM
3284 BFD_RELOC_ARM_LDR_IMM
3286 BFD_RELOC_ARM_LITERAL
3288 BFD_RELOC_ARM_IN_POOL
3290 BFD_RELOC_ARM_OFFSET_IMM8
3292 BFD_RELOC_ARM_T32_OFFSET_U8
3294 BFD_RELOC_ARM_T32_OFFSET_IMM
3296 BFD_RELOC_ARM_HWLITERAL
3298 BFD_RELOC_ARM_THUMB_ADD
3300 BFD_RELOC_ARM_THUMB_IMM
3302 BFD_RELOC_ARM_THUMB_SHIFT
3304 These relocs are only used within the ARM assembler. They are not
3305 (at present) written to any object files.
3308 BFD_RELOC_SH_PCDISP8BY2
3310 BFD_RELOC_SH_PCDISP12BY2
3318 BFD_RELOC_SH_DISP12BY2
3320 BFD_RELOC_SH_DISP12BY4
3322 BFD_RELOC_SH_DISP12BY8
3326 BFD_RELOC_SH_DISP20BY8
3330 BFD_RELOC_SH_IMM4BY2
3332 BFD_RELOC_SH_IMM4BY4
3336 BFD_RELOC_SH_IMM8BY2
3338 BFD_RELOC_SH_IMM8BY4
3340 BFD_RELOC_SH_PCRELIMM8BY2
3342 BFD_RELOC_SH_PCRELIMM8BY4
3344 BFD_RELOC_SH_SWITCH16
3346 BFD_RELOC_SH_SWITCH32
3360 BFD_RELOC_SH_LOOP_START
3362 BFD_RELOC_SH_LOOP_END
3366 BFD_RELOC_SH_GLOB_DAT
3368 BFD_RELOC_SH_JMP_SLOT
3370 BFD_RELOC_SH_RELATIVE
3374 BFD_RELOC_SH_GOT_LOW16
3376 BFD_RELOC_SH_GOT_MEDLOW16
3378 BFD_RELOC_SH_GOT_MEDHI16
3380 BFD_RELOC_SH_GOT_HI16
3382 BFD_RELOC_SH_GOTPLT_LOW16
3384 BFD_RELOC_SH_GOTPLT_MEDLOW16
3386 BFD_RELOC_SH_GOTPLT_MEDHI16
3388 BFD_RELOC_SH_GOTPLT_HI16
3390 BFD_RELOC_SH_PLT_LOW16
3392 BFD_RELOC_SH_PLT_MEDLOW16
3394 BFD_RELOC_SH_PLT_MEDHI16
3396 BFD_RELOC_SH_PLT_HI16
3398 BFD_RELOC_SH_GOTOFF_LOW16
3400 BFD_RELOC_SH_GOTOFF_MEDLOW16
3402 BFD_RELOC_SH_GOTOFF_MEDHI16
3404 BFD_RELOC_SH_GOTOFF_HI16
3406 BFD_RELOC_SH_GOTPC_LOW16
3408 BFD_RELOC_SH_GOTPC_MEDLOW16
3410 BFD_RELOC_SH_GOTPC_MEDHI16
3412 BFD_RELOC_SH_GOTPC_HI16
3416 BFD_RELOC_SH_GLOB_DAT64
3418 BFD_RELOC_SH_JMP_SLOT64
3420 BFD_RELOC_SH_RELATIVE64
3422 BFD_RELOC_SH_GOT10BY4
3424 BFD_RELOC_SH_GOT10BY8
3426 BFD_RELOC_SH_GOTPLT10BY4
3428 BFD_RELOC_SH_GOTPLT10BY8
3430 BFD_RELOC_SH_GOTPLT32
3432 BFD_RELOC_SH_SHMEDIA_CODE
3438 BFD_RELOC_SH_IMMS6BY32
3444 BFD_RELOC_SH_IMMS10BY2
3446 BFD_RELOC_SH_IMMS10BY4
3448 BFD_RELOC_SH_IMMS10BY8
3454 BFD_RELOC_SH_IMM_LOW16
3456 BFD_RELOC_SH_IMM_LOW16_PCREL
3458 BFD_RELOC_SH_IMM_MEDLOW16
3460 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3462 BFD_RELOC_SH_IMM_MEDHI16
3464 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3466 BFD_RELOC_SH_IMM_HI16
3468 BFD_RELOC_SH_IMM_HI16_PCREL
3472 BFD_RELOC_SH_TLS_GD_32
3474 BFD_RELOC_SH_TLS_LD_32
3476 BFD_RELOC_SH_TLS_LDO_32
3478 BFD_RELOC_SH_TLS_IE_32
3480 BFD_RELOC_SH_TLS_LE_32
3482 BFD_RELOC_SH_TLS_DTPMOD32
3484 BFD_RELOC_SH_TLS_DTPOFF32
3486 BFD_RELOC_SH_TLS_TPOFF32
3490 BFD_RELOC_SH_GOTOFF20
3492 BFD_RELOC_SH_GOTFUNCDESC
3494 BFD_RELOC_SH_GOTFUNCDESC20
3496 BFD_RELOC_SH_GOTOFFFUNCDESC
3498 BFD_RELOC_SH_GOTOFFFUNCDESC20
3500 BFD_RELOC_SH_FUNCDESC
3502 Renesas / SuperH SH relocs. Not all of these appear in object files.
3525 BFD_RELOC_ARC_SECTOFF
3527 BFD_RELOC_ARC_S21H_PCREL
3529 BFD_RELOC_ARC_S21W_PCREL
3531 BFD_RELOC_ARC_S25H_PCREL
3533 BFD_RELOC_ARC_S25W_PCREL
3537 BFD_RELOC_ARC_SDA_LDST
3539 BFD_RELOC_ARC_SDA_LDST1
3541 BFD_RELOC_ARC_SDA_LDST2
3543 BFD_RELOC_ARC_SDA16_LD
3545 BFD_RELOC_ARC_SDA16_LD1
3547 BFD_RELOC_ARC_SDA16_LD2
3549 BFD_RELOC_ARC_S13_PCREL
3555 BFD_RELOC_ARC_32_ME_S
3557 BFD_RELOC_ARC_N32_ME
3559 BFD_RELOC_ARC_SECTOFF_ME
3561 BFD_RELOC_ARC_SDA32_ME
3565 BFD_RELOC_AC_SECTOFF_U8
3567 BFD_RELOC_AC_SECTOFF_U8_1
3569 BFD_RELOC_AC_SECTOFF_U8_2
3571 BFD_RELOC_AC_SECTOFF_S9
3573 BFD_RELOC_AC_SECTOFF_S9_1
3575 BFD_RELOC_AC_SECTOFF_S9_2
3577 BFD_RELOC_ARC_SECTOFF_ME_1
3579 BFD_RELOC_ARC_SECTOFF_ME_2
3581 BFD_RELOC_ARC_SECTOFF_1
3583 BFD_RELOC_ARC_SECTOFF_2
3585 BFD_RELOC_ARC_SDA_12
3587 BFD_RELOC_ARC_SDA16_ST2
3589 BFD_RELOC_ARC_32_PCREL
3595 BFD_RELOC_ARC_GOTPC32
3601 BFD_RELOC_ARC_GLOB_DAT
3603 BFD_RELOC_ARC_JMP_SLOT
3605 BFD_RELOC_ARC_RELATIVE
3607 BFD_RELOC_ARC_GOTOFF
3611 BFD_RELOC_ARC_S21W_PCREL_PLT
3613 BFD_RELOC_ARC_S25H_PCREL_PLT
3615 BFD_RELOC_ARC_TLS_DTPMOD
3617 BFD_RELOC_ARC_TLS_TPOFF
3619 BFD_RELOC_ARC_TLS_GD_GOT
3621 BFD_RELOC_ARC_TLS_GD_LD
3623 BFD_RELOC_ARC_TLS_GD_CALL
3625 BFD_RELOC_ARC_TLS_IE_GOT
3627 BFD_RELOC_ARC_TLS_DTPOFF
3629 BFD_RELOC_ARC_TLS_DTPOFF_S9
3631 BFD_RELOC_ARC_TLS_LE_S9
3633 BFD_RELOC_ARC_TLS_LE_32
3635 BFD_RELOC_ARC_S25W_PCREL_PLT
3637 BFD_RELOC_ARC_S21H_PCREL_PLT
3639 BFD_RELOC_ARC_NPS_CMEM16
3641 BFD_RELOC_ARC_JLI_SECTOFF
3646 BFD_RELOC_BFIN_16_IMM
3648 ADI Blackfin 16 bit immediate absolute reloc.
3650 BFD_RELOC_BFIN_16_HIGH
3652 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3654 BFD_RELOC_BFIN_4_PCREL
3656 ADI Blackfin 'a' part of LSETUP.
3658 BFD_RELOC_BFIN_5_PCREL
3662 BFD_RELOC_BFIN_16_LOW
3664 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3666 BFD_RELOC_BFIN_10_PCREL
3670 BFD_RELOC_BFIN_11_PCREL
3672 ADI Blackfin 'b' part of LSETUP.
3674 BFD_RELOC_BFIN_12_PCREL_JUMP
3678 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3680 ADI Blackfin Short jump, pcrel.
3682 BFD_RELOC_BFIN_24_PCREL_CALL_X
3684 ADI Blackfin Call.x not implemented.
3686 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3688 ADI Blackfin Long Jump pcrel.
3690 BFD_RELOC_BFIN_GOT17M4
3692 BFD_RELOC_BFIN_GOTHI
3694 BFD_RELOC_BFIN_GOTLO
3696 BFD_RELOC_BFIN_FUNCDESC
3698 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3700 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3702 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3704 BFD_RELOC_BFIN_FUNCDESC_VALUE
3706 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3708 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3710 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3712 BFD_RELOC_BFIN_GOTOFF17M4
3714 BFD_RELOC_BFIN_GOTOFFHI
3716 BFD_RELOC_BFIN_GOTOFFLO
3718 ADI Blackfin FD-PIC relocations.
3722 ADI Blackfin GOT relocation.
3724 BFD_RELOC_BFIN_PLTPC
3726 ADI Blackfin PLTPC relocation.
3728 BFD_ARELOC_BFIN_PUSH
3730 ADI Blackfin arithmetic relocation.
3732 BFD_ARELOC_BFIN_CONST
3734 ADI Blackfin arithmetic relocation.
3738 ADI Blackfin arithmetic relocation.
3742 ADI Blackfin arithmetic relocation.
3744 BFD_ARELOC_BFIN_MULT
3746 ADI Blackfin arithmetic relocation.
3750 ADI Blackfin arithmetic relocation.
3754 ADI Blackfin arithmetic relocation.
3756 BFD_ARELOC_BFIN_LSHIFT
3758 ADI Blackfin arithmetic relocation.
3760 BFD_ARELOC_BFIN_RSHIFT
3762 ADI Blackfin arithmetic relocation.
3766 ADI Blackfin arithmetic relocation.
3770 ADI Blackfin arithmetic relocation.
3774 ADI Blackfin arithmetic relocation.
3776 BFD_ARELOC_BFIN_LAND
3778 ADI Blackfin arithmetic relocation.
3782 ADI Blackfin arithmetic relocation.
3786 ADI Blackfin arithmetic relocation.
3790 ADI Blackfin arithmetic relocation.
3792 BFD_ARELOC_BFIN_COMP
3794 ADI Blackfin arithmetic relocation.
3796 BFD_ARELOC_BFIN_PAGE
3798 ADI Blackfin arithmetic relocation.
3800 BFD_ARELOC_BFIN_HWPAGE
3802 ADI Blackfin arithmetic relocation.
3804 BFD_ARELOC_BFIN_ADDR
3806 ADI Blackfin arithmetic relocation.
3809 BFD_RELOC_D10V_10_PCREL_R
3811 Mitsubishi D10V relocs.
3812 This is a 10-bit reloc with the right 2 bits
3815 BFD_RELOC_D10V_10_PCREL_L
3817 Mitsubishi D10V relocs.
3818 This is a 10-bit reloc with the right 2 bits
3819 assumed to be 0. This is the same as the previous reloc
3820 except it is in the left container, i.e.,
3821 shifted left 15 bits.
3825 This is an 18-bit reloc with the right 2 bits
3828 BFD_RELOC_D10V_18_PCREL
3830 This is an 18-bit reloc with the right 2 bits
3836 Mitsubishi D30V relocs.
3837 This is a 6-bit absolute reloc.
3839 BFD_RELOC_D30V_9_PCREL
3841 This is a 6-bit pc-relative reloc with
3842 the right 3 bits assumed to be 0.
3844 BFD_RELOC_D30V_9_PCREL_R
3846 This is a 6-bit pc-relative reloc with
3847 the right 3 bits assumed to be 0. Same
3848 as the previous reloc but on the right side
3853 This is a 12-bit absolute reloc with the
3854 right 3 bitsassumed to be 0.
3856 BFD_RELOC_D30V_15_PCREL
3858 This is a 12-bit pc-relative reloc with
3859 the right 3 bits assumed to be 0.
3861 BFD_RELOC_D30V_15_PCREL_R
3863 This is a 12-bit pc-relative reloc with
3864 the right 3 bits assumed to be 0. Same
3865 as the previous reloc but on the right side
3870 This is an 18-bit absolute reloc with
3871 the right 3 bits assumed to be 0.
3873 BFD_RELOC_D30V_21_PCREL
3875 This is an 18-bit pc-relative reloc with
3876 the right 3 bits assumed to be 0.
3878 BFD_RELOC_D30V_21_PCREL_R
3880 This is an 18-bit pc-relative reloc with
3881 the right 3 bits assumed to be 0. Same
3882 as the previous reloc but on the right side
3887 This is a 32-bit absolute reloc.
3889 BFD_RELOC_D30V_32_PCREL
3891 This is a 32-bit pc-relative reloc.
3894 BFD_RELOC_DLX_HI16_S
3909 BFD_RELOC_M32C_RL_JUMP
3911 BFD_RELOC_M32C_RL_1ADDR
3913 BFD_RELOC_M32C_RL_2ADDR
3915 Renesas M16C/M32C Relocations.
3920 Renesas M32R (formerly Mitsubishi M32R) relocs.
3921 This is a 24 bit absolute address.
3923 BFD_RELOC_M32R_10_PCREL
3925 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3927 BFD_RELOC_M32R_18_PCREL
3929 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3931 BFD_RELOC_M32R_26_PCREL
3933 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3935 BFD_RELOC_M32R_HI16_ULO
3937 This is a 16-bit reloc containing the high 16 bits of an address
3938 used when the lower 16 bits are treated as unsigned.
3940 BFD_RELOC_M32R_HI16_SLO
3942 This is a 16-bit reloc containing the high 16 bits of an address
3943 used when the lower 16 bits are treated as signed.
3947 This is a 16-bit reloc containing the lower 16 bits of an address.
3949 BFD_RELOC_M32R_SDA16
3951 This is a 16-bit reloc containing the small data area offset for use in
3952 add3, load, and store instructions.
3954 BFD_RELOC_M32R_GOT24
3956 BFD_RELOC_M32R_26_PLTREL
3960 BFD_RELOC_M32R_GLOB_DAT
3962 BFD_RELOC_M32R_JMP_SLOT
3964 BFD_RELOC_M32R_RELATIVE
3966 BFD_RELOC_M32R_GOTOFF
3968 BFD_RELOC_M32R_GOTOFF_HI_ULO
3970 BFD_RELOC_M32R_GOTOFF_HI_SLO
3972 BFD_RELOC_M32R_GOTOFF_LO
3974 BFD_RELOC_M32R_GOTPC24
3976 BFD_RELOC_M32R_GOT16_HI_ULO
3978 BFD_RELOC_M32R_GOT16_HI_SLO
3980 BFD_RELOC_M32R_GOT16_LO
3982 BFD_RELOC_M32R_GOTPC_HI_ULO
3984 BFD_RELOC_M32R_GOTPC_HI_SLO
3986 BFD_RELOC_M32R_GOTPC_LO
3995 This is a 20 bit absolute address.
3997 BFD_RELOC_NDS32_9_PCREL
3999 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4001 BFD_RELOC_NDS32_WORD_9_PCREL
4003 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4005 BFD_RELOC_NDS32_15_PCREL
4007 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4009 BFD_RELOC_NDS32_17_PCREL
4011 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4013 BFD_RELOC_NDS32_25_PCREL
4015 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4017 BFD_RELOC_NDS32_HI20
4019 This is a 20-bit reloc containing the high 20 bits of an address
4020 used with the lower 12 bits
4022 BFD_RELOC_NDS32_LO12S3
4024 This is a 12-bit reloc containing the lower 12 bits of an address
4025 then shift right by 3. This is used with ldi,sdi...
4027 BFD_RELOC_NDS32_LO12S2
4029 This is a 12-bit reloc containing the lower 12 bits of an address
4030 then shift left by 2. This is used with lwi,swi...
4032 BFD_RELOC_NDS32_LO12S1
4034 This is a 12-bit reloc containing the lower 12 bits of an address
4035 then shift left by 1. This is used with lhi,shi...
4037 BFD_RELOC_NDS32_LO12S0
4039 This is a 12-bit reloc containing the lower 12 bits of an address
4040 then shift left by 0. This is used with lbisbi...
4042 BFD_RELOC_NDS32_LO12S0_ORI
4044 This is a 12-bit reloc containing the lower 12 bits of an address
4045 then shift left by 0. This is only used with branch relaxations
4047 BFD_RELOC_NDS32_SDA15S3
4049 This is a 15-bit reloc containing the small data area 18-bit signed offset
4050 and shift left by 3 for use in ldi, sdi...
4052 BFD_RELOC_NDS32_SDA15S2
4054 This is a 15-bit reloc containing the small data area 17-bit signed offset
4055 and shift left by 2 for use in lwi, swi...
4057 BFD_RELOC_NDS32_SDA15S1
4059 This is a 15-bit reloc containing the small data area 16-bit signed offset
4060 and shift left by 1 for use in lhi, shi...
4062 BFD_RELOC_NDS32_SDA15S0
4064 This is a 15-bit reloc containing the small data area 15-bit signed offset
4065 and shift left by 0 for use in lbi, sbi...
4067 BFD_RELOC_NDS32_SDA16S3
4069 This is a 16-bit reloc containing the small data area 16-bit signed offset
4072 BFD_RELOC_NDS32_SDA17S2
4074 This is a 17-bit reloc containing the small data area 17-bit signed offset
4075 and shift left by 2 for use in lwi.gp, swi.gp...
4077 BFD_RELOC_NDS32_SDA18S1
4079 This is a 18-bit reloc containing the small data area 18-bit signed offset
4080 and shift left by 1 for use in lhi.gp, shi.gp...
4082 BFD_RELOC_NDS32_SDA19S0
4084 This is a 19-bit reloc containing the small data area 19-bit signed offset
4085 and shift left by 0 for use in lbi.gp, sbi.gp...
4087 BFD_RELOC_NDS32_GOT20
4089 BFD_RELOC_NDS32_9_PLTREL
4091 BFD_RELOC_NDS32_25_PLTREL
4093 BFD_RELOC_NDS32_COPY
4095 BFD_RELOC_NDS32_GLOB_DAT
4097 BFD_RELOC_NDS32_JMP_SLOT
4099 BFD_RELOC_NDS32_RELATIVE
4101 BFD_RELOC_NDS32_GOTOFF
4103 BFD_RELOC_NDS32_GOTOFF_HI20
4105 BFD_RELOC_NDS32_GOTOFF_LO12
4107 BFD_RELOC_NDS32_GOTPC20
4109 BFD_RELOC_NDS32_GOT_HI20
4111 BFD_RELOC_NDS32_GOT_LO12
4113 BFD_RELOC_NDS32_GOTPC_HI20
4115 BFD_RELOC_NDS32_GOTPC_LO12
4119 BFD_RELOC_NDS32_INSN16
4121 BFD_RELOC_NDS32_LABEL
4123 BFD_RELOC_NDS32_LONGCALL1
4125 BFD_RELOC_NDS32_LONGCALL2
4127 BFD_RELOC_NDS32_LONGCALL3
4129 BFD_RELOC_NDS32_LONGJUMP1
4131 BFD_RELOC_NDS32_LONGJUMP2
4133 BFD_RELOC_NDS32_LONGJUMP3
4135 BFD_RELOC_NDS32_LOADSTORE
4137 BFD_RELOC_NDS32_9_FIXED
4139 BFD_RELOC_NDS32_15_FIXED
4141 BFD_RELOC_NDS32_17_FIXED
4143 BFD_RELOC_NDS32_25_FIXED
4145 BFD_RELOC_NDS32_LONGCALL4
4147 BFD_RELOC_NDS32_LONGCALL5
4149 BFD_RELOC_NDS32_LONGCALL6
4151 BFD_RELOC_NDS32_LONGJUMP4
4153 BFD_RELOC_NDS32_LONGJUMP5
4155 BFD_RELOC_NDS32_LONGJUMP6
4157 BFD_RELOC_NDS32_LONGJUMP7
4161 BFD_RELOC_NDS32_PLTREL_HI20
4163 BFD_RELOC_NDS32_PLTREL_LO12
4165 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4167 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4171 BFD_RELOC_NDS32_SDA12S2_DP
4173 BFD_RELOC_NDS32_SDA12S2_SP
4175 BFD_RELOC_NDS32_LO12S2_DP
4177 BFD_RELOC_NDS32_LO12S2_SP
4181 BFD_RELOC_NDS32_DWARF2_OP1
4183 BFD_RELOC_NDS32_DWARF2_OP2
4185 BFD_RELOC_NDS32_DWARF2_LEB
4187 for dwarf2 debug_line.
4189 BFD_RELOC_NDS32_UPDATE_TA
4191 for eliminate 16-bit instructions
4193 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4195 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4197 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4199 BFD_RELOC_NDS32_GOT_LO15
4201 BFD_RELOC_NDS32_GOT_LO19
4203 BFD_RELOC_NDS32_GOTOFF_LO15
4205 BFD_RELOC_NDS32_GOTOFF_LO19
4207 BFD_RELOC_NDS32_GOT15S2
4209 BFD_RELOC_NDS32_GOT17S2
4211 for PIC object relaxation
4216 This is a 5 bit absolute address.
4218 BFD_RELOC_NDS32_10_UPCREL
4220 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4222 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4224 If fp were omitted, fp can used as another gp.
4226 BFD_RELOC_NDS32_RELAX_ENTRY
4228 BFD_RELOC_NDS32_GOT_SUFF
4230 BFD_RELOC_NDS32_GOTOFF_SUFF
4232 BFD_RELOC_NDS32_PLT_GOT_SUFF
4234 BFD_RELOC_NDS32_MULCALL_SUFF
4238 BFD_RELOC_NDS32_PTR_COUNT
4240 BFD_RELOC_NDS32_PTR_RESOLVED
4242 BFD_RELOC_NDS32_PLTBLOCK
4244 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4246 BFD_RELOC_NDS32_RELAX_REGION_END
4248 BFD_RELOC_NDS32_MINUEND
4250 BFD_RELOC_NDS32_SUBTRAHEND
4252 BFD_RELOC_NDS32_DIFF8
4254 BFD_RELOC_NDS32_DIFF16
4256 BFD_RELOC_NDS32_DIFF32
4258 BFD_RELOC_NDS32_DIFF_ULEB128
4260 BFD_RELOC_NDS32_EMPTY
4262 relaxation relative relocation types
4264 BFD_RELOC_NDS32_25_ABS
4266 This is a 25 bit absolute address.
4268 BFD_RELOC_NDS32_DATA
4270 BFD_RELOC_NDS32_TRAN
4272 BFD_RELOC_NDS32_17IFC_PCREL
4274 BFD_RELOC_NDS32_10IFCU_PCREL
4276 For ex9 and ifc using.
4278 BFD_RELOC_NDS32_TPOFF
4280 BFD_RELOC_NDS32_TLS_LE_HI20
4282 BFD_RELOC_NDS32_TLS_LE_LO12
4284 BFD_RELOC_NDS32_TLS_LE_ADD
4286 BFD_RELOC_NDS32_TLS_LE_LS
4288 BFD_RELOC_NDS32_GOTTPOFF
4290 BFD_RELOC_NDS32_TLS_IE_HI20
4292 BFD_RELOC_NDS32_TLS_IE_LO12S2
4294 BFD_RELOC_NDS32_TLS_TPOFF
4296 BFD_RELOC_NDS32_TLS_LE_20
4298 BFD_RELOC_NDS32_TLS_LE_15S0
4300 BFD_RELOC_NDS32_TLS_LE_15S1
4302 BFD_RELOC_NDS32_TLS_LE_15S2
4308 BFD_RELOC_V850_9_PCREL
4310 This is a 9-bit reloc
4312 BFD_RELOC_V850_22_PCREL
4314 This is a 22-bit reloc
4317 BFD_RELOC_V850_SDA_16_16_OFFSET
4319 This is a 16 bit offset from the short data area pointer.
4321 BFD_RELOC_V850_SDA_15_16_OFFSET
4323 This is a 16 bit offset (of which only 15 bits are used) from the
4324 short data area pointer.
4326 BFD_RELOC_V850_ZDA_16_16_OFFSET
4328 This is a 16 bit offset from the zero data area pointer.
4330 BFD_RELOC_V850_ZDA_15_16_OFFSET
4332 This is a 16 bit offset (of which only 15 bits are used) from the
4333 zero data area pointer.
4335 BFD_RELOC_V850_TDA_6_8_OFFSET
4337 This is an 8 bit offset (of which only 6 bits are used) from the
4338 tiny data area pointer.
4340 BFD_RELOC_V850_TDA_7_8_OFFSET
4342 This is an 8bit offset (of which only 7 bits are used) from the tiny
4345 BFD_RELOC_V850_TDA_7_7_OFFSET
4347 This is a 7 bit offset from the tiny data area pointer.
4349 BFD_RELOC_V850_TDA_16_16_OFFSET
4351 This is a 16 bit offset from the tiny data area pointer.
4354 BFD_RELOC_V850_TDA_4_5_OFFSET
4356 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4359 BFD_RELOC_V850_TDA_4_4_OFFSET
4361 This is a 4 bit offset from the tiny data area pointer.
4363 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4365 This is a 16 bit offset from the short data area pointer, with the
4366 bits placed non-contiguously in the instruction.
4368 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4370 This is a 16 bit offset from the zero data area pointer, with the
4371 bits placed non-contiguously in the instruction.
4373 BFD_RELOC_V850_CALLT_6_7_OFFSET
4375 This is a 6 bit offset from the call table base pointer.
4377 BFD_RELOC_V850_CALLT_16_16_OFFSET
4379 This is a 16 bit offset from the call table base pointer.
4381 BFD_RELOC_V850_LONGCALL
4383 Used for relaxing indirect function calls.
4385 BFD_RELOC_V850_LONGJUMP
4387 Used for relaxing indirect jumps.
4389 BFD_RELOC_V850_ALIGN
4391 Used to maintain alignment whilst relaxing.
4393 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4395 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4398 BFD_RELOC_V850_16_PCREL
4400 This is a 16-bit reloc.
4402 BFD_RELOC_V850_17_PCREL
4404 This is a 17-bit reloc.
4408 This is a 23-bit reloc.
4410 BFD_RELOC_V850_32_PCREL
4412 This is a 32-bit reloc.
4414 BFD_RELOC_V850_32_ABS
4416 This is a 32-bit reloc.
4418 BFD_RELOC_V850_16_SPLIT_OFFSET
4420 This is a 16-bit reloc.
4422 BFD_RELOC_V850_16_S1
4424 This is a 16-bit reloc.
4426 BFD_RELOC_V850_LO16_S1
4428 Low 16 bits. 16 bit shifted by 1.
4430 BFD_RELOC_V850_CALLT_15_16_OFFSET
4432 This is a 16 bit offset from the call table base pointer.
4434 BFD_RELOC_V850_32_GOTPCREL
4438 BFD_RELOC_V850_16_GOT
4442 BFD_RELOC_V850_32_GOT
4446 BFD_RELOC_V850_22_PLT_PCREL
4450 BFD_RELOC_V850_32_PLT_PCREL
4458 BFD_RELOC_V850_GLOB_DAT
4462 BFD_RELOC_V850_JMP_SLOT
4466 BFD_RELOC_V850_RELATIVE
4470 BFD_RELOC_V850_16_GOTOFF
4474 BFD_RELOC_V850_32_GOTOFF
4489 This is a 8bit DP reloc for the tms320c30, where the most
4490 significant 8 bits of a 24 bit word are placed into the least
4491 significant 8 bits of the opcode.
4494 BFD_RELOC_TIC54X_PARTLS7
4496 This is a 7bit reloc for the tms320c54x, where the least
4497 significant 7 bits of a 16 bit word are placed into the least
4498 significant 7 bits of the opcode.
4501 BFD_RELOC_TIC54X_PARTMS9
4503 This is a 9bit DP reloc for the tms320c54x, where the most
4504 significant 9 bits of a 16 bit word are placed into the least
4505 significant 9 bits of the opcode.
4510 This is an extended address 23-bit reloc for the tms320c54x.
4513 BFD_RELOC_TIC54X_16_OF_23
4515 This is a 16-bit reloc for the tms320c54x, where the least
4516 significant 16 bits of a 23-bit extended address are placed into
4520 BFD_RELOC_TIC54X_MS7_OF_23
4522 This is a reloc for the tms320c54x, where the most
4523 significant 7 bits of a 23-bit extended address are placed into
4527 BFD_RELOC_C6000_PCR_S21
4529 BFD_RELOC_C6000_PCR_S12
4531 BFD_RELOC_C6000_PCR_S10
4533 BFD_RELOC_C6000_PCR_S7
4535 BFD_RELOC_C6000_ABS_S16
4537 BFD_RELOC_C6000_ABS_L16
4539 BFD_RELOC_C6000_ABS_H16
4541 BFD_RELOC_C6000_SBR_U15_B
4543 BFD_RELOC_C6000_SBR_U15_H
4545 BFD_RELOC_C6000_SBR_U15_W
4547 BFD_RELOC_C6000_SBR_S16
4549 BFD_RELOC_C6000_SBR_L16_B
4551 BFD_RELOC_C6000_SBR_L16_H
4553 BFD_RELOC_C6000_SBR_L16_W
4555 BFD_RELOC_C6000_SBR_H16_B
4557 BFD_RELOC_C6000_SBR_H16_H
4559 BFD_RELOC_C6000_SBR_H16_W
4561 BFD_RELOC_C6000_SBR_GOT_U15_W
4563 BFD_RELOC_C6000_SBR_GOT_L16_W
4565 BFD_RELOC_C6000_SBR_GOT_H16_W
4567 BFD_RELOC_C6000_DSBT_INDEX
4569 BFD_RELOC_C6000_PREL31
4571 BFD_RELOC_C6000_COPY
4573 BFD_RELOC_C6000_JUMP_SLOT
4575 BFD_RELOC_C6000_EHTYPE
4577 BFD_RELOC_C6000_PCR_H16
4579 BFD_RELOC_C6000_PCR_L16
4581 BFD_RELOC_C6000_ALIGN
4583 BFD_RELOC_C6000_FPHEAD
4585 BFD_RELOC_C6000_NOCMP
4587 TMS320C6000 relocations.
4592 This is a 48 bit reloc for the FR30 that stores 32 bits.
4596 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4599 BFD_RELOC_FR30_6_IN_4
4601 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4604 BFD_RELOC_FR30_8_IN_8
4606 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4609 BFD_RELOC_FR30_9_IN_8
4611 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4614 BFD_RELOC_FR30_10_IN_8
4616 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4619 BFD_RELOC_FR30_9_PCREL
4621 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4622 short offset into 8 bits.
4624 BFD_RELOC_FR30_12_PCREL
4626 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4627 short offset into 11 bits.
4630 BFD_RELOC_MCORE_PCREL_IMM8BY4
4632 BFD_RELOC_MCORE_PCREL_IMM11BY2
4634 BFD_RELOC_MCORE_PCREL_IMM4BY2
4636 BFD_RELOC_MCORE_PCREL_32
4638 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4642 Motorola Mcore relocations.
4651 BFD_RELOC_MEP_PCREL8A2
4653 BFD_RELOC_MEP_PCREL12A2
4655 BFD_RELOC_MEP_PCREL17A2
4657 BFD_RELOC_MEP_PCREL24A2
4659 BFD_RELOC_MEP_PCABS24A2
4671 BFD_RELOC_MEP_TPREL7
4673 BFD_RELOC_MEP_TPREL7A2
4675 BFD_RELOC_MEP_TPREL7A4
4677 BFD_RELOC_MEP_UIMM24
4679 BFD_RELOC_MEP_ADDR24A4
4681 BFD_RELOC_MEP_GNU_VTINHERIT
4683 BFD_RELOC_MEP_GNU_VTENTRY
4685 Toshiba Media Processor Relocations.
4689 BFD_RELOC_METAG_HIADDR16
4691 BFD_RELOC_METAG_LOADDR16
4693 BFD_RELOC_METAG_RELBRANCH
4695 BFD_RELOC_METAG_GETSETOFF
4697 BFD_RELOC_METAG_HIOG
4699 BFD_RELOC_METAG_LOOG
4701 BFD_RELOC_METAG_REL8
4703 BFD_RELOC_METAG_REL16
4705 BFD_RELOC_METAG_HI16_GOTOFF
4707 BFD_RELOC_METAG_LO16_GOTOFF
4709 BFD_RELOC_METAG_GETSET_GOTOFF
4711 BFD_RELOC_METAG_GETSET_GOT
4713 BFD_RELOC_METAG_HI16_GOTPC
4715 BFD_RELOC_METAG_LO16_GOTPC
4717 BFD_RELOC_METAG_HI16_PLT
4719 BFD_RELOC_METAG_LO16_PLT
4721 BFD_RELOC_METAG_RELBRANCH_PLT
4723 BFD_RELOC_METAG_GOTOFF
4727 BFD_RELOC_METAG_COPY
4729 BFD_RELOC_METAG_JMP_SLOT
4731 BFD_RELOC_METAG_RELATIVE
4733 BFD_RELOC_METAG_GLOB_DAT
4735 BFD_RELOC_METAG_TLS_GD
4737 BFD_RELOC_METAG_TLS_LDM
4739 BFD_RELOC_METAG_TLS_LDO_HI16
4741 BFD_RELOC_METAG_TLS_LDO_LO16
4743 BFD_RELOC_METAG_TLS_LDO
4745 BFD_RELOC_METAG_TLS_IE
4747 BFD_RELOC_METAG_TLS_IENONPIC
4749 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4751 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4753 BFD_RELOC_METAG_TLS_TPOFF
4755 BFD_RELOC_METAG_TLS_DTPMOD
4757 BFD_RELOC_METAG_TLS_DTPOFF
4759 BFD_RELOC_METAG_TLS_LE
4761 BFD_RELOC_METAG_TLS_LE_HI16
4763 BFD_RELOC_METAG_TLS_LE_LO16
4765 Imagination Technologies Meta relocations.
4770 BFD_RELOC_MMIX_GETA_1
4772 BFD_RELOC_MMIX_GETA_2
4774 BFD_RELOC_MMIX_GETA_3
4776 These are relocations for the GETA instruction.
4778 BFD_RELOC_MMIX_CBRANCH
4780 BFD_RELOC_MMIX_CBRANCH_J
4782 BFD_RELOC_MMIX_CBRANCH_1
4784 BFD_RELOC_MMIX_CBRANCH_2
4786 BFD_RELOC_MMIX_CBRANCH_3
4788 These are relocations for a conditional branch instruction.
4790 BFD_RELOC_MMIX_PUSHJ
4792 BFD_RELOC_MMIX_PUSHJ_1
4794 BFD_RELOC_MMIX_PUSHJ_2
4796 BFD_RELOC_MMIX_PUSHJ_3
4798 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4800 These are relocations for the PUSHJ instruction.
4804 BFD_RELOC_MMIX_JMP_1
4806 BFD_RELOC_MMIX_JMP_2
4808 BFD_RELOC_MMIX_JMP_3
4810 These are relocations for the JMP instruction.
4812 BFD_RELOC_MMIX_ADDR19
4814 This is a relocation for a relative address as in a GETA instruction or
4817 BFD_RELOC_MMIX_ADDR27
4819 This is a relocation for a relative address as in a JMP instruction.
4821 BFD_RELOC_MMIX_REG_OR_BYTE
4823 This is a relocation for an instruction field that may be a general
4824 register or a value 0..255.
4828 This is a relocation for an instruction field that may be a general
4831 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4833 This is a relocation for two instruction fields holding a register and
4834 an offset, the equivalent of the relocation.
4836 BFD_RELOC_MMIX_LOCAL
4838 This relocation is an assertion that the expression is not allocated as
4839 a global register. It does not modify contents.
4842 BFD_RELOC_AVR_7_PCREL
4844 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4845 short offset into 7 bits.
4847 BFD_RELOC_AVR_13_PCREL
4849 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4850 short offset into 12 bits.
4854 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4855 program memory address) into 16 bits.
4857 BFD_RELOC_AVR_LO8_LDI
4859 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4860 data memory address) into 8 bit immediate value of LDI insn.
4862 BFD_RELOC_AVR_HI8_LDI
4864 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4865 of data memory address) into 8 bit immediate value of LDI insn.
4867 BFD_RELOC_AVR_HH8_LDI
4869 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4870 of program memory address) into 8 bit immediate value of LDI insn.
4872 BFD_RELOC_AVR_MS8_LDI
4874 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4875 of 32 bit value) into 8 bit immediate value of LDI insn.
4877 BFD_RELOC_AVR_LO8_LDI_NEG
4879 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4880 (usually data memory address) into 8 bit immediate value of SUBI insn.
4882 BFD_RELOC_AVR_HI8_LDI_NEG
4884 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4885 (high 8 bit of data memory address) into 8 bit immediate value of
4888 BFD_RELOC_AVR_HH8_LDI_NEG
4890 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4891 (most high 8 bit of program memory address) into 8 bit immediate value
4892 of LDI or SUBI insn.
4894 BFD_RELOC_AVR_MS8_LDI_NEG
4896 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4897 of 32 bit value) into 8 bit immediate value of LDI insn.
4899 BFD_RELOC_AVR_LO8_LDI_PM
4901 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4902 command address) into 8 bit immediate value of LDI insn.
4904 BFD_RELOC_AVR_LO8_LDI_GS
4906 This is a 16 bit reloc for the AVR that stores 8 bit value
4907 (command address) into 8 bit immediate value of LDI insn. If the address
4908 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4911 BFD_RELOC_AVR_HI8_LDI_PM
4913 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4914 of command address) into 8 bit immediate value of LDI insn.
4916 BFD_RELOC_AVR_HI8_LDI_GS
4918 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4919 of command address) into 8 bit immediate value of LDI insn. If the address
4920 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4923 BFD_RELOC_AVR_HH8_LDI_PM
4925 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4926 of command address) into 8 bit immediate value of LDI insn.
4928 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4930 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4931 (usually command address) into 8 bit immediate value of SUBI insn.
4933 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4935 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4936 (high 8 bit of 16 bit command address) into 8 bit immediate value
4939 BFD_RELOC_AVR_HH8_LDI_PM_NEG
4941 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4942 (high 6 bit of 22 bit command address) into 8 bit immediate
4947 This is a 32 bit reloc for the AVR that stores 23 bit value
4952 This is a 16 bit reloc for the AVR that stores all needed bits
4953 for absolute addressing with ldi with overflow check to linktime
4957 This is a 6 bit reloc for the AVR that stores offset for ldd/std
4960 BFD_RELOC_AVR_6_ADIW
4962 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
4967 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
4968 in .byte lo8(symbol)
4972 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
4973 in .byte hi8(symbol)
4977 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
4978 in .byte hlo8(symbol)
4982 BFD_RELOC_AVR_DIFF16
4984 BFD_RELOC_AVR_DIFF32
4986 AVR relocations to mark the difference of two local symbols.
4987 These are only needed to support linker relaxation and can be ignored
4988 when not relaxing. The field is set to the value of the difference
4989 assuming no relaxation. The relocation encodes the position of the
4990 second symbol so the linker can determine whether to adjust the field
4993 BFD_RELOC_AVR_LDS_STS_16
4995 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
4996 lds and sts instructions supported only tiny core.
5000 This is a 6 bit reloc for the AVR that stores an I/O register
5001 number for the IN and OUT instructions
5005 This is a 5 bit reloc for the AVR that stores an I/O register
5006 number for the SBIC, SBIS, SBI and CBI instructions
5009 BFD_RELOC_RISCV_HI20
5011 BFD_RELOC_RISCV_PCREL_HI20
5013 BFD_RELOC_RISCV_PCREL_LO12_I
5015 BFD_RELOC_RISCV_PCREL_LO12_S
5017 BFD_RELOC_RISCV_LO12_I
5019 BFD_RELOC_RISCV_LO12_S
5021 BFD_RELOC_RISCV_GPREL12_I
5023 BFD_RELOC_RISCV_GPREL12_S
5025 BFD_RELOC_RISCV_TPREL_HI20
5027 BFD_RELOC_RISCV_TPREL_LO12_I
5029 BFD_RELOC_RISCV_TPREL_LO12_S
5031 BFD_RELOC_RISCV_TPREL_ADD
5033 BFD_RELOC_RISCV_CALL
5035 BFD_RELOC_RISCV_CALL_PLT
5037 BFD_RELOC_RISCV_ADD8
5039 BFD_RELOC_RISCV_ADD16
5041 BFD_RELOC_RISCV_ADD32
5043 BFD_RELOC_RISCV_ADD64
5045 BFD_RELOC_RISCV_SUB8
5047 BFD_RELOC_RISCV_SUB16
5049 BFD_RELOC_RISCV_SUB32
5051 BFD_RELOC_RISCV_SUB64
5053 BFD_RELOC_RISCV_GOT_HI20
5055 BFD_RELOC_RISCV_TLS_GOT_HI20
5057 BFD_RELOC_RISCV_TLS_GD_HI20
5061 BFD_RELOC_RISCV_TLS_DTPMOD32
5063 BFD_RELOC_RISCV_TLS_DTPREL32
5065 BFD_RELOC_RISCV_TLS_DTPMOD64
5067 BFD_RELOC_RISCV_TLS_DTPREL64
5069 BFD_RELOC_RISCV_TLS_TPREL32
5071 BFD_RELOC_RISCV_TLS_TPREL64
5073 BFD_RELOC_RISCV_ALIGN
5075 BFD_RELOC_RISCV_RVC_BRANCH
5077 BFD_RELOC_RISCV_RVC_JUMP
5079 BFD_RELOC_RISCV_RVC_LUI
5081 BFD_RELOC_RISCV_GPREL_I
5083 BFD_RELOC_RISCV_GPREL_S
5085 BFD_RELOC_RISCV_TPREL_I
5087 BFD_RELOC_RISCV_TPREL_S
5089 BFD_RELOC_RISCV_RELAX
5093 BFD_RELOC_RISCV_SUB6
5095 BFD_RELOC_RISCV_SET6
5097 BFD_RELOC_RISCV_SET8
5099 BFD_RELOC_RISCV_SET16
5101 BFD_RELOC_RISCV_SET32
5103 BFD_RELOC_RISCV_32_PCREL
5110 BFD_RELOC_RL78_NEG16
5112 BFD_RELOC_RL78_NEG24
5114 BFD_RELOC_RL78_NEG32
5116 BFD_RELOC_RL78_16_OP
5118 BFD_RELOC_RL78_24_OP
5120 BFD_RELOC_RL78_32_OP
5128 BFD_RELOC_RL78_DIR3U_PCREL
5132 BFD_RELOC_RL78_GPRELB
5134 BFD_RELOC_RL78_GPRELW
5136 BFD_RELOC_RL78_GPRELL
5140 BFD_RELOC_RL78_OP_SUBTRACT
5142 BFD_RELOC_RL78_OP_NEG
5144 BFD_RELOC_RL78_OP_AND
5146 BFD_RELOC_RL78_OP_SHRA
5150 BFD_RELOC_RL78_ABS16
5152 BFD_RELOC_RL78_ABS16_REV
5154 BFD_RELOC_RL78_ABS32
5156 BFD_RELOC_RL78_ABS32_REV
5158 BFD_RELOC_RL78_ABS16U
5160 BFD_RELOC_RL78_ABS16UW
5162 BFD_RELOC_RL78_ABS16UL
5164 BFD_RELOC_RL78_RELAX
5174 BFD_RELOC_RL78_SADDR
5176 Renesas RL78 Relocations.
5199 BFD_RELOC_RX_DIR3U_PCREL
5211 BFD_RELOC_RX_OP_SUBTRACT
5219 BFD_RELOC_RX_ABS16_REV
5223 BFD_RELOC_RX_ABS32_REV
5227 BFD_RELOC_RX_ABS16UW
5229 BFD_RELOC_RX_ABS16UL
5233 Renesas RX Relocations.
5246 32 bit PC relative PLT address.
5250 Copy symbol at runtime.
5252 BFD_RELOC_390_GLOB_DAT
5256 BFD_RELOC_390_JMP_SLOT
5260 BFD_RELOC_390_RELATIVE
5262 Adjust by program base.
5266 32 bit PC relative offset to GOT.
5272 BFD_RELOC_390_PC12DBL
5274 PC relative 12 bit shifted by 1.
5276 BFD_RELOC_390_PLT12DBL
5278 12 bit PC rel. PLT shifted by 1.
5280 BFD_RELOC_390_PC16DBL
5282 PC relative 16 bit shifted by 1.
5284 BFD_RELOC_390_PLT16DBL
5286 16 bit PC rel. PLT shifted by 1.
5288 BFD_RELOC_390_PC24DBL
5290 PC relative 24 bit shifted by 1.
5292 BFD_RELOC_390_PLT24DBL
5294 24 bit PC rel. PLT shifted by 1.
5296 BFD_RELOC_390_PC32DBL
5298 PC relative 32 bit shifted by 1.
5300 BFD_RELOC_390_PLT32DBL
5302 32 bit PC rel. PLT shifted by 1.
5304 BFD_RELOC_390_GOTPCDBL
5306 32 bit PC rel. GOT shifted by 1.
5314 64 bit PC relative PLT address.
5316 BFD_RELOC_390_GOTENT
5318 32 bit rel. offset to GOT entry.
5320 BFD_RELOC_390_GOTOFF64
5322 64 bit offset to GOT.
5324 BFD_RELOC_390_GOTPLT12
5326 12-bit offset to symbol-entry within GOT, with PLT handling.
5328 BFD_RELOC_390_GOTPLT16
5330 16-bit offset to symbol-entry within GOT, with PLT handling.
5332 BFD_RELOC_390_GOTPLT32
5334 32-bit offset to symbol-entry within GOT, with PLT handling.
5336 BFD_RELOC_390_GOTPLT64
5338 64-bit offset to symbol-entry within GOT, with PLT handling.
5340 BFD_RELOC_390_GOTPLTENT
5342 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5344 BFD_RELOC_390_PLTOFF16
5346 16-bit rel. offset from the GOT to a PLT entry.
5348 BFD_RELOC_390_PLTOFF32
5350 32-bit rel. offset from the GOT to a PLT entry.
5352 BFD_RELOC_390_PLTOFF64
5354 64-bit rel. offset from the GOT to a PLT entry.
5357 BFD_RELOC_390_TLS_LOAD
5359 BFD_RELOC_390_TLS_GDCALL
5361 BFD_RELOC_390_TLS_LDCALL
5363 BFD_RELOC_390_TLS_GD32
5365 BFD_RELOC_390_TLS_GD64
5367 BFD_RELOC_390_TLS_GOTIE12
5369 BFD_RELOC_390_TLS_GOTIE32
5371 BFD_RELOC_390_TLS_GOTIE64
5373 BFD_RELOC_390_TLS_LDM32
5375 BFD_RELOC_390_TLS_LDM64
5377 BFD_RELOC_390_TLS_IE32
5379 BFD_RELOC_390_TLS_IE64
5381 BFD_RELOC_390_TLS_IEENT
5383 BFD_RELOC_390_TLS_LE32
5385 BFD_RELOC_390_TLS_LE64
5387 BFD_RELOC_390_TLS_LDO32
5389 BFD_RELOC_390_TLS_LDO64
5391 BFD_RELOC_390_TLS_DTPMOD
5393 BFD_RELOC_390_TLS_DTPOFF
5395 BFD_RELOC_390_TLS_TPOFF
5397 s390 tls relocations.
5404 BFD_RELOC_390_GOTPLT20
5406 BFD_RELOC_390_TLS_GOTIE20
5408 Long displacement extension.
5411 BFD_RELOC_390_IRELATIVE
5413 STT_GNU_IFUNC relocation.
5416 BFD_RELOC_SCORE_GPREL15
5419 Low 16 bit for load/store
5421 BFD_RELOC_SCORE_DUMMY2
5425 This is a 24-bit reloc with the right 1 bit assumed to be 0
5427 BFD_RELOC_SCORE_BRANCH
5429 This is a 19-bit reloc with the right 1 bit assumed to be 0
5431 BFD_RELOC_SCORE_IMM30
5433 This is a 32-bit reloc for 48-bit instructions.
5435 BFD_RELOC_SCORE_IMM32
5437 This is a 32-bit reloc for 48-bit instructions.
5439 BFD_RELOC_SCORE16_JMP
5441 This is a 11-bit reloc with the right 1 bit assumed to be 0
5443 BFD_RELOC_SCORE16_BRANCH
5445 This is a 8-bit reloc with the right 1 bit assumed to be 0
5447 BFD_RELOC_SCORE_BCMP
5449 This is a 9-bit reloc with the right 1 bit assumed to be 0
5451 BFD_RELOC_SCORE_GOT15
5453 BFD_RELOC_SCORE_GOT_LO16
5455 BFD_RELOC_SCORE_CALL15
5457 BFD_RELOC_SCORE_DUMMY_HI16
5459 Undocumented Score relocs
5464 Scenix IP2K - 9-bit register number / data address
5468 Scenix IP2K - 4-bit register/data bank number
5470 BFD_RELOC_IP2K_ADDR16CJP
5472 Scenix IP2K - low 13 bits of instruction word address
5474 BFD_RELOC_IP2K_PAGE3
5476 Scenix IP2K - high 3 bits of instruction word address
5478 BFD_RELOC_IP2K_LO8DATA
5480 BFD_RELOC_IP2K_HI8DATA
5482 BFD_RELOC_IP2K_EX8DATA
5484 Scenix IP2K - ext/low/high 8 bits of data address
5486 BFD_RELOC_IP2K_LO8INSN
5488 BFD_RELOC_IP2K_HI8INSN
5490 Scenix IP2K - low/high 8 bits of instruction word address
5492 BFD_RELOC_IP2K_PC_SKIP
5494 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5498 Scenix IP2K - 16 bit word address in text section.
5500 BFD_RELOC_IP2K_FR_OFFSET
5502 Scenix IP2K - 7-bit sp or dp offset
5504 BFD_RELOC_VPE4KMATH_DATA
5506 BFD_RELOC_VPE4KMATH_INSN
5508 Scenix VPE4K coprocessor - data/insn-space addressing
5511 BFD_RELOC_VTABLE_INHERIT
5513 BFD_RELOC_VTABLE_ENTRY
5515 These two relocations are used by the linker to determine which of
5516 the entries in a C++ virtual function table are actually used. When
5517 the --gc-sections option is given, the linker will zero out the entries
5518 that are not used, so that the code for those functions need not be
5519 included in the output.
5521 VTABLE_INHERIT is a zero-space relocation used to describe to the
5522 linker the inheritance tree of a C++ virtual function table. The
5523 relocation's symbol should be the parent class' vtable, and the
5524 relocation should be located at the child vtable.
5526 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5527 virtual function table entry. The reloc's symbol should refer to the
5528 table of the class mentioned in the code. Off of that base, an offset
5529 describes the entry that is being used. For Rela hosts, this offset
5530 is stored in the reloc's addend. For Rel hosts, we are forced to put
5531 this offset in the reloc's section offset.
5534 BFD_RELOC_IA64_IMM14
5536 BFD_RELOC_IA64_IMM22
5538 BFD_RELOC_IA64_IMM64
5540 BFD_RELOC_IA64_DIR32MSB
5542 BFD_RELOC_IA64_DIR32LSB
5544 BFD_RELOC_IA64_DIR64MSB
5546 BFD_RELOC_IA64_DIR64LSB
5548 BFD_RELOC_IA64_GPREL22
5550 BFD_RELOC_IA64_GPREL64I
5552 BFD_RELOC_IA64_GPREL32MSB
5554 BFD_RELOC_IA64_GPREL32LSB
5556 BFD_RELOC_IA64_GPREL64MSB
5558 BFD_RELOC_IA64_GPREL64LSB
5560 BFD_RELOC_IA64_LTOFF22
5562 BFD_RELOC_IA64_LTOFF64I
5564 BFD_RELOC_IA64_PLTOFF22
5566 BFD_RELOC_IA64_PLTOFF64I
5568 BFD_RELOC_IA64_PLTOFF64MSB
5570 BFD_RELOC_IA64_PLTOFF64LSB
5572 BFD_RELOC_IA64_FPTR64I
5574 BFD_RELOC_IA64_FPTR32MSB
5576 BFD_RELOC_IA64_FPTR32LSB
5578 BFD_RELOC_IA64_FPTR64MSB
5580 BFD_RELOC_IA64_FPTR64LSB
5582 BFD_RELOC_IA64_PCREL21B
5584 BFD_RELOC_IA64_PCREL21BI
5586 BFD_RELOC_IA64_PCREL21M
5588 BFD_RELOC_IA64_PCREL21F
5590 BFD_RELOC_IA64_PCREL22
5592 BFD_RELOC_IA64_PCREL60B
5594 BFD_RELOC_IA64_PCREL64I
5596 BFD_RELOC_IA64_PCREL32MSB
5598 BFD_RELOC_IA64_PCREL32LSB
5600 BFD_RELOC_IA64_PCREL64MSB
5602 BFD_RELOC_IA64_PCREL64LSB
5604 BFD_RELOC_IA64_LTOFF_FPTR22
5606 BFD_RELOC_IA64_LTOFF_FPTR64I
5608 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5610 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5612 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5614 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5616 BFD_RELOC_IA64_SEGREL32MSB
5618 BFD_RELOC_IA64_SEGREL32LSB
5620 BFD_RELOC_IA64_SEGREL64MSB
5622 BFD_RELOC_IA64_SEGREL64LSB
5624 BFD_RELOC_IA64_SECREL32MSB
5626 BFD_RELOC_IA64_SECREL32LSB
5628 BFD_RELOC_IA64_SECREL64MSB
5630 BFD_RELOC_IA64_SECREL64LSB
5632 BFD_RELOC_IA64_REL32MSB
5634 BFD_RELOC_IA64_REL32LSB
5636 BFD_RELOC_IA64_REL64MSB
5638 BFD_RELOC_IA64_REL64LSB
5640 BFD_RELOC_IA64_LTV32MSB
5642 BFD_RELOC_IA64_LTV32LSB
5644 BFD_RELOC_IA64_LTV64MSB
5646 BFD_RELOC_IA64_LTV64LSB
5648 BFD_RELOC_IA64_IPLTMSB
5650 BFD_RELOC_IA64_IPLTLSB
5654 BFD_RELOC_IA64_LTOFF22X
5656 BFD_RELOC_IA64_LDXMOV
5658 BFD_RELOC_IA64_TPREL14
5660 BFD_RELOC_IA64_TPREL22
5662 BFD_RELOC_IA64_TPREL64I
5664 BFD_RELOC_IA64_TPREL64MSB
5666 BFD_RELOC_IA64_TPREL64LSB
5668 BFD_RELOC_IA64_LTOFF_TPREL22
5670 BFD_RELOC_IA64_DTPMOD64MSB
5672 BFD_RELOC_IA64_DTPMOD64LSB
5674 BFD_RELOC_IA64_LTOFF_DTPMOD22
5676 BFD_RELOC_IA64_DTPREL14
5678 BFD_RELOC_IA64_DTPREL22
5680 BFD_RELOC_IA64_DTPREL64I
5682 BFD_RELOC_IA64_DTPREL32MSB
5684 BFD_RELOC_IA64_DTPREL32LSB
5686 BFD_RELOC_IA64_DTPREL64MSB
5688 BFD_RELOC_IA64_DTPREL64LSB
5690 BFD_RELOC_IA64_LTOFF_DTPREL22
5692 Intel IA64 Relocations.
5695 BFD_RELOC_M68HC11_HI8
5697 Motorola 68HC11 reloc.
5698 This is the 8 bit high part of an absolute address.
5700 BFD_RELOC_M68HC11_LO8
5702 Motorola 68HC11 reloc.
5703 This is the 8 bit low part of an absolute address.
5705 BFD_RELOC_M68HC11_3B
5707 Motorola 68HC11 reloc.
5708 This is the 3 bit of a value.
5710 BFD_RELOC_M68HC11_RL_JUMP
5712 Motorola 68HC11 reloc.
5713 This reloc marks the beginning of a jump/call instruction.
5714 It is used for linker relaxation to correctly identify beginning
5715 of instruction and change some branches to use PC-relative
5718 BFD_RELOC_M68HC11_RL_GROUP
5720 Motorola 68HC11 reloc.
5721 This reloc marks a group of several instructions that gcc generates
5722 and for which the linker relaxation pass can modify and/or remove
5725 BFD_RELOC_M68HC11_LO16
5727 Motorola 68HC11 reloc.
5728 This is the 16-bit lower part of an address. It is used for 'call'
5729 instruction to specify the symbol address without any special
5730 transformation (due to memory bank window).
5732 BFD_RELOC_M68HC11_PAGE
5734 Motorola 68HC11 reloc.
5735 This is a 8-bit reloc that specifies the page number of an address.
5736 It is used by 'call' instruction to specify the page number of
5739 BFD_RELOC_M68HC11_24
5741 Motorola 68HC11 reloc.
5742 This is a 24-bit reloc that represents the address with a 16-bit
5743 value and a 8-bit page number. The symbol address is transformed
5744 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5746 BFD_RELOC_M68HC12_5B
5748 Motorola 68HC12 reloc.
5749 This is the 5 bits of a value.
5751 BFD_RELOC_XGATE_RL_JUMP
5753 Freescale XGATE reloc.
5754 This reloc marks the beginning of a bra/jal instruction.
5756 BFD_RELOC_XGATE_RL_GROUP
5758 Freescale XGATE reloc.
5759 This reloc marks a group of several instructions that gcc generates
5760 and for which the linker relaxation pass can modify and/or remove
5763 BFD_RELOC_XGATE_LO16
5765 Freescale XGATE reloc.
5766 This is the 16-bit lower part of an address. It is used for the '16-bit'
5769 BFD_RELOC_XGATE_GPAGE
5771 Freescale XGATE reloc.
5775 Freescale XGATE reloc.
5777 BFD_RELOC_XGATE_PCREL_9
5779 Freescale XGATE reloc.
5780 This is a 9-bit pc-relative reloc.
5782 BFD_RELOC_XGATE_PCREL_10
5784 Freescale XGATE reloc.
5785 This is a 10-bit pc-relative reloc.
5787 BFD_RELOC_XGATE_IMM8_LO
5789 Freescale XGATE reloc.
5790 This is the 16-bit lower part of an address. It is used for the '16-bit'
5793 BFD_RELOC_XGATE_IMM8_HI
5795 Freescale XGATE reloc.
5796 This is the 16-bit higher part of an address. It is used for the '16-bit'
5799 BFD_RELOC_XGATE_IMM3
5801 Freescale XGATE reloc.
5802 This is a 3-bit pc-relative reloc.
5804 BFD_RELOC_XGATE_IMM4
5806 Freescale XGATE reloc.
5807 This is a 4-bit pc-relative reloc.
5809 BFD_RELOC_XGATE_IMM5
5811 Freescale XGATE reloc.
5812 This is a 5-bit pc-relative reloc.
5814 BFD_RELOC_M68HC12_9B
5816 Motorola 68HC12 reloc.
5817 This is the 9 bits of a value.
5819 BFD_RELOC_M68HC12_16B
5821 Motorola 68HC12 reloc.
5822 This is the 16 bits of a value.
5824 BFD_RELOC_M68HC12_9_PCREL
5826 Motorola 68HC12/XGATE reloc.
5827 This is a PCREL9 branch.
5829 BFD_RELOC_M68HC12_10_PCREL
5831 Motorola 68HC12/XGATE reloc.
5832 This is a PCREL10 branch.
5834 BFD_RELOC_M68HC12_LO8XG
5836 Motorola 68HC12/XGATE reloc.
5837 This is the 8 bit low part of an absolute address and immediately precedes
5838 a matching HI8XG part.
5840 BFD_RELOC_M68HC12_HI8XG
5842 Motorola 68HC12/XGATE reloc.
5843 This is the 8 bit high part of an absolute address and immediately follows
5844 a matching LO8XG part.
5846 BFD_RELOC_S12Z_15_PCREL
5848 Freescale S12Z reloc.
5849 This is a 15 bit relative address. If the most significant bits are all zero
5850 then it may be truncated to 8 bits.
5854 BFD_RELOC_16C_NUM08_C
5858 BFD_RELOC_16C_NUM16_C
5862 BFD_RELOC_16C_NUM32_C
5864 BFD_RELOC_16C_DISP04
5866 BFD_RELOC_16C_DISP04_C
5868 BFD_RELOC_16C_DISP08
5870 BFD_RELOC_16C_DISP08_C
5872 BFD_RELOC_16C_DISP16
5874 BFD_RELOC_16C_DISP16_C
5876 BFD_RELOC_16C_DISP24
5878 BFD_RELOC_16C_DISP24_C
5880 BFD_RELOC_16C_DISP24a
5882 BFD_RELOC_16C_DISP24a_C
5886 BFD_RELOC_16C_REG04_C
5888 BFD_RELOC_16C_REG04a
5890 BFD_RELOC_16C_REG04a_C
5894 BFD_RELOC_16C_REG14_C
5898 BFD_RELOC_16C_REG16_C
5902 BFD_RELOC_16C_REG20_C
5906 BFD_RELOC_16C_ABS20_C
5910 BFD_RELOC_16C_ABS24_C
5914 BFD_RELOC_16C_IMM04_C
5918 BFD_RELOC_16C_IMM16_C
5922 BFD_RELOC_16C_IMM20_C
5926 BFD_RELOC_16C_IMM24_C
5930 BFD_RELOC_16C_IMM32_C
5932 NS CR16C Relocations.
5937 BFD_RELOC_CR16_NUM16
5939 BFD_RELOC_CR16_NUM32
5941 BFD_RELOC_CR16_NUM32a
5943 BFD_RELOC_CR16_REGREL0
5945 BFD_RELOC_CR16_REGREL4
5947 BFD_RELOC_CR16_REGREL4a
5949 BFD_RELOC_CR16_REGREL14
5951 BFD_RELOC_CR16_REGREL14a
5953 BFD_RELOC_CR16_REGREL16
5955 BFD_RELOC_CR16_REGREL20
5957 BFD_RELOC_CR16_REGREL20a
5959 BFD_RELOC_CR16_ABS20
5961 BFD_RELOC_CR16_ABS24
5967 BFD_RELOC_CR16_IMM16
5969 BFD_RELOC_CR16_IMM20
5971 BFD_RELOC_CR16_IMM24
5973 BFD_RELOC_CR16_IMM32
5975 BFD_RELOC_CR16_IMM32a
5977 BFD_RELOC_CR16_DISP4
5979 BFD_RELOC_CR16_DISP8
5981 BFD_RELOC_CR16_DISP16
5983 BFD_RELOC_CR16_DISP20
5985 BFD_RELOC_CR16_DISP24
5987 BFD_RELOC_CR16_DISP24a
5989 BFD_RELOC_CR16_SWITCH8
5991 BFD_RELOC_CR16_SWITCH16
5993 BFD_RELOC_CR16_SWITCH32
5995 BFD_RELOC_CR16_GOT_REGREL20
5997 BFD_RELOC_CR16_GOTC_REGREL20
5999 BFD_RELOC_CR16_GLOB_DAT
6001 NS CR16 Relocations.
6008 BFD_RELOC_CRX_REL8_CMP
6016 BFD_RELOC_CRX_REGREL12
6018 BFD_RELOC_CRX_REGREL22
6020 BFD_RELOC_CRX_REGREL28
6022 BFD_RELOC_CRX_REGREL32
6038 BFD_RELOC_CRX_SWITCH8
6040 BFD_RELOC_CRX_SWITCH16
6042 BFD_RELOC_CRX_SWITCH32
6047 BFD_RELOC_CRIS_BDISP8
6049 BFD_RELOC_CRIS_UNSIGNED_5
6051 BFD_RELOC_CRIS_SIGNED_6
6053 BFD_RELOC_CRIS_UNSIGNED_6
6055 BFD_RELOC_CRIS_SIGNED_8
6057 BFD_RELOC_CRIS_UNSIGNED_8
6059 BFD_RELOC_CRIS_SIGNED_16
6061 BFD_RELOC_CRIS_UNSIGNED_16
6063 BFD_RELOC_CRIS_LAPCQ_OFFSET
6065 BFD_RELOC_CRIS_UNSIGNED_4
6067 These relocs are only used within the CRIS assembler. They are not
6068 (at present) written to any object files.
6072 BFD_RELOC_CRIS_GLOB_DAT
6074 BFD_RELOC_CRIS_JUMP_SLOT
6076 BFD_RELOC_CRIS_RELATIVE
6078 Relocs used in ELF shared libraries for CRIS.
6080 BFD_RELOC_CRIS_32_GOT
6082 32-bit offset to symbol-entry within GOT.
6084 BFD_RELOC_CRIS_16_GOT
6086 16-bit offset to symbol-entry within GOT.
6088 BFD_RELOC_CRIS_32_GOTPLT
6090 32-bit offset to symbol-entry within GOT, with PLT handling.
6092 BFD_RELOC_CRIS_16_GOTPLT
6094 16-bit offset to symbol-entry within GOT, with PLT handling.
6096 BFD_RELOC_CRIS_32_GOTREL
6098 32-bit offset to symbol, relative to GOT.
6100 BFD_RELOC_CRIS_32_PLT_GOTREL
6102 32-bit offset to symbol with PLT entry, relative to GOT.
6104 BFD_RELOC_CRIS_32_PLT_PCREL
6106 32-bit offset to symbol with PLT entry, relative to this relocation.
6109 BFD_RELOC_CRIS_32_GOT_GD
6111 BFD_RELOC_CRIS_16_GOT_GD
6113 BFD_RELOC_CRIS_32_GD
6117 BFD_RELOC_CRIS_32_DTPREL
6119 BFD_RELOC_CRIS_16_DTPREL
6121 BFD_RELOC_CRIS_32_GOT_TPREL
6123 BFD_RELOC_CRIS_16_GOT_TPREL
6125 BFD_RELOC_CRIS_32_TPREL
6127 BFD_RELOC_CRIS_16_TPREL
6129 BFD_RELOC_CRIS_DTPMOD
6131 BFD_RELOC_CRIS_32_IE
6133 Relocs used in TLS code for CRIS.
6136 BFD_RELOC_OR1K_REL_26
6138 BFD_RELOC_OR1K_GOTPC_HI16
6140 BFD_RELOC_OR1K_GOTPC_LO16
6142 BFD_RELOC_OR1K_GOT16
6144 BFD_RELOC_OR1K_PLT26
6146 BFD_RELOC_OR1K_GOTOFF_HI16
6148 BFD_RELOC_OR1K_GOTOFF_LO16
6152 BFD_RELOC_OR1K_GLOB_DAT
6154 BFD_RELOC_OR1K_JMP_SLOT
6156 BFD_RELOC_OR1K_RELATIVE
6158 BFD_RELOC_OR1K_TLS_GD_HI16
6160 BFD_RELOC_OR1K_TLS_GD_LO16
6162 BFD_RELOC_OR1K_TLS_LDM_HI16
6164 BFD_RELOC_OR1K_TLS_LDM_LO16
6166 BFD_RELOC_OR1K_TLS_LDO_HI16
6168 BFD_RELOC_OR1K_TLS_LDO_LO16
6170 BFD_RELOC_OR1K_TLS_IE_HI16
6172 BFD_RELOC_OR1K_TLS_IE_LO16
6174 BFD_RELOC_OR1K_TLS_LE_HI16
6176 BFD_RELOC_OR1K_TLS_LE_LO16
6178 BFD_RELOC_OR1K_TLS_TPOFF
6180 BFD_RELOC_OR1K_TLS_DTPOFF
6182 BFD_RELOC_OR1K_TLS_DTPMOD
6184 OpenRISC 1000 Relocations.
6187 BFD_RELOC_H8_DIR16A8
6189 BFD_RELOC_H8_DIR16R8
6191 BFD_RELOC_H8_DIR24A8
6193 BFD_RELOC_H8_DIR24R8
6195 BFD_RELOC_H8_DIR32A16
6197 BFD_RELOC_H8_DISP32A16
6202 BFD_RELOC_XSTORMY16_REL_12
6204 BFD_RELOC_XSTORMY16_12
6206 BFD_RELOC_XSTORMY16_24
6208 BFD_RELOC_XSTORMY16_FPTR16
6210 Sony Xstormy16 Relocations.
6215 Self-describing complex relocations.
6227 Infineon Relocations.
6230 BFD_RELOC_VAX_GLOB_DAT
6232 BFD_RELOC_VAX_JMP_SLOT
6234 BFD_RELOC_VAX_RELATIVE
6236 Relocations used by VAX ELF.
6241 Morpho MT - 16 bit immediate relocation.
6245 Morpho MT - Hi 16 bits of an address.
6249 Morpho MT - Low 16 bits of an address.
6251 BFD_RELOC_MT_GNU_VTINHERIT
6253 Morpho MT - Used to tell the linker which vtable entries are used.
6255 BFD_RELOC_MT_GNU_VTENTRY
6257 Morpho MT - Used to tell the linker which vtable entries are used.
6259 BFD_RELOC_MT_PCINSN8
6261 Morpho MT - 8 bit immediate relocation.
6264 BFD_RELOC_MSP430_10_PCREL
6266 BFD_RELOC_MSP430_16_PCREL
6270 BFD_RELOC_MSP430_16_PCREL_BYTE
6272 BFD_RELOC_MSP430_16_BYTE
6274 BFD_RELOC_MSP430_2X_PCREL
6276 BFD_RELOC_MSP430_RL_PCREL
6278 BFD_RELOC_MSP430_ABS8
6280 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6282 BFD_RELOC_MSP430X_PCR20_EXT_DST
6284 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6286 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6288 BFD_RELOC_MSP430X_ABS20_EXT_DST
6290 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6292 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6294 BFD_RELOC_MSP430X_ABS20_ADR_DST
6296 BFD_RELOC_MSP430X_PCR16
6298 BFD_RELOC_MSP430X_PCR20_CALL
6300 BFD_RELOC_MSP430X_ABS16
6302 BFD_RELOC_MSP430_ABS_HI16
6304 BFD_RELOC_MSP430_PREL31
6306 BFD_RELOC_MSP430_SYM_DIFF
6308 msp430 specific relocation codes
6315 BFD_RELOC_NIOS2_CALL26
6317 BFD_RELOC_NIOS2_IMM5
6319 BFD_RELOC_NIOS2_CACHE_OPX
6321 BFD_RELOC_NIOS2_IMM6
6323 BFD_RELOC_NIOS2_IMM8
6325 BFD_RELOC_NIOS2_HI16
6327 BFD_RELOC_NIOS2_LO16
6329 BFD_RELOC_NIOS2_HIADJ16
6331 BFD_RELOC_NIOS2_GPREL
6333 BFD_RELOC_NIOS2_UJMP
6335 BFD_RELOC_NIOS2_CJMP
6337 BFD_RELOC_NIOS2_CALLR
6339 BFD_RELOC_NIOS2_ALIGN
6341 BFD_RELOC_NIOS2_GOT16
6343 BFD_RELOC_NIOS2_CALL16
6345 BFD_RELOC_NIOS2_GOTOFF_LO
6347 BFD_RELOC_NIOS2_GOTOFF_HA
6349 BFD_RELOC_NIOS2_PCREL_LO
6351 BFD_RELOC_NIOS2_PCREL_HA
6353 BFD_RELOC_NIOS2_TLS_GD16
6355 BFD_RELOC_NIOS2_TLS_LDM16
6357 BFD_RELOC_NIOS2_TLS_LDO16
6359 BFD_RELOC_NIOS2_TLS_IE16
6361 BFD_RELOC_NIOS2_TLS_LE16
6363 BFD_RELOC_NIOS2_TLS_DTPMOD
6365 BFD_RELOC_NIOS2_TLS_DTPREL
6367 BFD_RELOC_NIOS2_TLS_TPREL
6369 BFD_RELOC_NIOS2_COPY
6371 BFD_RELOC_NIOS2_GLOB_DAT
6373 BFD_RELOC_NIOS2_JUMP_SLOT
6375 BFD_RELOC_NIOS2_RELATIVE
6377 BFD_RELOC_NIOS2_GOTOFF
6379 BFD_RELOC_NIOS2_CALL26_NOAT
6381 BFD_RELOC_NIOS2_GOT_LO
6383 BFD_RELOC_NIOS2_GOT_HA
6385 BFD_RELOC_NIOS2_CALL_LO
6387 BFD_RELOC_NIOS2_CALL_HA
6389 BFD_RELOC_NIOS2_R2_S12
6391 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6393 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6395 BFD_RELOC_NIOS2_R2_T1I7_2
6397 BFD_RELOC_NIOS2_R2_T2I4
6399 BFD_RELOC_NIOS2_R2_T2I4_1
6401 BFD_RELOC_NIOS2_R2_T2I4_2
6403 BFD_RELOC_NIOS2_R2_X1I7_2
6405 BFD_RELOC_NIOS2_R2_X2L5
6407 BFD_RELOC_NIOS2_R2_F1I5_2
6409 BFD_RELOC_NIOS2_R2_L5I4X1
6411 BFD_RELOC_NIOS2_R2_T1X1I6
6413 BFD_RELOC_NIOS2_R2_T1X1I6_2
6415 Relocations used by the Altera Nios II core.
6420 PRU LDI 16-bit unsigned data-memory relocation.
6422 BFD_RELOC_PRU_U16_PMEMIMM
6424 PRU LDI 16-bit unsigned instruction-memory relocation.
6428 PRU relocation for two consecutive LDI load instructions that load a
6429 32 bit value into a register. If the higher bits are all zero, then
6430 the second instruction may be relaxed.
6432 BFD_RELOC_PRU_S10_PCREL
6434 PRU QBBx 10-bit signed PC-relative relocation.
6436 BFD_RELOC_PRU_U8_PCREL
6438 PRU 8-bit unsigned relocation used for the LOOP instruction.
6440 BFD_RELOC_PRU_32_PMEM
6442 BFD_RELOC_PRU_16_PMEM
6444 PRU Program Memory relocations. Used to convert from byte addressing to
6445 32-bit word addressing.
6447 BFD_RELOC_PRU_GNU_DIFF8
6449 BFD_RELOC_PRU_GNU_DIFF16
6451 BFD_RELOC_PRU_GNU_DIFF32
6453 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6455 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6457 PRU relocations to mark the difference of two local symbols.
6458 These are only needed to support linker relaxation and can be ignored
6459 when not relaxing. The field is set to the value of the difference
6460 assuming no relaxation. The relocation encodes the position of the
6461 second symbol so the linker can determine whether to adjust the field
6462 value. The PMEM variants encode the word difference, instead of byte
6463 difference between symbols.
6466 BFD_RELOC_IQ2000_OFFSET_16
6468 BFD_RELOC_IQ2000_OFFSET_21
6470 BFD_RELOC_IQ2000_UHI16
6475 BFD_RELOC_XTENSA_RTLD
6477 Special Xtensa relocation used only by PLT entries in ELF shared
6478 objects to indicate that the runtime linker should set the value
6479 to one of its own internal functions or data structures.
6481 BFD_RELOC_XTENSA_GLOB_DAT
6483 BFD_RELOC_XTENSA_JMP_SLOT
6485 BFD_RELOC_XTENSA_RELATIVE
6487 Xtensa relocations for ELF shared objects.
6489 BFD_RELOC_XTENSA_PLT
6491 Xtensa relocation used in ELF object files for symbols that may require
6492 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6494 BFD_RELOC_XTENSA_DIFF8
6496 BFD_RELOC_XTENSA_DIFF16
6498 BFD_RELOC_XTENSA_DIFF32
6500 Xtensa relocations to mark the difference of two local symbols.
6501 These are only needed to support linker relaxation and can be ignored
6502 when not relaxing. The field is set to the value of the difference
6503 assuming no relaxation. The relocation encodes the position of the
6504 first symbol so the linker can determine whether to adjust the field
6507 BFD_RELOC_XTENSA_SLOT0_OP
6509 BFD_RELOC_XTENSA_SLOT1_OP
6511 BFD_RELOC_XTENSA_SLOT2_OP
6513 BFD_RELOC_XTENSA_SLOT3_OP
6515 BFD_RELOC_XTENSA_SLOT4_OP
6517 BFD_RELOC_XTENSA_SLOT5_OP
6519 BFD_RELOC_XTENSA_SLOT6_OP
6521 BFD_RELOC_XTENSA_SLOT7_OP
6523 BFD_RELOC_XTENSA_SLOT8_OP
6525 BFD_RELOC_XTENSA_SLOT9_OP
6527 BFD_RELOC_XTENSA_SLOT10_OP
6529 BFD_RELOC_XTENSA_SLOT11_OP
6531 BFD_RELOC_XTENSA_SLOT12_OP
6533 BFD_RELOC_XTENSA_SLOT13_OP
6535 BFD_RELOC_XTENSA_SLOT14_OP
6537 Generic Xtensa relocations for instruction operands. Only the slot
6538 number is encoded in the relocation. The relocation applies to the
6539 last PC-relative immediate operand, or if there are no PC-relative
6540 immediates, to the last immediate operand.
6542 BFD_RELOC_XTENSA_SLOT0_ALT
6544 BFD_RELOC_XTENSA_SLOT1_ALT
6546 BFD_RELOC_XTENSA_SLOT2_ALT
6548 BFD_RELOC_XTENSA_SLOT3_ALT
6550 BFD_RELOC_XTENSA_SLOT4_ALT
6552 BFD_RELOC_XTENSA_SLOT5_ALT
6554 BFD_RELOC_XTENSA_SLOT6_ALT
6556 BFD_RELOC_XTENSA_SLOT7_ALT
6558 BFD_RELOC_XTENSA_SLOT8_ALT
6560 BFD_RELOC_XTENSA_SLOT9_ALT
6562 BFD_RELOC_XTENSA_SLOT10_ALT
6564 BFD_RELOC_XTENSA_SLOT11_ALT
6566 BFD_RELOC_XTENSA_SLOT12_ALT
6568 BFD_RELOC_XTENSA_SLOT13_ALT
6570 BFD_RELOC_XTENSA_SLOT14_ALT
6572 Alternate Xtensa relocations. Only the slot is encoded in the
6573 relocation. The meaning of these relocations is opcode-specific.
6575 BFD_RELOC_XTENSA_OP0
6577 BFD_RELOC_XTENSA_OP1
6579 BFD_RELOC_XTENSA_OP2
6581 Xtensa relocations for backward compatibility. These have all been
6582 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6584 BFD_RELOC_XTENSA_ASM_EXPAND
6586 Xtensa relocation to mark that the assembler expanded the
6587 instructions from an original target. The expansion size is
6588 encoded in the reloc size.
6590 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6592 Xtensa relocation to mark that the linker should simplify
6593 assembler-expanded instructions. This is commonly used
6594 internally by the linker after analysis of a
6595 BFD_RELOC_XTENSA_ASM_EXPAND.
6597 BFD_RELOC_XTENSA_TLSDESC_FN
6599 BFD_RELOC_XTENSA_TLSDESC_ARG
6601 BFD_RELOC_XTENSA_TLS_DTPOFF
6603 BFD_RELOC_XTENSA_TLS_TPOFF
6605 BFD_RELOC_XTENSA_TLS_FUNC
6607 BFD_RELOC_XTENSA_TLS_ARG
6609 BFD_RELOC_XTENSA_TLS_CALL
6611 Xtensa TLS relocations.
6616 8 bit signed offset in (ix+d) or (iy+d).
6634 BFD_RELOC_LM32_BRANCH
6636 BFD_RELOC_LM32_16_GOT
6638 BFD_RELOC_LM32_GOTOFF_HI16
6640 BFD_RELOC_LM32_GOTOFF_LO16
6644 BFD_RELOC_LM32_GLOB_DAT
6646 BFD_RELOC_LM32_JMP_SLOT
6648 BFD_RELOC_LM32_RELATIVE
6650 Lattice Mico32 relocations.
6653 BFD_RELOC_MACH_O_SECTDIFF
6655 Difference between two section addreses. Must be followed by a
6656 BFD_RELOC_MACH_O_PAIR.
6658 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6660 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6662 BFD_RELOC_MACH_O_PAIR
6664 Pair of relocation. Contains the first symbol.
6666 BFD_RELOC_MACH_O_SUBTRACTOR32
6668 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6670 BFD_RELOC_MACH_O_SUBTRACTOR64
6672 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6675 BFD_RELOC_MACH_O_X86_64_BRANCH32
6677 BFD_RELOC_MACH_O_X86_64_BRANCH8
6679 PCREL relocations. They are marked as branch to create PLT entry if
6682 BFD_RELOC_MACH_O_X86_64_GOT
6684 Used when referencing a GOT entry.
6686 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6688 Used when loading a GOT entry with movq. It is specially marked so that
6689 the linker could optimize the movq to a leaq if possible.
6691 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6693 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6695 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6697 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6699 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6701 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6703 BFD_RELOC_MACH_O_X86_64_TLV
6705 Used when referencing a TLV entry.
6709 BFD_RELOC_MACH_O_ARM64_ADDEND
6711 Addend for PAGE or PAGEOFF.
6713 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6715 Relative offset to page of GOT slot.
6717 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6719 Relative offset within page of GOT slot.
6721 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6723 Address of a GOT entry.
6726 BFD_RELOC_MICROBLAZE_32_LO
6728 This is a 32 bit reloc for the microblaze that stores the
6729 low 16 bits of a value
6731 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6733 This is a 32 bit pc-relative reloc for the microblaze that
6734 stores the low 16 bits of a value
6736 BFD_RELOC_MICROBLAZE_32_ROSDA
6738 This is a 32 bit reloc for the microblaze that stores a
6739 value relative to the read-only small data area anchor
6741 BFD_RELOC_MICROBLAZE_32_RWSDA
6743 This is a 32 bit reloc for the microblaze that stores a
6744 value relative to the read-write small data area anchor
6746 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6748 This is a 32 bit reloc for the microblaze to handle
6749 expressions of the form "Symbol Op Symbol"
6751 BFD_RELOC_MICROBLAZE_64_NONE
6753 This is a 64 bit reloc that stores the 32 bit pc relative
6754 value in two words (with an imm instruction). No relocation is
6755 done here - only used for relaxing
6757 BFD_RELOC_MICROBLAZE_64_GOTPC
6759 This is a 64 bit reloc that stores the 32 bit pc relative
6760 value in two words (with an imm instruction). The relocation is
6761 PC-relative GOT offset
6763 BFD_RELOC_MICROBLAZE_64_GOT
6765 This is a 64 bit reloc that stores the 32 bit pc relative
6766 value in two words (with an imm instruction). The relocation is
6769 BFD_RELOC_MICROBLAZE_64_PLT
6771 This is a 64 bit reloc that stores the 32 bit pc relative
6772 value in two words (with an imm instruction). The relocation is
6773 PC-relative offset into PLT
6775 BFD_RELOC_MICROBLAZE_64_GOTOFF
6777 This is a 64 bit reloc that stores the 32 bit GOT relative
6778 value in two words (with an imm instruction). The relocation is
6779 relative offset from _GLOBAL_OFFSET_TABLE_
6781 BFD_RELOC_MICROBLAZE_32_GOTOFF
6783 This is a 32 bit reloc that stores the 32 bit GOT relative
6784 value in a word. The relocation is relative offset from
6785 _GLOBAL_OFFSET_TABLE_
6787 BFD_RELOC_MICROBLAZE_COPY
6789 This is used to tell the dynamic linker to copy the value out of
6790 the dynamic object into the runtime process image.
6792 BFD_RELOC_MICROBLAZE_64_TLS
6796 BFD_RELOC_MICROBLAZE_64_TLSGD
6798 This is a 64 bit reloc that stores the 32 bit GOT relative value
6799 of the GOT TLS GD info entry in two words (with an imm instruction). The
6800 relocation is GOT offset.
6802 BFD_RELOC_MICROBLAZE_64_TLSLD
6804 This is a 64 bit reloc that stores the 32 bit GOT relative value
6805 of the GOT TLS LD info entry in two words (with an imm instruction). The
6806 relocation is GOT offset.
6808 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6810 This is a 32 bit reloc that stores the Module ID to GOT(n).
6812 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6814 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6816 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6818 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6821 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6823 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6824 to two words (uses imm instruction).
6826 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6828 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6829 to two words (uses imm instruction).
6831 BFD_RELOC_MICROBLAZE_64_TEXTPCREL
6833 This is a 64 bit reloc that stores the 32 bit pc relative
6834 value in two words (with an imm instruction). The relocation is
6835 PC-relative offset from start of TEXT.
6837 BFD_RELOC_MICROBLAZE_64_TEXTREL
6839 This is a 64 bit reloc that stores the 32 bit offset
6840 value in two words (with an imm instruction). The relocation is
6841 relative offset from start of TEXT.
6844 BFD_RELOC_AARCH64_RELOC_START
6846 AArch64 pseudo relocation code to mark the start of the AArch64
6847 relocation enumerators. N.B. the order of the enumerators is
6848 important as several tables in the AArch64 bfd backend are indexed
6849 by these enumerators; make sure they are all synced.
6851 BFD_RELOC_AARCH64_NULL
6853 Deprecated AArch64 null relocation code.
6855 BFD_RELOC_AARCH64_NONE
6857 AArch64 null relocation code.
6859 BFD_RELOC_AARCH64_64
6861 BFD_RELOC_AARCH64_32
6863 BFD_RELOC_AARCH64_16
6865 Basic absolute relocations of N bits. These are equivalent to
6866 BFD_RELOC_N and they were added to assist the indexing of the howto
6869 BFD_RELOC_AARCH64_64_PCREL
6871 BFD_RELOC_AARCH64_32_PCREL
6873 BFD_RELOC_AARCH64_16_PCREL
6875 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6876 and they were added to assist the indexing of the howto table.
6878 BFD_RELOC_AARCH64_MOVW_G0
6880 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6881 of an unsigned address/value.
6883 BFD_RELOC_AARCH64_MOVW_G0_NC
6885 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6886 an address/value. No overflow checking.
6888 BFD_RELOC_AARCH64_MOVW_G1
6890 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
6891 of an unsigned address/value.
6893 BFD_RELOC_AARCH64_MOVW_G1_NC
6895 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
6896 of an address/value. No overflow checking.
6898 BFD_RELOC_AARCH64_MOVW_G2
6900 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
6901 of an unsigned address/value.
6903 BFD_RELOC_AARCH64_MOVW_G2_NC
6905 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
6906 of an address/value. No overflow checking.
6908 BFD_RELOC_AARCH64_MOVW_G3
6910 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
6911 of a signed or unsigned address/value.
6913 BFD_RELOC_AARCH64_MOVW_G0_S
6915 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6916 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6919 BFD_RELOC_AARCH64_MOVW_G1_S
6921 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
6922 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6925 BFD_RELOC_AARCH64_MOVW_G2_S
6927 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
6928 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6931 BFD_RELOC_AARCH64_MOVW_PREL_G0
6933 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6934 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6937 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
6939 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6940 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6943 BFD_RELOC_AARCH64_MOVW_PREL_G1
6945 AArch64 MOVK instruction with most significant bits 16 to 31
6948 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
6950 AArch64 MOVK instruction with most significant bits 16 to 31
6953 BFD_RELOC_AARCH64_MOVW_PREL_G2
6955 AArch64 MOVK instruction with most significant bits 32 to 47
6958 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
6960 AArch64 MOVK instruction with most significant bits 32 to 47
6963 BFD_RELOC_AARCH64_MOVW_PREL_G3
6965 AArch64 MOVK instruction with most significant bits 47 to 63
6968 BFD_RELOC_AARCH64_LD_LO19_PCREL
6970 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
6971 offset. The lowest two bits must be zero and are not stored in the
6972 instruction, giving a 21 bit signed byte offset.
6974 BFD_RELOC_AARCH64_ADR_LO21_PCREL
6976 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
6978 BFD_RELOC_AARCH64_ADR_HI21_PCREL
6980 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6981 offset, giving a 4KB aligned page base address.
6983 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
6985 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6986 offset, giving a 4KB aligned page base address, but with no overflow
6989 BFD_RELOC_AARCH64_ADD_LO12
6991 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
6992 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6994 BFD_RELOC_AARCH64_LDST8_LO12
6996 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
6997 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6999 BFD_RELOC_AARCH64_TSTBR14
7001 AArch64 14 bit pc-relative test bit and branch.
7002 The lowest two bits must be zero and are not stored in the instruction,
7003 giving a 16 bit signed byte offset.
7005 BFD_RELOC_AARCH64_BRANCH19
7007 AArch64 19 bit pc-relative conditional branch and compare & branch.
7008 The lowest two bits must be zero and are not stored in the instruction,
7009 giving a 21 bit signed byte offset.
7011 BFD_RELOC_AARCH64_JUMP26
7013 AArch64 26 bit pc-relative unconditional branch.
7014 The lowest two bits must be zero and are not stored in the instruction,
7015 giving a 28 bit signed byte offset.
7017 BFD_RELOC_AARCH64_CALL26
7019 AArch64 26 bit pc-relative unconditional branch and link.
7020 The lowest two bits must be zero and are not stored in the instruction,
7021 giving a 28 bit signed byte offset.
7023 BFD_RELOC_AARCH64_LDST16_LO12
7025 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7026 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7028 BFD_RELOC_AARCH64_LDST32_LO12
7030 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7031 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7033 BFD_RELOC_AARCH64_LDST64_LO12
7035 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7036 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7038 BFD_RELOC_AARCH64_LDST128_LO12
7040 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7041 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7043 BFD_RELOC_AARCH64_GOT_LD_PREL19
7045 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7046 offset of the global offset table entry for a symbol. The lowest two
7047 bits must be zero and are not stored in the instruction, giving a 21
7048 bit signed byte offset. This relocation type requires signed overflow
7051 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7053 Get to the page base of the global offset table entry for a symbol as
7054 part of an ADRP instruction using a 21 bit PC relative value.Used in
7055 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7057 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7059 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7060 the GOT entry for this symbol. Used in conjunction with
7061 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
7063 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7065 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7066 the GOT entry for this symbol. Used in conjunction with
7067 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
7069 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7071 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7072 for this symbol. Valid in LP64 ABI only.
7074 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7076 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7077 for this symbol. Valid in LP64 ABI only.
7079 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7081 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7082 the GOT entry for this symbol. Valid in LP64 ABI only.
7084 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7086 Scaled 14 bit byte offset to the page base of the global offset table.
7088 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7090 Scaled 15 bit byte offset to the page base of the global offset table.
7092 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7094 Get to the page base of the global offset table entry for a symbols
7095 tls_index structure as part of an adrp instruction using a 21 bit PC
7096 relative value. Used in conjunction with
7097 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7099 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7101 AArch64 TLS General Dynamic
7103 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7105 Unsigned 12 bit byte offset to global offset table entry for a symbols
7106 tls_index structure. Used in conjunction with
7107 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7109 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7111 AArch64 TLS General Dynamic relocation.
7113 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7115 AArch64 TLS General Dynamic relocation.
7117 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7119 AArch64 TLS INITIAL EXEC relocation.
7121 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7123 AArch64 TLS INITIAL EXEC relocation.
7125 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7127 AArch64 TLS INITIAL EXEC relocation.
7129 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7131 AArch64 TLS INITIAL EXEC relocation.
7133 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7135 AArch64 TLS INITIAL EXEC relocation.
7137 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7139 AArch64 TLS INITIAL EXEC relocation.
7141 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7143 bit[23:12] of byte offset to module TLS base address.
7145 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7147 Unsigned 12 bit byte offset to module TLS base address.
7149 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7151 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7153 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7155 Unsigned 12 bit byte offset to global offset table entry for a symbols
7156 tls_index structure. Used in conjunction with
7157 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7159 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7161 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7164 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7166 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7168 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7170 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7173 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7175 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7177 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7179 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7182 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7184 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7186 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7188 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7191 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7193 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7195 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7197 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7200 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7202 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7204 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7206 bit[15:0] of byte offset to module TLS base address.
7208 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7210 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7212 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7214 bit[31:16] of byte offset to module TLS base address.
7216 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7218 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7220 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7222 bit[47:32] of byte offset to module TLS base address.
7224 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7226 AArch64 TLS LOCAL EXEC relocation.
7228 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7230 AArch64 TLS LOCAL EXEC relocation.
7232 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7234 AArch64 TLS LOCAL EXEC relocation.
7236 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7238 AArch64 TLS LOCAL EXEC relocation.
7240 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7242 AArch64 TLS LOCAL EXEC relocation.
7244 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7246 AArch64 TLS LOCAL EXEC relocation.
7248 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7250 AArch64 TLS LOCAL EXEC relocation.
7252 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7254 AArch64 TLS LOCAL EXEC relocation.
7256 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
7258 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7261 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
7263 Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check.
7265 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
7267 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7270 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
7272 Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check.
7274 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
7276 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7279 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
7281 Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check.
7283 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
7285 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7288 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
7290 Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check.
7292 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7294 AArch64 TLS DESC relocation.
7296 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7298 AArch64 TLS DESC relocation.
7300 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7302 AArch64 TLS DESC relocation.
7304 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7306 AArch64 TLS DESC relocation.
7308 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7310 AArch64 TLS DESC relocation.
7312 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7314 AArch64 TLS DESC relocation.
7316 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7318 AArch64 TLS DESC relocation.
7320 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7322 AArch64 TLS DESC relocation.
7324 BFD_RELOC_AARCH64_TLSDESC_LDR
7326 AArch64 TLS DESC relocation.
7328 BFD_RELOC_AARCH64_TLSDESC_ADD
7330 AArch64 TLS DESC relocation.
7332 BFD_RELOC_AARCH64_TLSDESC_CALL
7334 AArch64 TLS DESC relocation.
7336 BFD_RELOC_AARCH64_COPY
7338 AArch64 TLS relocation.
7340 BFD_RELOC_AARCH64_GLOB_DAT
7342 AArch64 TLS relocation.
7344 BFD_RELOC_AARCH64_JUMP_SLOT
7346 AArch64 TLS relocation.
7348 BFD_RELOC_AARCH64_RELATIVE
7350 AArch64 TLS relocation.
7352 BFD_RELOC_AARCH64_TLS_DTPMOD
7354 AArch64 TLS relocation.
7356 BFD_RELOC_AARCH64_TLS_DTPREL
7358 AArch64 TLS relocation.
7360 BFD_RELOC_AARCH64_TLS_TPREL
7362 AArch64 TLS relocation.
7364 BFD_RELOC_AARCH64_TLSDESC
7366 AArch64 TLS relocation.
7368 BFD_RELOC_AARCH64_IRELATIVE
7370 AArch64 support for STT_GNU_IFUNC.
7372 BFD_RELOC_AARCH64_RELOC_END
7374 AArch64 pseudo relocation code to mark the end of the AArch64
7375 relocation enumerators that have direct mapping to ELF reloc codes.
7376 There are a few more enumerators after this one; those are mainly
7377 used by the AArch64 assembler for the internal fixup or to select
7378 one of the above enumerators.
7380 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7382 AArch64 pseudo relocation code to be used internally by the AArch64
7383 assembler and not (currently) written to any object files.
7385 BFD_RELOC_AARCH64_LDST_LO12
7387 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7388 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7390 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7392 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7393 used internally by the AArch64 assembler and not (currently) written to
7396 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7398 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7400 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
7402 AArch64 pseudo relocation code for TLS local exec mode. It's to be
7403 used internally by the AArch64 assembler and not (currently) written to
7406 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
7408 Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check.
7410 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7412 AArch64 pseudo relocation code to be used internally by the AArch64
7413 assembler and not (currently) written to any object files.
7415 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7417 AArch64 pseudo relocation code to be used internally by the AArch64
7418 assembler and not (currently) written to any object files.
7420 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7422 AArch64 pseudo relocation code to be used internally by the AArch64
7423 assembler and not (currently) written to any object files.
7425 BFD_RELOC_TILEPRO_COPY
7427 BFD_RELOC_TILEPRO_GLOB_DAT
7429 BFD_RELOC_TILEPRO_JMP_SLOT
7431 BFD_RELOC_TILEPRO_RELATIVE
7433 BFD_RELOC_TILEPRO_BROFF_X1
7435 BFD_RELOC_TILEPRO_JOFFLONG_X1
7437 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7439 BFD_RELOC_TILEPRO_IMM8_X0
7441 BFD_RELOC_TILEPRO_IMM8_Y0
7443 BFD_RELOC_TILEPRO_IMM8_X1
7445 BFD_RELOC_TILEPRO_IMM8_Y1
7447 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7449 BFD_RELOC_TILEPRO_MT_IMM15_X1
7451 BFD_RELOC_TILEPRO_MF_IMM15_X1
7453 BFD_RELOC_TILEPRO_IMM16_X0
7455 BFD_RELOC_TILEPRO_IMM16_X1
7457 BFD_RELOC_TILEPRO_IMM16_X0_LO
7459 BFD_RELOC_TILEPRO_IMM16_X1_LO
7461 BFD_RELOC_TILEPRO_IMM16_X0_HI
7463 BFD_RELOC_TILEPRO_IMM16_X1_HI
7465 BFD_RELOC_TILEPRO_IMM16_X0_HA
7467 BFD_RELOC_TILEPRO_IMM16_X1_HA
7469 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7471 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7473 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7475 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7477 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7479 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7481 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7483 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7485 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7487 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7489 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7491 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7493 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7495 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7497 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7499 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7501 BFD_RELOC_TILEPRO_MMSTART_X0
7503 BFD_RELOC_TILEPRO_MMEND_X0
7505 BFD_RELOC_TILEPRO_MMSTART_X1
7507 BFD_RELOC_TILEPRO_MMEND_X1
7509 BFD_RELOC_TILEPRO_SHAMT_X0
7511 BFD_RELOC_TILEPRO_SHAMT_X1
7513 BFD_RELOC_TILEPRO_SHAMT_Y0
7515 BFD_RELOC_TILEPRO_SHAMT_Y1
7517 BFD_RELOC_TILEPRO_TLS_GD_CALL
7519 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7521 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7523 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7525 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7527 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7529 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7531 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7533 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7535 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7537 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7539 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7541 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7543 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7545 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7547 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7549 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7551 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7553 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7555 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7557 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7559 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7561 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7563 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7565 BFD_RELOC_TILEPRO_TLS_TPOFF32
7567 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7569 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7571 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7573 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7575 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7577 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7579 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7581 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7583 Tilera TILEPro Relocations.
7585 BFD_RELOC_TILEGX_HW0
7587 BFD_RELOC_TILEGX_HW1
7589 BFD_RELOC_TILEGX_HW2
7591 BFD_RELOC_TILEGX_HW3
7593 BFD_RELOC_TILEGX_HW0_LAST
7595 BFD_RELOC_TILEGX_HW1_LAST
7597 BFD_RELOC_TILEGX_HW2_LAST
7599 BFD_RELOC_TILEGX_COPY
7601 BFD_RELOC_TILEGX_GLOB_DAT
7603 BFD_RELOC_TILEGX_JMP_SLOT
7605 BFD_RELOC_TILEGX_RELATIVE
7607 BFD_RELOC_TILEGX_BROFF_X1
7609 BFD_RELOC_TILEGX_JUMPOFF_X1
7611 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7613 BFD_RELOC_TILEGX_IMM8_X0
7615 BFD_RELOC_TILEGX_IMM8_Y0
7617 BFD_RELOC_TILEGX_IMM8_X1
7619 BFD_RELOC_TILEGX_IMM8_Y1
7621 BFD_RELOC_TILEGX_DEST_IMM8_X1
7623 BFD_RELOC_TILEGX_MT_IMM14_X1
7625 BFD_RELOC_TILEGX_MF_IMM14_X1
7627 BFD_RELOC_TILEGX_MMSTART_X0
7629 BFD_RELOC_TILEGX_MMEND_X0
7631 BFD_RELOC_TILEGX_SHAMT_X0
7633 BFD_RELOC_TILEGX_SHAMT_X1
7635 BFD_RELOC_TILEGX_SHAMT_Y0
7637 BFD_RELOC_TILEGX_SHAMT_Y1
7639 BFD_RELOC_TILEGX_IMM16_X0_HW0
7641 BFD_RELOC_TILEGX_IMM16_X1_HW0
7643 BFD_RELOC_TILEGX_IMM16_X0_HW1
7645 BFD_RELOC_TILEGX_IMM16_X1_HW1
7647 BFD_RELOC_TILEGX_IMM16_X0_HW2
7649 BFD_RELOC_TILEGX_IMM16_X1_HW2
7651 BFD_RELOC_TILEGX_IMM16_X0_HW3
7653 BFD_RELOC_TILEGX_IMM16_X1_HW3
7655 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7657 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7659 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7661 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7663 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7665 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7667 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7669 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7671 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7673 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7675 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7677 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7679 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7681 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7683 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7685 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7687 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7689 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7691 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7693 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7695 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7697 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7699 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7701 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7703 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7705 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7707 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7709 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7711 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7713 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7715 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7717 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7719 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7721 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7723 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7725 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7727 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7729 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7731 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7733 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7735 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7737 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7739 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7741 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7743 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7745 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7747 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7749 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7751 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7753 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7755 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7757 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7759 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7761 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7763 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7765 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7767 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7769 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7771 BFD_RELOC_TILEGX_TLS_DTPMOD64
7773 BFD_RELOC_TILEGX_TLS_DTPOFF64
7775 BFD_RELOC_TILEGX_TLS_TPOFF64
7777 BFD_RELOC_TILEGX_TLS_DTPMOD32
7779 BFD_RELOC_TILEGX_TLS_DTPOFF32
7781 BFD_RELOC_TILEGX_TLS_TPOFF32
7783 BFD_RELOC_TILEGX_TLS_GD_CALL
7785 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7787 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7789 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7791 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7793 BFD_RELOC_TILEGX_TLS_IE_LOAD
7795 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7797 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7799 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7801 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7803 Tilera TILE-Gx Relocations.
7806 BFD_RELOC_EPIPHANY_SIMM8
7808 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7810 BFD_RELOC_EPIPHANY_SIMM24
7812 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7814 BFD_RELOC_EPIPHANY_HIGH
7816 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7818 BFD_RELOC_EPIPHANY_LOW
7820 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7822 BFD_RELOC_EPIPHANY_SIMM11
7824 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7826 BFD_RELOC_EPIPHANY_IMM11
7828 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7830 BFD_RELOC_EPIPHANY_IMM8
7832 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7835 BFD_RELOC_VISIUM_HI16
7837 BFD_RELOC_VISIUM_LO16
7839 BFD_RELOC_VISIUM_IM16
7841 BFD_RELOC_VISIUM_REL16
7843 BFD_RELOC_VISIUM_HI16_PCREL
7845 BFD_RELOC_VISIUM_LO16_PCREL
7847 BFD_RELOC_VISIUM_IM16_PCREL
7852 BFD_RELOC_WASM32_LEB128
7854 BFD_RELOC_WASM32_LEB128_GOT
7856 BFD_RELOC_WASM32_LEB128_GOT_CODE
7858 BFD_RELOC_WASM32_LEB128_PLT
7860 BFD_RELOC_WASM32_PLT_INDEX
7862 BFD_RELOC_WASM32_ABS32_CODE
7864 BFD_RELOC_WASM32_COPY
7866 BFD_RELOC_WASM32_CODE_POINTER
7868 BFD_RELOC_WASM32_INDEX
7870 BFD_RELOC_WASM32_PLT_SIG
7872 WebAssembly relocations.
7875 BFD_RELOC_CKCORE_NONE
7877 BFD_RELOC_CKCORE_ADDR32
7879 BFD_RELOC_CKCORE_PCREL_IMM8BY4
7881 BFD_RELOC_CKCORE_PCREL_IMM11BY2
7883 BFD_RELOC_CKCORE_PCREL_IMM4BY2
7885 BFD_RELOC_CKCORE_PCREL32
7887 BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2
7889 BFD_RELOC_CKCORE_GNU_VTINHERIT
7891 BFD_RELOC_CKCORE_GNU_VTENTRY
7893 BFD_RELOC_CKCORE_RELATIVE
7895 BFD_RELOC_CKCORE_COPY
7897 BFD_RELOC_CKCORE_GLOB_DAT
7899 BFD_RELOC_CKCORE_JUMP_SLOT
7901 BFD_RELOC_CKCORE_GOTOFF
7903 BFD_RELOC_CKCORE_GOTPC
7905 BFD_RELOC_CKCORE_GOT32
7907 BFD_RELOC_CKCORE_PLT32
7909 BFD_RELOC_CKCORE_ADDRGOT
7911 BFD_RELOC_CKCORE_ADDRPLT
7913 BFD_RELOC_CKCORE_PCREL_IMM26BY2
7915 BFD_RELOC_CKCORE_PCREL_IMM16BY2
7917 BFD_RELOC_CKCORE_PCREL_IMM16BY4
7919 BFD_RELOC_CKCORE_PCREL_IMM10BY2
7921 BFD_RELOC_CKCORE_PCREL_IMM10BY4
7923 BFD_RELOC_CKCORE_ADDR_HI16
7925 BFD_RELOC_CKCORE_ADDR_LO16
7927 BFD_RELOC_CKCORE_GOTPC_HI16
7929 BFD_RELOC_CKCORE_GOTPC_LO16
7931 BFD_RELOC_CKCORE_GOTOFF_HI16
7933 BFD_RELOC_CKCORE_GOTOFF_LO16
7935 BFD_RELOC_CKCORE_GOT12
7937 BFD_RELOC_CKCORE_GOT_HI16
7939 BFD_RELOC_CKCORE_GOT_LO16
7941 BFD_RELOC_CKCORE_PLT12
7943 BFD_RELOC_CKCORE_PLT_HI16
7945 BFD_RELOC_CKCORE_PLT_LO16
7947 BFD_RELOC_CKCORE_ADDRGOT_HI16
7949 BFD_RELOC_CKCORE_ADDRGOT_LO16
7951 BFD_RELOC_CKCORE_ADDRPLT_HI16
7953 BFD_RELOC_CKCORE_ADDRPLT_LO16
7955 BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2
7957 BFD_RELOC_CKCORE_TOFFSET_LO16
7959 BFD_RELOC_CKCORE_DOFFSET_LO16
7961 BFD_RELOC_CKCORE_PCREL_IMM18BY2
7963 BFD_RELOC_CKCORE_DOFFSET_IMM18
7965 BFD_RELOC_CKCORE_DOFFSET_IMM18BY2
7967 BFD_RELOC_CKCORE_DOFFSET_IMM18BY4
7969 BFD_RELOC_CKCORE_GOTOFF_IMM18
7971 BFD_RELOC_CKCORE_GOT_IMM18BY4
7973 BFD_RELOC_CKCORE_PLT_IMM18BY4
7975 BFD_RELOC_CKCORE_PCREL_IMM7BY4
7977 BFD_RELOC_CKCORE_TLS_LE32
7979 BFD_RELOC_CKCORE_TLS_IE32
7981 BFD_RELOC_CKCORE_TLS_GD32
7983 BFD_RELOC_CKCORE_TLS_LDM32
7985 BFD_RELOC_CKCORE_TLS_LDO32
7987 BFD_RELOC_CKCORE_TLS_DTPMOD32
7989 BFD_RELOC_CKCORE_TLS_DTPOFF32
7991 BFD_RELOC_CKCORE_TLS_TPOFF32
7993 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4
7995 BFD_RELOC_CKCORE_NOJSRI
7997 BFD_RELOC_CKCORE_CALLGRAPH
7999 BFD_RELOC_CKCORE_IRELATIVE
8001 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4
8003 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4
8011 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
8016 bfd_reloc_type_lookup
8017 bfd_reloc_name_lookup
8020 reloc_howto_type *bfd_reloc_type_lookup
8021 (bfd *abfd, bfd_reloc_code_real_type code);
8022 reloc_howto_type *bfd_reloc_name_lookup
8023 (bfd *abfd, const char *reloc_name);
8026 Return a pointer to a howto structure which, when
8027 invoked, will perform the relocation @var{code} on data from the
8033 bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
8035 return BFD_SEND (abfd, reloc_type_lookup, (abfd, code));
8039 bfd_reloc_name_lookup (bfd *abfd, const char *reloc_name)
8041 return BFD_SEND (abfd, reloc_name_lookup, (abfd, reloc_name));
8044 static reloc_howto_type bfd_howto_32 =
8045 HOWTO (0, 00, 2, 32, FALSE, 0, complain_overflow_dont, 0, "VRT32", FALSE, 0xffffffff, 0xffffffff, TRUE);
8049 bfd_default_reloc_type_lookup
8052 reloc_howto_type *bfd_default_reloc_type_lookup
8053 (bfd *abfd, bfd_reloc_code_real_type code);
8056 Provides a default relocation lookup routine for any architecture.
8061 bfd_default_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
8065 case BFD_RELOC_CTOR:
8066 /* The type of reloc used in a ctor, which will be as wide as the
8067 address - so either a 64, 32, or 16 bitter. */
8068 switch (bfd_arch_bits_per_address (abfd))
8074 return &bfd_howto_32;
8090 bfd_get_reloc_code_name
8093 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
8096 Provides a printable name for the supplied relocation code.
8097 Useful mainly for printing error messages.
8101 bfd_get_reloc_code_name (bfd_reloc_code_real_type code)
8103 if (code > BFD_RELOC_UNUSED)
8105 return bfd_reloc_code_real_names[code];
8110 bfd_generic_relax_section
8113 bfd_boolean bfd_generic_relax_section
8116 struct bfd_link_info *,
8120 Provides default handling for relaxing for back ends which
8125 bfd_generic_relax_section (bfd *abfd ATTRIBUTE_UNUSED,
8126 asection *section ATTRIBUTE_UNUSED,
8127 struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
8130 if (bfd_link_relocatable (link_info))
8131 (*link_info->callbacks->einfo)
8132 (_("%P%F: --relax and -r may not be used together\n"));
8140 bfd_generic_gc_sections
8143 bfd_boolean bfd_generic_gc_sections
8144 (bfd *, struct bfd_link_info *);
8147 Provides default handling for relaxing for back ends which
8148 don't do section gc -- i.e., does nothing.
8152 bfd_generic_gc_sections (bfd *abfd ATTRIBUTE_UNUSED,
8153 struct bfd_link_info *info ATTRIBUTE_UNUSED)
8160 bfd_generic_lookup_section_flags
8163 bfd_boolean bfd_generic_lookup_section_flags
8164 (struct bfd_link_info *, struct flag_info *, asection *);
8167 Provides default handling for section flags lookup
8168 -- i.e., does nothing.
8169 Returns FALSE if the section should be omitted, otherwise TRUE.
8173 bfd_generic_lookup_section_flags (struct bfd_link_info *info ATTRIBUTE_UNUSED,
8174 struct flag_info *flaginfo,
8175 asection *section ATTRIBUTE_UNUSED)
8177 if (flaginfo != NULL)
8179 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported"));
8187 bfd_generic_merge_sections
8190 bfd_boolean bfd_generic_merge_sections
8191 (bfd *, struct bfd_link_info *);
8194 Provides default handling for SEC_MERGE section merging for back ends
8195 which don't have SEC_MERGE support -- i.e., does nothing.
8199 bfd_generic_merge_sections (bfd *abfd ATTRIBUTE_UNUSED,
8200 struct bfd_link_info *link_info ATTRIBUTE_UNUSED)
8207 bfd_generic_get_relocated_section_contents
8210 bfd_byte *bfd_generic_get_relocated_section_contents
8212 struct bfd_link_info *link_info,
8213 struct bfd_link_order *link_order,
8215 bfd_boolean relocatable,
8219 Provides default handling of relocation effort for back ends
8220 which can't be bothered to do it efficiently.
8225 bfd_generic_get_relocated_section_contents (bfd *abfd,
8226 struct bfd_link_info *link_info,
8227 struct bfd_link_order *link_order,
8229 bfd_boolean relocatable,
8232 bfd *input_bfd = link_order->u.indirect.section->owner;
8233 asection *input_section = link_order->u.indirect.section;
8235 arelent **reloc_vector;
8238 reloc_size = bfd_get_reloc_upper_bound (input_bfd, input_section);
8242 /* Read in the section. */
8243 if (!bfd_get_full_section_contents (input_bfd, input_section, &data))
8249 if (reloc_size == 0)
8252 reloc_vector = (arelent **) bfd_malloc (reloc_size);
8253 if (reloc_vector == NULL)
8256 reloc_count = bfd_canonicalize_reloc (input_bfd,
8260 if (reloc_count < 0)
8263 if (reloc_count > 0)
8267 for (parent = reloc_vector; *parent != NULL; parent++)
8269 char *error_message = NULL;
8271 bfd_reloc_status_type r;
8273 symbol = *(*parent)->sym_ptr_ptr;
8274 /* PR ld/19628: A specially crafted input file
8275 can result in a NULL symbol pointer here. */
8278 link_info->callbacks->einfo
8279 /* xgettext:c-format */
8280 (_("%X%P: %pB(%pA): error: relocation for offset %V has no value\n"),
8281 abfd, input_section, (* parent)->address);
8285 if (symbol->section && discarded_section (symbol->section))
8288 static reloc_howto_type none_howto
8289 = HOWTO (0, 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL,
8290 "unused", FALSE, 0, 0, FALSE);
8292 p = data + (*parent)->address * bfd_octets_per_byte (input_bfd);
8293 _bfd_clear_contents ((*parent)->howto, input_bfd, input_section,
8295 (*parent)->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
8296 (*parent)->addend = 0;
8297 (*parent)->howto = &none_howto;
8301 r = bfd_perform_relocation (input_bfd,
8305 relocatable ? abfd : NULL,
8310 asection *os = input_section->output_section;
8312 /* A partial link, so keep the relocs. */
8313 os->orelocation[os->reloc_count] = *parent;
8317 if (r != bfd_reloc_ok)
8321 case bfd_reloc_undefined:
8322 (*link_info->callbacks->undefined_symbol)
8323 (link_info, bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
8324 input_bfd, input_section, (*parent)->address, TRUE);
8326 case bfd_reloc_dangerous:
8327 BFD_ASSERT (error_message != NULL);
8328 (*link_info->callbacks->reloc_dangerous)
8329 (link_info, error_message,
8330 input_bfd, input_section, (*parent)->address);
8332 case bfd_reloc_overflow:
8333 (*link_info->callbacks->reloc_overflow)
8335 bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
8336 (*parent)->howto->name, (*parent)->addend,
8337 input_bfd, input_section, (*parent)->address);
8339 case bfd_reloc_outofrange:
8341 This error can result when processing some partially
8342 complete binaries. Do not abort, but issue an error
8344 link_info->callbacks->einfo
8345 /* xgettext:c-format */
8346 (_("%X%P: %pB(%pA): relocation \"%pR\" goes out of range\n"),
8347 abfd, input_section, * parent);
8350 case bfd_reloc_notsupported:
8352 This error can result when processing a corrupt binary.
8353 Do not abort. Issue an error message instead. */
8354 link_info->callbacks->einfo
8355 /* xgettext:c-format */
8356 (_("%X%P: %pB(%pA): relocation \"%pR\" is not supported\n"),
8357 abfd, input_section, * parent);
8361 /* PR 17512; file: 90c2a92e.
8362 Report unexpected results, without aborting. */
8363 link_info->callbacks->einfo
8364 /* xgettext:c-format */
8365 (_("%X%P: %pB(%pA): relocation \"%pR\" returns an unrecognized value %x\n"),
8366 abfd, input_section, * parent, r);
8374 free (reloc_vector);
8378 free (reloc_vector);
8384 _bfd_generic_set_reloc
8387 void _bfd_generic_set_reloc
8391 unsigned int count);
8394 Installs a new set of internal relocations in SECTION.
8398 _bfd_generic_set_reloc (bfd *abfd ATTRIBUTE_UNUSED,
8403 section->orelocation = relptr;
8404 section->reloc_count = count;
8409 _bfd_unrecognized_reloc
8412 bfd_boolean _bfd_unrecognized_reloc
8415 unsigned int r_type);
8418 Reports an unrecognized reloc.
8419 Written as a function in order to reduce code duplication.
8420 Returns FALSE so that it can be called from a return statement.
8424 _bfd_unrecognized_reloc (bfd * abfd, sec_ptr section, unsigned int r_type)
8426 /* xgettext:c-format */
8427 _bfd_error_handler (_("%pB: unrecognized relocation type %#x in section `%pA'"),
8428 abfd, r_type, section);
8430 /* PR 21803: Suggest the most likely cause of this error. */
8431 _bfd_error_handler (_("is this version of the linker - %s - out of date ?"),
8432 BFD_VERSION_STRING);
8434 bfd_set_error (bfd_error_bad_value);
8439 _bfd_norelocs_bfd_reloc_type_lookup
8441 bfd_reloc_code_real_type code ATTRIBUTE_UNUSED)
8443 return (reloc_howto_type *) _bfd_ptr_bfd_null_error (abfd);
8447 _bfd_norelocs_bfd_reloc_name_lookup (bfd *abfd,
8448 const char *reloc_name ATTRIBUTE_UNUSED)
8450 return (reloc_howto_type *) _bfd_ptr_bfd_null_error (abfd);
8454 _bfd_nodynamic_canonicalize_dynamic_reloc (bfd *abfd,
8455 arelent **relp ATTRIBUTE_UNUSED,
8456 asymbol **symp ATTRIBUTE_UNUSED)
8458 return _bfd_long_bfd_n1_error (abfd);