1 /* BFD support for handling relocation entries.
2 Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
6 Written by Cygnus Support.
8 This file is part of BFD, the Binary File Descriptor library.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
23 MA 02110-1301, USA. */
29 BFD maintains relocations in much the same way it maintains
30 symbols: they are left alone until required, then read in
31 en-masse and translated into an internal form. A common
32 routine <<bfd_perform_relocation>> acts upon the
33 canonical form to do the fixup.
35 Relocations are maintained on a per section basis,
36 while symbols are maintained on a per BFD basis.
38 All that a back end has to do to fit the BFD interface is to create
39 a <<struct reloc_cache_entry>> for each relocation
40 in a particular section, and fill in the right bits of the structures.
49 /* DO compile in the reloc_code name table from libbfd.h. */
50 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
59 typedef arelent, howto manager, Relocations, Relocations
64 This is the structure of a relocation entry:
68 .typedef enum bfd_reloc_status
70 . {* No errors detected. *}
73 . {* The relocation was performed, but there was an overflow. *}
76 . {* The address to relocate was not within the section supplied. *}
77 . bfd_reloc_outofrange,
79 . {* Used by special functions. *}
82 . {* Unsupported relocation size requested. *}
83 . bfd_reloc_notsupported,
88 . {* The symbol to relocate against was undefined. *}
89 . bfd_reloc_undefined,
91 . {* The relocation was performed, but may not be ok - presently
92 . generated only when linking i960 coff files with i960 b.out
93 . symbols. If this type is returned, the error_message argument
94 . to bfd_perform_relocation will be set. *}
97 . bfd_reloc_status_type;
100 .typedef struct reloc_cache_entry
102 . {* A pointer into the canonical table of pointers. *}
103 . struct bfd_symbol **sym_ptr_ptr;
105 . {* offset in section. *}
106 . bfd_size_type address;
108 . {* addend for relocation value. *}
111 . {* Pointer to how to perform the required relocation. *}
112 . reloc_howto_type *howto;
122 Here is a description of each of the fields within an <<arelent>>:
126 The symbol table pointer points to a pointer to the symbol
127 associated with the relocation request. It is the pointer
128 into the table returned by the back end's
129 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
130 referenced through a pointer to a pointer so that tools like
131 the linker can fix up all the symbols of the same name by
132 modifying only one pointer. The relocation routine looks in
133 the symbol and uses the base of the section the symbol is
134 attached to and the value of the symbol as the initial
135 relocation offset. If the symbol pointer is zero, then the
136 section provided is looked up.
140 The <<address>> field gives the offset in bytes from the base of
141 the section data which owns the relocation record to the first
142 byte of relocatable information. The actual data relocated
143 will be relative to this point; for example, a relocation
144 type which modifies the bottom two bytes of a four byte word
145 would not touch the first byte pointed to in a big endian
150 The <<addend>> is a value provided by the back end to be added (!)
151 to the relocation offset. Its interpretation is dependent upon
152 the howto. For example, on the 68k the code:
157 | return foo[0x12345678];
160 Could be compiled into:
163 | moveb @@#12345678,d0
168 This could create a reloc pointing to <<foo>>, but leave the
169 offset in the data, something like:
171 |RELOCATION RECORDS FOR [.text]:
175 |00000000 4e56 fffc ; linkw fp,#-4
176 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
177 |0000000a 49c0 ; extbl d0
178 |0000000c 4e5e ; unlk fp
181 Using coff and an 88k, some instructions don't have enough
182 space in them to represent the full address range, and
183 pointers have to be loaded in two parts. So you'd get something like:
185 | or.u r13,r0,hi16(_foo+0x12345678)
186 | ld.b r2,r13,lo16(_foo+0x12345678)
189 This should create two relocs, both pointing to <<_foo>>, and with
190 0x12340000 in their addend field. The data would consist of:
192 |RELOCATION RECORDS FOR [.text]:
194 |00000002 HVRT16 _foo+0x12340000
195 |00000006 LVRT16 _foo+0x12340000
197 |00000000 5da05678 ; or.u r13,r0,0x5678
198 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
199 |00000008 f400c001 ; jmp r1
201 The relocation routine digs out the value from the data, adds
202 it to the addend to get the original offset, and then adds the
203 value of <<_foo>>. Note that all 32 bits have to be kept around
204 somewhere, to cope with carry from bit 15 to bit 16.
206 One further example is the sparc and the a.out format. The
207 sparc has a similar problem to the 88k, in that some
208 instructions don't have room for an entire offset, but on the
209 sparc the parts are created in odd sized lumps. The designers of
210 the a.out format chose to not use the data within the section
211 for storing part of the offset; all the offset is kept within
212 the reloc. Anything in the data should be ignored.
215 | sethi %hi(_foo+0x12345678),%g2
216 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
220 Both relocs contain a pointer to <<foo>>, and the offsets
223 |RELOCATION RECORDS FOR [.text]:
225 |00000004 HI22 _foo+0x12345678
226 |00000008 LO10 _foo+0x12345678
228 |00000000 9de3bf90 ; save %sp,-112,%sp
229 |00000004 05000000 ; sethi %hi(_foo+0),%g2
230 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
231 |0000000c 81c7e008 ; ret
232 |00000010 81e80000 ; restore
236 The <<howto>> field can be imagined as a
237 relocation instruction. It is a pointer to a structure which
238 contains information on what to do with all of the other
239 information in the reloc record and data section. A back end
240 would normally have a relocation instruction set and turn
241 relocations into pointers to the correct structure on input -
242 but it would be possible to create each howto field on demand.
248 <<enum complain_overflow>>
250 Indicates what sort of overflow checking should be done when
251 performing a relocation.
255 .enum complain_overflow
257 . {* Do not complain on overflow. *}
258 . complain_overflow_dont,
260 . {* Complain if the value overflows when considered as a signed
261 . number one bit larger than the field. ie. A bitfield of N bits
262 . is allowed to represent -2**n to 2**n-1. *}
263 . complain_overflow_bitfield,
265 . {* Complain if the value overflows when considered as a signed
267 . complain_overflow_signed,
269 . {* Complain if the value overflows when considered as an
270 . unsigned number. *}
271 . complain_overflow_unsigned
280 The <<reloc_howto_type>> is a structure which contains all the
281 information that libbfd needs to know to tie up a back end's data.
284 .struct bfd_symbol; {* Forward declaration. *}
286 .struct reloc_howto_struct
288 . {* The type field has mainly a documentary use - the back end can
289 . do what it wants with it, though normally the back end's
290 . external idea of what a reloc number is stored
291 . in this field. For example, a PC relative word relocation
292 . in a coff environment has the type 023 - because that's
293 . what the outside world calls a R_PCRWORD reloc. *}
296 . {* The value the final relocation is shifted right by. This drops
297 . unwanted data from the relocation. *}
298 . unsigned int rightshift;
300 . {* The size of the item to be relocated. This is *not* a
301 . power-of-two measure. To get the number of bytes operated
302 . on by a type of relocation, use bfd_get_reloc_size. *}
305 . {* The number of bits in the item to be relocated. This is used
306 . when doing overflow checking. *}
307 . unsigned int bitsize;
309 . {* The relocation is relative to the field being relocated. *}
310 . bfd_boolean pc_relative;
312 . {* The bit position of the reloc value in the destination.
313 . The relocated value is left shifted by this amount. *}
314 . unsigned int bitpos;
316 . {* What type of overflow error should be checked for when
318 . enum complain_overflow complain_on_overflow;
320 . {* If this field is non null, then the supplied function is
321 . called rather than the normal function. This allows really
322 . strange relocation methods to be accommodated (e.g., i960 callj
324 . bfd_reloc_status_type (*special_function)
325 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
328 . {* The textual name of the relocation type. *}
331 . {* Some formats record a relocation addend in the section contents
332 . rather than with the relocation. For ELF formats this is the
333 . distinction between USE_REL and USE_RELA (though the code checks
334 . for USE_REL == 1/0). The value of this field is TRUE if the
335 . addend is recorded with the section contents; when performing a
336 . partial link (ld -r) the section contents (the data) will be
337 . modified. The value of this field is FALSE if addends are
338 . recorded with the relocation (in arelent.addend); when performing
339 . a partial link the relocation will be modified.
340 . All relocations for all ELF USE_RELA targets should set this field
341 . to FALSE (values of TRUE should be looked on with suspicion).
342 . However, the converse is not true: not all relocations of all ELF
343 . USE_REL targets set this field to TRUE. Why this is so is peculiar
344 . to each particular target. For relocs that aren't used in partial
345 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
346 . bfd_boolean partial_inplace;
348 . {* src_mask selects the part of the instruction (or data) to be used
349 . in the relocation sum. If the target relocations don't have an
350 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
351 . dst_mask to extract the addend from the section contents. If
352 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
353 . field should be zero. Non-zero values for ELF USE_RELA targets are
354 . bogus as in those cases the value in the dst_mask part of the
355 . section contents should be treated as garbage. *}
358 . {* dst_mask selects which parts of the instruction (or data) are
359 . replaced with a relocated value. *}
362 . {* When some formats create PC relative instructions, they leave
363 . the value of the pc of the place being relocated in the offset
364 . slot of the instruction, so that a PC relative relocation can
365 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
366 . Some formats leave the displacement part of an instruction
367 . empty (e.g., m88k bcs); this flag signals the fact. *}
368 . bfd_boolean pcrel_offset;
378 The HOWTO define is horrible and will go away.
380 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
381 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
384 And will be replaced with the totally magic way. But for the
385 moment, we are compatible, so do it this way.
387 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
388 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
389 . NAME, FALSE, 0, 0, IN)
393 This is used to fill in an empty howto entry in an array.
395 .#define EMPTY_HOWTO(C) \
396 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
397 . NULL, FALSE, 0, 0, FALSE)
401 Helper routine to turn a symbol into a relocation value.
403 .#define HOWTO_PREPARE(relocation, symbol) \
405 . if (symbol != NULL) \
407 . if (bfd_is_com_section (symbol->section)) \
413 . relocation = symbol->value; \
425 unsigned int bfd_get_reloc_size (reloc_howto_type *);
428 For a reloc_howto_type that operates on a fixed number of bytes,
429 this returns the number of bytes operated on.
433 bfd_get_reloc_size (reloc_howto_type *howto)
454 How relocs are tied together in an <<asection>>:
456 .typedef struct relent_chain
459 . struct relent_chain *next;
465 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
466 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
473 bfd_reloc_status_type bfd_check_overflow
474 (enum complain_overflow how,
475 unsigned int bitsize,
476 unsigned int rightshift,
477 unsigned int addrsize,
481 Perform overflow checking on @var{relocation} which has
482 @var{bitsize} significant bits and will be shifted right by
483 @var{rightshift} bits, on a machine with addresses containing
484 @var{addrsize} significant bits. The result is either of
485 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
489 bfd_reloc_status_type
490 bfd_check_overflow (enum complain_overflow how,
491 unsigned int bitsize,
492 unsigned int rightshift,
493 unsigned int addrsize,
496 bfd_vma fieldmask, addrmask, signmask, ss, a;
497 bfd_reloc_status_type flag = bfd_reloc_ok;
499 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
500 we'll be permissive: extra bits in the field mask will
501 automatically extend the address mask for purposes of the
503 fieldmask = N_ONES (bitsize);
504 signmask = ~fieldmask;
505 addrmask = N_ONES (addrsize) | (fieldmask << rightshift);
506 a = (relocation & addrmask) >> rightshift;
510 case complain_overflow_dont:
513 case complain_overflow_signed:
514 /* If any sign bits are set, all sign bits must be set. That
515 is, A must be a valid negative address after shifting. */
516 signmask = ~ (fieldmask >> 1);
519 case complain_overflow_bitfield:
520 /* Bitfields are sometimes signed, sometimes unsigned. We
521 explicitly allow an address wrap too, which means a bitfield
522 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
523 if the value has some, but not all, bits set outside the
526 if (ss != 0 && ss != ((addrmask >> rightshift) & signmask))
527 flag = bfd_reloc_overflow;
530 case complain_overflow_unsigned:
531 /* We have an overflow if the address does not fit in the field. */
532 if ((a & signmask) != 0)
533 flag = bfd_reloc_overflow;
545 bfd_perform_relocation
548 bfd_reloc_status_type bfd_perform_relocation
550 arelent *reloc_entry,
552 asection *input_section,
554 char **error_message);
557 If @var{output_bfd} is supplied to this function, the
558 generated image will be relocatable; the relocations are
559 copied to the output file after they have been changed to
560 reflect the new state of the world. There are two ways of
561 reflecting the results of partial linkage in an output file:
562 by modifying the output data in place, and by modifying the
563 relocation record. Some native formats (e.g., basic a.out and
564 basic coff) have no way of specifying an addend in the
565 relocation type, so the addend has to go in the output data.
566 This is no big deal since in these formats the output data
567 slot will always be big enough for the addend. Complex reloc
568 types with addends were invented to solve just this problem.
569 The @var{error_message} argument is set to an error message if
570 this return @code{bfd_reloc_dangerous}.
574 bfd_reloc_status_type
575 bfd_perform_relocation (bfd *abfd,
576 arelent *reloc_entry,
578 asection *input_section,
580 char **error_message)
583 bfd_reloc_status_type flag = bfd_reloc_ok;
584 bfd_size_type octets = reloc_entry->address * bfd_octets_per_byte (abfd);
585 bfd_vma output_base = 0;
586 reloc_howto_type *howto = reloc_entry->howto;
587 asection *reloc_target_output_section;
590 symbol = *(reloc_entry->sym_ptr_ptr);
591 if (bfd_is_abs_section (symbol->section)
592 && output_bfd != NULL)
594 reloc_entry->address += input_section->output_offset;
598 /* If we are not producing relocatable output, return an error if
599 the symbol is not defined. An undefined weak symbol is
600 considered to have a value of zero (SVR4 ABI, p. 4-27). */
601 if (bfd_is_und_section (symbol->section)
602 && (symbol->flags & BSF_WEAK) == 0
603 && output_bfd == NULL)
604 flag = bfd_reloc_undefined;
606 /* If there is a function supplied to handle this relocation type,
607 call it. It'll return `bfd_reloc_continue' if further processing
609 if (howto->special_function)
611 bfd_reloc_status_type cont;
612 cont = howto->special_function (abfd, reloc_entry, symbol, data,
613 input_section, output_bfd,
615 if (cont != bfd_reloc_continue)
619 /* Is the address of the relocation really within the section? */
620 if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
621 return bfd_reloc_outofrange;
623 /* Work out which section the relocation is targeted at and the
624 initial relocation command value. */
626 /* Get symbol value. (Common symbols are special.) */
627 if (bfd_is_com_section (symbol->section))
630 relocation = symbol->value;
632 reloc_target_output_section = symbol->section->output_section;
634 /* Convert input-section-relative symbol value to absolute. */
635 if ((output_bfd && ! howto->partial_inplace)
636 || reloc_target_output_section == NULL)
639 output_base = reloc_target_output_section->vma;
641 relocation += output_base + symbol->section->output_offset;
643 /* Add in supplied addend. */
644 relocation += reloc_entry->addend;
646 /* Here the variable relocation holds the final address of the
647 symbol we are relocating against, plus any addend. */
649 if (howto->pc_relative)
651 /* This is a PC relative relocation. We want to set RELOCATION
652 to the distance between the address of the symbol and the
653 location. RELOCATION is already the address of the symbol.
655 We start by subtracting the address of the section containing
658 If pcrel_offset is set, we must further subtract the position
659 of the location within the section. Some targets arrange for
660 the addend to be the negative of the position of the location
661 within the section; for example, i386-aout does this. For
662 i386-aout, pcrel_offset is FALSE. Some other targets do not
663 include the position of the location; for example, m88kbcs,
664 or ELF. For those targets, pcrel_offset is TRUE.
666 If we are producing relocatable output, then we must ensure
667 that this reloc will be correctly computed when the final
668 relocation is done. If pcrel_offset is FALSE we want to wind
669 up with the negative of the location within the section,
670 which means we must adjust the existing addend by the change
671 in the location within the section. If pcrel_offset is TRUE
672 we do not want to adjust the existing addend at all.
674 FIXME: This seems logical to me, but for the case of
675 producing relocatable output it is not what the code
676 actually does. I don't want to change it, because it seems
677 far too likely that something will break. */
680 input_section->output_section->vma + input_section->output_offset;
682 if (howto->pcrel_offset)
683 relocation -= reloc_entry->address;
686 if (output_bfd != NULL)
688 if (! howto->partial_inplace)
690 /* This is a partial relocation, and we want to apply the relocation
691 to the reloc entry rather than the raw data. Modify the reloc
692 inplace to reflect what we now know. */
693 reloc_entry->addend = relocation;
694 reloc_entry->address += input_section->output_offset;
699 /* This is a partial relocation, but inplace, so modify the
702 If we've relocated with a symbol with a section, change
703 into a ref to the section belonging to the symbol. */
705 reloc_entry->address += input_section->output_offset;
708 if (abfd->xvec->flavour == bfd_target_coff_flavour
709 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
710 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
712 /* For m68k-coff, the addend was being subtracted twice during
713 relocation with -r. Removing the line below this comment
714 fixes that problem; see PR 2953.
716 However, Ian wrote the following, regarding removing the line below,
717 which explains why it is still enabled: --djm
719 If you put a patch like that into BFD you need to check all the COFF
720 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
721 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
722 problem in a different way. There may very well be a reason that the
723 code works as it does.
725 Hmmm. The first obvious point is that bfd_perform_relocation should
726 not have any tests that depend upon the flavour. It's seem like
727 entirely the wrong place for such a thing. The second obvious point
728 is that the current code ignores the reloc addend when producing
729 relocatable output for COFF. That's peculiar. In fact, I really
730 have no idea what the point of the line you want to remove is.
732 A typical COFF reloc subtracts the old value of the symbol and adds in
733 the new value to the location in the object file (if it's a pc
734 relative reloc it adds the difference between the symbol value and the
735 location). When relocating we need to preserve that property.
737 BFD handles this by setting the addend to the negative of the old
738 value of the symbol. Unfortunately it handles common symbols in a
739 non-standard way (it doesn't subtract the old value) but that's a
740 different story (we can't change it without losing backward
741 compatibility with old object files) (coff-i386 does subtract the old
742 value, to be compatible with existing coff-i386 targets, like SCO).
744 So everything works fine when not producing relocatable output. When
745 we are producing relocatable output, logically we should do exactly
746 what we do when not producing relocatable output. Therefore, your
747 patch is correct. In fact, it should probably always just set
748 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
749 add the value into the object file. This won't hurt the COFF code,
750 which doesn't use the addend; I'm not sure what it will do to other
751 formats (the thing to check for would be whether any formats both use
752 the addend and set partial_inplace).
754 When I wanted to make coff-i386 produce relocatable output, I ran
755 into the problem that you are running into: I wanted to remove that
756 line. Rather than risk it, I made the coff-i386 relocs use a special
757 function; it's coff_i386_reloc in coff-i386.c. The function
758 specifically adds the addend field into the object file, knowing that
759 bfd_perform_relocation is not going to. If you remove that line, then
760 coff-i386.c will wind up adding the addend field in twice. It's
761 trivial to fix; it just needs to be done.
763 The problem with removing the line is just that it may break some
764 working code. With BFD it's hard to be sure of anything. The right
765 way to deal with this is simply to build and test at least all the
766 supported COFF targets. It should be straightforward if time and disk
767 space consuming. For each target:
769 2) generate some executable, and link it using -r (I would
770 probably use paranoia.o and link against newlib/libc.a, which
771 for all the supported targets would be available in
772 /usr/cygnus/progressive/H-host/target/lib/libc.a).
773 3) make the change to reloc.c
774 4) rebuild the linker
776 6) if the resulting object files are the same, you have at least
778 7) if they are different you have to figure out which version is
781 relocation -= reloc_entry->addend;
782 reloc_entry->addend = 0;
786 reloc_entry->addend = relocation;
792 reloc_entry->addend = 0;
795 /* FIXME: This overflow checking is incomplete, because the value
796 might have overflowed before we get here. For a correct check we
797 need to compute the value in a size larger than bitsize, but we
798 can't reasonably do that for a reloc the same size as a host
800 FIXME: We should also do overflow checking on the result after
801 adding in the value contained in the object file. */
802 if (howto->complain_on_overflow != complain_overflow_dont
803 && flag == bfd_reloc_ok)
804 flag = bfd_check_overflow (howto->complain_on_overflow,
807 bfd_arch_bits_per_address (abfd),
810 /* Either we are relocating all the way, or we don't want to apply
811 the relocation to the reloc entry (probably because there isn't
812 any room in the output format to describe addends to relocs). */
814 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
815 (OSF version 1.3, compiler version 3.11). It miscompiles the
829 x <<= (unsigned long) s.i0;
833 printf ("succeeded (%lx)\n", x);
837 relocation >>= (bfd_vma) howto->rightshift;
839 /* Shift everything up to where it's going to be used. */
840 relocation <<= (bfd_vma) howto->bitpos;
842 /* Wait for the day when all have the mask in them. */
845 i instruction to be left alone
846 o offset within instruction
847 r relocation offset to apply
856 (( i i i i i o o o o o from bfd_get<size>
857 and S S S S S) to get the size offset we want
858 + r r r r r r r r r r) to get the final value to place
859 and D D D D D to chop to right size
860 -----------------------
863 ( i i i i i o o o o o from bfd_get<size>
864 and N N N N N ) get instruction
865 -----------------------
871 -----------------------
872 = R R R R R R R R R R put into bfd_put<size>
876 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
882 char x = bfd_get_8 (abfd, (char *) data + octets);
884 bfd_put_8 (abfd, x, (unsigned char *) data + octets);
890 short x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
892 bfd_put_16 (abfd, (bfd_vma) x, (unsigned char *) data + octets);
897 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
899 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
904 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
905 relocation = -relocation;
907 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
913 long x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
914 relocation = -relocation;
916 bfd_put_16 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
927 bfd_vma x = bfd_get_64 (abfd, (bfd_byte *) data + octets);
929 bfd_put_64 (abfd, x, (bfd_byte *) data + octets);
936 return bfd_reloc_other;
944 bfd_install_relocation
947 bfd_reloc_status_type bfd_install_relocation
949 arelent *reloc_entry,
950 void *data, bfd_vma data_start,
951 asection *input_section,
952 char **error_message);
955 This looks remarkably like <<bfd_perform_relocation>>, except it
956 does not expect that the section contents have been filled in.
957 I.e., it's suitable for use when creating, rather than applying
960 For now, this function should be considered reserved for the
964 bfd_reloc_status_type
965 bfd_install_relocation (bfd *abfd,
966 arelent *reloc_entry,
968 bfd_vma data_start_offset,
969 asection *input_section,
970 char **error_message)
973 bfd_reloc_status_type flag = bfd_reloc_ok;
974 bfd_size_type octets = reloc_entry->address * bfd_octets_per_byte (abfd);
975 bfd_vma output_base = 0;
976 reloc_howto_type *howto = reloc_entry->howto;
977 asection *reloc_target_output_section;
981 symbol = *(reloc_entry->sym_ptr_ptr);
982 if (bfd_is_abs_section (symbol->section))
984 reloc_entry->address += input_section->output_offset;
988 /* If there is a function supplied to handle this relocation type,
989 call it. It'll return `bfd_reloc_continue' if further processing
991 if (howto->special_function)
993 bfd_reloc_status_type cont;
995 /* XXX - The special_function calls haven't been fixed up to deal
996 with creating new relocations and section contents. */
997 cont = howto->special_function (abfd, reloc_entry, symbol,
998 /* XXX - Non-portable! */
999 ((bfd_byte *) data_start
1000 - data_start_offset),
1001 input_section, abfd, error_message);
1002 if (cont != bfd_reloc_continue)
1006 /* Is the address of the relocation really within the section? */
1007 if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
1008 return bfd_reloc_outofrange;
1010 /* Work out which section the relocation is targeted at and the
1011 initial relocation command value. */
1013 /* Get symbol value. (Common symbols are special.) */
1014 if (bfd_is_com_section (symbol->section))
1017 relocation = symbol->value;
1019 reloc_target_output_section = symbol->section->output_section;
1021 /* Convert input-section-relative symbol value to absolute. */
1022 if (! howto->partial_inplace)
1025 output_base = reloc_target_output_section->vma;
1027 relocation += output_base + symbol->section->output_offset;
1029 /* Add in supplied addend. */
1030 relocation += reloc_entry->addend;
1032 /* Here the variable relocation holds the final address of the
1033 symbol we are relocating against, plus any addend. */
1035 if (howto->pc_relative)
1037 /* This is a PC relative relocation. We want to set RELOCATION
1038 to the distance between the address of the symbol and the
1039 location. RELOCATION is already the address of the symbol.
1041 We start by subtracting the address of the section containing
1044 If pcrel_offset is set, we must further subtract the position
1045 of the location within the section. Some targets arrange for
1046 the addend to be the negative of the position of the location
1047 within the section; for example, i386-aout does this. For
1048 i386-aout, pcrel_offset is FALSE. Some other targets do not
1049 include the position of the location; for example, m88kbcs,
1050 or ELF. For those targets, pcrel_offset is TRUE.
1052 If we are producing relocatable output, then we must ensure
1053 that this reloc will be correctly computed when the final
1054 relocation is done. If pcrel_offset is FALSE we want to wind
1055 up with the negative of the location within the section,
1056 which means we must adjust the existing addend by the change
1057 in the location within the section. If pcrel_offset is TRUE
1058 we do not want to adjust the existing addend at all.
1060 FIXME: This seems logical to me, but for the case of
1061 producing relocatable output it is not what the code
1062 actually does. I don't want to change it, because it seems
1063 far too likely that something will break. */
1066 input_section->output_section->vma + input_section->output_offset;
1068 if (howto->pcrel_offset && howto->partial_inplace)
1069 relocation -= reloc_entry->address;
1072 if (! howto->partial_inplace)
1074 /* This is a partial relocation, and we want to apply the relocation
1075 to the reloc entry rather than the raw data. Modify the reloc
1076 inplace to reflect what we now know. */
1077 reloc_entry->addend = relocation;
1078 reloc_entry->address += input_section->output_offset;
1083 /* This is a partial relocation, but inplace, so modify the
1086 If we've relocated with a symbol with a section, change
1087 into a ref to the section belonging to the symbol. */
1088 reloc_entry->address += input_section->output_offset;
1091 if (abfd->xvec->flavour == bfd_target_coff_flavour
1092 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
1093 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
1096 /* For m68k-coff, the addend was being subtracted twice during
1097 relocation with -r. Removing the line below this comment
1098 fixes that problem; see PR 2953.
1100 However, Ian wrote the following, regarding removing the line below,
1101 which explains why it is still enabled: --djm
1103 If you put a patch like that into BFD you need to check all the COFF
1104 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1105 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1106 problem in a different way. There may very well be a reason that the
1107 code works as it does.
1109 Hmmm. The first obvious point is that bfd_install_relocation should
1110 not have any tests that depend upon the flavour. It's seem like
1111 entirely the wrong place for such a thing. The second obvious point
1112 is that the current code ignores the reloc addend when producing
1113 relocatable output for COFF. That's peculiar. In fact, I really
1114 have no idea what the point of the line you want to remove is.
1116 A typical COFF reloc subtracts the old value of the symbol and adds in
1117 the new value to the location in the object file (if it's a pc
1118 relative reloc it adds the difference between the symbol value and the
1119 location). When relocating we need to preserve that property.
1121 BFD handles this by setting the addend to the negative of the old
1122 value of the symbol. Unfortunately it handles common symbols in a
1123 non-standard way (it doesn't subtract the old value) but that's a
1124 different story (we can't change it without losing backward
1125 compatibility with old object files) (coff-i386 does subtract the old
1126 value, to be compatible with existing coff-i386 targets, like SCO).
1128 So everything works fine when not producing relocatable output. When
1129 we are producing relocatable output, logically we should do exactly
1130 what we do when not producing relocatable output. Therefore, your
1131 patch is correct. In fact, it should probably always just set
1132 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1133 add the value into the object file. This won't hurt the COFF code,
1134 which doesn't use the addend; I'm not sure what it will do to other
1135 formats (the thing to check for would be whether any formats both use
1136 the addend and set partial_inplace).
1138 When I wanted to make coff-i386 produce relocatable output, I ran
1139 into the problem that you are running into: I wanted to remove that
1140 line. Rather than risk it, I made the coff-i386 relocs use a special
1141 function; it's coff_i386_reloc in coff-i386.c. The function
1142 specifically adds the addend field into the object file, knowing that
1143 bfd_install_relocation is not going to. If you remove that line, then
1144 coff-i386.c will wind up adding the addend field in twice. It's
1145 trivial to fix; it just needs to be done.
1147 The problem with removing the line is just that it may break some
1148 working code. With BFD it's hard to be sure of anything. The right
1149 way to deal with this is simply to build and test at least all the
1150 supported COFF targets. It should be straightforward if time and disk
1151 space consuming. For each target:
1153 2) generate some executable, and link it using -r (I would
1154 probably use paranoia.o and link against newlib/libc.a, which
1155 for all the supported targets would be available in
1156 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1157 3) make the change to reloc.c
1158 4) rebuild the linker
1160 6) if the resulting object files are the same, you have at least
1162 7) if they are different you have to figure out which version is
1164 relocation -= reloc_entry->addend;
1165 /* FIXME: There should be no target specific code here... */
1166 if (strcmp (abfd->xvec->name, "coff-z8k") != 0)
1167 reloc_entry->addend = 0;
1171 reloc_entry->addend = relocation;
1175 /* FIXME: This overflow checking is incomplete, because the value
1176 might have overflowed before we get here. For a correct check we
1177 need to compute the value in a size larger than bitsize, but we
1178 can't reasonably do that for a reloc the same size as a host
1180 FIXME: We should also do overflow checking on the result after
1181 adding in the value contained in the object file. */
1182 if (howto->complain_on_overflow != complain_overflow_dont)
1183 flag = bfd_check_overflow (howto->complain_on_overflow,
1186 bfd_arch_bits_per_address (abfd),
1189 /* Either we are relocating all the way, or we don't want to apply
1190 the relocation to the reloc entry (probably because there isn't
1191 any room in the output format to describe addends to relocs). */
1193 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1194 (OSF version 1.3, compiler version 3.11). It miscompiles the
1208 x <<= (unsigned long) s.i0;
1210 printf ("failed\n");
1212 printf ("succeeded (%lx)\n", x);
1216 relocation >>= (bfd_vma) howto->rightshift;
1218 /* Shift everything up to where it's going to be used. */
1219 relocation <<= (bfd_vma) howto->bitpos;
1221 /* Wait for the day when all have the mask in them. */
1224 i instruction to be left alone
1225 o offset within instruction
1226 r relocation offset to apply
1235 (( i i i i i o o o o o from bfd_get<size>
1236 and S S S S S) to get the size offset we want
1237 + r r r r r r r r r r) to get the final value to place
1238 and D D D D D to chop to right size
1239 -----------------------
1242 ( i i i i i o o o o o from bfd_get<size>
1243 and N N N N N ) get instruction
1244 -----------------------
1250 -----------------------
1251 = R R R R R R R R R R put into bfd_put<size>
1255 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1257 data = (bfd_byte *) data_start + (octets - data_start_offset);
1259 switch (howto->size)
1263 char x = bfd_get_8 (abfd, data);
1265 bfd_put_8 (abfd, x, data);
1271 short x = bfd_get_16 (abfd, data);
1273 bfd_put_16 (abfd, (bfd_vma) x, data);
1278 long x = bfd_get_32 (abfd, data);
1280 bfd_put_32 (abfd, (bfd_vma) x, data);
1285 long x = bfd_get_32 (abfd, data);
1286 relocation = -relocation;
1288 bfd_put_32 (abfd, (bfd_vma) x, data);
1298 bfd_vma x = bfd_get_64 (abfd, data);
1300 bfd_put_64 (abfd, x, data);
1304 return bfd_reloc_other;
1310 /* This relocation routine is used by some of the backend linkers.
1311 They do not construct asymbol or arelent structures, so there is no
1312 reason for them to use bfd_perform_relocation. Also,
1313 bfd_perform_relocation is so hacked up it is easier to write a new
1314 function than to try to deal with it.
1316 This routine does a final relocation. Whether it is useful for a
1317 relocatable link depends upon how the object format defines
1320 FIXME: This routine ignores any special_function in the HOWTO,
1321 since the existing special_function values have been written for
1322 bfd_perform_relocation.
1324 HOWTO is the reloc howto information.
1325 INPUT_BFD is the BFD which the reloc applies to.
1326 INPUT_SECTION is the section which the reloc applies to.
1327 CONTENTS is the contents of the section.
1328 ADDRESS is the address of the reloc within INPUT_SECTION.
1329 VALUE is the value of the symbol the reloc refers to.
1330 ADDEND is the addend of the reloc. */
1332 bfd_reloc_status_type
1333 _bfd_final_link_relocate (reloc_howto_type *howto,
1335 asection *input_section,
1343 /* Sanity check the address. */
1344 if (address > bfd_get_section_limit (input_bfd, input_section))
1345 return bfd_reloc_outofrange;
1347 /* This function assumes that we are dealing with a basic relocation
1348 against a symbol. We want to compute the value of the symbol to
1349 relocate to. This is just VALUE, the value of the symbol, plus
1350 ADDEND, any addend associated with the reloc. */
1351 relocation = value + addend;
1353 /* If the relocation is PC relative, we want to set RELOCATION to
1354 the distance between the symbol (currently in RELOCATION) and the
1355 location we are relocating. Some targets (e.g., i386-aout)
1356 arrange for the contents of the section to be the negative of the
1357 offset of the location within the section; for such targets
1358 pcrel_offset is FALSE. Other targets (e.g., m88kbcs or ELF)
1359 simply leave the contents of the section as zero; for such
1360 targets pcrel_offset is TRUE. If pcrel_offset is FALSE we do not
1361 need to subtract out the offset of the location within the
1362 section (which is just ADDRESS). */
1363 if (howto->pc_relative)
1365 relocation -= (input_section->output_section->vma
1366 + input_section->output_offset);
1367 if (howto->pcrel_offset)
1368 relocation -= address;
1371 return _bfd_relocate_contents (howto, input_bfd, relocation,
1372 contents + address);
1375 /* Relocate a given location using a given value and howto. */
1377 bfd_reloc_status_type
1378 _bfd_relocate_contents (reloc_howto_type *howto,
1385 bfd_reloc_status_type flag;
1386 unsigned int rightshift = howto->rightshift;
1387 unsigned int bitpos = howto->bitpos;
1389 /* If the size is negative, negate RELOCATION. This isn't very
1391 if (howto->size < 0)
1392 relocation = -relocation;
1394 /* Get the value we are going to relocate. */
1395 size = bfd_get_reloc_size (howto);
1402 x = bfd_get_8 (input_bfd, location);
1405 x = bfd_get_16 (input_bfd, location);
1408 x = bfd_get_32 (input_bfd, location);
1412 x = bfd_get_64 (input_bfd, location);
1419 /* Check for overflow. FIXME: We may drop bits during the addition
1420 which we don't check for. We must either check at every single
1421 operation, which would be tedious, or we must do the computations
1422 in a type larger than bfd_vma, which would be inefficient. */
1423 flag = bfd_reloc_ok;
1424 if (howto->complain_on_overflow != complain_overflow_dont)
1426 bfd_vma addrmask, fieldmask, signmask, ss;
1429 /* Get the values to be added together. For signed and unsigned
1430 relocations, we assume that all values should be truncated to
1431 the size of an address. For bitfields, all the bits matter.
1432 See also bfd_check_overflow. */
1433 fieldmask = N_ONES (howto->bitsize);
1434 signmask = ~fieldmask;
1435 addrmask = (N_ONES (bfd_arch_bits_per_address (input_bfd))
1436 | (fieldmask << rightshift));
1437 a = (relocation & addrmask) >> rightshift;
1438 b = (x & howto->src_mask & addrmask) >> bitpos;
1439 addrmask >>= rightshift;
1441 switch (howto->complain_on_overflow)
1443 case complain_overflow_signed:
1444 /* If any sign bits are set, all sign bits must be set.
1445 That is, A must be a valid negative address after
1447 signmask = ~(fieldmask >> 1);
1450 case complain_overflow_bitfield:
1451 /* Much like the signed check, but for a field one bit
1452 wider. We allow a bitfield to represent numbers in the
1453 range -2**n to 2**n-1, where n is the number of bits in the
1454 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1455 can't overflow, which is exactly what we want. */
1457 if (ss != 0 && ss != (addrmask & signmask))
1458 flag = bfd_reloc_overflow;
1460 /* We only need this next bit of code if the sign bit of B
1461 is below the sign bit of A. This would only happen if
1462 SRC_MASK had fewer bits than BITSIZE. Note that if
1463 SRC_MASK has more bits than BITSIZE, we can get into
1464 trouble; we would need to verify that B is in range, as
1465 we do for A above. */
1466 ss = ((~howto->src_mask) >> 1) & howto->src_mask;
1469 /* Set all the bits above the sign bit. */
1472 /* Now we can do the addition. */
1475 /* See if the result has the correct sign. Bits above the
1476 sign bit are junk now; ignore them. If the sum is
1477 positive, make sure we did not have all negative inputs;
1478 if the sum is negative, make sure we did not have all
1479 positive inputs. The test below looks only at the sign
1480 bits, and it really just
1481 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1483 We mask with addrmask here to explicitly allow an address
1484 wrap-around. The Linux kernel relies on it, and it is
1485 the only way to write assembler code which can run when
1486 loaded at a location 0x80000000 away from the location at
1487 which it is linked. */
1488 if (((~(a ^ b)) & (a ^ sum)) & signmask & addrmask)
1489 flag = bfd_reloc_overflow;
1492 case complain_overflow_unsigned:
1493 /* Checking for an unsigned overflow is relatively easy:
1494 trim the addresses and add, and trim the result as well.
1495 Overflow is normally indicated when the result does not
1496 fit in the field. However, we also need to consider the
1497 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1498 input is 0x80000000, and bfd_vma is only 32 bits; then we
1499 will get sum == 0, but there is an overflow, since the
1500 inputs did not fit in the field. Instead of doing a
1501 separate test, we can check for this by or-ing in the
1502 operands when testing for the sum overflowing its final
1504 sum = (a + b) & addrmask;
1505 if ((a | b | sum) & signmask)
1506 flag = bfd_reloc_overflow;
1514 /* Put RELOCATION in the right bits. */
1515 relocation >>= (bfd_vma) rightshift;
1516 relocation <<= (bfd_vma) bitpos;
1518 /* Add RELOCATION to the right bits of X. */
1519 x = ((x & ~howto->dst_mask)
1520 | (((x & howto->src_mask) + relocation) & howto->dst_mask));
1522 /* Put the relocated value back in the object file. */
1528 bfd_put_8 (input_bfd, x, location);
1531 bfd_put_16 (input_bfd, x, location);
1534 bfd_put_32 (input_bfd, x, location);
1538 bfd_put_64 (input_bfd, x, location);
1548 /* Clear a given location using a given howto, by applying a fixed relocation
1549 value and discarding any in-place addend. This is used for fixed-up
1550 relocations against discarded symbols, to make ignorable debug or unwind
1551 information more obvious. */
1554 _bfd_clear_contents (reloc_howto_type *howto,
1556 asection *input_section,
1562 /* Get the value we are going to relocate. */
1563 size = bfd_get_reloc_size (howto);
1570 x = bfd_get_8 (input_bfd, location);
1573 x = bfd_get_16 (input_bfd, location);
1576 x = bfd_get_32 (input_bfd, location);
1580 x = bfd_get_64 (input_bfd, location);
1587 /* Zero out the unwanted bits of X. */
1588 x &= ~howto->dst_mask;
1590 /* For a range list, use 1 instead of 0 as placeholder. 0
1591 would terminate the list, hiding any later entries. */
1592 if (strcmp (bfd_get_section_name (input_bfd, input_section),
1593 ".debug_ranges") == 0
1594 && (howto->dst_mask & 1) != 0)
1597 /* Put the relocated value back in the object file. */
1604 bfd_put_8 (input_bfd, x, location);
1607 bfd_put_16 (input_bfd, x, location);
1610 bfd_put_32 (input_bfd, x, location);
1614 bfd_put_64 (input_bfd, x, location);
1625 howto manager, , typedef arelent, Relocations
1630 When an application wants to create a relocation, but doesn't
1631 know what the target machine might call it, it can find out by
1632 using this bit of code.
1641 The insides of a reloc code. The idea is that, eventually, there
1642 will be one enumerator for every type of relocation we ever do.
1643 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1644 return a howto pointer.
1646 This does mean that the application must determine the correct
1647 enumerator value; you can't get a howto pointer from a random set
1668 Basic absolute relocations of N bits.
1683 PC-relative relocations. Sometimes these are relative to the address
1684 of the relocation itself; sometimes they are relative to the start of
1685 the section containing the relocation. It depends on the specific target.
1687 The 24-bit relocation is used in some Intel 960 configurations.
1692 Section relative relocations. Some targets need this for DWARF2.
1695 BFD_RELOC_32_GOT_PCREL
1697 BFD_RELOC_16_GOT_PCREL
1699 BFD_RELOC_8_GOT_PCREL
1705 BFD_RELOC_LO16_GOTOFF
1707 BFD_RELOC_HI16_GOTOFF
1709 BFD_RELOC_HI16_S_GOTOFF
1713 BFD_RELOC_64_PLT_PCREL
1715 BFD_RELOC_32_PLT_PCREL
1717 BFD_RELOC_24_PLT_PCREL
1719 BFD_RELOC_16_PLT_PCREL
1721 BFD_RELOC_8_PLT_PCREL
1729 BFD_RELOC_LO16_PLTOFF
1731 BFD_RELOC_HI16_PLTOFF
1733 BFD_RELOC_HI16_S_PLTOFF
1747 BFD_RELOC_68K_GLOB_DAT
1749 BFD_RELOC_68K_JMP_SLOT
1751 BFD_RELOC_68K_RELATIVE
1753 BFD_RELOC_68K_TLS_GD32
1755 BFD_RELOC_68K_TLS_GD16
1757 BFD_RELOC_68K_TLS_GD8
1759 BFD_RELOC_68K_TLS_LDM32
1761 BFD_RELOC_68K_TLS_LDM16
1763 BFD_RELOC_68K_TLS_LDM8
1765 BFD_RELOC_68K_TLS_LDO32
1767 BFD_RELOC_68K_TLS_LDO16
1769 BFD_RELOC_68K_TLS_LDO8
1771 BFD_RELOC_68K_TLS_IE32
1773 BFD_RELOC_68K_TLS_IE16
1775 BFD_RELOC_68K_TLS_IE8
1777 BFD_RELOC_68K_TLS_LE32
1779 BFD_RELOC_68K_TLS_LE16
1781 BFD_RELOC_68K_TLS_LE8
1783 Relocations used by 68K ELF.
1786 BFD_RELOC_32_BASEREL
1788 BFD_RELOC_16_BASEREL
1790 BFD_RELOC_LO16_BASEREL
1792 BFD_RELOC_HI16_BASEREL
1794 BFD_RELOC_HI16_S_BASEREL
1800 Linkage-table relative.
1805 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1808 BFD_RELOC_32_PCREL_S2
1810 BFD_RELOC_16_PCREL_S2
1812 BFD_RELOC_23_PCREL_S2
1814 These PC-relative relocations are stored as word displacements --
1815 i.e., byte displacements shifted right two bits. The 30-bit word
1816 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1817 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1818 signed 16-bit displacement is used on the MIPS, and the 23-bit
1819 displacement is used on the Alpha.
1826 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1827 the target word. These are used on the SPARC.
1834 For systems that allocate a Global Pointer register, these are
1835 displacements off that register. These relocation types are
1836 handled specially, because the value the register will have is
1837 decided relatively late.
1840 BFD_RELOC_I960_CALLJ
1842 Reloc types used for i960/b.out.
1847 BFD_RELOC_SPARC_WDISP22
1853 BFD_RELOC_SPARC_GOT10
1855 BFD_RELOC_SPARC_GOT13
1857 BFD_RELOC_SPARC_GOT22
1859 BFD_RELOC_SPARC_PC10
1861 BFD_RELOC_SPARC_PC22
1863 BFD_RELOC_SPARC_WPLT30
1865 BFD_RELOC_SPARC_COPY
1867 BFD_RELOC_SPARC_GLOB_DAT
1869 BFD_RELOC_SPARC_JMP_SLOT
1871 BFD_RELOC_SPARC_RELATIVE
1873 BFD_RELOC_SPARC_UA16
1875 BFD_RELOC_SPARC_UA32
1877 BFD_RELOC_SPARC_UA64
1879 BFD_RELOC_SPARC_GOTDATA_HIX22
1881 BFD_RELOC_SPARC_GOTDATA_LOX10
1883 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1885 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1887 BFD_RELOC_SPARC_GOTDATA_OP
1889 BFD_RELOC_SPARC_JMP_IREL
1891 BFD_RELOC_SPARC_IRELATIVE
1893 SPARC ELF relocations. There is probably some overlap with other
1894 relocation types already defined.
1897 BFD_RELOC_SPARC_BASE13
1899 BFD_RELOC_SPARC_BASE22
1901 I think these are specific to SPARC a.out (e.g., Sun 4).
1911 BFD_RELOC_SPARC_OLO10
1913 BFD_RELOC_SPARC_HH22
1915 BFD_RELOC_SPARC_HM10
1917 BFD_RELOC_SPARC_LM22
1919 BFD_RELOC_SPARC_PC_HH22
1921 BFD_RELOC_SPARC_PC_HM10
1923 BFD_RELOC_SPARC_PC_LM22
1925 BFD_RELOC_SPARC_WDISP16
1927 BFD_RELOC_SPARC_WDISP19
1935 BFD_RELOC_SPARC_DISP64
1938 BFD_RELOC_SPARC_PLT32
1940 BFD_RELOC_SPARC_PLT64
1942 BFD_RELOC_SPARC_HIX22
1944 BFD_RELOC_SPARC_LOX10
1952 BFD_RELOC_SPARC_REGISTER
1956 BFD_RELOC_SPARC_SIZE32
1958 BFD_RELOC_SPARC_SIZE64
1960 BFD_RELOC_SPARC_WDISP10
1965 BFD_RELOC_SPARC_REV32
1967 SPARC little endian relocation
1969 BFD_RELOC_SPARC_TLS_GD_HI22
1971 BFD_RELOC_SPARC_TLS_GD_LO10
1973 BFD_RELOC_SPARC_TLS_GD_ADD
1975 BFD_RELOC_SPARC_TLS_GD_CALL
1977 BFD_RELOC_SPARC_TLS_LDM_HI22
1979 BFD_RELOC_SPARC_TLS_LDM_LO10
1981 BFD_RELOC_SPARC_TLS_LDM_ADD
1983 BFD_RELOC_SPARC_TLS_LDM_CALL
1985 BFD_RELOC_SPARC_TLS_LDO_HIX22
1987 BFD_RELOC_SPARC_TLS_LDO_LOX10
1989 BFD_RELOC_SPARC_TLS_LDO_ADD
1991 BFD_RELOC_SPARC_TLS_IE_HI22
1993 BFD_RELOC_SPARC_TLS_IE_LO10
1995 BFD_RELOC_SPARC_TLS_IE_LD
1997 BFD_RELOC_SPARC_TLS_IE_LDX
1999 BFD_RELOC_SPARC_TLS_IE_ADD
2001 BFD_RELOC_SPARC_TLS_LE_HIX22
2003 BFD_RELOC_SPARC_TLS_LE_LOX10
2005 BFD_RELOC_SPARC_TLS_DTPMOD32
2007 BFD_RELOC_SPARC_TLS_DTPMOD64
2009 BFD_RELOC_SPARC_TLS_DTPOFF32
2011 BFD_RELOC_SPARC_TLS_DTPOFF64
2013 BFD_RELOC_SPARC_TLS_TPOFF32
2015 BFD_RELOC_SPARC_TLS_TPOFF64
2017 SPARC TLS relocations
2026 BFD_RELOC_SPU_IMM10W
2030 BFD_RELOC_SPU_IMM16W
2034 BFD_RELOC_SPU_PCREL9a
2036 BFD_RELOC_SPU_PCREL9b
2038 BFD_RELOC_SPU_PCREL16
2048 BFD_RELOC_SPU_ADD_PIC
2053 BFD_RELOC_ALPHA_GPDISP_HI16
2055 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2056 "addend" in some special way.
2057 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2058 writing; when reading, it will be the absolute section symbol. The
2059 addend is the displacement in bytes of the "lda" instruction from
2060 the "ldah" instruction (which is at the address of this reloc).
2062 BFD_RELOC_ALPHA_GPDISP_LO16
2064 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2065 with GPDISP_HI16 relocs. The addend is ignored when writing the
2066 relocations out, and is filled in with the file's GP value on
2067 reading, for convenience.
2070 BFD_RELOC_ALPHA_GPDISP
2072 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2073 relocation except that there is no accompanying GPDISP_LO16
2077 BFD_RELOC_ALPHA_LITERAL
2079 BFD_RELOC_ALPHA_ELF_LITERAL
2081 BFD_RELOC_ALPHA_LITUSE
2083 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2084 the assembler turns it into a LDQ instruction to load the address of
2085 the symbol, and then fills in a register in the real instruction.
2087 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2088 section symbol. The addend is ignored when writing, but is filled
2089 in with the file's GP value on reading, for convenience, as with the
2092 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2093 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2094 but it generates output not based on the position within the .got
2095 section, but relative to the GP value chosen for the file during the
2098 The LITUSE reloc, on the instruction using the loaded address, gives
2099 information to the linker that it might be able to use to optimize
2100 away some literal section references. The symbol is ignored (read
2101 as the absolute section symbol), and the "addend" indicates the type
2102 of instruction using the register:
2103 1 - "memory" fmt insn
2104 2 - byte-manipulation (byte offset reg)
2105 3 - jsr (target of branch)
2108 BFD_RELOC_ALPHA_HINT
2110 The HINT relocation indicates a value that should be filled into the
2111 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2112 prediction logic which may be provided on some processors.
2115 BFD_RELOC_ALPHA_LINKAGE
2117 The LINKAGE relocation outputs a linkage pair in the object file,
2118 which is filled by the linker.
2121 BFD_RELOC_ALPHA_CODEADDR
2123 The CODEADDR relocation outputs a STO_CA in the object file,
2124 which is filled by the linker.
2127 BFD_RELOC_ALPHA_GPREL_HI16
2129 BFD_RELOC_ALPHA_GPREL_LO16
2131 The GPREL_HI/LO relocations together form a 32-bit offset from the
2135 BFD_RELOC_ALPHA_BRSGP
2137 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2138 share a common GP, and the target address is adjusted for
2139 STO_ALPHA_STD_GPLOAD.
2144 The NOP relocation outputs a NOP if the longword displacement
2145 between two procedure entry points is < 2^21.
2150 The BSR relocation outputs a BSR if the longword displacement
2151 between two procedure entry points is < 2^21.
2156 The LDA relocation outputs a LDA if the longword displacement
2157 between two procedure entry points is < 2^16.
2162 The BOH relocation outputs a BSR if the longword displacement
2163 between two procedure entry points is < 2^21, or else a hint.
2166 BFD_RELOC_ALPHA_TLSGD
2168 BFD_RELOC_ALPHA_TLSLDM
2170 BFD_RELOC_ALPHA_DTPMOD64
2172 BFD_RELOC_ALPHA_GOTDTPREL16
2174 BFD_RELOC_ALPHA_DTPREL64
2176 BFD_RELOC_ALPHA_DTPREL_HI16
2178 BFD_RELOC_ALPHA_DTPREL_LO16
2180 BFD_RELOC_ALPHA_DTPREL16
2182 BFD_RELOC_ALPHA_GOTTPREL16
2184 BFD_RELOC_ALPHA_TPREL64
2186 BFD_RELOC_ALPHA_TPREL_HI16
2188 BFD_RELOC_ALPHA_TPREL_LO16
2190 BFD_RELOC_ALPHA_TPREL16
2192 Alpha thread-local storage relocations.
2197 BFD_RELOC_MICROMIPS_JMP
2199 The MIPS jump instruction.
2202 BFD_RELOC_MIPS16_JMP
2204 The MIPS16 jump instruction.
2207 BFD_RELOC_MIPS16_GPREL
2209 MIPS16 GP relative reloc.
2214 High 16 bits of 32-bit value; simple reloc.
2219 High 16 bits of 32-bit value but the low 16 bits will be sign
2220 extended and added to form the final result. If the low 16
2221 bits form a negative number, we need to add one to the high value
2222 to compensate for the borrow when the low bits are added.
2230 BFD_RELOC_HI16_PCREL
2232 High 16 bits of 32-bit pc-relative value
2234 BFD_RELOC_HI16_S_PCREL
2236 High 16 bits of 32-bit pc-relative value, adjusted
2238 BFD_RELOC_LO16_PCREL
2240 Low 16 bits of pc-relative value
2243 BFD_RELOC_MIPS16_GOT16
2245 BFD_RELOC_MIPS16_CALL16
2247 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2248 16-bit immediate fields
2250 BFD_RELOC_MIPS16_HI16
2252 MIPS16 high 16 bits of 32-bit value.
2254 BFD_RELOC_MIPS16_HI16_S
2256 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2257 extended and added to form the final result. If the low 16
2258 bits form a negative number, we need to add one to the high value
2259 to compensate for the borrow when the low bits are added.
2261 BFD_RELOC_MIPS16_LO16
2266 BFD_RELOC_MIPS16_TLS_GD
2268 BFD_RELOC_MIPS16_TLS_LDM
2270 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2272 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2274 BFD_RELOC_MIPS16_TLS_GOTTPREL
2276 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2278 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2280 MIPS16 TLS relocations
2283 BFD_RELOC_MIPS_LITERAL
2285 BFD_RELOC_MICROMIPS_LITERAL
2287 Relocation against a MIPS literal section.
2290 BFD_RELOC_MICROMIPS_7_PCREL_S1
2292 BFD_RELOC_MICROMIPS_10_PCREL_S1
2294 BFD_RELOC_MICROMIPS_16_PCREL_S1
2296 microMIPS PC-relative relocations.
2299 BFD_RELOC_MICROMIPS_GPREL16
2301 BFD_RELOC_MICROMIPS_HI16
2303 BFD_RELOC_MICROMIPS_HI16_S
2305 BFD_RELOC_MICROMIPS_LO16
2307 microMIPS versions of generic BFD relocs.
2310 BFD_RELOC_MIPS_GOT16
2312 BFD_RELOC_MICROMIPS_GOT16
2314 BFD_RELOC_MIPS_CALL16
2316 BFD_RELOC_MICROMIPS_CALL16
2318 BFD_RELOC_MIPS_GOT_HI16
2320 BFD_RELOC_MICROMIPS_GOT_HI16
2322 BFD_RELOC_MIPS_GOT_LO16
2324 BFD_RELOC_MICROMIPS_GOT_LO16
2326 BFD_RELOC_MIPS_CALL_HI16
2328 BFD_RELOC_MICROMIPS_CALL_HI16
2330 BFD_RELOC_MIPS_CALL_LO16
2332 BFD_RELOC_MICROMIPS_CALL_LO16
2336 BFD_RELOC_MICROMIPS_SUB
2338 BFD_RELOC_MIPS_GOT_PAGE
2340 BFD_RELOC_MICROMIPS_GOT_PAGE
2342 BFD_RELOC_MIPS_GOT_OFST
2344 BFD_RELOC_MICROMIPS_GOT_OFST
2346 BFD_RELOC_MIPS_GOT_DISP
2348 BFD_RELOC_MICROMIPS_GOT_DISP
2350 BFD_RELOC_MIPS_SHIFT5
2352 BFD_RELOC_MIPS_SHIFT6
2354 BFD_RELOC_MIPS_INSERT_A
2356 BFD_RELOC_MIPS_INSERT_B
2358 BFD_RELOC_MIPS_DELETE
2360 BFD_RELOC_MIPS_HIGHEST
2362 BFD_RELOC_MICROMIPS_HIGHEST
2364 BFD_RELOC_MIPS_HIGHER
2366 BFD_RELOC_MICROMIPS_HIGHER
2368 BFD_RELOC_MIPS_SCN_DISP
2370 BFD_RELOC_MICROMIPS_SCN_DISP
2372 BFD_RELOC_MIPS_REL16
2374 BFD_RELOC_MIPS_RELGOT
2378 BFD_RELOC_MICROMIPS_JALR
2380 BFD_RELOC_MIPS_TLS_DTPMOD32
2382 BFD_RELOC_MIPS_TLS_DTPREL32
2384 BFD_RELOC_MIPS_TLS_DTPMOD64
2386 BFD_RELOC_MIPS_TLS_DTPREL64
2388 BFD_RELOC_MIPS_TLS_GD
2390 BFD_RELOC_MICROMIPS_TLS_GD
2392 BFD_RELOC_MIPS_TLS_LDM
2394 BFD_RELOC_MICROMIPS_TLS_LDM
2396 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2398 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2400 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2402 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2404 BFD_RELOC_MIPS_TLS_GOTTPREL
2406 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2408 BFD_RELOC_MIPS_TLS_TPREL32
2410 BFD_RELOC_MIPS_TLS_TPREL64
2412 BFD_RELOC_MIPS_TLS_TPREL_HI16
2414 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2416 BFD_RELOC_MIPS_TLS_TPREL_LO16
2418 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2420 MIPS ELF relocations.
2426 BFD_RELOC_MIPS_JUMP_SLOT
2428 MIPS ELF relocations (VxWorks and PLT extensions).
2432 BFD_RELOC_MOXIE_10_PCREL
2434 Moxie ELF relocations.
2438 BFD_RELOC_FRV_LABEL16
2440 BFD_RELOC_FRV_LABEL24
2446 BFD_RELOC_FRV_GPREL12
2448 BFD_RELOC_FRV_GPRELU12
2450 BFD_RELOC_FRV_GPREL32
2452 BFD_RELOC_FRV_GPRELHI
2454 BFD_RELOC_FRV_GPRELLO
2462 BFD_RELOC_FRV_FUNCDESC
2464 BFD_RELOC_FRV_FUNCDESC_GOT12
2466 BFD_RELOC_FRV_FUNCDESC_GOTHI
2468 BFD_RELOC_FRV_FUNCDESC_GOTLO
2470 BFD_RELOC_FRV_FUNCDESC_VALUE
2472 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2474 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2476 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2478 BFD_RELOC_FRV_GOTOFF12
2480 BFD_RELOC_FRV_GOTOFFHI
2482 BFD_RELOC_FRV_GOTOFFLO
2484 BFD_RELOC_FRV_GETTLSOFF
2486 BFD_RELOC_FRV_TLSDESC_VALUE
2488 BFD_RELOC_FRV_GOTTLSDESC12
2490 BFD_RELOC_FRV_GOTTLSDESCHI
2492 BFD_RELOC_FRV_GOTTLSDESCLO
2494 BFD_RELOC_FRV_TLSMOFF12
2496 BFD_RELOC_FRV_TLSMOFFHI
2498 BFD_RELOC_FRV_TLSMOFFLO
2500 BFD_RELOC_FRV_GOTTLSOFF12
2502 BFD_RELOC_FRV_GOTTLSOFFHI
2504 BFD_RELOC_FRV_GOTTLSOFFLO
2506 BFD_RELOC_FRV_TLSOFF
2508 BFD_RELOC_FRV_TLSDESC_RELAX
2510 BFD_RELOC_FRV_GETTLSOFF_RELAX
2512 BFD_RELOC_FRV_TLSOFF_RELAX
2514 BFD_RELOC_FRV_TLSMOFF
2516 Fujitsu Frv Relocations.
2520 BFD_RELOC_MN10300_GOTOFF24
2522 This is a 24bit GOT-relative reloc for the mn10300.
2524 BFD_RELOC_MN10300_GOT32
2526 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2529 BFD_RELOC_MN10300_GOT24
2531 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2534 BFD_RELOC_MN10300_GOT16
2536 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2539 BFD_RELOC_MN10300_COPY
2541 Copy symbol at runtime.
2543 BFD_RELOC_MN10300_GLOB_DAT
2547 BFD_RELOC_MN10300_JMP_SLOT
2551 BFD_RELOC_MN10300_RELATIVE
2553 Adjust by program base.
2555 BFD_RELOC_MN10300_SYM_DIFF
2557 Together with another reloc targeted at the same location,
2558 allows for a value that is the difference of two symbols
2559 in the same section.
2561 BFD_RELOC_MN10300_ALIGN
2563 The addend of this reloc is an alignment power that must
2564 be honoured at the offset's location, regardless of linker
2567 BFD_RELOC_MN10300_TLS_GD
2569 BFD_RELOC_MN10300_TLS_LD
2571 BFD_RELOC_MN10300_TLS_LDO
2573 BFD_RELOC_MN10300_TLS_GOTIE
2575 BFD_RELOC_MN10300_TLS_IE
2577 BFD_RELOC_MN10300_TLS_LE
2579 BFD_RELOC_MN10300_TLS_DTPMOD
2581 BFD_RELOC_MN10300_TLS_DTPOFF
2583 BFD_RELOC_MN10300_TLS_TPOFF
2585 Various TLS-related relocations.
2587 BFD_RELOC_MN10300_32_PCREL
2589 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2592 BFD_RELOC_MN10300_16_PCREL
2594 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2605 BFD_RELOC_386_GLOB_DAT
2607 BFD_RELOC_386_JUMP_SLOT
2609 BFD_RELOC_386_RELATIVE
2611 BFD_RELOC_386_GOTOFF
2615 BFD_RELOC_386_TLS_TPOFF
2617 BFD_RELOC_386_TLS_IE
2619 BFD_RELOC_386_TLS_GOTIE
2621 BFD_RELOC_386_TLS_LE
2623 BFD_RELOC_386_TLS_GD
2625 BFD_RELOC_386_TLS_LDM
2627 BFD_RELOC_386_TLS_LDO_32
2629 BFD_RELOC_386_TLS_IE_32
2631 BFD_RELOC_386_TLS_LE_32
2633 BFD_RELOC_386_TLS_DTPMOD32
2635 BFD_RELOC_386_TLS_DTPOFF32
2637 BFD_RELOC_386_TLS_TPOFF32
2639 BFD_RELOC_386_TLS_GOTDESC
2641 BFD_RELOC_386_TLS_DESC_CALL
2643 BFD_RELOC_386_TLS_DESC
2645 BFD_RELOC_386_IRELATIVE
2647 i386/elf relocations
2650 BFD_RELOC_X86_64_GOT32
2652 BFD_RELOC_X86_64_PLT32
2654 BFD_RELOC_X86_64_COPY
2656 BFD_RELOC_X86_64_GLOB_DAT
2658 BFD_RELOC_X86_64_JUMP_SLOT
2660 BFD_RELOC_X86_64_RELATIVE
2662 BFD_RELOC_X86_64_GOTPCREL
2664 BFD_RELOC_X86_64_32S
2666 BFD_RELOC_X86_64_DTPMOD64
2668 BFD_RELOC_X86_64_DTPOFF64
2670 BFD_RELOC_X86_64_TPOFF64
2672 BFD_RELOC_X86_64_TLSGD
2674 BFD_RELOC_X86_64_TLSLD
2676 BFD_RELOC_X86_64_DTPOFF32
2678 BFD_RELOC_X86_64_GOTTPOFF
2680 BFD_RELOC_X86_64_TPOFF32
2682 BFD_RELOC_X86_64_GOTOFF64
2684 BFD_RELOC_X86_64_GOTPC32
2686 BFD_RELOC_X86_64_GOT64
2688 BFD_RELOC_X86_64_GOTPCREL64
2690 BFD_RELOC_X86_64_GOTPC64
2692 BFD_RELOC_X86_64_GOTPLT64
2694 BFD_RELOC_X86_64_PLTOFF64
2696 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2698 BFD_RELOC_X86_64_TLSDESC_CALL
2700 BFD_RELOC_X86_64_TLSDESC
2702 BFD_RELOC_X86_64_IRELATIVE
2704 x86-64/elf relocations
2707 BFD_RELOC_NS32K_IMM_8
2709 BFD_RELOC_NS32K_IMM_16
2711 BFD_RELOC_NS32K_IMM_32
2713 BFD_RELOC_NS32K_IMM_8_PCREL
2715 BFD_RELOC_NS32K_IMM_16_PCREL
2717 BFD_RELOC_NS32K_IMM_32_PCREL
2719 BFD_RELOC_NS32K_DISP_8
2721 BFD_RELOC_NS32K_DISP_16
2723 BFD_RELOC_NS32K_DISP_32
2725 BFD_RELOC_NS32K_DISP_8_PCREL
2727 BFD_RELOC_NS32K_DISP_16_PCREL
2729 BFD_RELOC_NS32K_DISP_32_PCREL
2734 BFD_RELOC_PDP11_DISP_8_PCREL
2736 BFD_RELOC_PDP11_DISP_6_PCREL
2741 BFD_RELOC_PJ_CODE_HI16
2743 BFD_RELOC_PJ_CODE_LO16
2745 BFD_RELOC_PJ_CODE_DIR16
2747 BFD_RELOC_PJ_CODE_DIR32
2749 BFD_RELOC_PJ_CODE_REL16
2751 BFD_RELOC_PJ_CODE_REL32
2753 Picojava relocs. Not all of these appear in object files.
2764 BFD_RELOC_PPC_B16_BRTAKEN
2766 BFD_RELOC_PPC_B16_BRNTAKEN
2770 BFD_RELOC_PPC_BA16_BRTAKEN
2772 BFD_RELOC_PPC_BA16_BRNTAKEN
2776 BFD_RELOC_PPC_GLOB_DAT
2778 BFD_RELOC_PPC_JMP_SLOT
2780 BFD_RELOC_PPC_RELATIVE
2782 BFD_RELOC_PPC_LOCAL24PC
2784 BFD_RELOC_PPC_EMB_NADDR32
2786 BFD_RELOC_PPC_EMB_NADDR16
2788 BFD_RELOC_PPC_EMB_NADDR16_LO
2790 BFD_RELOC_PPC_EMB_NADDR16_HI
2792 BFD_RELOC_PPC_EMB_NADDR16_HA
2794 BFD_RELOC_PPC_EMB_SDAI16
2796 BFD_RELOC_PPC_EMB_SDA2I16
2798 BFD_RELOC_PPC_EMB_SDA2REL
2800 BFD_RELOC_PPC_EMB_SDA21
2802 BFD_RELOC_PPC_EMB_MRKREF
2804 BFD_RELOC_PPC_EMB_RELSEC16
2806 BFD_RELOC_PPC_EMB_RELST_LO
2808 BFD_RELOC_PPC_EMB_RELST_HI
2810 BFD_RELOC_PPC_EMB_RELST_HA
2812 BFD_RELOC_PPC_EMB_BIT_FLD
2814 BFD_RELOC_PPC_EMB_RELSDA
2816 BFD_RELOC_PPC_VLE_REL8
2818 BFD_RELOC_PPC_VLE_REL15
2820 BFD_RELOC_PPC_VLE_REL24
2822 BFD_RELOC_PPC_VLE_LO16A
2824 BFD_RELOC_PPC_VLE_LO16D
2826 BFD_RELOC_PPC_VLE_HI16A
2828 BFD_RELOC_PPC_VLE_HI16D
2830 BFD_RELOC_PPC_VLE_HA16A
2832 BFD_RELOC_PPC_VLE_HA16D
2834 BFD_RELOC_PPC_VLE_SDA21
2836 BFD_RELOC_PPC_VLE_SDA21_LO
2838 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2840 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2842 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2844 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2846 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2848 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2850 BFD_RELOC_PPC64_HIGHER
2852 BFD_RELOC_PPC64_HIGHER_S
2854 BFD_RELOC_PPC64_HIGHEST
2856 BFD_RELOC_PPC64_HIGHEST_S
2858 BFD_RELOC_PPC64_TOC16_LO
2860 BFD_RELOC_PPC64_TOC16_HI
2862 BFD_RELOC_PPC64_TOC16_HA
2866 BFD_RELOC_PPC64_PLTGOT16
2868 BFD_RELOC_PPC64_PLTGOT16_LO
2870 BFD_RELOC_PPC64_PLTGOT16_HI
2872 BFD_RELOC_PPC64_PLTGOT16_HA
2874 BFD_RELOC_PPC64_ADDR16_DS
2876 BFD_RELOC_PPC64_ADDR16_LO_DS
2878 BFD_RELOC_PPC64_GOT16_DS
2880 BFD_RELOC_PPC64_GOT16_LO_DS
2882 BFD_RELOC_PPC64_PLT16_LO_DS
2884 BFD_RELOC_PPC64_SECTOFF_DS
2886 BFD_RELOC_PPC64_SECTOFF_LO_DS
2888 BFD_RELOC_PPC64_TOC16_DS
2890 BFD_RELOC_PPC64_TOC16_LO_DS
2892 BFD_RELOC_PPC64_PLTGOT16_DS
2894 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2896 Power(rs6000) and PowerPC relocations.
2905 BFD_RELOC_PPC_DTPMOD
2907 BFD_RELOC_PPC_TPREL16
2909 BFD_RELOC_PPC_TPREL16_LO
2911 BFD_RELOC_PPC_TPREL16_HI
2913 BFD_RELOC_PPC_TPREL16_HA
2917 BFD_RELOC_PPC_DTPREL16
2919 BFD_RELOC_PPC_DTPREL16_LO
2921 BFD_RELOC_PPC_DTPREL16_HI
2923 BFD_RELOC_PPC_DTPREL16_HA
2925 BFD_RELOC_PPC_DTPREL
2927 BFD_RELOC_PPC_GOT_TLSGD16
2929 BFD_RELOC_PPC_GOT_TLSGD16_LO
2931 BFD_RELOC_PPC_GOT_TLSGD16_HI
2933 BFD_RELOC_PPC_GOT_TLSGD16_HA
2935 BFD_RELOC_PPC_GOT_TLSLD16
2937 BFD_RELOC_PPC_GOT_TLSLD16_LO
2939 BFD_RELOC_PPC_GOT_TLSLD16_HI
2941 BFD_RELOC_PPC_GOT_TLSLD16_HA
2943 BFD_RELOC_PPC_GOT_TPREL16
2945 BFD_RELOC_PPC_GOT_TPREL16_LO
2947 BFD_RELOC_PPC_GOT_TPREL16_HI
2949 BFD_RELOC_PPC_GOT_TPREL16_HA
2951 BFD_RELOC_PPC_GOT_DTPREL16
2953 BFD_RELOC_PPC_GOT_DTPREL16_LO
2955 BFD_RELOC_PPC_GOT_DTPREL16_HI
2957 BFD_RELOC_PPC_GOT_DTPREL16_HA
2959 BFD_RELOC_PPC64_TPREL16_DS
2961 BFD_RELOC_PPC64_TPREL16_LO_DS
2963 BFD_RELOC_PPC64_TPREL16_HIGHER
2965 BFD_RELOC_PPC64_TPREL16_HIGHERA
2967 BFD_RELOC_PPC64_TPREL16_HIGHEST
2969 BFD_RELOC_PPC64_TPREL16_HIGHESTA
2971 BFD_RELOC_PPC64_DTPREL16_DS
2973 BFD_RELOC_PPC64_DTPREL16_LO_DS
2975 BFD_RELOC_PPC64_DTPREL16_HIGHER
2977 BFD_RELOC_PPC64_DTPREL16_HIGHERA
2979 BFD_RELOC_PPC64_DTPREL16_HIGHEST
2981 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
2983 PowerPC and PowerPC64 thread-local storage relocations.
2988 IBM 370/390 relocations
2993 The type of reloc used to build a constructor table - at the moment
2994 probably a 32 bit wide absolute relocation, but the target can choose.
2995 It generally does map to one of the other relocation types.
2998 BFD_RELOC_ARM_PCREL_BRANCH
3000 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3001 not stored in the instruction.
3003 BFD_RELOC_ARM_PCREL_BLX
3005 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3006 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3007 field in the instruction.
3009 BFD_RELOC_THUMB_PCREL_BLX
3011 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3012 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3013 field in the instruction.
3015 BFD_RELOC_ARM_PCREL_CALL
3017 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3019 BFD_RELOC_ARM_PCREL_JUMP
3021 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3024 BFD_RELOC_THUMB_PCREL_BRANCH7
3026 BFD_RELOC_THUMB_PCREL_BRANCH9
3028 BFD_RELOC_THUMB_PCREL_BRANCH12
3030 BFD_RELOC_THUMB_PCREL_BRANCH20
3032 BFD_RELOC_THUMB_PCREL_BRANCH23
3034 BFD_RELOC_THUMB_PCREL_BRANCH25
3036 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3037 The lowest bit must be zero and is not stored in the instruction.
3038 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3039 "nn" one smaller in all cases. Note further that BRANCH23
3040 corresponds to R_ARM_THM_CALL.
3043 BFD_RELOC_ARM_OFFSET_IMM
3045 12-bit immediate offset, used in ARM-format ldr and str instructions.
3048 BFD_RELOC_ARM_THUMB_OFFSET
3050 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3053 BFD_RELOC_ARM_TARGET1
3055 Pc-relative or absolute relocation depending on target. Used for
3056 entries in .init_array sections.
3058 BFD_RELOC_ARM_ROSEGREL32
3060 Read-only segment base relative address.
3062 BFD_RELOC_ARM_SBREL32
3064 Data segment base relative address.
3066 BFD_RELOC_ARM_TARGET2
3068 This reloc is used for references to RTTI data from exception handling
3069 tables. The actual definition depends on the target. It may be a
3070 pc-relative or some form of GOT-indirect relocation.
3072 BFD_RELOC_ARM_PREL31
3074 31-bit PC relative address.
3080 BFD_RELOC_ARM_MOVW_PCREL
3082 BFD_RELOC_ARM_MOVT_PCREL
3084 BFD_RELOC_ARM_THUMB_MOVW
3086 BFD_RELOC_ARM_THUMB_MOVT
3088 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3090 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3092 Low and High halfword relocations for MOVW and MOVT instructions.
3095 BFD_RELOC_ARM_JUMP_SLOT
3097 BFD_RELOC_ARM_GLOB_DAT
3103 BFD_RELOC_ARM_RELATIVE
3105 BFD_RELOC_ARM_GOTOFF
3109 BFD_RELOC_ARM_GOT_PREL
3111 Relocations for setting up GOTs and PLTs for shared libraries.
3114 BFD_RELOC_ARM_TLS_GD32
3116 BFD_RELOC_ARM_TLS_LDO32
3118 BFD_RELOC_ARM_TLS_LDM32
3120 BFD_RELOC_ARM_TLS_DTPOFF32
3122 BFD_RELOC_ARM_TLS_DTPMOD32
3124 BFD_RELOC_ARM_TLS_TPOFF32
3126 BFD_RELOC_ARM_TLS_IE32
3128 BFD_RELOC_ARM_TLS_LE32
3130 BFD_RELOC_ARM_TLS_GOTDESC
3132 BFD_RELOC_ARM_TLS_CALL
3134 BFD_RELOC_ARM_THM_TLS_CALL
3136 BFD_RELOC_ARM_TLS_DESCSEQ
3138 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3140 BFD_RELOC_ARM_TLS_DESC
3142 ARM thread-local storage relocations.
3145 BFD_RELOC_ARM_ALU_PC_G0_NC
3147 BFD_RELOC_ARM_ALU_PC_G0
3149 BFD_RELOC_ARM_ALU_PC_G1_NC
3151 BFD_RELOC_ARM_ALU_PC_G1
3153 BFD_RELOC_ARM_ALU_PC_G2
3155 BFD_RELOC_ARM_LDR_PC_G0
3157 BFD_RELOC_ARM_LDR_PC_G1
3159 BFD_RELOC_ARM_LDR_PC_G2
3161 BFD_RELOC_ARM_LDRS_PC_G0
3163 BFD_RELOC_ARM_LDRS_PC_G1
3165 BFD_RELOC_ARM_LDRS_PC_G2
3167 BFD_RELOC_ARM_LDC_PC_G0
3169 BFD_RELOC_ARM_LDC_PC_G1
3171 BFD_RELOC_ARM_LDC_PC_G2
3173 BFD_RELOC_ARM_ALU_SB_G0_NC
3175 BFD_RELOC_ARM_ALU_SB_G0
3177 BFD_RELOC_ARM_ALU_SB_G1_NC
3179 BFD_RELOC_ARM_ALU_SB_G1
3181 BFD_RELOC_ARM_ALU_SB_G2
3183 BFD_RELOC_ARM_LDR_SB_G0
3185 BFD_RELOC_ARM_LDR_SB_G1
3187 BFD_RELOC_ARM_LDR_SB_G2
3189 BFD_RELOC_ARM_LDRS_SB_G0
3191 BFD_RELOC_ARM_LDRS_SB_G1
3193 BFD_RELOC_ARM_LDRS_SB_G2
3195 BFD_RELOC_ARM_LDC_SB_G0
3197 BFD_RELOC_ARM_LDC_SB_G1
3199 BFD_RELOC_ARM_LDC_SB_G2
3201 ARM group relocations.
3206 Annotation of BX instructions.
3209 BFD_RELOC_ARM_IRELATIVE
3211 ARM support for STT_GNU_IFUNC.
3214 BFD_RELOC_ARM_IMMEDIATE
3216 BFD_RELOC_ARM_ADRL_IMMEDIATE
3218 BFD_RELOC_ARM_T32_IMMEDIATE
3220 BFD_RELOC_ARM_T32_ADD_IMM
3222 BFD_RELOC_ARM_T32_IMM12
3224 BFD_RELOC_ARM_T32_ADD_PC12
3226 BFD_RELOC_ARM_SHIFT_IMM
3236 BFD_RELOC_ARM_CP_OFF_IMM
3238 BFD_RELOC_ARM_CP_OFF_IMM_S2
3240 BFD_RELOC_ARM_T32_CP_OFF_IMM
3242 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3244 BFD_RELOC_ARM_ADR_IMM
3246 BFD_RELOC_ARM_LDR_IMM
3248 BFD_RELOC_ARM_LITERAL
3250 BFD_RELOC_ARM_IN_POOL
3252 BFD_RELOC_ARM_OFFSET_IMM8
3254 BFD_RELOC_ARM_T32_OFFSET_U8
3256 BFD_RELOC_ARM_T32_OFFSET_IMM
3258 BFD_RELOC_ARM_HWLITERAL
3260 BFD_RELOC_ARM_THUMB_ADD
3262 BFD_RELOC_ARM_THUMB_IMM
3264 BFD_RELOC_ARM_THUMB_SHIFT
3266 These relocs are only used within the ARM assembler. They are not
3267 (at present) written to any object files.
3270 BFD_RELOC_SH_PCDISP8BY2
3272 BFD_RELOC_SH_PCDISP12BY2
3280 BFD_RELOC_SH_DISP12BY2
3282 BFD_RELOC_SH_DISP12BY4
3284 BFD_RELOC_SH_DISP12BY8
3288 BFD_RELOC_SH_DISP20BY8
3292 BFD_RELOC_SH_IMM4BY2
3294 BFD_RELOC_SH_IMM4BY4
3298 BFD_RELOC_SH_IMM8BY2
3300 BFD_RELOC_SH_IMM8BY4
3302 BFD_RELOC_SH_PCRELIMM8BY2
3304 BFD_RELOC_SH_PCRELIMM8BY4
3306 BFD_RELOC_SH_SWITCH16
3308 BFD_RELOC_SH_SWITCH32
3322 BFD_RELOC_SH_LOOP_START
3324 BFD_RELOC_SH_LOOP_END
3328 BFD_RELOC_SH_GLOB_DAT
3330 BFD_RELOC_SH_JMP_SLOT
3332 BFD_RELOC_SH_RELATIVE
3336 BFD_RELOC_SH_GOT_LOW16
3338 BFD_RELOC_SH_GOT_MEDLOW16
3340 BFD_RELOC_SH_GOT_MEDHI16
3342 BFD_RELOC_SH_GOT_HI16
3344 BFD_RELOC_SH_GOTPLT_LOW16
3346 BFD_RELOC_SH_GOTPLT_MEDLOW16
3348 BFD_RELOC_SH_GOTPLT_MEDHI16
3350 BFD_RELOC_SH_GOTPLT_HI16
3352 BFD_RELOC_SH_PLT_LOW16
3354 BFD_RELOC_SH_PLT_MEDLOW16
3356 BFD_RELOC_SH_PLT_MEDHI16
3358 BFD_RELOC_SH_PLT_HI16
3360 BFD_RELOC_SH_GOTOFF_LOW16
3362 BFD_RELOC_SH_GOTOFF_MEDLOW16
3364 BFD_RELOC_SH_GOTOFF_MEDHI16
3366 BFD_RELOC_SH_GOTOFF_HI16
3368 BFD_RELOC_SH_GOTPC_LOW16
3370 BFD_RELOC_SH_GOTPC_MEDLOW16
3372 BFD_RELOC_SH_GOTPC_MEDHI16
3374 BFD_RELOC_SH_GOTPC_HI16
3378 BFD_RELOC_SH_GLOB_DAT64
3380 BFD_RELOC_SH_JMP_SLOT64
3382 BFD_RELOC_SH_RELATIVE64
3384 BFD_RELOC_SH_GOT10BY4
3386 BFD_RELOC_SH_GOT10BY8
3388 BFD_RELOC_SH_GOTPLT10BY4
3390 BFD_RELOC_SH_GOTPLT10BY8
3392 BFD_RELOC_SH_GOTPLT32
3394 BFD_RELOC_SH_SHMEDIA_CODE
3400 BFD_RELOC_SH_IMMS6BY32
3406 BFD_RELOC_SH_IMMS10BY2
3408 BFD_RELOC_SH_IMMS10BY4
3410 BFD_RELOC_SH_IMMS10BY8
3416 BFD_RELOC_SH_IMM_LOW16
3418 BFD_RELOC_SH_IMM_LOW16_PCREL
3420 BFD_RELOC_SH_IMM_MEDLOW16
3422 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3424 BFD_RELOC_SH_IMM_MEDHI16
3426 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3428 BFD_RELOC_SH_IMM_HI16
3430 BFD_RELOC_SH_IMM_HI16_PCREL
3434 BFD_RELOC_SH_TLS_GD_32
3436 BFD_RELOC_SH_TLS_LD_32
3438 BFD_RELOC_SH_TLS_LDO_32
3440 BFD_RELOC_SH_TLS_IE_32
3442 BFD_RELOC_SH_TLS_LE_32
3444 BFD_RELOC_SH_TLS_DTPMOD32
3446 BFD_RELOC_SH_TLS_DTPOFF32
3448 BFD_RELOC_SH_TLS_TPOFF32
3452 BFD_RELOC_SH_GOTOFF20
3454 BFD_RELOC_SH_GOTFUNCDESC
3456 BFD_RELOC_SH_GOTFUNCDESC20
3458 BFD_RELOC_SH_GOTOFFFUNCDESC
3460 BFD_RELOC_SH_GOTOFFFUNCDESC20
3462 BFD_RELOC_SH_FUNCDESC
3464 Renesas / SuperH SH relocs. Not all of these appear in object files.
3467 BFD_RELOC_ARC_B22_PCREL
3470 ARC 22 bit pc-relative branch. The lowest two bits must be zero and are
3471 not stored in the instruction. The high 20 bits are installed in bits 26
3472 through 7 of the instruction.
3476 ARC 26 bit absolute branch. The lowest two bits must be zero and are not
3477 stored in the instruction. The high 24 bits are installed in bits 23
3481 BFD_RELOC_BFIN_16_IMM
3483 ADI Blackfin 16 bit immediate absolute reloc.
3485 BFD_RELOC_BFIN_16_HIGH
3487 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3489 BFD_RELOC_BFIN_4_PCREL
3491 ADI Blackfin 'a' part of LSETUP.
3493 BFD_RELOC_BFIN_5_PCREL
3497 BFD_RELOC_BFIN_16_LOW
3499 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3501 BFD_RELOC_BFIN_10_PCREL
3505 BFD_RELOC_BFIN_11_PCREL
3507 ADI Blackfin 'b' part of LSETUP.
3509 BFD_RELOC_BFIN_12_PCREL_JUMP
3513 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3515 ADI Blackfin Short jump, pcrel.
3517 BFD_RELOC_BFIN_24_PCREL_CALL_X
3519 ADI Blackfin Call.x not implemented.
3521 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3523 ADI Blackfin Long Jump pcrel.
3525 BFD_RELOC_BFIN_GOT17M4
3527 BFD_RELOC_BFIN_GOTHI
3529 BFD_RELOC_BFIN_GOTLO
3531 BFD_RELOC_BFIN_FUNCDESC
3533 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3535 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3537 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3539 BFD_RELOC_BFIN_FUNCDESC_VALUE
3541 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3543 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3545 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3547 BFD_RELOC_BFIN_GOTOFF17M4
3549 BFD_RELOC_BFIN_GOTOFFHI
3551 BFD_RELOC_BFIN_GOTOFFLO
3553 ADI Blackfin FD-PIC relocations.
3557 ADI Blackfin GOT relocation.
3559 BFD_RELOC_BFIN_PLTPC
3561 ADI Blackfin PLTPC relocation.
3563 BFD_ARELOC_BFIN_PUSH
3565 ADI Blackfin arithmetic relocation.
3567 BFD_ARELOC_BFIN_CONST
3569 ADI Blackfin arithmetic relocation.
3573 ADI Blackfin arithmetic relocation.
3577 ADI Blackfin arithmetic relocation.
3579 BFD_ARELOC_BFIN_MULT
3581 ADI Blackfin arithmetic relocation.
3585 ADI Blackfin arithmetic relocation.
3589 ADI Blackfin arithmetic relocation.
3591 BFD_ARELOC_BFIN_LSHIFT
3593 ADI Blackfin arithmetic relocation.
3595 BFD_ARELOC_BFIN_RSHIFT
3597 ADI Blackfin arithmetic relocation.
3601 ADI Blackfin arithmetic relocation.
3605 ADI Blackfin arithmetic relocation.
3609 ADI Blackfin arithmetic relocation.
3611 BFD_ARELOC_BFIN_LAND
3613 ADI Blackfin arithmetic relocation.
3617 ADI Blackfin arithmetic relocation.
3621 ADI Blackfin arithmetic relocation.
3625 ADI Blackfin arithmetic relocation.
3627 BFD_ARELOC_BFIN_COMP
3629 ADI Blackfin arithmetic relocation.
3631 BFD_ARELOC_BFIN_PAGE
3633 ADI Blackfin arithmetic relocation.
3635 BFD_ARELOC_BFIN_HWPAGE
3637 ADI Blackfin arithmetic relocation.
3639 BFD_ARELOC_BFIN_ADDR
3641 ADI Blackfin arithmetic relocation.
3644 BFD_RELOC_D10V_10_PCREL_R
3646 Mitsubishi D10V relocs.
3647 This is a 10-bit reloc with the right 2 bits
3650 BFD_RELOC_D10V_10_PCREL_L
3652 Mitsubishi D10V relocs.
3653 This is a 10-bit reloc with the right 2 bits
3654 assumed to be 0. This is the same as the previous reloc
3655 except it is in the left container, i.e.,
3656 shifted left 15 bits.
3660 This is an 18-bit reloc with the right 2 bits
3663 BFD_RELOC_D10V_18_PCREL
3665 This is an 18-bit reloc with the right 2 bits
3671 Mitsubishi D30V relocs.
3672 This is a 6-bit absolute reloc.
3674 BFD_RELOC_D30V_9_PCREL
3676 This is a 6-bit pc-relative reloc with
3677 the right 3 bits assumed to be 0.
3679 BFD_RELOC_D30V_9_PCREL_R
3681 This is a 6-bit pc-relative reloc with
3682 the right 3 bits assumed to be 0. Same
3683 as the previous reloc but on the right side
3688 This is a 12-bit absolute reloc with the
3689 right 3 bitsassumed to be 0.
3691 BFD_RELOC_D30V_15_PCREL
3693 This is a 12-bit pc-relative reloc with
3694 the right 3 bits assumed to be 0.
3696 BFD_RELOC_D30V_15_PCREL_R
3698 This is a 12-bit pc-relative reloc with
3699 the right 3 bits assumed to be 0. Same
3700 as the previous reloc but on the right side
3705 This is an 18-bit absolute reloc with
3706 the right 3 bits assumed to be 0.
3708 BFD_RELOC_D30V_21_PCREL
3710 This is an 18-bit pc-relative reloc with
3711 the right 3 bits assumed to be 0.
3713 BFD_RELOC_D30V_21_PCREL_R
3715 This is an 18-bit pc-relative reloc with
3716 the right 3 bits assumed to be 0. Same
3717 as the previous reloc but on the right side
3722 This is a 32-bit absolute reloc.
3724 BFD_RELOC_D30V_32_PCREL
3726 This is a 32-bit pc-relative reloc.
3729 BFD_RELOC_DLX_HI16_S
3744 BFD_RELOC_M32C_RL_JUMP
3746 BFD_RELOC_M32C_RL_1ADDR
3748 BFD_RELOC_M32C_RL_2ADDR
3750 Renesas M16C/M32C Relocations.
3755 Renesas M32R (formerly Mitsubishi M32R) relocs.
3756 This is a 24 bit absolute address.
3758 BFD_RELOC_M32R_10_PCREL
3760 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3762 BFD_RELOC_M32R_18_PCREL
3764 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3766 BFD_RELOC_M32R_26_PCREL
3768 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3770 BFD_RELOC_M32R_HI16_ULO
3772 This is a 16-bit reloc containing the high 16 bits of an address
3773 used when the lower 16 bits are treated as unsigned.
3775 BFD_RELOC_M32R_HI16_SLO
3777 This is a 16-bit reloc containing the high 16 bits of an address
3778 used when the lower 16 bits are treated as signed.
3782 This is a 16-bit reloc containing the lower 16 bits of an address.
3784 BFD_RELOC_M32R_SDA16
3786 This is a 16-bit reloc containing the small data area offset for use in
3787 add3, load, and store instructions.
3789 BFD_RELOC_M32R_GOT24
3791 BFD_RELOC_M32R_26_PLTREL
3795 BFD_RELOC_M32R_GLOB_DAT
3797 BFD_RELOC_M32R_JMP_SLOT
3799 BFD_RELOC_M32R_RELATIVE
3801 BFD_RELOC_M32R_GOTOFF
3803 BFD_RELOC_M32R_GOTOFF_HI_ULO
3805 BFD_RELOC_M32R_GOTOFF_HI_SLO
3807 BFD_RELOC_M32R_GOTOFF_LO
3809 BFD_RELOC_M32R_GOTPC24
3811 BFD_RELOC_M32R_GOT16_HI_ULO
3813 BFD_RELOC_M32R_GOT16_HI_SLO
3815 BFD_RELOC_M32R_GOT16_LO
3817 BFD_RELOC_M32R_GOTPC_HI_ULO
3819 BFD_RELOC_M32R_GOTPC_HI_SLO
3821 BFD_RELOC_M32R_GOTPC_LO
3827 BFD_RELOC_V850_9_PCREL
3829 This is a 9-bit reloc
3831 BFD_RELOC_V850_22_PCREL
3833 This is a 22-bit reloc
3836 BFD_RELOC_V850_SDA_16_16_OFFSET
3838 This is a 16 bit offset from the short data area pointer.
3840 BFD_RELOC_V850_SDA_15_16_OFFSET
3842 This is a 16 bit offset (of which only 15 bits are used) from the
3843 short data area pointer.
3845 BFD_RELOC_V850_ZDA_16_16_OFFSET
3847 This is a 16 bit offset from the zero data area pointer.
3849 BFD_RELOC_V850_ZDA_15_16_OFFSET
3851 This is a 16 bit offset (of which only 15 bits are used) from the
3852 zero data area pointer.
3854 BFD_RELOC_V850_TDA_6_8_OFFSET
3856 This is an 8 bit offset (of which only 6 bits are used) from the
3857 tiny data area pointer.
3859 BFD_RELOC_V850_TDA_7_8_OFFSET
3861 This is an 8bit offset (of which only 7 bits are used) from the tiny
3864 BFD_RELOC_V850_TDA_7_7_OFFSET
3866 This is a 7 bit offset from the tiny data area pointer.
3868 BFD_RELOC_V850_TDA_16_16_OFFSET
3870 This is a 16 bit offset from the tiny data area pointer.
3873 BFD_RELOC_V850_TDA_4_5_OFFSET
3875 This is a 5 bit offset (of which only 4 bits are used) from the tiny
3878 BFD_RELOC_V850_TDA_4_4_OFFSET
3880 This is a 4 bit offset from the tiny data area pointer.
3882 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
3884 This is a 16 bit offset from the short data area pointer, with the
3885 bits placed non-contiguously in the instruction.
3887 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
3889 This is a 16 bit offset from the zero data area pointer, with the
3890 bits placed non-contiguously in the instruction.
3892 BFD_RELOC_V850_CALLT_6_7_OFFSET
3894 This is a 6 bit offset from the call table base pointer.
3896 BFD_RELOC_V850_CALLT_16_16_OFFSET
3898 This is a 16 bit offset from the call table base pointer.
3900 BFD_RELOC_V850_LONGCALL
3902 Used for relaxing indirect function calls.
3904 BFD_RELOC_V850_LONGJUMP
3906 Used for relaxing indirect jumps.
3908 BFD_RELOC_V850_ALIGN
3910 Used to maintain alignment whilst relaxing.
3912 BFD_RELOC_V850_LO16_SPLIT_OFFSET
3914 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
3917 BFD_RELOC_V850_16_PCREL
3919 This is a 16-bit reloc.
3921 BFD_RELOC_V850_17_PCREL
3923 This is a 17-bit reloc.
3927 This is a 23-bit reloc.
3929 BFD_RELOC_V850_32_PCREL
3931 This is a 32-bit reloc.
3933 BFD_RELOC_V850_32_ABS
3935 This is a 32-bit reloc.
3937 BFD_RELOC_V850_16_SPLIT_OFFSET
3939 This is a 16-bit reloc.
3941 BFD_RELOC_V850_16_S1
3943 This is a 16-bit reloc.
3945 BFD_RELOC_V850_LO16_S1
3947 Low 16 bits. 16 bit shifted by 1.
3949 BFD_RELOC_V850_CALLT_15_16_OFFSET
3951 This is a 16 bit offset from the call table base pointer.
3953 BFD_RELOC_V850_32_GOTPCREL
3957 BFD_RELOC_V850_16_GOT
3961 BFD_RELOC_V850_32_GOT
3965 BFD_RELOC_V850_22_PLT_PCREL
3969 BFD_RELOC_V850_32_PLT_PCREL
3977 BFD_RELOC_V850_GLOB_DAT
3981 BFD_RELOC_V850_JMP_SLOT
3985 BFD_RELOC_V850_RELATIVE
3989 BFD_RELOC_V850_16_GOTOFF
3993 BFD_RELOC_V850_32_GOTOFF
4008 This is a 8bit DP reloc for the tms320c30, where the most
4009 significant 8 bits of a 24 bit word are placed into the least
4010 significant 8 bits of the opcode.
4013 BFD_RELOC_TIC54X_PARTLS7
4015 This is a 7bit reloc for the tms320c54x, where the least
4016 significant 7 bits of a 16 bit word are placed into the least
4017 significant 7 bits of the opcode.
4020 BFD_RELOC_TIC54X_PARTMS9
4022 This is a 9bit DP reloc for the tms320c54x, where the most
4023 significant 9 bits of a 16 bit word are placed into the least
4024 significant 9 bits of the opcode.
4029 This is an extended address 23-bit reloc for the tms320c54x.
4032 BFD_RELOC_TIC54X_16_OF_23
4034 This is a 16-bit reloc for the tms320c54x, where the least
4035 significant 16 bits of a 23-bit extended address are placed into
4039 BFD_RELOC_TIC54X_MS7_OF_23
4041 This is a reloc for the tms320c54x, where the most
4042 significant 7 bits of a 23-bit extended address are placed into
4046 BFD_RELOC_C6000_PCR_S21
4048 BFD_RELOC_C6000_PCR_S12
4050 BFD_RELOC_C6000_PCR_S10
4052 BFD_RELOC_C6000_PCR_S7
4054 BFD_RELOC_C6000_ABS_S16
4056 BFD_RELOC_C6000_ABS_L16
4058 BFD_RELOC_C6000_ABS_H16
4060 BFD_RELOC_C6000_SBR_U15_B
4062 BFD_RELOC_C6000_SBR_U15_H
4064 BFD_RELOC_C6000_SBR_U15_W
4066 BFD_RELOC_C6000_SBR_S16
4068 BFD_RELOC_C6000_SBR_L16_B
4070 BFD_RELOC_C6000_SBR_L16_H
4072 BFD_RELOC_C6000_SBR_L16_W
4074 BFD_RELOC_C6000_SBR_H16_B
4076 BFD_RELOC_C6000_SBR_H16_H
4078 BFD_RELOC_C6000_SBR_H16_W
4080 BFD_RELOC_C6000_SBR_GOT_U15_W
4082 BFD_RELOC_C6000_SBR_GOT_L16_W
4084 BFD_RELOC_C6000_SBR_GOT_H16_W
4086 BFD_RELOC_C6000_DSBT_INDEX
4088 BFD_RELOC_C6000_PREL31
4090 BFD_RELOC_C6000_COPY
4092 BFD_RELOC_C6000_JUMP_SLOT
4094 BFD_RELOC_C6000_EHTYPE
4096 BFD_RELOC_C6000_PCR_H16
4098 BFD_RELOC_C6000_PCR_L16
4100 BFD_RELOC_C6000_ALIGN
4102 BFD_RELOC_C6000_FPHEAD
4104 BFD_RELOC_C6000_NOCMP
4106 TMS320C6000 relocations.
4111 This is a 48 bit reloc for the FR30 that stores 32 bits.
4115 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4118 BFD_RELOC_FR30_6_IN_4
4120 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4123 BFD_RELOC_FR30_8_IN_8
4125 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4128 BFD_RELOC_FR30_9_IN_8
4130 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4133 BFD_RELOC_FR30_10_IN_8
4135 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4138 BFD_RELOC_FR30_9_PCREL
4140 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4141 short offset into 8 bits.
4143 BFD_RELOC_FR30_12_PCREL
4145 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4146 short offset into 11 bits.
4149 BFD_RELOC_MCORE_PCREL_IMM8BY4
4151 BFD_RELOC_MCORE_PCREL_IMM11BY2
4153 BFD_RELOC_MCORE_PCREL_IMM4BY2
4155 BFD_RELOC_MCORE_PCREL_32
4157 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4161 Motorola Mcore relocations.
4170 BFD_RELOC_MEP_PCREL8A2
4172 BFD_RELOC_MEP_PCREL12A2
4174 BFD_RELOC_MEP_PCREL17A2
4176 BFD_RELOC_MEP_PCREL24A2
4178 BFD_RELOC_MEP_PCABS24A2
4190 BFD_RELOC_MEP_TPREL7
4192 BFD_RELOC_MEP_TPREL7A2
4194 BFD_RELOC_MEP_TPREL7A4
4196 BFD_RELOC_MEP_UIMM24
4198 BFD_RELOC_MEP_ADDR24A4
4200 BFD_RELOC_MEP_GNU_VTINHERIT
4202 BFD_RELOC_MEP_GNU_VTENTRY
4204 Toshiba Media Processor Relocations.
4208 BFD_RELOC_METAG_HIADDR16
4210 BFD_RELOC_METAG_LOADDR16
4212 BFD_RELOC_METAG_RELBRANCH
4214 BFD_RELOC_METAG_GETSETOFF
4216 BFD_RELOC_METAG_HIOG
4218 BFD_RELOC_METAG_LOOG
4220 BFD_RELOC_METAG_REL8
4222 BFD_RELOC_METAG_REL16
4224 BFD_RELOC_METAG_HI16_GOTOFF
4226 BFD_RELOC_METAG_LO16_GOTOFF
4228 BFD_RELOC_METAG_GETSET_GOTOFF
4230 BFD_RELOC_METAG_GETSET_GOT
4232 BFD_RELOC_METAG_HI16_GOTPC
4234 BFD_RELOC_METAG_LO16_GOTPC
4236 BFD_RELOC_METAG_HI16_PLT
4238 BFD_RELOC_METAG_LO16_PLT
4240 BFD_RELOC_METAG_RELBRANCH_PLT
4242 BFD_RELOC_METAG_GOTOFF
4246 BFD_RELOC_METAG_COPY
4248 BFD_RELOC_METAG_JMP_SLOT
4250 BFD_RELOC_METAG_RELATIVE
4252 BFD_RELOC_METAG_GLOB_DAT
4254 BFD_RELOC_METAG_TLS_GD
4256 BFD_RELOC_METAG_TLS_LDM
4258 BFD_RELOC_METAG_TLS_LDO_HI16
4260 BFD_RELOC_METAG_TLS_LDO_LO16
4262 BFD_RELOC_METAG_TLS_LDO
4264 BFD_RELOC_METAG_TLS_IE
4266 BFD_RELOC_METAG_TLS_IENONPIC
4268 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4270 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4272 BFD_RELOC_METAG_TLS_TPOFF
4274 BFD_RELOC_METAG_TLS_DTPMOD
4276 BFD_RELOC_METAG_TLS_DTPOFF
4278 BFD_RELOC_METAG_TLS_LE
4280 BFD_RELOC_METAG_TLS_LE_HI16
4282 BFD_RELOC_METAG_TLS_LE_LO16
4284 Imagination Technologies Meta relocations.
4289 BFD_RELOC_MMIX_GETA_1
4291 BFD_RELOC_MMIX_GETA_2
4293 BFD_RELOC_MMIX_GETA_3
4295 These are relocations for the GETA instruction.
4297 BFD_RELOC_MMIX_CBRANCH
4299 BFD_RELOC_MMIX_CBRANCH_J
4301 BFD_RELOC_MMIX_CBRANCH_1
4303 BFD_RELOC_MMIX_CBRANCH_2
4305 BFD_RELOC_MMIX_CBRANCH_3
4307 These are relocations for a conditional branch instruction.
4309 BFD_RELOC_MMIX_PUSHJ
4311 BFD_RELOC_MMIX_PUSHJ_1
4313 BFD_RELOC_MMIX_PUSHJ_2
4315 BFD_RELOC_MMIX_PUSHJ_3
4317 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4319 These are relocations for the PUSHJ instruction.
4323 BFD_RELOC_MMIX_JMP_1
4325 BFD_RELOC_MMIX_JMP_2
4327 BFD_RELOC_MMIX_JMP_3
4329 These are relocations for the JMP instruction.
4331 BFD_RELOC_MMIX_ADDR19
4333 This is a relocation for a relative address as in a GETA instruction or
4336 BFD_RELOC_MMIX_ADDR27
4338 This is a relocation for a relative address as in a JMP instruction.
4340 BFD_RELOC_MMIX_REG_OR_BYTE
4342 This is a relocation for an instruction field that may be a general
4343 register or a value 0..255.
4347 This is a relocation for an instruction field that may be a general
4350 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4352 This is a relocation for two instruction fields holding a register and
4353 an offset, the equivalent of the relocation.
4355 BFD_RELOC_MMIX_LOCAL
4357 This relocation is an assertion that the expression is not allocated as
4358 a global register. It does not modify contents.
4361 BFD_RELOC_AVR_7_PCREL
4363 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4364 short offset into 7 bits.
4366 BFD_RELOC_AVR_13_PCREL
4368 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4369 short offset into 12 bits.
4373 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4374 program memory address) into 16 bits.
4376 BFD_RELOC_AVR_LO8_LDI
4378 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4379 data memory address) into 8 bit immediate value of LDI insn.
4381 BFD_RELOC_AVR_HI8_LDI
4383 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4384 of data memory address) into 8 bit immediate value of LDI insn.
4386 BFD_RELOC_AVR_HH8_LDI
4388 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4389 of program memory address) into 8 bit immediate value of LDI insn.
4391 BFD_RELOC_AVR_MS8_LDI
4393 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4394 of 32 bit value) into 8 bit immediate value of LDI insn.
4396 BFD_RELOC_AVR_LO8_LDI_NEG
4398 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4399 (usually data memory address) into 8 bit immediate value of SUBI insn.
4401 BFD_RELOC_AVR_HI8_LDI_NEG
4403 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4404 (high 8 bit of data memory address) into 8 bit immediate value of
4407 BFD_RELOC_AVR_HH8_LDI_NEG
4409 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4410 (most high 8 bit of program memory address) into 8 bit immediate value
4411 of LDI or SUBI insn.
4413 BFD_RELOC_AVR_MS8_LDI_NEG
4415 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4416 of 32 bit value) into 8 bit immediate value of LDI insn.
4418 BFD_RELOC_AVR_LO8_LDI_PM
4420 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4421 command address) into 8 bit immediate value of LDI insn.
4423 BFD_RELOC_AVR_LO8_LDI_GS
4425 This is a 16 bit reloc for the AVR that stores 8 bit value
4426 (command address) into 8 bit immediate value of LDI insn. If the address
4427 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4430 BFD_RELOC_AVR_HI8_LDI_PM
4432 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4433 of command address) into 8 bit immediate value of LDI insn.
4435 BFD_RELOC_AVR_HI8_LDI_GS
4437 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4438 of command address) into 8 bit immediate value of LDI insn. If the address
4439 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4442 BFD_RELOC_AVR_HH8_LDI_PM
4444 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4445 of command address) into 8 bit immediate value of LDI insn.
4447 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4449 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4450 (usually command address) into 8 bit immediate value of SUBI insn.
4452 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4454 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4455 (high 8 bit of 16 bit command address) into 8 bit immediate value
4458 BFD_RELOC_AVR_HH8_LDI_PM_NEG
4460 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4461 (high 6 bit of 22 bit command address) into 8 bit immediate
4466 This is a 32 bit reloc for the AVR that stores 23 bit value
4471 This is a 16 bit reloc for the AVR that stores all needed bits
4472 for absolute addressing with ldi with overflow check to linktime
4476 This is a 6 bit reloc for the AVR that stores offset for ldd/std
4479 BFD_RELOC_AVR_6_ADIW
4481 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
4486 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
4487 in .byte lo8(symbol)
4491 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
4492 in .byte hi8(symbol)
4496 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
4497 in .byte hlo8(symbol)
4502 BFD_RELOC_RL78_NEG16
4504 BFD_RELOC_RL78_NEG24
4506 BFD_RELOC_RL78_NEG32
4508 BFD_RELOC_RL78_16_OP
4510 BFD_RELOC_RL78_24_OP
4512 BFD_RELOC_RL78_32_OP
4520 BFD_RELOC_RL78_DIR3U_PCREL
4524 BFD_RELOC_RL78_GPRELB
4526 BFD_RELOC_RL78_GPRELW
4528 BFD_RELOC_RL78_GPRELL
4532 BFD_RELOC_RL78_OP_SUBTRACT
4534 BFD_RELOC_RL78_OP_NEG
4536 BFD_RELOC_RL78_OP_AND
4538 BFD_RELOC_RL78_OP_SHRA
4542 BFD_RELOC_RL78_ABS16
4544 BFD_RELOC_RL78_ABS16_REV
4546 BFD_RELOC_RL78_ABS32
4548 BFD_RELOC_RL78_ABS32_REV
4550 BFD_RELOC_RL78_ABS16U
4552 BFD_RELOC_RL78_ABS16UW
4554 BFD_RELOC_RL78_ABS16UL
4556 BFD_RELOC_RL78_RELAX
4564 Renesas RL78 Relocations.
4587 BFD_RELOC_RX_DIR3U_PCREL
4599 BFD_RELOC_RX_OP_SUBTRACT
4607 BFD_RELOC_RX_ABS16_REV
4611 BFD_RELOC_RX_ABS32_REV
4615 BFD_RELOC_RX_ABS16UW
4617 BFD_RELOC_RX_ABS16UL
4621 Renesas RX Relocations.
4634 32 bit PC relative PLT address.
4638 Copy symbol at runtime.
4640 BFD_RELOC_390_GLOB_DAT
4644 BFD_RELOC_390_JMP_SLOT
4648 BFD_RELOC_390_RELATIVE
4650 Adjust by program base.
4654 32 bit PC relative offset to GOT.
4660 BFD_RELOC_390_PC16DBL
4662 PC relative 16 bit shifted by 1.
4664 BFD_RELOC_390_PLT16DBL
4666 16 bit PC rel. PLT shifted by 1.
4668 BFD_RELOC_390_PC32DBL
4670 PC relative 32 bit shifted by 1.
4672 BFD_RELOC_390_PLT32DBL
4674 32 bit PC rel. PLT shifted by 1.
4676 BFD_RELOC_390_GOTPCDBL
4678 32 bit PC rel. GOT shifted by 1.
4686 64 bit PC relative PLT address.
4688 BFD_RELOC_390_GOTENT
4690 32 bit rel. offset to GOT entry.
4692 BFD_RELOC_390_GOTOFF64
4694 64 bit offset to GOT.
4696 BFD_RELOC_390_GOTPLT12
4698 12-bit offset to symbol-entry within GOT, with PLT handling.
4700 BFD_RELOC_390_GOTPLT16
4702 16-bit offset to symbol-entry within GOT, with PLT handling.
4704 BFD_RELOC_390_GOTPLT32
4706 32-bit offset to symbol-entry within GOT, with PLT handling.
4708 BFD_RELOC_390_GOTPLT64
4710 64-bit offset to symbol-entry within GOT, with PLT handling.
4712 BFD_RELOC_390_GOTPLTENT
4714 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
4716 BFD_RELOC_390_PLTOFF16
4718 16-bit rel. offset from the GOT to a PLT entry.
4720 BFD_RELOC_390_PLTOFF32
4722 32-bit rel. offset from the GOT to a PLT entry.
4724 BFD_RELOC_390_PLTOFF64
4726 64-bit rel. offset from the GOT to a PLT entry.
4729 BFD_RELOC_390_TLS_LOAD
4731 BFD_RELOC_390_TLS_GDCALL
4733 BFD_RELOC_390_TLS_LDCALL
4735 BFD_RELOC_390_TLS_GD32
4737 BFD_RELOC_390_TLS_GD64
4739 BFD_RELOC_390_TLS_GOTIE12
4741 BFD_RELOC_390_TLS_GOTIE32
4743 BFD_RELOC_390_TLS_GOTIE64
4745 BFD_RELOC_390_TLS_LDM32
4747 BFD_RELOC_390_TLS_LDM64
4749 BFD_RELOC_390_TLS_IE32
4751 BFD_RELOC_390_TLS_IE64
4753 BFD_RELOC_390_TLS_IEENT
4755 BFD_RELOC_390_TLS_LE32
4757 BFD_RELOC_390_TLS_LE64
4759 BFD_RELOC_390_TLS_LDO32
4761 BFD_RELOC_390_TLS_LDO64
4763 BFD_RELOC_390_TLS_DTPMOD
4765 BFD_RELOC_390_TLS_DTPOFF
4767 BFD_RELOC_390_TLS_TPOFF
4769 s390 tls relocations.
4776 BFD_RELOC_390_GOTPLT20
4778 BFD_RELOC_390_TLS_GOTIE20
4780 Long displacement extension.
4783 BFD_RELOC_390_IRELATIVE
4785 STT_GNU_IFUNC relocation.
4788 BFD_RELOC_SCORE_GPREL15
4791 Low 16 bit for load/store
4793 BFD_RELOC_SCORE_DUMMY2
4797 This is a 24-bit reloc with the right 1 bit assumed to be 0
4799 BFD_RELOC_SCORE_BRANCH
4801 This is a 19-bit reloc with the right 1 bit assumed to be 0
4803 BFD_RELOC_SCORE_IMM30
4805 This is a 32-bit reloc for 48-bit instructions.
4807 BFD_RELOC_SCORE_IMM32
4809 This is a 32-bit reloc for 48-bit instructions.
4811 BFD_RELOC_SCORE16_JMP
4813 This is a 11-bit reloc with the right 1 bit assumed to be 0
4815 BFD_RELOC_SCORE16_BRANCH
4817 This is a 8-bit reloc with the right 1 bit assumed to be 0
4819 BFD_RELOC_SCORE_BCMP
4821 This is a 9-bit reloc with the right 1 bit assumed to be 0
4823 BFD_RELOC_SCORE_GOT15
4825 BFD_RELOC_SCORE_GOT_LO16
4827 BFD_RELOC_SCORE_CALL15
4829 BFD_RELOC_SCORE_DUMMY_HI16
4831 Undocumented Score relocs
4836 Scenix IP2K - 9-bit register number / data address
4840 Scenix IP2K - 4-bit register/data bank number
4842 BFD_RELOC_IP2K_ADDR16CJP
4844 Scenix IP2K - low 13 bits of instruction word address
4846 BFD_RELOC_IP2K_PAGE3
4848 Scenix IP2K - high 3 bits of instruction word address
4850 BFD_RELOC_IP2K_LO8DATA
4852 BFD_RELOC_IP2K_HI8DATA
4854 BFD_RELOC_IP2K_EX8DATA
4856 Scenix IP2K - ext/low/high 8 bits of data address
4858 BFD_RELOC_IP2K_LO8INSN
4860 BFD_RELOC_IP2K_HI8INSN
4862 Scenix IP2K - low/high 8 bits of instruction word address
4864 BFD_RELOC_IP2K_PC_SKIP
4866 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
4870 Scenix IP2K - 16 bit word address in text section.
4872 BFD_RELOC_IP2K_FR_OFFSET
4874 Scenix IP2K - 7-bit sp or dp offset
4876 BFD_RELOC_VPE4KMATH_DATA
4878 BFD_RELOC_VPE4KMATH_INSN
4880 Scenix VPE4K coprocessor - data/insn-space addressing
4883 BFD_RELOC_VTABLE_INHERIT
4885 BFD_RELOC_VTABLE_ENTRY
4887 These two relocations are used by the linker to determine which of
4888 the entries in a C++ virtual function table are actually used. When
4889 the --gc-sections option is given, the linker will zero out the entries
4890 that are not used, so that the code for those functions need not be
4891 included in the output.
4893 VTABLE_INHERIT is a zero-space relocation used to describe to the
4894 linker the inheritance tree of a C++ virtual function table. The
4895 relocation's symbol should be the parent class' vtable, and the
4896 relocation should be located at the child vtable.
4898 VTABLE_ENTRY is a zero-space relocation that describes the use of a
4899 virtual function table entry. The reloc's symbol should refer to the
4900 table of the class mentioned in the code. Off of that base, an offset
4901 describes the entry that is being used. For Rela hosts, this offset
4902 is stored in the reloc's addend. For Rel hosts, we are forced to put
4903 this offset in the reloc's section offset.
4906 BFD_RELOC_IA64_IMM14
4908 BFD_RELOC_IA64_IMM22
4910 BFD_RELOC_IA64_IMM64
4912 BFD_RELOC_IA64_DIR32MSB
4914 BFD_RELOC_IA64_DIR32LSB
4916 BFD_RELOC_IA64_DIR64MSB
4918 BFD_RELOC_IA64_DIR64LSB
4920 BFD_RELOC_IA64_GPREL22
4922 BFD_RELOC_IA64_GPREL64I
4924 BFD_RELOC_IA64_GPREL32MSB
4926 BFD_RELOC_IA64_GPREL32LSB
4928 BFD_RELOC_IA64_GPREL64MSB
4930 BFD_RELOC_IA64_GPREL64LSB
4932 BFD_RELOC_IA64_LTOFF22
4934 BFD_RELOC_IA64_LTOFF64I
4936 BFD_RELOC_IA64_PLTOFF22
4938 BFD_RELOC_IA64_PLTOFF64I
4940 BFD_RELOC_IA64_PLTOFF64MSB
4942 BFD_RELOC_IA64_PLTOFF64LSB
4944 BFD_RELOC_IA64_FPTR64I
4946 BFD_RELOC_IA64_FPTR32MSB
4948 BFD_RELOC_IA64_FPTR32LSB
4950 BFD_RELOC_IA64_FPTR64MSB
4952 BFD_RELOC_IA64_FPTR64LSB
4954 BFD_RELOC_IA64_PCREL21B
4956 BFD_RELOC_IA64_PCREL21BI
4958 BFD_RELOC_IA64_PCREL21M
4960 BFD_RELOC_IA64_PCREL21F
4962 BFD_RELOC_IA64_PCREL22
4964 BFD_RELOC_IA64_PCREL60B
4966 BFD_RELOC_IA64_PCREL64I
4968 BFD_RELOC_IA64_PCREL32MSB
4970 BFD_RELOC_IA64_PCREL32LSB
4972 BFD_RELOC_IA64_PCREL64MSB
4974 BFD_RELOC_IA64_PCREL64LSB
4976 BFD_RELOC_IA64_LTOFF_FPTR22
4978 BFD_RELOC_IA64_LTOFF_FPTR64I
4980 BFD_RELOC_IA64_LTOFF_FPTR32MSB
4982 BFD_RELOC_IA64_LTOFF_FPTR32LSB
4984 BFD_RELOC_IA64_LTOFF_FPTR64MSB
4986 BFD_RELOC_IA64_LTOFF_FPTR64LSB
4988 BFD_RELOC_IA64_SEGREL32MSB
4990 BFD_RELOC_IA64_SEGREL32LSB
4992 BFD_RELOC_IA64_SEGREL64MSB
4994 BFD_RELOC_IA64_SEGREL64LSB
4996 BFD_RELOC_IA64_SECREL32MSB
4998 BFD_RELOC_IA64_SECREL32LSB
5000 BFD_RELOC_IA64_SECREL64MSB
5002 BFD_RELOC_IA64_SECREL64LSB
5004 BFD_RELOC_IA64_REL32MSB
5006 BFD_RELOC_IA64_REL32LSB
5008 BFD_RELOC_IA64_REL64MSB
5010 BFD_RELOC_IA64_REL64LSB
5012 BFD_RELOC_IA64_LTV32MSB
5014 BFD_RELOC_IA64_LTV32LSB
5016 BFD_RELOC_IA64_LTV64MSB
5018 BFD_RELOC_IA64_LTV64LSB
5020 BFD_RELOC_IA64_IPLTMSB
5022 BFD_RELOC_IA64_IPLTLSB
5026 BFD_RELOC_IA64_LTOFF22X
5028 BFD_RELOC_IA64_LDXMOV
5030 BFD_RELOC_IA64_TPREL14
5032 BFD_RELOC_IA64_TPREL22
5034 BFD_RELOC_IA64_TPREL64I
5036 BFD_RELOC_IA64_TPREL64MSB
5038 BFD_RELOC_IA64_TPREL64LSB
5040 BFD_RELOC_IA64_LTOFF_TPREL22
5042 BFD_RELOC_IA64_DTPMOD64MSB
5044 BFD_RELOC_IA64_DTPMOD64LSB
5046 BFD_RELOC_IA64_LTOFF_DTPMOD22
5048 BFD_RELOC_IA64_DTPREL14
5050 BFD_RELOC_IA64_DTPREL22
5052 BFD_RELOC_IA64_DTPREL64I
5054 BFD_RELOC_IA64_DTPREL32MSB
5056 BFD_RELOC_IA64_DTPREL32LSB
5058 BFD_RELOC_IA64_DTPREL64MSB
5060 BFD_RELOC_IA64_DTPREL64LSB
5062 BFD_RELOC_IA64_LTOFF_DTPREL22
5064 Intel IA64 Relocations.
5067 BFD_RELOC_M68HC11_HI8
5069 Motorola 68HC11 reloc.
5070 This is the 8 bit high part of an absolute address.
5072 BFD_RELOC_M68HC11_LO8
5074 Motorola 68HC11 reloc.
5075 This is the 8 bit low part of an absolute address.
5077 BFD_RELOC_M68HC11_3B
5079 Motorola 68HC11 reloc.
5080 This is the 3 bit of a value.
5082 BFD_RELOC_M68HC11_RL_JUMP
5084 Motorola 68HC11 reloc.
5085 This reloc marks the beginning of a jump/call instruction.
5086 It is used for linker relaxation to correctly identify beginning
5087 of instruction and change some branches to use PC-relative
5090 BFD_RELOC_M68HC11_RL_GROUP
5092 Motorola 68HC11 reloc.
5093 This reloc marks a group of several instructions that gcc generates
5094 and for which the linker relaxation pass can modify and/or remove
5097 BFD_RELOC_M68HC11_LO16
5099 Motorola 68HC11 reloc.
5100 This is the 16-bit lower part of an address. It is used for 'call'
5101 instruction to specify the symbol address without any special
5102 transformation (due to memory bank window).
5104 BFD_RELOC_M68HC11_PAGE
5106 Motorola 68HC11 reloc.
5107 This is a 8-bit reloc that specifies the page number of an address.
5108 It is used by 'call' instruction to specify the page number of
5111 BFD_RELOC_M68HC11_24
5113 Motorola 68HC11 reloc.
5114 This is a 24-bit reloc that represents the address with a 16-bit
5115 value and a 8-bit page number. The symbol address is transformed
5116 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5118 BFD_RELOC_M68HC12_5B
5120 Motorola 68HC12 reloc.
5121 This is the 5 bits of a value.
5123 BFD_RELOC_XGATE_RL_JUMP
5125 Freescale XGATE reloc.
5126 This reloc marks the beginning of a bra/jal instruction.
5128 BFD_RELOC_XGATE_RL_GROUP
5130 Freescale XGATE reloc.
5131 This reloc marks a group of several instructions that gcc generates
5132 and for which the linker relaxation pass can modify and/or remove
5135 BFD_RELOC_XGATE_LO16
5137 Freescale XGATE reloc.
5138 This is the 16-bit lower part of an address. It is used for the '16-bit'
5141 BFD_RELOC_XGATE_GPAGE
5143 Freescale XGATE reloc.
5147 Freescale XGATE reloc.
5149 BFD_RELOC_XGATE_PCREL_9
5151 Freescale XGATE reloc.
5152 This is a 9-bit pc-relative reloc.
5154 BFD_RELOC_XGATE_PCREL_10
5156 Freescale XGATE reloc.
5157 This is a 10-bit pc-relative reloc.
5159 BFD_RELOC_XGATE_IMM8_LO
5161 Freescale XGATE reloc.
5162 This is the 16-bit lower part of an address. It is used for the '16-bit'
5165 BFD_RELOC_XGATE_IMM8_HI
5167 Freescale XGATE reloc.
5168 This is the 16-bit higher part of an address. It is used for the '16-bit'
5171 BFD_RELOC_XGATE_IMM3
5173 Freescale XGATE reloc.
5174 This is a 3-bit pc-relative reloc.
5176 BFD_RELOC_XGATE_IMM4
5178 Freescale XGATE reloc.
5179 This is a 4-bit pc-relative reloc.
5181 BFD_RELOC_XGATE_IMM5
5183 Freescale XGATE reloc.
5184 This is a 5-bit pc-relative reloc.
5186 BFD_RELOC_M68HC12_9B
5188 Motorola 68HC12 reloc.
5189 This is the 9 bits of a value.
5191 BFD_RELOC_M68HC12_16B
5193 Motorola 68HC12 reloc.
5194 This is the 16 bits of a value.
5196 BFD_RELOC_M68HC12_9_PCREL
5198 Motorola 68HC12/XGATE reloc.
5199 This is a PCREL9 branch.
5201 BFD_RELOC_M68HC12_10_PCREL
5203 Motorola 68HC12/XGATE reloc.
5204 This is a PCREL10 branch.
5206 BFD_RELOC_M68HC12_LO8XG
5208 Motorola 68HC12/XGATE reloc.
5209 This is the 8 bit low part of an absolute address and immediately precedes
5210 a matching HI8XG part.
5212 BFD_RELOC_M68HC12_HI8XG
5214 Motorola 68HC12/XGATE reloc.
5215 This is the 8 bit high part of an absolute address and immediately follows
5216 a matching LO8XG part.
5220 BFD_RELOC_16C_NUM08_C
5224 BFD_RELOC_16C_NUM16_C
5228 BFD_RELOC_16C_NUM32_C
5230 BFD_RELOC_16C_DISP04
5232 BFD_RELOC_16C_DISP04_C
5234 BFD_RELOC_16C_DISP08
5236 BFD_RELOC_16C_DISP08_C
5238 BFD_RELOC_16C_DISP16
5240 BFD_RELOC_16C_DISP16_C
5242 BFD_RELOC_16C_DISP24
5244 BFD_RELOC_16C_DISP24_C
5246 BFD_RELOC_16C_DISP24a
5248 BFD_RELOC_16C_DISP24a_C
5252 BFD_RELOC_16C_REG04_C
5254 BFD_RELOC_16C_REG04a
5256 BFD_RELOC_16C_REG04a_C
5260 BFD_RELOC_16C_REG14_C
5264 BFD_RELOC_16C_REG16_C
5268 BFD_RELOC_16C_REG20_C
5272 BFD_RELOC_16C_ABS20_C
5276 BFD_RELOC_16C_ABS24_C
5280 BFD_RELOC_16C_IMM04_C
5284 BFD_RELOC_16C_IMM16_C
5288 BFD_RELOC_16C_IMM20_C
5292 BFD_RELOC_16C_IMM24_C
5296 BFD_RELOC_16C_IMM32_C
5298 NS CR16C Relocations.
5303 BFD_RELOC_CR16_NUM16
5305 BFD_RELOC_CR16_NUM32
5307 BFD_RELOC_CR16_NUM32a
5309 BFD_RELOC_CR16_REGREL0
5311 BFD_RELOC_CR16_REGREL4
5313 BFD_RELOC_CR16_REGREL4a
5315 BFD_RELOC_CR16_REGREL14
5317 BFD_RELOC_CR16_REGREL14a
5319 BFD_RELOC_CR16_REGREL16
5321 BFD_RELOC_CR16_REGREL20
5323 BFD_RELOC_CR16_REGREL20a
5325 BFD_RELOC_CR16_ABS20
5327 BFD_RELOC_CR16_ABS24
5333 BFD_RELOC_CR16_IMM16
5335 BFD_RELOC_CR16_IMM20
5337 BFD_RELOC_CR16_IMM24
5339 BFD_RELOC_CR16_IMM32
5341 BFD_RELOC_CR16_IMM32a
5343 BFD_RELOC_CR16_DISP4
5345 BFD_RELOC_CR16_DISP8
5347 BFD_RELOC_CR16_DISP16
5349 BFD_RELOC_CR16_DISP20
5351 BFD_RELOC_CR16_DISP24
5353 BFD_RELOC_CR16_DISP24a
5355 BFD_RELOC_CR16_SWITCH8
5357 BFD_RELOC_CR16_SWITCH16
5359 BFD_RELOC_CR16_SWITCH32
5361 BFD_RELOC_CR16_GOT_REGREL20
5363 BFD_RELOC_CR16_GOTC_REGREL20
5365 BFD_RELOC_CR16_GLOB_DAT
5367 NS CR16 Relocations.
5374 BFD_RELOC_CRX_REL8_CMP
5382 BFD_RELOC_CRX_REGREL12
5384 BFD_RELOC_CRX_REGREL22
5386 BFD_RELOC_CRX_REGREL28
5388 BFD_RELOC_CRX_REGREL32
5404 BFD_RELOC_CRX_SWITCH8
5406 BFD_RELOC_CRX_SWITCH16
5408 BFD_RELOC_CRX_SWITCH32
5413 BFD_RELOC_CRIS_BDISP8
5415 BFD_RELOC_CRIS_UNSIGNED_5
5417 BFD_RELOC_CRIS_SIGNED_6
5419 BFD_RELOC_CRIS_UNSIGNED_6
5421 BFD_RELOC_CRIS_SIGNED_8
5423 BFD_RELOC_CRIS_UNSIGNED_8
5425 BFD_RELOC_CRIS_SIGNED_16
5427 BFD_RELOC_CRIS_UNSIGNED_16
5429 BFD_RELOC_CRIS_LAPCQ_OFFSET
5431 BFD_RELOC_CRIS_UNSIGNED_4
5433 These relocs are only used within the CRIS assembler. They are not
5434 (at present) written to any object files.
5438 BFD_RELOC_CRIS_GLOB_DAT
5440 BFD_RELOC_CRIS_JUMP_SLOT
5442 BFD_RELOC_CRIS_RELATIVE
5444 Relocs used in ELF shared libraries for CRIS.
5446 BFD_RELOC_CRIS_32_GOT
5448 32-bit offset to symbol-entry within GOT.
5450 BFD_RELOC_CRIS_16_GOT
5452 16-bit offset to symbol-entry within GOT.
5454 BFD_RELOC_CRIS_32_GOTPLT
5456 32-bit offset to symbol-entry within GOT, with PLT handling.
5458 BFD_RELOC_CRIS_16_GOTPLT
5460 16-bit offset to symbol-entry within GOT, with PLT handling.
5462 BFD_RELOC_CRIS_32_GOTREL
5464 32-bit offset to symbol, relative to GOT.
5466 BFD_RELOC_CRIS_32_PLT_GOTREL
5468 32-bit offset to symbol with PLT entry, relative to GOT.
5470 BFD_RELOC_CRIS_32_PLT_PCREL
5472 32-bit offset to symbol with PLT entry, relative to this relocation.
5475 BFD_RELOC_CRIS_32_GOT_GD
5477 BFD_RELOC_CRIS_16_GOT_GD
5479 BFD_RELOC_CRIS_32_GD
5483 BFD_RELOC_CRIS_32_DTPREL
5485 BFD_RELOC_CRIS_16_DTPREL
5487 BFD_RELOC_CRIS_32_GOT_TPREL
5489 BFD_RELOC_CRIS_16_GOT_TPREL
5491 BFD_RELOC_CRIS_32_TPREL
5493 BFD_RELOC_CRIS_16_TPREL
5495 BFD_RELOC_CRIS_DTPMOD
5497 BFD_RELOC_CRIS_32_IE
5499 Relocs used in TLS code for CRIS.
5504 BFD_RELOC_860_GLOB_DAT
5506 BFD_RELOC_860_JUMP_SLOT
5508 BFD_RELOC_860_RELATIVE
5518 BFD_RELOC_860_SPLIT0
5522 BFD_RELOC_860_SPLIT1
5526 BFD_RELOC_860_SPLIT2
5530 BFD_RELOC_860_LOGOT0
5532 BFD_RELOC_860_SPGOT0
5534 BFD_RELOC_860_LOGOT1
5536 BFD_RELOC_860_SPGOT1
5538 BFD_RELOC_860_LOGOTOFF0
5540 BFD_RELOC_860_SPGOTOFF0
5542 BFD_RELOC_860_LOGOTOFF1
5544 BFD_RELOC_860_SPGOTOFF1
5546 BFD_RELOC_860_LOGOTOFF2
5548 BFD_RELOC_860_LOGOTOFF3
5552 BFD_RELOC_860_HIGHADJ
5556 BFD_RELOC_860_HAGOTOFF
5564 BFD_RELOC_860_HIGOTOFF
5566 Intel i860 Relocations.
5569 BFD_RELOC_OPENRISC_ABS_26
5571 BFD_RELOC_OPENRISC_REL_26
5573 OpenRISC Relocations.
5576 BFD_RELOC_H8_DIR16A8
5578 BFD_RELOC_H8_DIR16R8
5580 BFD_RELOC_H8_DIR24A8
5582 BFD_RELOC_H8_DIR24R8
5584 BFD_RELOC_H8_DIR32A16
5589 BFD_RELOC_XSTORMY16_REL_12
5591 BFD_RELOC_XSTORMY16_12
5593 BFD_RELOC_XSTORMY16_24
5595 BFD_RELOC_XSTORMY16_FPTR16
5597 Sony Xstormy16 Relocations.
5602 Self-describing complex relocations.
5614 Infineon Relocations.
5617 BFD_RELOC_VAX_GLOB_DAT
5619 BFD_RELOC_VAX_JMP_SLOT
5621 BFD_RELOC_VAX_RELATIVE
5623 Relocations used by VAX ELF.
5628 Morpho MT - 16 bit immediate relocation.
5632 Morpho MT - Hi 16 bits of an address.
5636 Morpho MT - Low 16 bits of an address.
5638 BFD_RELOC_MT_GNU_VTINHERIT
5640 Morpho MT - Used to tell the linker which vtable entries are used.
5642 BFD_RELOC_MT_GNU_VTENTRY
5644 Morpho MT - Used to tell the linker which vtable entries are used.
5646 BFD_RELOC_MT_PCINSN8
5648 Morpho MT - 8 bit immediate relocation.
5651 BFD_RELOC_MSP430_10_PCREL
5653 BFD_RELOC_MSP430_16_PCREL
5657 BFD_RELOC_MSP430_16_PCREL_BYTE
5659 BFD_RELOC_MSP430_16_BYTE
5661 BFD_RELOC_MSP430_2X_PCREL
5663 BFD_RELOC_MSP430_RL_PCREL
5665 msp430 specific relocation codes
5668 BFD_RELOC_IQ2000_OFFSET_16
5670 BFD_RELOC_IQ2000_OFFSET_21
5672 BFD_RELOC_IQ2000_UHI16
5677 BFD_RELOC_XTENSA_RTLD
5679 Special Xtensa relocation used only by PLT entries in ELF shared
5680 objects to indicate that the runtime linker should set the value
5681 to one of its own internal functions or data structures.
5683 BFD_RELOC_XTENSA_GLOB_DAT
5685 BFD_RELOC_XTENSA_JMP_SLOT
5687 BFD_RELOC_XTENSA_RELATIVE
5689 Xtensa relocations for ELF shared objects.
5691 BFD_RELOC_XTENSA_PLT
5693 Xtensa relocation used in ELF object files for symbols that may require
5694 PLT entries. Otherwise, this is just a generic 32-bit relocation.
5696 BFD_RELOC_XTENSA_DIFF8
5698 BFD_RELOC_XTENSA_DIFF16
5700 BFD_RELOC_XTENSA_DIFF32
5702 Xtensa relocations to mark the difference of two local symbols.
5703 These are only needed to support linker relaxation and can be ignored
5704 when not relaxing. The field is set to the value of the difference
5705 assuming no relaxation. The relocation encodes the position of the
5706 first symbol so the linker can determine whether to adjust the field
5709 BFD_RELOC_XTENSA_SLOT0_OP
5711 BFD_RELOC_XTENSA_SLOT1_OP
5713 BFD_RELOC_XTENSA_SLOT2_OP
5715 BFD_RELOC_XTENSA_SLOT3_OP
5717 BFD_RELOC_XTENSA_SLOT4_OP
5719 BFD_RELOC_XTENSA_SLOT5_OP
5721 BFD_RELOC_XTENSA_SLOT6_OP
5723 BFD_RELOC_XTENSA_SLOT7_OP
5725 BFD_RELOC_XTENSA_SLOT8_OP
5727 BFD_RELOC_XTENSA_SLOT9_OP
5729 BFD_RELOC_XTENSA_SLOT10_OP
5731 BFD_RELOC_XTENSA_SLOT11_OP
5733 BFD_RELOC_XTENSA_SLOT12_OP
5735 BFD_RELOC_XTENSA_SLOT13_OP
5737 BFD_RELOC_XTENSA_SLOT14_OP
5739 Generic Xtensa relocations for instruction operands. Only the slot
5740 number is encoded in the relocation. The relocation applies to the
5741 last PC-relative immediate operand, or if there are no PC-relative
5742 immediates, to the last immediate operand.
5744 BFD_RELOC_XTENSA_SLOT0_ALT
5746 BFD_RELOC_XTENSA_SLOT1_ALT
5748 BFD_RELOC_XTENSA_SLOT2_ALT
5750 BFD_RELOC_XTENSA_SLOT3_ALT
5752 BFD_RELOC_XTENSA_SLOT4_ALT
5754 BFD_RELOC_XTENSA_SLOT5_ALT
5756 BFD_RELOC_XTENSA_SLOT6_ALT
5758 BFD_RELOC_XTENSA_SLOT7_ALT
5760 BFD_RELOC_XTENSA_SLOT8_ALT
5762 BFD_RELOC_XTENSA_SLOT9_ALT
5764 BFD_RELOC_XTENSA_SLOT10_ALT
5766 BFD_RELOC_XTENSA_SLOT11_ALT
5768 BFD_RELOC_XTENSA_SLOT12_ALT
5770 BFD_RELOC_XTENSA_SLOT13_ALT
5772 BFD_RELOC_XTENSA_SLOT14_ALT
5774 Alternate Xtensa relocations. Only the slot is encoded in the
5775 relocation. The meaning of these relocations is opcode-specific.
5777 BFD_RELOC_XTENSA_OP0
5779 BFD_RELOC_XTENSA_OP1
5781 BFD_RELOC_XTENSA_OP2
5783 Xtensa relocations for backward compatibility. These have all been
5784 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
5786 BFD_RELOC_XTENSA_ASM_EXPAND
5788 Xtensa relocation to mark that the assembler expanded the
5789 instructions from an original target. The expansion size is
5790 encoded in the reloc size.
5792 BFD_RELOC_XTENSA_ASM_SIMPLIFY
5794 Xtensa relocation to mark that the linker should simplify
5795 assembler-expanded instructions. This is commonly used
5796 internally by the linker after analysis of a
5797 BFD_RELOC_XTENSA_ASM_EXPAND.
5799 BFD_RELOC_XTENSA_TLSDESC_FN
5801 BFD_RELOC_XTENSA_TLSDESC_ARG
5803 BFD_RELOC_XTENSA_TLS_DTPOFF
5805 BFD_RELOC_XTENSA_TLS_TPOFF
5807 BFD_RELOC_XTENSA_TLS_FUNC
5809 BFD_RELOC_XTENSA_TLS_ARG
5811 BFD_RELOC_XTENSA_TLS_CALL
5813 Xtensa TLS relocations.
5818 8 bit signed offset in (ix+d) or (iy+d).
5836 BFD_RELOC_LM32_BRANCH
5838 BFD_RELOC_LM32_16_GOT
5840 BFD_RELOC_LM32_GOTOFF_HI16
5842 BFD_RELOC_LM32_GOTOFF_LO16
5846 BFD_RELOC_LM32_GLOB_DAT
5848 BFD_RELOC_LM32_JMP_SLOT
5850 BFD_RELOC_LM32_RELATIVE
5852 Lattice Mico32 relocations.
5855 BFD_RELOC_MACH_O_SECTDIFF
5857 Difference between two section addreses. Must be followed by a
5858 BFD_RELOC_MACH_O_PAIR.
5860 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
5862 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
5864 BFD_RELOC_MACH_O_PAIR
5866 Pair of relocation. Contains the first symbol.
5869 BFD_RELOC_MACH_O_X86_64_BRANCH32
5871 BFD_RELOC_MACH_O_X86_64_BRANCH8
5873 PCREL relocations. They are marked as branch to create PLT entry if
5876 BFD_RELOC_MACH_O_X86_64_GOT
5878 Used when referencing a GOT entry.
5880 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
5882 Used when loading a GOT entry with movq. It is specially marked so that
5883 the linker could optimize the movq to a leaq if possible.
5885 BFD_RELOC_MACH_O_X86_64_SUBTRACTOR32
5887 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
5889 BFD_RELOC_MACH_O_X86_64_SUBTRACTOR64
5891 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
5893 BFD_RELOC_MACH_O_X86_64_PCREL32_1
5895 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
5897 BFD_RELOC_MACH_O_X86_64_PCREL32_2
5899 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
5901 BFD_RELOC_MACH_O_X86_64_PCREL32_4
5903 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
5906 BFD_RELOC_MICROBLAZE_32_LO
5908 This is a 32 bit reloc for the microblaze that stores the
5909 low 16 bits of a value
5911 BFD_RELOC_MICROBLAZE_32_LO_PCREL
5913 This is a 32 bit pc-relative reloc for the microblaze that
5914 stores the low 16 bits of a value
5916 BFD_RELOC_MICROBLAZE_32_ROSDA
5918 This is a 32 bit reloc for the microblaze that stores a
5919 value relative to the read-only small data area anchor
5921 BFD_RELOC_MICROBLAZE_32_RWSDA
5923 This is a 32 bit reloc for the microblaze that stores a
5924 value relative to the read-write small data area anchor
5926 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
5928 This is a 32 bit reloc for the microblaze to handle
5929 expressions of the form "Symbol Op Symbol"
5931 BFD_RELOC_MICROBLAZE_64_NONE
5933 This is a 64 bit reloc that stores the 32 bit pc relative
5934 value in two words (with an imm instruction). No relocation is
5935 done here - only used for relaxing
5937 BFD_RELOC_MICROBLAZE_64_GOTPC
5939 This is a 64 bit reloc that stores the 32 bit pc relative
5940 value in two words (with an imm instruction). The relocation is
5941 PC-relative GOT offset
5943 BFD_RELOC_MICROBLAZE_64_GOT
5945 This is a 64 bit reloc that stores the 32 bit pc relative
5946 value in two words (with an imm instruction). The relocation is
5949 BFD_RELOC_MICROBLAZE_64_PLT
5951 This is a 64 bit reloc that stores the 32 bit pc relative
5952 value in two words (with an imm instruction). The relocation is
5953 PC-relative offset into PLT
5955 BFD_RELOC_MICROBLAZE_64_GOTOFF
5957 This is a 64 bit reloc that stores the 32 bit GOT relative
5958 value in two words (with an imm instruction). The relocation is
5959 relative offset from _GLOBAL_OFFSET_TABLE_
5961 BFD_RELOC_MICROBLAZE_32_GOTOFF
5963 This is a 32 bit reloc that stores the 32 bit GOT relative
5964 value in a word. The relocation is relative offset from
5965 _GLOBAL_OFFSET_TABLE_
5967 BFD_RELOC_MICROBLAZE_COPY
5969 This is used to tell the dynamic linker to copy the value out of
5970 the dynamic object into the runtime process image.
5972 BFD_RELOC_MICROBLAZE_64_TLS
5976 BFD_RELOC_MICROBLAZE_64_TLSGD
5978 This is a 64 bit reloc that stores the 32 bit GOT relative value
5979 of the GOT TLS GD info entry in two words (with an imm instruction). The
5980 relocation is GOT offset.
5982 BFD_RELOC_MICROBLAZE_64_TLSLD
5984 This is a 64 bit reloc that stores the 32 bit GOT relative value
5985 of the GOT TLS LD info entry in two words (with an imm instruction). The
5986 relocation is GOT offset.
5988 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
5990 This is a 32 bit reloc that stores the Module ID to GOT(n).
5992 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
5994 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
5996 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
5998 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6001 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6003 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6004 to two words (uses imm instruction).
6006 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6008 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6009 to two words (uses imm instruction).
6012 BFD_RELOC_AARCH64_ADD_LO12
6014 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
6015 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6017 BFD_RELOC_AARCH64_GOT_LD_PREL19
6019 AArch64 Load Literal instruction, holding a 19 bit PC relative word
6020 offset of the global offset table entry for a symbol. The lowest two
6021 bits must be zero and are not stored in the instruction, giving a 21
6022 bit signed byte offset. This relocation type requires signed overflow
6025 BFD_RELOC_AARCH64_ADR_GOT_PAGE
6027 Get to the page base of the global offset table entry for a symbol as
6028 part of an ADRP instruction using a 21 bit PC relative value.Used in
6029 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
6031 BFD_RELOC_AARCH64_ADR_HI21_PCREL
6033 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6034 offset, giving a 4KB aligned page base address.
6036 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
6038 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6039 offset, giving a 4KB aligned page base address, but with no overflow
6042 BFD_RELOC_AARCH64_ADR_LO21_PCREL
6044 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
6046 BFD_RELOC_AARCH64_BRANCH19
6048 AArch64 19 bit pc-relative conditional branch and compare & branch.
6049 The lowest two bits must be zero and are not stored in the instruction,
6050 giving a 21 bit signed byte offset.
6052 BFD_RELOC_AARCH64_CALL26
6054 AArch64 26 bit pc-relative unconditional branch and link.
6055 The lowest two bits must be zero and are not stored in the instruction,
6056 giving a 28 bit signed byte offset.
6058 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
6060 AArch64 pseudo relocation code to be used internally by the AArch64
6061 assembler and not (currently) written to any object files.
6063 BFD_RELOC_AARCH64_JUMP26
6065 AArch64 26 bit pc-relative unconditional branch.
6066 The lowest two bits must be zero and are not stored in the instruction,
6067 giving a 28 bit signed byte offset.
6069 BFD_RELOC_AARCH64_LD_LO19_PCREL
6071 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
6072 offset. The lowest two bits must be zero and are not stored in the
6073 instruction, giving a 21 bit signed byte offset.
6075 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
6077 Unsigned 12 bit byte offset for 64 bit load/store from the page of
6078 the GOT entry for this symbol. Used in conjunction with
6079 BFD_RELOC_AARCH64_ADR_GOTPAGE.
6081 BFD_RELOC_AARCH64_LDST_LO12
6083 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
6084 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6086 BFD_RELOC_AARCH64_LDST8_LO12
6088 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
6089 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6091 BFD_RELOC_AARCH64_LDST16_LO12
6093 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
6094 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6096 BFD_RELOC_AARCH64_LDST32_LO12
6098 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
6099 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6101 BFD_RELOC_AARCH64_LDST64_LO12
6103 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
6104 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6106 BFD_RELOC_AARCH64_LDST128_LO12
6108 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
6109 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6111 BFD_RELOC_AARCH64_MOVW_G0
6113 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6114 of an unsigned address/value.
6116 BFD_RELOC_AARCH64_MOVW_G0_S
6118 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6119 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6122 BFD_RELOC_AARCH64_MOVW_G0_NC
6124 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6125 an address/value. No overflow checking.
6127 BFD_RELOC_AARCH64_MOVW_G1
6129 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
6130 of an unsigned address/value.
6132 BFD_RELOC_AARCH64_MOVW_G1_NC
6134 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
6135 of an address/value. No overflow checking.
6137 BFD_RELOC_AARCH64_MOVW_G1_S
6139 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
6140 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6143 BFD_RELOC_AARCH64_MOVW_G2
6145 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
6146 of an unsigned address/value.
6148 BFD_RELOC_AARCH64_MOVW_G2_NC
6150 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
6151 of an address/value. No overflow checking.
6153 BFD_RELOC_AARCH64_MOVW_G2_S
6155 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
6156 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6159 BFD_RELOC_AARCH64_MOVW_G3
6161 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
6162 of a signed or unsigned address/value.
6164 BFD_RELOC_AARCH64_TLSDESC
6166 AArch64 TLS relocation.
6168 BFD_RELOC_AARCH64_TLSDESC_ADD
6170 AArch64 TLS DESC relocation.
6172 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
6174 AArch64 TLS DESC relocation.
6176 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE
6178 AArch64 TLS DESC relocation.
6180 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
6182 AArch64 TLS DESC relocation.
6184 BFD_RELOC_AARCH64_TLSDESC_CALL
6186 AArch64 TLS DESC relocation.
6188 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
6190 AArch64 TLS DESC relocation.
6192 BFD_RELOC_AARCH64_TLSDESC_LD64_PREL19
6194 AArch64 TLS DESC relocation.
6196 BFD_RELOC_AARCH64_TLSDESC_LDR
6198 AArch64 TLS DESC relocation.
6200 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
6202 AArch64 TLS DESC relocation.
6204 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
6206 AArch64 TLS DESC relocation.
6208 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
6210 Unsigned 12 bit byte offset to global offset table entry for a symbols
6211 tls_index structure. Used in conjunction with
6212 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
6214 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
6216 Get to the page base of the global offset table entry for a symbols
6217 tls_index structure as part of an adrp instruction using a 21 bit PC
6218 relative value. Used in conjunction with
6219 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
6221 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
6223 AArch64 TLS INITIAL EXEC relocation.
6225 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
6227 AArch64 TLS INITIAL EXEC relocation.
6229 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
6231 AArch64 TLS INITIAL EXEC relocation.
6233 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
6235 AArch64 TLS INITIAL EXEC relocation.
6237 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
6239 AArch64 TLS INITIAL EXEC relocation.
6241 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
6243 AArch64 TLS LOCAL EXEC relocation.
6245 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
6247 AArch64 TLS LOCAL EXEC relocation.
6249 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
6251 AArch64 TLS LOCAL EXEC relocation.
6253 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
6255 AArch64 TLS LOCAL EXEC relocation.
6257 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
6259 AArch64 TLS LOCAL EXEC relocation.
6261 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
6263 AArch64 TLS LOCAL EXEC relocation.
6265 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
6267 AArch64 TLS LOCAL EXEC relocation.
6269 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
6271 AArch64 TLS LOCAL EXEC relocation.
6273 BFD_RELOC_AARCH64_TLS_DTPMOD64
6275 AArch64 TLS relocation.
6277 BFD_RELOC_AARCH64_TLS_DTPREL64
6279 AArch64 TLS relocation.
6281 BFD_RELOC_AARCH64_TLS_TPREL64
6283 AArch64 TLS relocation.
6285 BFD_RELOC_AARCH64_TSTBR14
6287 AArch64 14 bit pc-relative test bit and branch.
6288 The lowest two bits must be zero and are not stored in the instruction,
6289 giving a 16 bit signed byte offset.
6292 BFD_RELOC_TILEPRO_COPY
6294 BFD_RELOC_TILEPRO_GLOB_DAT
6296 BFD_RELOC_TILEPRO_JMP_SLOT
6298 BFD_RELOC_TILEPRO_RELATIVE
6300 BFD_RELOC_TILEPRO_BROFF_X1
6302 BFD_RELOC_TILEPRO_JOFFLONG_X1
6304 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
6306 BFD_RELOC_TILEPRO_IMM8_X0
6308 BFD_RELOC_TILEPRO_IMM8_Y0
6310 BFD_RELOC_TILEPRO_IMM8_X1
6312 BFD_RELOC_TILEPRO_IMM8_Y1
6314 BFD_RELOC_TILEPRO_DEST_IMM8_X1
6316 BFD_RELOC_TILEPRO_MT_IMM15_X1
6318 BFD_RELOC_TILEPRO_MF_IMM15_X1
6320 BFD_RELOC_TILEPRO_IMM16_X0
6322 BFD_RELOC_TILEPRO_IMM16_X1
6324 BFD_RELOC_TILEPRO_IMM16_X0_LO
6326 BFD_RELOC_TILEPRO_IMM16_X1_LO
6328 BFD_RELOC_TILEPRO_IMM16_X0_HI
6330 BFD_RELOC_TILEPRO_IMM16_X1_HI
6332 BFD_RELOC_TILEPRO_IMM16_X0_HA
6334 BFD_RELOC_TILEPRO_IMM16_X1_HA
6336 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
6338 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
6340 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
6342 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
6344 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
6346 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
6348 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
6350 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
6352 BFD_RELOC_TILEPRO_IMM16_X0_GOT
6354 BFD_RELOC_TILEPRO_IMM16_X1_GOT
6356 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
6358 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
6360 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
6362 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
6364 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
6366 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
6368 BFD_RELOC_TILEPRO_MMSTART_X0
6370 BFD_RELOC_TILEPRO_MMEND_X0
6372 BFD_RELOC_TILEPRO_MMSTART_X1
6374 BFD_RELOC_TILEPRO_MMEND_X1
6376 BFD_RELOC_TILEPRO_SHAMT_X0
6378 BFD_RELOC_TILEPRO_SHAMT_X1
6380 BFD_RELOC_TILEPRO_SHAMT_Y0
6382 BFD_RELOC_TILEPRO_SHAMT_Y1
6384 BFD_RELOC_TILEPRO_TLS_GD_CALL
6386 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
6388 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
6390 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
6392 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
6394 BFD_RELOC_TILEPRO_TLS_IE_LOAD
6396 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
6398 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
6400 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
6402 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
6404 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
6406 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
6408 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
6410 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
6412 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
6414 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
6416 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
6418 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
6420 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
6422 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
6424 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
6426 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
6428 BFD_RELOC_TILEPRO_TLS_DTPMOD32
6430 BFD_RELOC_TILEPRO_TLS_DTPOFF32
6432 BFD_RELOC_TILEPRO_TLS_TPOFF32
6434 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
6436 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
6438 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
6440 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
6442 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
6444 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
6446 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
6448 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
6450 Tilera TILEPro Relocations.
6452 BFD_RELOC_TILEGX_HW0
6454 BFD_RELOC_TILEGX_HW1
6456 BFD_RELOC_TILEGX_HW2
6458 BFD_RELOC_TILEGX_HW3
6460 BFD_RELOC_TILEGX_HW0_LAST
6462 BFD_RELOC_TILEGX_HW1_LAST
6464 BFD_RELOC_TILEGX_HW2_LAST
6466 BFD_RELOC_TILEGX_COPY
6468 BFD_RELOC_TILEGX_GLOB_DAT
6470 BFD_RELOC_TILEGX_JMP_SLOT
6472 BFD_RELOC_TILEGX_RELATIVE
6474 BFD_RELOC_TILEGX_BROFF_X1
6476 BFD_RELOC_TILEGX_JUMPOFF_X1
6478 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
6480 BFD_RELOC_TILEGX_IMM8_X0
6482 BFD_RELOC_TILEGX_IMM8_Y0
6484 BFD_RELOC_TILEGX_IMM8_X1
6486 BFD_RELOC_TILEGX_IMM8_Y1
6488 BFD_RELOC_TILEGX_DEST_IMM8_X1
6490 BFD_RELOC_TILEGX_MT_IMM14_X1
6492 BFD_RELOC_TILEGX_MF_IMM14_X1
6494 BFD_RELOC_TILEGX_MMSTART_X0
6496 BFD_RELOC_TILEGX_MMEND_X0
6498 BFD_RELOC_TILEGX_SHAMT_X0
6500 BFD_RELOC_TILEGX_SHAMT_X1
6502 BFD_RELOC_TILEGX_SHAMT_Y0
6504 BFD_RELOC_TILEGX_SHAMT_Y1
6506 BFD_RELOC_TILEGX_IMM16_X0_HW0
6508 BFD_RELOC_TILEGX_IMM16_X1_HW0
6510 BFD_RELOC_TILEGX_IMM16_X0_HW1
6512 BFD_RELOC_TILEGX_IMM16_X1_HW1
6514 BFD_RELOC_TILEGX_IMM16_X0_HW2
6516 BFD_RELOC_TILEGX_IMM16_X1_HW2
6518 BFD_RELOC_TILEGX_IMM16_X0_HW3
6520 BFD_RELOC_TILEGX_IMM16_X1_HW3
6522 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
6524 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
6526 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
6528 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
6530 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
6532 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
6534 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
6536 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
6538 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
6540 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
6542 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
6544 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
6546 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
6548 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
6550 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
6552 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
6554 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
6556 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
6558 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
6560 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
6562 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
6564 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
6566 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
6568 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
6570 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
6572 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
6574 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
6576 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
6578 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
6580 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
6582 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
6584 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
6586 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
6588 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
6590 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
6592 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
6594 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
6596 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
6598 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
6600 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
6602 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
6604 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
6606 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
6608 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
6610 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
6612 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
6614 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
6616 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
6618 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
6620 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
6622 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
6624 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
6626 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
6628 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
6630 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
6632 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
6634 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
6636 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
6638 BFD_RELOC_TILEGX_TLS_DTPMOD64
6640 BFD_RELOC_TILEGX_TLS_DTPOFF64
6642 BFD_RELOC_TILEGX_TLS_TPOFF64
6644 BFD_RELOC_TILEGX_TLS_DTPMOD32
6646 BFD_RELOC_TILEGX_TLS_DTPOFF32
6648 BFD_RELOC_TILEGX_TLS_TPOFF32
6650 BFD_RELOC_TILEGX_TLS_GD_CALL
6652 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
6654 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
6656 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
6658 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
6660 BFD_RELOC_TILEGX_TLS_IE_LOAD
6662 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
6664 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
6666 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
6668 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
6670 Tilera TILE-Gx Relocations.
6672 BFD_RELOC_EPIPHANY_SIMM8
6674 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
6676 BFD_RELOC_EPIPHANY_SIMM24
6678 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
6680 BFD_RELOC_EPIPHANY_HIGH
6682 Adapteva EPIPHANY - 16 most-significant bits of absolute address
6684 BFD_RELOC_EPIPHANY_LOW
6686 Adapteva EPIPHANY - 16 least-significant bits of absolute address
6688 BFD_RELOC_EPIPHANY_SIMM11
6690 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
6692 BFD_RELOC_EPIPHANY_IMM11
6694 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
6696 BFD_RELOC_EPIPHANY_IMM8
6698 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
6705 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
6710 bfd_reloc_type_lookup
6711 bfd_reloc_name_lookup
6714 reloc_howto_type *bfd_reloc_type_lookup
6715 (bfd *abfd, bfd_reloc_code_real_type code);
6716 reloc_howto_type *bfd_reloc_name_lookup
6717 (bfd *abfd, const char *reloc_name);
6720 Return a pointer to a howto structure which, when
6721 invoked, will perform the relocation @var{code} on data from the
6727 bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
6729 return BFD_SEND (abfd, reloc_type_lookup, (abfd, code));
6733 bfd_reloc_name_lookup (bfd *abfd, const char *reloc_name)
6735 return BFD_SEND (abfd, reloc_name_lookup, (abfd, reloc_name));
6738 static reloc_howto_type bfd_howto_32 =
6739 HOWTO (0, 00, 2, 32, FALSE, 0, complain_overflow_dont, 0, "VRT32", FALSE, 0xffffffff, 0xffffffff, TRUE);
6743 bfd_default_reloc_type_lookup
6746 reloc_howto_type *bfd_default_reloc_type_lookup
6747 (bfd *abfd, bfd_reloc_code_real_type code);
6750 Provides a default relocation lookup routine for any architecture.
6755 bfd_default_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
6759 case BFD_RELOC_CTOR:
6760 /* The type of reloc used in a ctor, which will be as wide as the
6761 address - so either a 64, 32, or 16 bitter. */
6762 switch (bfd_arch_bits_per_address (abfd))
6767 return &bfd_howto_32;
6781 bfd_get_reloc_code_name
6784 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
6787 Provides a printable name for the supplied relocation code.
6788 Useful mainly for printing error messages.
6792 bfd_get_reloc_code_name (bfd_reloc_code_real_type code)
6794 if (code > BFD_RELOC_UNUSED)
6796 return bfd_reloc_code_real_names[code];
6801 bfd_generic_relax_section
6804 bfd_boolean bfd_generic_relax_section
6807 struct bfd_link_info *,
6811 Provides default handling for relaxing for back ends which
6816 bfd_generic_relax_section (bfd *abfd ATTRIBUTE_UNUSED,
6817 asection *section ATTRIBUTE_UNUSED,
6818 struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
6821 if (link_info->relocatable)
6822 (*link_info->callbacks->einfo)
6823 (_("%P%F: --relax and -r may not be used together\n"));
6831 bfd_generic_gc_sections
6834 bfd_boolean bfd_generic_gc_sections
6835 (bfd *, struct bfd_link_info *);
6838 Provides default handling for relaxing for back ends which
6839 don't do section gc -- i.e., does nothing.
6843 bfd_generic_gc_sections (bfd *abfd ATTRIBUTE_UNUSED,
6844 struct bfd_link_info *info ATTRIBUTE_UNUSED)
6851 bfd_generic_lookup_section_flags
6854 bfd_boolean bfd_generic_lookup_section_flags
6855 (struct bfd_link_info *, struct flag_info *, asection *);
6858 Provides default handling for section flags lookup
6859 -- i.e., does nothing.
6860 Returns FALSE if the section should be omitted, otherwise TRUE.
6864 bfd_generic_lookup_section_flags (struct bfd_link_info *info ATTRIBUTE_UNUSED,
6865 struct flag_info *flaginfo,
6866 asection *section ATTRIBUTE_UNUSED)
6868 if (flaginfo != NULL)
6870 (*_bfd_error_handler) (_("INPUT_SECTION_FLAGS are not supported.\n"));
6878 bfd_generic_merge_sections
6881 bfd_boolean bfd_generic_merge_sections
6882 (bfd *, struct bfd_link_info *);
6885 Provides default handling for SEC_MERGE section merging for back ends
6886 which don't have SEC_MERGE support -- i.e., does nothing.
6890 bfd_generic_merge_sections (bfd *abfd ATTRIBUTE_UNUSED,
6891 struct bfd_link_info *link_info ATTRIBUTE_UNUSED)
6898 bfd_generic_get_relocated_section_contents
6901 bfd_byte *bfd_generic_get_relocated_section_contents
6903 struct bfd_link_info *link_info,
6904 struct bfd_link_order *link_order,
6906 bfd_boolean relocatable,
6910 Provides default handling of relocation effort for back ends
6911 which can't be bothered to do it efficiently.
6916 bfd_generic_get_relocated_section_contents (bfd *abfd,
6917 struct bfd_link_info *link_info,
6918 struct bfd_link_order *link_order,
6920 bfd_boolean relocatable,
6923 bfd *input_bfd = link_order->u.indirect.section->owner;
6924 asection *input_section = link_order->u.indirect.section;
6926 arelent **reloc_vector;
6929 reloc_size = bfd_get_reloc_upper_bound (input_bfd, input_section);
6933 /* Read in the section. */
6934 if (!bfd_get_full_section_contents (input_bfd, input_section, &data))
6937 if (reloc_size == 0)
6940 reloc_vector = (arelent **) bfd_malloc (reloc_size);
6941 if (reloc_vector == NULL)
6944 reloc_count = bfd_canonicalize_reloc (input_bfd,
6948 if (reloc_count < 0)
6951 if (reloc_count > 0)
6954 for (parent = reloc_vector; *parent != NULL; parent++)
6956 char *error_message = NULL;
6958 bfd_reloc_status_type r;
6960 symbol = *(*parent)->sym_ptr_ptr;
6961 if (symbol->section && discarded_section (symbol->section))
6964 static reloc_howto_type none_howto
6965 = HOWTO (0, 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL,
6966 "unused", FALSE, 0, 0, FALSE);
6968 p = data + (*parent)->address * bfd_octets_per_byte (input_bfd);
6969 _bfd_clear_contents ((*parent)->howto, input_bfd, input_section,
6971 (*parent)->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
6972 (*parent)->addend = 0;
6973 (*parent)->howto = &none_howto;
6977 r = bfd_perform_relocation (input_bfd,
6981 relocatable ? abfd : NULL,
6986 asection *os = input_section->output_section;
6988 /* A partial link, so keep the relocs. */
6989 os->orelocation[os->reloc_count] = *parent;
6993 if (r != bfd_reloc_ok)
6997 case bfd_reloc_undefined:
6998 if (!((*link_info->callbacks->undefined_symbol)
6999 (link_info, bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
7000 input_bfd, input_section, (*parent)->address,
7004 case bfd_reloc_dangerous:
7005 BFD_ASSERT (error_message != NULL);
7006 if (!((*link_info->callbacks->reloc_dangerous)
7007 (link_info, error_message, input_bfd, input_section,
7008 (*parent)->address)))
7011 case bfd_reloc_overflow:
7012 if (!((*link_info->callbacks->reloc_overflow)
7014 bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
7015 (*parent)->howto->name, (*parent)->addend,
7016 input_bfd, input_section, (*parent)->address)))
7019 case bfd_reloc_outofrange:
7021 This error can result when processing some partially
7022 complete binaries. Do not abort, but issue an error
7024 link_info->callbacks->einfo
7025 (_("%X%P: %B(%A): relocation \"%R\" goes out of range\n"),
7026 abfd, input_section, * parent);
7038 free (reloc_vector);
7042 free (reloc_vector);