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Add Xtensa port
[binutils.git] / bfd / xtensa-modules.c
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NC		 1/* Xtensa configuration-specific ISA information.
2 Copyright 2003 Free Software Foundation, Inc.
3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
19
20/* Automatically generated by gen-opcode-code - DO NOT EDIT! */
21
22#include <xtensa-isa.h>
23#include "xtensa-isa-internal.h"
24#include "ansidecl.h"
25
26#define BPW 32
27#define WINDEX(_n) ((_n) / BPW)
28#define BINDEX(_n) ((_n) %% BPW)
29
30static uint32 tie_do_reloc_l (uint32, uint32) ATTRIBUTE_UNUSED;
31static uint32 tie_undo_reloc_l (uint32, uint32) ATTRIBUTE_UNUSED;
32
33static uint32
34tie_do_reloc_l (uint32 addr, uint32 pc)
35{
36 return (addr - pc);
37}
38
39static uint32
40tie_undo_reloc_l (uint32 offset, uint32 pc)
41{
42 return (pc + offset);
43}
44
45xtensa_opcode_internal** get_opcodes (void);
46const int get_num_opcodes (void);
47int decode_insn (const xtensa_insnbuf);
48int interface_version (void);
49
50uint32 get_bbi_field (const xtensa_insnbuf);
51void set_bbi_field (xtensa_insnbuf, uint32);
52uint32 get_bbi4_field (const xtensa_insnbuf);
53void set_bbi4_field (xtensa_insnbuf, uint32);
54uint32 get_i_field (const xtensa_insnbuf);
55void set_i_field (xtensa_insnbuf, uint32);
56uint32 get_imm12_field (const xtensa_insnbuf);
57void set_imm12_field (xtensa_insnbuf, uint32);
58uint32 get_imm12b_field (const xtensa_insnbuf);
59void set_imm12b_field (xtensa_insnbuf, uint32);
60uint32 get_imm16_field (const xtensa_insnbuf);
61void set_imm16_field (xtensa_insnbuf, uint32);
62uint32 get_imm4_field (const xtensa_insnbuf);
63void set_imm4_field (xtensa_insnbuf, uint32);
64uint32 get_imm6_field (const xtensa_insnbuf);
65void set_imm6_field (xtensa_insnbuf, uint32);
66uint32 get_imm6hi_field (const xtensa_insnbuf);
67void set_imm6hi_field (xtensa_insnbuf, uint32);
68uint32 get_imm6lo_field (const xtensa_insnbuf);
69void set_imm6lo_field (xtensa_insnbuf, uint32);
70uint32 get_imm7_field (const xtensa_insnbuf);
71void set_imm7_field (xtensa_insnbuf, uint32);
72uint32 get_imm7hi_field (const xtensa_insnbuf);
73void set_imm7hi_field (xtensa_insnbuf, uint32);
74uint32 get_imm7lo_field (const xtensa_insnbuf);
75void set_imm7lo_field (xtensa_insnbuf, uint32);
76uint32 get_imm8_field (const xtensa_insnbuf);
77void set_imm8_field (xtensa_insnbuf, uint32);
78uint32 get_m_field (const xtensa_insnbuf);
79void set_m_field (xtensa_insnbuf, uint32);
80uint32 get_mn_field (const xtensa_insnbuf);
81void set_mn_field (xtensa_insnbuf, uint32);
82uint32 get_n_field (const xtensa_insnbuf);
83void set_n_field (xtensa_insnbuf, uint32);
84uint32 get_none_field (const xtensa_insnbuf);
85void set_none_field (xtensa_insnbuf, uint32);
86uint32 get_offset_field (const xtensa_insnbuf);
87void set_offset_field (xtensa_insnbuf, uint32);
88uint32 get_op0_field (const xtensa_insnbuf);
89void set_op0_field (xtensa_insnbuf, uint32);
90uint32 get_op1_field (const xtensa_insnbuf);
91void set_op1_field (xtensa_insnbuf, uint32);
92uint32 get_op2_field (const xtensa_insnbuf);
93void set_op2_field (xtensa_insnbuf, uint32);
94uint32 get_r_field (const xtensa_insnbuf);
95void set_r_field (xtensa_insnbuf, uint32);
96uint32 get_s_field (const xtensa_insnbuf);
97void set_s_field (xtensa_insnbuf, uint32);
98uint32 get_sa4_field (const xtensa_insnbuf);
99void set_sa4_field (xtensa_insnbuf, uint32);
100uint32 get_sae_field (const xtensa_insnbuf);
101void set_sae_field (xtensa_insnbuf, uint32);
102uint32 get_sae4_field (const xtensa_insnbuf);
103void set_sae4_field (xtensa_insnbuf, uint32);
104uint32 get_sal_field (const xtensa_insnbuf);
105void set_sal_field (xtensa_insnbuf, uint32);
106uint32 get_sar_field (const xtensa_insnbuf);
107void set_sar_field (xtensa_insnbuf, uint32);
108uint32 get_sas_field (const xtensa_insnbuf);
109void set_sas_field (xtensa_insnbuf, uint32);
110uint32 get_sas4_field (const xtensa_insnbuf);
111void set_sas4_field (xtensa_insnbuf, uint32);
112uint32 get_sr_field (const xtensa_insnbuf);
113void set_sr_field (xtensa_insnbuf, uint32);
114uint32 get_t_field (const xtensa_insnbuf);
115void set_t_field (xtensa_insnbuf, uint32);
116uint32 get_thi3_field (const xtensa_insnbuf);
117void set_thi3_field (xtensa_insnbuf, uint32);
118uint32 get_z_field (const xtensa_insnbuf);
119void set_z_field (xtensa_insnbuf, uint32);
120
121
122uint32
123get_bbi_field (const xtensa_insnbuf insn)
124{
125 return ((insn[0] & 0xf0000) >> 16) |
126 ((insn[0] & 0x100) >> 4);
127}
128
129void
130set_bbi_field (xtensa_insnbuf insn, uint32 val)
131{
132 insn[0] = (insn[0] & 0xfff0ffff) | ((val << 16) & 0xf0000);
133 insn[0] = (insn[0] & 0xfffffeff) | ((val << 4) & 0x100);
134}
135
136uint32
137get_bbi4_field (const xtensa_insnbuf insn)
138{
139 return ((insn[0] & 0x100) >> 8);
140}
141
142void
143set_bbi4_field (xtensa_insnbuf insn, uint32 val)
144{
145 insn[0] = (insn[0] & 0xfffffeff) | ((val << 8) & 0x100);
146}
147
148uint32
149get_i_field (const xtensa_insnbuf insn)
150{
151 return ((insn[0] & 0x80000) >> 19);
152}
153
154void
155set_i_field (xtensa_insnbuf insn, uint32 val)
156{
157 insn[0] = (insn[0] & 0xfff7ffff) | ((val << 19) & 0x80000);
158}
159
160uint32
161get_imm12_field (const xtensa_insnbuf insn)
162{
163 return ((insn[0] & 0xfff));
164}
165
166void
167set_imm12_field (xtensa_insnbuf insn, uint32 val)
168{
169 insn[0] = (insn[0] & 0xfffff000) | (val & 0xfff);
170}
171
172uint32
173get_imm12b_field (const xtensa_insnbuf insn)
174{
175 return ((insn[0] & 0xff)) |
176 ((insn[0] & 0xf000) >> 4);
177}
178
179void
180set_imm12b_field (xtensa_insnbuf insn, uint32 val)
181{
182 insn[0] = (insn[0] & 0xffffff00) | (val & 0xff);
183 insn[0] = (insn[0] & 0xffff0fff) | ((val << 4) & 0xf000);
184}
185
186uint32
187get_imm16_field (const xtensa_insnbuf insn)
188{
189 return ((insn[0] & 0xffff));
190}
191
192void
193set_imm16_field (xtensa_insnbuf insn, uint32 val)
194{
195 insn[0] = (insn[0] & 0xffff0000) | (val & 0xffff);
196}
197
198uint32
199get_imm4_field (const xtensa_insnbuf insn)
200{
201 return ((insn[0] & 0xf00) >> 8);
202}
203
204void
205set_imm4_field (xtensa_insnbuf insn, uint32 val)
206{
207 insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00);
208}
209
210uint32
211get_imm6_field (const xtensa_insnbuf insn)
212{
213 return ((insn[0] & 0xf00) >> 8) |
214 ((insn[0] & 0x30000) >> 12);
215}
216
217void
218set_imm6_field (xtensa_insnbuf insn, uint32 val)
219{
220 insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00);
221 insn[0] = (insn[0] & 0xfffcffff) | ((val << 12) & 0x30000);
222}
223
224uint32
225get_imm6hi_field (const xtensa_insnbuf insn)
226{
227 return ((insn[0] & 0x30000) >> 16);
228}
229
230void
231set_imm6hi_field (xtensa_insnbuf insn, uint32 val)
232{
233 insn[0] = (insn[0] & 0xfffcffff) | ((val << 16) & 0x30000);
234}
235
236uint32
237get_imm6lo_field (const xtensa_insnbuf insn)
238{
239 return ((insn[0] & 0xf00) >> 8);
240}
241
242void
243set_imm6lo_field (xtensa_insnbuf insn, uint32 val)
244{
245 insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00);
246}
247
248uint32
249get_imm7_field (const xtensa_insnbuf insn)
250{
251 return ((insn[0] & 0xf00) >> 8) |
252 ((insn[0] & 0x70000) >> 12);
253}
254
255void
256set_imm7_field (xtensa_insnbuf insn, uint32 val)
257{
258 insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00);
259 insn[0] = (insn[0] & 0xfff8ffff) | ((val << 12) & 0x70000);
260}
261
262uint32
263get_imm7hi_field (const xtensa_insnbuf insn)
264{
265 return ((insn[0] & 0x70000) >> 16);
266}
267
268void
269set_imm7hi_field (xtensa_insnbuf insn, uint32 val)
270{
271 insn[0] = (insn[0] & 0xfff8ffff) | ((val << 16) & 0x70000);
272}
273
274uint32
275get_imm7lo_field (const xtensa_insnbuf insn)
276{
277 return ((insn[0] & 0xf00) >> 8);
278}
279
280void
281set_imm7lo_field (xtensa_insnbuf insn, uint32 val)
282{
283 insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00);
284}
285
286uint32
287get_imm8_field (const xtensa_insnbuf insn)
288{
289 return ((insn[0] & 0xff));
290}
291
292void
293set_imm8_field (xtensa_insnbuf insn, uint32 val)
294{
295 insn[0] = (insn[0] & 0xffffff00) | (val & 0xff);
296}
297
298uint32
299get_m_field (const xtensa_insnbuf insn)
300{
301 return ((insn[0] & 0x30000) >> 16);
302}
303
304void
305set_m_field (xtensa_insnbuf insn, uint32 val)
306{
307 insn[0] = (insn[0] & 0xfffcffff) | ((val << 16) & 0x30000);
308}
309
310uint32
311get_mn_field (const xtensa_insnbuf insn)
312{
313 return ((insn[0] & 0x30000) >> 16) |
314 ((insn[0] & 0xc0000) >> 16);
315}
316
317void
318set_mn_field (xtensa_insnbuf insn, uint32 val)
319{
320 insn[0] = (insn[0] & 0xfffcffff) | ((val << 16) & 0x30000);
321 insn[0] = (insn[0] & 0xfff3ffff) | ((val << 16) & 0xc0000);
322}
323
324uint32
325get_n_field (const xtensa_insnbuf insn)
326{
327 return ((insn[0] & 0xc0000) >> 18);
328}
329
330void
331set_n_field (xtensa_insnbuf insn, uint32 val)
332{
333 insn[0] = (insn[0] & 0xfff3ffff) | ((val << 18) & 0xc0000);
334}
335
336uint32
337get_none_field (const xtensa_insnbuf insn)
338{
339 return ((insn[0] & 0x0));
340}
341
342void
343set_none_field (xtensa_insnbuf insn, uint32 val)
344{
345 insn[0] = (insn[0] & 0xffffffff) | (val & 0x0);
346}
347
348uint32
349get_offset_field (const xtensa_insnbuf insn)
350{
351 return ((insn[0] & 0x3ffff));
352}
353
354void
355set_offset_field (xtensa_insnbuf insn, uint32 val)
356{
357 insn[0] = (insn[0] & 0xfffc0000) | (val & 0x3ffff);
358}
359
360uint32
361get_op0_field (const xtensa_insnbuf insn)
362{
363 return ((insn[0] & 0xf00000) >> 20);
364}
365
366void
367set_op0_field (xtensa_insnbuf insn, uint32 val)
368{
369 insn[0] = (insn[0] & 0xff0fffff) | ((val << 20) & 0xf00000);
370}
371
372uint32
373get_op1_field (const xtensa_insnbuf insn)
374{
375 return ((insn[0] & 0xf0) >> 4);
376}
377
378void
379set_op1_field (xtensa_insnbuf insn, uint32 val)
380{
381 insn[0] = (insn[0] & 0xffffff0f) | ((val << 4) & 0xf0);
382}
383
384uint32
385get_op2_field (const xtensa_insnbuf insn)
386{
387 return ((insn[0] & 0xf));
388}
389
390void
391set_op2_field (xtensa_insnbuf insn, uint32 val)
392{
393 insn[0] = (insn[0] & 0xfffffff0) | (val & 0xf);
394}
395
396uint32
397get_r_field (const xtensa_insnbuf insn)
398{
399 return ((insn[0] & 0xf00) >> 8);
400}
401
402void
403set_r_field (xtensa_insnbuf insn, uint32 val)
404{
405 insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00);
406}
407
408uint32
409get_s_field (const xtensa_insnbuf insn)
410{
411 return ((insn[0] & 0xf000) >> 12);
412}
413
414void
415set_s_field (xtensa_insnbuf insn, uint32 val)
416{
417 insn[0] = (insn[0] & 0xffff0fff) | ((val << 12) & 0xf000);
418}
419
420uint32
421get_sa4_field (const xtensa_insnbuf insn)
422{
423 return ((insn[0] & 0x1));
424}
425
426void
427set_sa4_field (xtensa_insnbuf insn, uint32 val)
428{
429 insn[0] = (insn[0] & 0xfffffffe) | (val & 0x1);
430}
431
432uint32
433get_sae_field (const xtensa_insnbuf insn)
434{
435 return ((insn[0] & 0xf000) >> 12) |
436 ((insn[0] & 0x10));
437}
438
439void
440set_sae_field (xtensa_insnbuf insn, uint32 val)
441{
442 insn[0] = (insn[0] & 0xffff0fff) | ((val << 12) & 0xf000);
443 insn[0] = (insn[0] & 0xffffffef) | (val & 0x10);
444}
445
446uint32
447get_sae4_field (const xtensa_insnbuf insn)
448{
449 return ((insn[0] & 0x10) >> 4);
450}
451
452void
453set_sae4_field (xtensa_insnbuf insn, uint32 val)
454{
455 insn[0] = (insn[0] & 0xffffffef) | ((val << 4) & 0x10);
456}
457
458uint32
459get_sal_field (const xtensa_insnbuf insn)
460{
461 return ((insn[0] & 0xf0000) >> 16) |
462 ((insn[0] & 0x1) << 4);
463}
464
465void
466set_sal_field (xtensa_insnbuf insn, uint32 val)
467{
468 insn[0] = (insn[0] & 0xfff0ffff) | ((val << 16) & 0xf0000);
469 insn[0] = (insn[0] & 0xfffffffe) | ((val >> 4) & 0x1);
470}
471
472uint32
473get_sar_field (const xtensa_insnbuf insn)
474{
475 return ((insn[0] & 0xf000) >> 12) |
476 ((insn[0] & 0x1) << 4);
477}
478
479void
480set_sar_field (xtensa_insnbuf insn, uint32 val)
481{
482 insn[0] = (insn[0] & 0xffff0fff) | ((val << 12) & 0xf000);
483 insn[0] = (insn[0] & 0xfffffffe) | ((val >> 4) & 0x1);
484}
485
486uint32
487get_sas_field (const xtensa_insnbuf insn)
488{
489 return ((insn[0] & 0xf000) >> 12) |
490 ((insn[0] & 0x10000) >> 12);
491}
492
493void
494set_sas_field (xtensa_insnbuf insn, uint32 val)
495{
496 insn[0] = (insn[0] & 0xffff0fff) | ((val << 12) & 0xf000);
497 insn[0] = (insn[0] & 0xfffeffff) | ((val << 12) & 0x10000);
498}
499
500uint32
501get_sas4_field (const xtensa_insnbuf insn)
502{
503 return ((insn[0] & 0x10000) >> 16);
504}
505
506void
507set_sas4_field (xtensa_insnbuf insn, uint32 val)
508{
509 insn[0] = (insn[0] & 0xfffeffff) | ((val << 16) & 0x10000);
510}
511
512uint32
513get_sr_field (const xtensa_insnbuf insn)
514{
515 return ((insn[0] & 0xf00) >> 8) |
516 ((insn[0] & 0xf000) >> 8);
517}
518
519void
520set_sr_field (xtensa_insnbuf insn, uint32 val)
521{
522 insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00);
523 insn[0] = (insn[0] & 0xffff0fff) | ((val << 8) & 0xf000);
524}
525
526uint32
527get_t_field (const xtensa_insnbuf insn)
528{
529 return ((insn[0] & 0xf0000) >> 16);
530}
531
532void
533set_t_field (xtensa_insnbuf insn, uint32 val)
534{
535 insn[0] = (insn[0] & 0xfff0ffff) | ((val << 16) & 0xf0000);
536}
537
538uint32
539get_thi3_field (const xtensa_insnbuf insn)
540{
541 return ((insn[0] & 0xe0000) >> 17);
542}
543
544void
545set_thi3_field (xtensa_insnbuf insn, uint32 val)
546{
547 insn[0] = (insn[0] & 0xfff1ffff) | ((val << 17) & 0xe0000);
548}
549
550uint32
551get_z_field (const xtensa_insnbuf insn)
552{
553 return ((insn[0] & 0x40000) >> 18);
554}
555
556void
557set_z_field (xtensa_insnbuf insn, uint32 val)
558{
559 insn[0] = (insn[0] & 0xfffbffff) | ((val << 18) & 0x40000);
560}
561
562uint32 decode_b4constu (uint32);
563xtensa_encode_result encode_b4constu (uint32 *);
564uint32 decode_simm8x256 (uint32);
565xtensa_encode_result encode_simm8x256 (uint32 *);
566uint32 decode_soffset (uint32);
567xtensa_encode_result encode_soffset (uint32 *);
568uint32 decode_imm4 (uint32);
569xtensa_encode_result encode_imm4 (uint32 *);
570uint32 decode_op0 (uint32);
571xtensa_encode_result encode_op0 (uint32 *);
572uint32 decode_op1 (uint32);
573xtensa_encode_result encode_op1 (uint32 *);
574uint32 decode_imm6 (uint32);
575xtensa_encode_result encode_imm6 (uint32 *);
576uint32 decode_op2 (uint32);
577xtensa_encode_result encode_op2 (uint32 *);
578uint32 decode_imm7 (uint32);
579xtensa_encode_result encode_imm7 (uint32 *);
580uint32 decode_simm4 (uint32);
581xtensa_encode_result encode_simm4 (uint32 *);
582uint32 decode_ai4const (uint32);
583xtensa_encode_result encode_ai4const (uint32 *);
584uint32 decode_imm8 (uint32);
585xtensa_encode_result encode_imm8 (uint32 *);
586uint32 decode_sae (uint32);
587xtensa_encode_result encode_sae (uint32 *);
588uint32 decode_imm7lo (uint32);
589xtensa_encode_result encode_imm7lo (uint32 *);
590uint32 decode_simm7 (uint32);
591xtensa_encode_result encode_simm7 (uint32 *);
592uint32 decode_simm8 (uint32);
593xtensa_encode_result encode_simm8 (uint32 *);
594uint32 decode_uimm12x8 (uint32);
595xtensa_encode_result encode_uimm12x8 (uint32 *);
596uint32 decode_sal (uint32);
597xtensa_encode_result encode_sal (uint32 *);
598uint32 decode_uimm6 (uint32);
599xtensa_encode_result encode_uimm6 (uint32 *);
600uint32 decode_sas4 (uint32);
601xtensa_encode_result encode_sas4 (uint32 *);
602uint32 decode_uimm8 (uint32);
603xtensa_encode_result encode_uimm8 (uint32 *);
604uint32 decode_uimm16x4 (uint32);
605xtensa_encode_result encode_uimm16x4 (uint32 *);
606uint32 decode_sar (uint32);
607xtensa_encode_result encode_sar (uint32 *);
608uint32 decode_sa4 (uint32);
609xtensa_encode_result encode_sa4 (uint32 *);
610uint32 decode_sas (uint32);
611xtensa_encode_result encode_sas (uint32 *);
612uint32 decode_imm6hi (uint32);
613xtensa_encode_result encode_imm6hi (uint32 *);
614uint32 decode_bbi (uint32);
615xtensa_encode_result encode_bbi (uint32 *);
616uint32 decode_uimm8x2 (uint32);
617xtensa_encode_result encode_uimm8x2 (uint32 *);
618uint32 decode_uimm8x4 (uint32);
619xtensa_encode_result encode_uimm8x4 (uint32 *);
620uint32 decode_msalp32 (uint32);
621xtensa_encode_result encode_msalp32 (uint32 *);
622uint32 decode_bbi4 (uint32);
623xtensa_encode_result encode_bbi4 (uint32 *);
624uint32 decode_op2p1 (uint32);
625xtensa_encode_result encode_op2p1 (uint32 *);
626uint32 decode_soffsetx4 (uint32);
627xtensa_encode_result encode_soffsetx4 (uint32 *);
628uint32 decode_imm6lo (uint32);
629xtensa_encode_result encode_imm6lo (uint32 *);
630uint32 decode_imm12 (uint32);
631xtensa_encode_result encode_imm12 (uint32 *);
632uint32 decode_b4const (uint32);
633xtensa_encode_result encode_b4const (uint32 *);
634uint32 decode_i (uint32);
635xtensa_encode_result encode_i (uint32 *);
636uint32 decode_imm16 (uint32);
637xtensa_encode_result encode_imm16 (uint32 *);
638uint32 decode_mn (uint32);
639xtensa_encode_result encode_mn (uint32 *);
640uint32 decode_m (uint32);
641xtensa_encode_result encode_m (uint32 *);
642uint32 decode_n (uint32);
643xtensa_encode_result encode_n (uint32 *);
644uint32 decode_none (uint32);
645xtensa_encode_result encode_none (uint32 *);
646uint32 decode_imm12b (uint32);
647xtensa_encode_result encode_imm12b (uint32 *);
648uint32 decode_r (uint32);
649xtensa_encode_result encode_r (uint32 *);
650uint32 decode_s (uint32);
651xtensa_encode_result encode_s (uint32 *);
652uint32 decode_t (uint32);
653xtensa_encode_result encode_t (uint32 *);
654uint32 decode_thi3 (uint32);
655xtensa_encode_result encode_thi3 (uint32 *);
656uint32 decode_sae4 (uint32);
657xtensa_encode_result encode_sae4 (uint32 *);
658uint32 decode_offset (uint32);
659xtensa_encode_result encode_offset (uint32 *);
660uint32 decode_imm7hi (uint32);
661xtensa_encode_result encode_imm7hi (uint32 *);
662uint32 decode_uimm4x16 (uint32);
663xtensa_encode_result encode_uimm4x16 (uint32 *);
664uint32 decode_simm12b (uint32);
665xtensa_encode_result encode_simm12b (uint32 *);
666uint32 decode_lsi4x4 (uint32);
667xtensa_encode_result encode_lsi4x4 (uint32 *);
668uint32 decode_z (uint32);
669xtensa_encode_result encode_z (uint32 *);
670uint32 decode_simm12 (uint32);
671xtensa_encode_result encode_simm12 (uint32 *);
672uint32 decode_sr (uint32);
673xtensa_encode_result encode_sr (uint32 *);
674uint32 decode_nimm4x2 (uint32);
675xtensa_encode_result encode_nimm4x2 (uint32 *);
676
677
678static const uint32 b4constu_table[] = {
679 32768,
680 65536,
681 2,
682 3,
683 4,
684 5,
685 6,
686 7,
687 8,
688 10,
689 12,
690 16,
691 32,
692 64,
693 128,
694 256
695};
696
697uint32
698decode_b4constu (uint32 val)
699{
700 val = b4constu_table[val];
701 return val;
702}
703
704xtensa_encode_result
705encode_b4constu (uint32 *valp)
706{
707 uint32 val = *valp;
708 unsigned i;
709 for (i = 0; i < (1 << 4); i += 1)
710 if (b4constu_table[i] == val) goto found;
711 return xtensa_encode_result_not_in_table;
712 found:
713 val = i;
714 *valp = val;
715 return xtensa_encode_result_ok;
716}
717
718uint32
719decode_simm8x256 (uint32 val)
720{
721 val = (val ^ 0x80) - 0x80;
722 val <<= 8;
723 return val;
724}
725
726xtensa_encode_result
727encode_simm8x256 (uint32 *valp)
728{
729 uint32 val = *valp;
730 if ((val & ((1 << 8) - 1)) != 0)
731 return xtensa_encode_result_align;
732 val = (signed int) val >> 8;
733 if (((val + (1 << 7)) >> 8) != 0)
734 {
735 if ((signed int) val > 0)
736 return xtensa_encode_result_too_high;
737 else
738 return xtensa_encode_result_too_low;
739 }
740 *valp = val;
741 return xtensa_encode_result_ok;
742}
743
744uint32
745decode_soffset (uint32 val)
746{
747 val = (val ^ 0x20000) - 0x20000;
748 return val;
749}
750
751xtensa_encode_result
752encode_soffset (uint32 *valp)
753{
754 uint32 val = *valp;
755 if (((val + (1 << 17)) >> 18) != 0)
756 {
757 if ((signed int) val > 0)
758 return xtensa_encode_result_too_high;
759 else
760 return xtensa_encode_result_too_low;
761 }
762 *valp = val;
763 return xtensa_encode_result_ok;
764}
765
766uint32
767decode_imm4 (uint32 val)
768{
769 return val;
770}
771
772xtensa_encode_result
773encode_imm4 (uint32 *valp)
774{
775 uint32 val = *valp;
776 if ((val >> 4) != 0)
777 return xtensa_encode_result_too_high;
778 *valp = val;
779 return xtensa_encode_result_ok;
780}
781
782uint32
783decode_op0 (uint32 val)
784{
785 return val;
786}
787
788xtensa_encode_result
789encode_op0 (uint32 *valp)
790{
791 uint32 val = *valp;
792 if ((val >> 4) != 0)
793 return xtensa_encode_result_too_high;
794 *valp = val;
795 return xtensa_encode_result_ok;
796}
797
798uint32
799decode_op1 (uint32 val)
800{
801 return val;
802}
803
804xtensa_encode_result
805encode_op1 (uint32 *valp)
806{
807 uint32 val = *valp;
808 if ((val >> 4) != 0)
809 return xtensa_encode_result_too_high;
810 *valp = val;
811 return xtensa_encode_result_ok;
812}
813
814uint32
815decode_imm6 (uint32 val)
816{
817 return val;
818}
819
820xtensa_encode_result
821encode_imm6 (uint32 *valp)
822{
823 uint32 val = *valp;
824 if ((val >> 6) != 0)
825 return xtensa_encode_result_too_high;
826 *valp = val;
827 return xtensa_encode_result_ok;
828}
829
830uint32
831decode_op2 (uint32 val)
832{
833 return val;
834}
835
836xtensa_encode_result
837encode_op2 (uint32 *valp)
838{
839 uint32 val = *valp;
840 if ((val >> 4) != 0)
841 return xtensa_encode_result_too_high;
842 *valp = val;
843 return xtensa_encode_result_ok;
844}
845
846uint32
847decode_imm7 (uint32 val)
848{
849 return val;
850}
851
852xtensa_encode_result
853encode_imm7 (uint32 *valp)
854{
855 uint32 val = *valp;
856 if ((val >> 7) != 0)
857 return xtensa_encode_result_too_high;
858 *valp = val;
859 return xtensa_encode_result_ok;
860}
861
862uint32
863decode_simm4 (uint32 val)
864{
865 val = (val ^ 0x8) - 0x8;
866 return val;
867}
868
869xtensa_encode_result
870encode_simm4 (uint32 *valp)
871{
872 uint32 val = *valp;
873 if (((val + (1 << 3)) >> 4) != 0)
874 {
875 if ((signed int) val > 0)
876 return xtensa_encode_result_too_high;
877 else
878 return xtensa_encode_result_too_low;
879 }
880 *valp = val;
881 return xtensa_encode_result_ok;
882}
883
884static const uint32 ai4const_table[] = {
885 -1,
886 1,
887 2,
888 3,
889 4,
890 5,
891 6,
892 7,
893 8,
894 9,
895 10,
896 11,
897 12,
898 13,
899 14,
900 15
901};
902
903uint32
904decode_ai4const (uint32 val)
905{
906 val = ai4const_table[val];
907 return val;
908}
909
910xtensa_encode_result
911encode_ai4const (uint32 *valp)
912{
913 uint32 val = *valp;
914 unsigned i;
915 for (i = 0; i < (1 << 4); i += 1)
916 if (ai4const_table[i] == val) goto found;
917 return xtensa_encode_result_not_in_table;
918 found:
919 val = i;
920 *valp = val;
921 return xtensa_encode_result_ok;
922}
923
924uint32
925decode_imm8 (uint32 val)
926{
927 return val;
928}
929
930xtensa_encode_result
931encode_imm8 (uint32 *valp)
932{
933 uint32 val = *valp;
934 if ((val >> 8) != 0)
935 return xtensa_encode_result_too_high;
936 *valp = val;
937 return xtensa_encode_result_ok;
938}
939
940uint32
941decode_sae (uint32 val)
942{
943 return val;
944}
945
946xtensa_encode_result
947encode_sae (uint32 *valp)
948{
949 uint32 val = *valp;
950 if ((val >> 5) != 0)
951 return xtensa_encode_result_too_high;
952 *valp = val;
953 return xtensa_encode_result_ok;
954}
955
956uint32
957decode_imm7lo (uint32 val)
958{
959 return val;
960}
961
962xtensa_encode_result
963encode_imm7lo (uint32 *valp)
964{
965 uint32 val = *valp;
966 if ((val >> 4) != 0)
967 return xtensa_encode_result_too_high;
968 *valp = val;
969 return xtensa_encode_result_ok;
970}
971
972uint32
973decode_simm7 (uint32 val)
974{
975 if (val > 95)
976 val |= -32;
977 return val;
978}
979
980xtensa_encode_result
981encode_simm7 (uint32 *valp)
982{
983 uint32 val = *valp;
984 if ((signed int) val < -32)
985 return xtensa_encode_result_too_low;
986 if ((signed int) val > 95)
987 return xtensa_encode_result_too_high;
988 *valp = val;
989 return xtensa_encode_result_ok;
990}
991
992uint32
993decode_simm8 (uint32 val)
994{
995 val = (val ^ 0x80) - 0x80;
996 return val;
997}
998
999xtensa_encode_result
1000encode_simm8 (uint32 *valp)
1001{
1002 uint32 val = *valp;
1003 if (((val + (1 << 7)) >> 8) != 0)
1004 {
1005 if ((signed int) val > 0)
1006 return xtensa_encode_result_too_high;
1007 else
1008 return xtensa_encode_result_too_low;
1009 }
1010 *valp = val;
1011 return xtensa_encode_result_ok;
1012}
1013
1014uint32
1015decode_uimm12x8 (uint32 val)
1016{
1017 val <<= 3;
1018 return val;
1019}
1020
1021xtensa_encode_result
1022encode_uimm12x8 (uint32 *valp)
1023{
1024 uint32 val = *valp;
1025 if ((val & ((1 << 3) - 1)) != 0)
1026 return xtensa_encode_result_align;
1027 val = (signed int) val >> 3;
1028 if ((val >> 12) != 0)
1029 return xtensa_encode_result_too_high;
1030 *valp = val;
1031 return xtensa_encode_result_ok;
1032}
1033
1034uint32
1035decode_sal (uint32 val)
1036{
1037 return val;
1038}
1039
1040xtensa_encode_result
1041encode_sal (uint32 *valp)
1042{
1043 uint32 val = *valp;
1044 if ((val >> 5) != 0)
1045 return xtensa_encode_result_too_high;
1046 *valp = val;
1047 return xtensa_encode_result_ok;
1048}
1049
1050uint32
1051decode_uimm6 (uint32 val)
1052{
1053 return val;
1054}
1055
1056xtensa_encode_result
1057encode_uimm6 (uint32 *valp)
1058{
1059 uint32 val = *valp;
1060 if ((val >> 6) != 0)
1061 return xtensa_encode_result_too_high;
1062 *valp = val;
1063 return xtensa_encode_result_ok;
1064}
1065
1066uint32
1067decode_sas4 (uint32 val)
1068{
1069 return val;
1070}
1071
1072xtensa_encode_result
1073encode_sas4 (uint32 *valp)
1074{
1075 uint32 val = *valp;
1076 if ((val >> 1) != 0)
1077 return xtensa_encode_result_too_high;
1078 *valp = val;
1079 return xtensa_encode_result_ok;
1080}
1081
1082uint32
1083decode_uimm8 (uint32 val)
1084{
1085 return val;
1086}
1087
1088xtensa_encode_result
1089encode_uimm8 (uint32 *valp)
1090{
1091 uint32 val = *valp;
1092 if ((val >> 8) != 0)
1093 return xtensa_encode_result_too_high;
1094 *valp = val;
1095 return xtensa_encode_result_ok;
1096}
1097
1098uint32
1099decode_uimm16x4 (uint32 val)
1100{
1101 val |= -1 << 16;
1102 val <<= 2;
1103 return val;
1104}
1105
1106xtensa_encode_result
1107encode_uimm16x4 (uint32 *valp)
1108{
1109 uint32 val = *valp;
1110 if ((val & ((1 << 2) - 1)) != 0)
1111 return xtensa_encode_result_align;
1112 val = (signed int) val >> 2;
1113 if ((signed int) val >> 16 != -1)
1114 {
1115 if ((signed int) val >= 0)
1116 return xtensa_encode_result_too_high;
1117 else
1118 return xtensa_encode_result_too_low;
1119 }
1120 *valp = val;
1121 return xtensa_encode_result_ok;
1122}
1123
1124uint32
1125decode_sar (uint32 val)
1126{
1127 return val;
1128}
1129
1130xtensa_encode_result
1131encode_sar (uint32 *valp)
1132{
1133 uint32 val = *valp;
1134 if ((val >> 5) != 0)
1135 return xtensa_encode_result_too_high;
1136 *valp = val;
1137 return xtensa_encode_result_ok;
1138}
1139
1140uint32
1141decode_sa4 (uint32 val)
1142{
1143 return val;
1144}
1145
1146xtensa_encode_result
1147encode_sa4 (uint32 *valp)
1148{
1149 uint32 val = *valp;
1150 if ((val >> 1) != 0)
1151 return xtensa_encode_result_too_high;
1152 *valp = val;
1153 return xtensa_encode_result_ok;
1154}
1155
1156uint32
1157decode_sas (uint32 val)
1158{
1159 return val;
1160}
1161
1162xtensa_encode_result
1163encode_sas (uint32 *valp)
1164{
1165 uint32 val = *valp;
1166 if ((val >> 5) != 0)
1167 return xtensa_encode_result_too_high;
1168 *valp = val;
1169 return xtensa_encode_result_ok;
1170}
1171
1172uint32
1173decode_imm6hi (uint32 val)
1174{
1175 return val;
1176}
1177
1178xtensa_encode_result
1179encode_imm6hi (uint32 *valp)
1180{
1181 uint32 val = *valp;
1182 if ((val >> 2) != 0)
1183 return xtensa_encode_result_too_high;
1184 *valp = val;
1185 return xtensa_encode_result_ok;
1186}
1187
1188uint32
1189decode_bbi (uint32 val)
1190{
1191 return val;
1192}
1193
1194xtensa_encode_result
1195encode_bbi (uint32 *valp)
1196{
1197 uint32 val = *valp;
1198 if ((val >> 5) != 0)
1199 return xtensa_encode_result_too_high;
1200 *valp = val;
1201 return xtensa_encode_result_ok;
1202}
1203
1204uint32
1205decode_uimm8x2 (uint32 val)
1206{
1207 val <<= 1;
1208 return val;
1209}
1210
1211xtensa_encode_result
1212encode_uimm8x2 (uint32 *valp)
1213{
1214 uint32 val = *valp;
1215 if ((val & ((1 << 1) - 1)) != 0)
1216 return xtensa_encode_result_align;
1217 val = (signed int) val >> 1;
1218 if ((val >> 8) != 0)
1219 return xtensa_encode_result_too_high;
1220 *valp = val;
1221 return xtensa_encode_result_ok;
1222}
1223
1224uint32
1225decode_uimm8x4 (uint32 val)
1226{
1227 val <<= 2;
1228 return val;
1229}
1230
1231xtensa_encode_result
1232encode_uimm8x4 (uint32 *valp)
1233{
1234 uint32 val = *valp;
1235 if ((val & ((1 << 2) - 1)) != 0)
1236 return xtensa_encode_result_align;
1237 val = (signed int) val >> 2;
1238 if ((val >> 8) != 0)
1239 return xtensa_encode_result_too_high;
1240 *valp = val;
1241 return xtensa_encode_result_ok;
1242}
1243
1244static const uint32 mip32const_table[] = {
1245 32,
1246 31,
1247 30,
1248 29,
1249 28,
1250 27,
1251 26,
1252 25,
1253 24,
1254 23,
1255 22,
1256 21,
1257 20,
1258 19,
1259 18,
1260 17,
1261 16,
1262 15,
1263 14,
1264 13,
1265 12,
1266 11,
1267 10,
1268 9,
1269 8,
1270 7,
1271 6,
1272 5,
1273 4,
1274 3,
1275 2,
1276 1
1277};
1278
1279uint32
1280decode_msalp32 (uint32 val)
1281{
1282 val = mip32const_table[val];
1283 return val;
1284}
1285
1286xtensa_encode_result
1287encode_msalp32 (uint32 *valp)
1288{
1289 uint32 val = *valp;
1290 unsigned i;
1291 for (i = 0; i < (1 << 5); i += 1)
1292 if (mip32const_table[i] == val) goto found;
1293 return xtensa_encode_result_not_in_table;
1294 found:
1295 val = i;
1296 *valp = val;
1297 return xtensa_encode_result_ok;
1298}
1299
1300uint32
1301decode_bbi4 (uint32 val)
1302{
1303 return val;
1304}
1305
1306xtensa_encode_result
1307encode_bbi4 (uint32 *valp)
1308{
1309 uint32 val = *valp;
1310 if ((val >> 1) != 0)
1311 return xtensa_encode_result_too_high;
1312 *valp = val;
1313 return xtensa_encode_result_ok;
1314}
1315
1316static const uint32 i4p1const_table[] = {
1317 1,
1318 2,
1319 3,
1320 4,
1321 5,
1322 6,
1323 7,
1324 8,
1325 9,
1326 10,
1327 11,
1328 12,
1329 13,
1330 14,
1331 15,
1332 16
1333};
1334
1335uint32
1336decode_op2p1 (uint32 val)
1337{
1338 val = i4p1const_table[val];
1339 return val;
1340}
1341
1342xtensa_encode_result
1343encode_op2p1 (uint32 *valp)
1344{
1345 uint32 val = *valp;
1346 unsigned i;
1347 for (i = 0; i < (1 << 4); i += 1)
1348 if (i4p1const_table[i] == val) goto found;
1349 return xtensa_encode_result_not_in_table;
1350 found:
1351 val = i;
1352 *valp = val;
1353 return xtensa_encode_result_ok;
1354}
1355
1356uint32
1357decode_soffsetx4 (uint32 val)
1358{
1359 val = (val ^ 0x20000) - 0x20000;
1360 val <<= 2;
1361 return val;
1362}
1363
1364xtensa_encode_result
1365encode_soffsetx4 (uint32 *valp)
1366{
1367 uint32 val = *valp;
1368 if ((val & ((1 << 2) - 1)) != 0)
1369 return xtensa_encode_result_align;
1370 val = (signed int) val >> 2;
1371 if (((val + (1 << 17)) >> 18) != 0)
1372 {
1373 if ((signed int) val > 0)
1374 return xtensa_encode_result_too_high;
1375 else
1376 return xtensa_encode_result_too_low;
1377 }
1378 *valp = val;
1379 return xtensa_encode_result_ok;
1380}
1381
1382uint32
1383decode_imm6lo (uint32 val)
1384{
1385 return val;
1386}
1387
1388xtensa_encode_result
1389encode_imm6lo (uint32 *valp)
1390{
1391 uint32 val = *valp;
1392 if ((val >> 4) != 0)
1393 return xtensa_encode_result_too_high;
1394 *valp = val;
1395 return xtensa_encode_result_ok;
1396}
1397
1398uint32
1399decode_imm12 (uint32 val)
1400{
1401 return val;
1402}
1403
1404xtensa_encode_result
1405encode_imm12 (uint32 *valp)
1406{
1407 uint32 val = *valp;
1408 if ((val >> 12) != 0)
1409 return xtensa_encode_result_too_high;
1410 *valp = val;
1411 return xtensa_encode_result_ok;
1412}
1413
1414static const uint32 b4const_table[] = {
1415 -1,
1416 1,
1417 2,
1418 3,
1419 4,
1420 5,
1421 6,
1422 7,
1423 8,
1424 10,
1425 12,
1426 16,
1427 32,
1428 64,
1429 128,
1430 256
1431};
1432
1433uint32
1434decode_b4const (uint32 val)
1435{
1436 val = b4const_table[val];
1437 return val;
1438}
1439
1440xtensa_encode_result
1441encode_b4const (uint32 *valp)
1442{
1443 uint32 val = *valp;
1444 unsigned i;
1445 for (i = 0; i < (1 << 4); i += 1)
1446 if (b4const_table[i] == val) goto found;
1447 return xtensa_encode_result_not_in_table;
1448 found:
1449 val = i;
1450 *valp = val;
1451 return xtensa_encode_result_ok;
1452}
1453
1454uint32
1455decode_i (uint32 val)
1456{
1457 return val;
1458}
1459
1460xtensa_encode_result
1461encode_i (uint32 *valp)
1462{
1463 uint32 val = *valp;
1464 if ((val >> 1) != 0)
1465 return xtensa_encode_result_too_high;
1466 *valp = val;
1467 return xtensa_encode_result_ok;
1468}
1469
1470uint32
1471decode_imm16 (uint32 val)
1472{
1473 return val;
1474}
1475
1476xtensa_encode_result
1477encode_imm16 (uint32 *valp)
1478{
1479 uint32 val = *valp;
1480 if ((val >> 16) != 0)
1481 return xtensa_encode_result_too_high;
1482 *valp = val;
1483 return xtensa_encode_result_ok;
1484}
1485
1486uint32
1487decode_mn (uint32 val)
1488{
1489 return val;
1490}
1491
1492xtensa_encode_result
1493encode_mn (uint32 *valp)
1494{
1495 uint32 val = *valp;
1496 if ((val >> 4) != 0)
1497 return xtensa_encode_result_too_high;
1498 *valp = val;
1499 return xtensa_encode_result_ok;
1500}
1501
1502uint32
1503decode_m (uint32 val)
1504{
1505 return val;
1506}
1507
1508xtensa_encode_result
1509encode_m (uint32 *valp)
1510{
1511 uint32 val = *valp;
1512 if ((val >> 2) != 0)
1513 return xtensa_encode_result_too_high;
1514 *valp = val;
1515 return xtensa_encode_result_ok;
1516}
1517
1518uint32
1519decode_n (uint32 val)
1520{
1521 return val;
1522}
1523
1524xtensa_encode_result
1525encode_n (uint32 *valp)
1526{
1527 uint32 val = *valp;
1528 if ((val >> 2) != 0)
1529 return xtensa_encode_result_too_high;
1530 *valp = val;
1531 return xtensa_encode_result_ok;
1532}
1533
1534uint32
1535decode_none (uint32 val)
1536{
1537 return val;
1538}
1539
1540xtensa_encode_result
1541encode_none (uint32 *valp)
1542{
1543 uint32 val = *valp;
1544 if ((val >> 0) != 0)
1545 return xtensa_encode_result_too_high;
1546 *valp = val;
1547 return xtensa_encode_result_ok;
1548}
1549
1550uint32
1551decode_imm12b (uint32 val)
1552{
1553 return val;
1554}
1555
1556xtensa_encode_result
1557encode_imm12b (uint32 *valp)
1558{
1559 uint32 val = *valp;
1560 if ((val >> 12) != 0)
1561 return xtensa_encode_result_too_high;
1562 *valp = val;
1563 return xtensa_encode_result_ok;
1564}
1565
1566uint32
1567decode_r (uint32 val)
1568{
1569 return val;
1570}
1571
1572xtensa_encode_result
1573encode_r (uint32 *valp)
1574{
1575 uint32 val = *valp;
1576 if ((val >> 4) != 0)
1577 return xtensa_encode_result_too_high;
1578 *valp = val;
1579 return xtensa_encode_result_ok;
1580}
1581
1582uint32
1583decode_s (uint32 val)
1584{
1585 return val;
1586}
1587
1588xtensa_encode_result
1589encode_s (uint32 *valp)
1590{
1591 uint32 val = *valp;
1592 if ((val >> 4) != 0)
1593 return xtensa_encode_result_too_high;
1594 *valp = val;
1595 return xtensa_encode_result_ok;
1596}
1597
1598uint32
1599decode_t (uint32 val)
1600{
1601 return val;
1602}
1603
1604xtensa_encode_result
1605encode_t (uint32 *valp)
1606{
1607 uint32 val = *valp;
1608 if ((val >> 4) != 0)
1609 return xtensa_encode_result_too_high;
1610 *valp = val;
1611 return xtensa_encode_result_ok;
1612}
1613
1614uint32
1615decode_thi3 (uint32 val)
1616{
1617 return val;
1618}
1619
1620xtensa_encode_result
1621encode_thi3 (uint32 *valp)
1622{
1623 uint32 val = *valp;
1624 if ((val >> 3) != 0)
1625 return xtensa_encode_result_too_high;
1626 *valp = val;
1627 return xtensa_encode_result_ok;
1628}
1629
1630uint32
1631decode_sae4 (uint32 val)
1632{
1633 return val;
1634}
1635
1636xtensa_encode_result
1637encode_sae4 (uint32 *valp)
1638{
1639 uint32 val = *valp;
1640 if ((val >> 1) != 0)
1641 return xtensa_encode_result_too_high;
1642 *valp = val;
1643 return xtensa_encode_result_ok;
1644}
1645
1646uint32
1647decode_offset (uint32 val)
1648{
1649 return val;
1650}
1651
1652xtensa_encode_result
1653encode_offset (uint32 *valp)
1654{
1655 uint32 val = *valp;
1656 if ((val >> 18) != 0)
1657 return xtensa_encode_result_too_high;
1658 *valp = val;
1659 return xtensa_encode_result_ok;
1660}
1661
1662uint32
1663decode_imm7hi (uint32 val)
1664{
1665 return val;
1666}
1667
1668xtensa_encode_result
1669encode_imm7hi (uint32 *valp)
1670{
1671 uint32 val = *valp;
1672 if ((val >> 3) != 0)
1673 return xtensa_encode_result_too_high;
1674 *valp = val;
1675 return xtensa_encode_result_ok;
1676}
1677
1678uint32
1679decode_uimm4x16 (uint32 val)
1680{
1681 val <<= 4;
1682 return val;
1683}
1684
1685xtensa_encode_result
1686encode_uimm4x16 (uint32 *valp)
1687{
1688 uint32 val = *valp;
1689 if ((val & ((1 << 4) - 1)) != 0)
1690 return xtensa_encode_result_align;
1691 val = (signed int) val >> 4;
1692 if ((val >> 4) != 0)
1693 return xtensa_encode_result_too_high;
1694 *valp = val;
1695 return xtensa_encode_result_ok;
1696}
1697
1698uint32
1699decode_simm12b (uint32 val)
1700{
1701 val = (val ^ 0x800) - 0x800;
1702 return val;
1703}
1704
1705xtensa_encode_result
1706encode_simm12b (uint32 *valp)
1707{
1708 uint32 val = *valp;
1709 if (((val + (1 << 11)) >> 12) != 0)
1710 {
1711 if ((signed int) val > 0)
1712 return xtensa_encode_result_too_high;
1713 else
1714 return xtensa_encode_result_too_low;
1715 }
1716 *valp = val;
1717 return xtensa_encode_result_ok;
1718}
1719
1720uint32
1721decode_lsi4x4 (uint32 val)
1722{
1723 val <<= 2;
1724 return val;
1725}
1726
1727xtensa_encode_result
1728encode_lsi4x4 (uint32 *valp)
1729{
1730 uint32 val = *valp;
1731 if ((val & ((1 << 2) - 1)) != 0)
1732 return xtensa_encode_result_align;
1733 val = (signed int) val >> 2;
1734 if ((val >> 4) != 0)
1735 return xtensa_encode_result_too_high;
1736 *valp = val;
1737 return xtensa_encode_result_ok;
1738}
1739
1740uint32
1741decode_z (uint32 val)
1742{
1743 return val;
1744}
1745
1746xtensa_encode_result
1747encode_z (uint32 *valp)
1748{
1749 uint32 val = *valp;
1750 if ((val >> 1) != 0)
1751 return xtensa_encode_result_too_high;
1752 *valp = val;
1753 return xtensa_encode_result_ok;
1754}
1755
1756uint32
1757decode_simm12 (uint32 val)
1758{
1759 val = (val ^ 0x800) - 0x800;
1760 return val;
1761}
1762
1763xtensa_encode_result
1764encode_simm12 (uint32 *valp)
1765{
1766 uint32 val = *valp;
1767 if (((val + (1 << 11)) >> 12) != 0)
1768 {
1769 if ((signed int) val > 0)
1770 return xtensa_encode_result_too_high;
1771 else
1772 return xtensa_encode_result_too_low;
1773 }
1774 *valp = val;
1775 return xtensa_encode_result_ok;
1776}
1777
1778uint32
1779decode_sr (uint32 val)
1780{
1781 return val;
1782}
1783
1784xtensa_encode_result
1785encode_sr (uint32 *valp)
1786{
1787 uint32 val = *valp;
1788 if ((val >> 8) != 0)
1789 return xtensa_encode_result_too_high;
1790 *valp = val;
1791 return xtensa_encode_result_ok;
1792}
1793
1794uint32
1795decode_nimm4x2 (uint32 val)
1796{
1797 val |= -1 << 4;
1798 val <<= 2;
1799 return val;
1800}
1801
1802xtensa_encode_result
1803encode_nimm4x2 (uint32 *valp)
1804{
1805 uint32 val = *valp;
1806 if ((val & ((1 << 2) - 1)) != 0)
1807 return xtensa_encode_result_align;
1808 val = (signed int) val >> 2;
1809 if ((signed int) val >> 4 != -1)
1810 {
1811 if ((signed int) val >= 0)
1812 return xtensa_encode_result_too_high;
1813 else
1814 return xtensa_encode_result_too_low;
1815 }
1816 *valp = val;
1817 return xtensa_encode_result_ok;
1818}
1819
1820
1821
1822uint32 do_reloc_l (uint32, uint32);
1823uint32 undo_reloc_l (uint32, uint32);
1824uint32 do_reloc_L (uint32, uint32);
1825uint32 undo_reloc_L (uint32, uint32);
1826uint32 do_reloc_r (uint32, uint32);
1827uint32 undo_reloc_r (uint32, uint32);
1828
1829
1830uint32
1831do_reloc_l (uint32 addr, uint32 pc)
1832{
1833 return addr - pc - 4;
1834}
1835
1836uint32
1837undo_reloc_l (uint32 offset, uint32 pc)
1838{
1839 return pc + offset + 4;
1840}
1841
1842uint32
1843do_reloc_L (uint32 addr, uint32 pc)
1844{
1845 return addr - (pc & -4) - 4;
1846}
1847
1848uint32
1849undo_reloc_L (uint32 offset, uint32 pc)
1850{
1851 return (pc & -4) + offset + 4;
1852}
1853
1854uint32
1855do_reloc_r (uint32 addr, uint32 pc)
1856{
1857 return addr - ((pc+3) & -4);
1858}
1859
1860uint32
1861undo_reloc_r (uint32 offset, uint32 pc)
1862{
1863 return ((pc+3) & -4) + offset;
1864}
1865
1866static xtensa_operand_internal iib4const_operand = {
1867 "i",
1868 '<',
1869 0,
1870 get_r_field,
1871 set_r_field,
1872 encode_b4const,
1873 decode_b4const,
1874 0,
1875 0
1876};
1877
1878static xtensa_operand_internal iiuimm8_operand = {
1879 "i",
1880 '<',
1881 0,
1882 get_imm8_field,
1883 set_imm8_field,
1884 encode_uimm8,
1885 decode_uimm8,
1886 0,
1887 0
1888};
1889
1890static xtensa_operand_internal lisoffsetx4_operand = {
1891 "L",
1892 '<',
1893 1,
1894 get_offset_field,
1895 set_offset_field,
1896 encode_soffsetx4,
1897 decode_soffsetx4,
1898 do_reloc_L,
1899 undo_reloc_L,
1900};
1901
1902static xtensa_operand_internal iisimm8x256_operand = {
1903 "i",
1904 '<',
1905 0,
1906 get_imm8_field,
1907 set_imm8_field,
1908 encode_simm8x256,
1909 decode_simm8x256,
1910 0,
1911 0
1912};
1913
1914static xtensa_operand_internal lisimm12_operand = {
1915 "l",
1916 '<',
1917 1,
1918 get_imm12_field,
1919 set_imm12_field,
1920 encode_simm12,
1921 decode_simm12,
1922 do_reloc_l,
1923 undo_reloc_l,
1924};
1925
1926static xtensa_operand_internal iiop2p1_operand = {
1927 "i",
1928 '<',
1929 0,
1930 get_op2_field,
1931 set_op2_field,
1932 encode_op2p1,
1933 decode_op2p1,
1934 0,
1935 0
1936};
1937
1938static xtensa_operand_internal iisae_operand = {
1939 "i",
1940 '<',
1941 0,
1942 get_sae_field,
1943 set_sae_field,
1944 encode_sae,
1945 decode_sae,
1946 0,
1947 0
1948};
1949
1950static xtensa_operand_internal iis_operand = {
1951 "i",
1952 '<',
1953 0,
1954 get_s_field,
1955 set_s_field,
1956 encode_s,
1957 decode_s,
1958 0,
1959 0
1960};
1961
1962static xtensa_operand_internal iit_operand = {
1963 "i",
1964 '<',
1965 0,
1966 get_t_field,
1967 set_t_field,
1968 encode_t,
1969 decode_t,
1970 0,
1971 0
1972};
1973
1974static xtensa_operand_internal iisimm12b_operand = {
1975 "i",
1976 '<',
1977 0,
1978 get_imm12b_field,
1979 set_imm12b_field,
1980 encode_simm12b,
1981 decode_simm12b,
1982 0,
1983 0
1984};
1985
1986static xtensa_operand_internal iinimm4x2_operand = {
1987 "i",
1988 '<',
1989 0,
1990 get_imm4_field,
1991 set_imm4_field,
1992 encode_nimm4x2,
1993 decode_nimm4x2,
1994 0,
1995 0
1996};
1997
1998static xtensa_operand_internal iiuimm4x16_operand = {
1999 "i",
2000 '<',
2001 0,
2002 get_op2_field,
2003 set_op2_field,
2004 encode_uimm4x16,
2005 decode_uimm4x16,
2006 0,
2007 0
2008};
2009
2010static xtensa_operand_internal abs_operand = {
2011 "a",
2012 '=',
2013 0,
2014 get_s_field,
2015 set_s_field,
2016 encode_s,
2017 decode_s,
2018 0,
2019 0
2020};
2021
2022static xtensa_operand_internal iisar_operand = {
2023 "i",
2024 '<',
2025 0,
2026 get_sar_field,
2027 set_sar_field,
2028 encode_sar,
2029 decode_sar,
2030 0,
2031 0
2032};
2033
2034static xtensa_operand_internal abt_operand = {
2035 "a",
2036 '=',
2037 0,
2038 get_t_field,
2039 set_t_field,
2040 encode_t,
2041 decode_t,
2042 0,
2043 0
2044};
2045
2046static xtensa_operand_internal iisas_operand = {
2047 "i",
2048 '<',
2049 0,
2050 get_sas_field,
2051 set_sas_field,
2052 encode_sas,
2053 decode_sas,
2054 0,
2055 0
2056};
2057
2058static xtensa_operand_internal amr_operand = {
2059 "a",
2060 '=',
2061 0,
2062 get_r_field,
2063 set_r_field,
2064 encode_r,
2065 decode_r,
2066 0,
2067 0
2068};
2069
2070static xtensa_operand_internal iib4constu_operand = {
2071 "i",
2072 '<',
2073 0,
2074 get_r_field,
2075 set_r_field,
2076 encode_b4constu,
2077 decode_b4constu,
2078 0,
2079 0
2080};
2081
2082static xtensa_operand_internal iisr_operand = {
2083 "i",
2084 '<',
2085 0,
2086 get_sr_field,
2087 set_sr_field,
2088 encode_sr,
2089 decode_sr,
2090 0,
2091 0
2092};
2093
2094static xtensa_operand_internal iibbi_operand = {
2095 "i",
2096 '<',
2097 0,
2098 get_bbi_field,
2099 set_bbi_field,
2100 encode_bbi,
2101 decode_bbi,
2102 0,
2103 0
2104};
2105
2106static xtensa_operand_internal iiai4const_operand = {
2107 "i",
2108 '<',
2109 0,
2110 get_t_field,
2111 set_t_field,
2112 encode_ai4const,
2113 decode_ai4const,
2114 0,
2115 0
2116};
2117
2118static xtensa_operand_internal iiuimm12x8_operand = {
2119 "i",
2120 '<',
2121 0,
2122 get_imm12_field,
2123 set_imm12_field,
2124 encode_uimm12x8,
2125 decode_uimm12x8,
2126 0,
2127 0
2128};
2129
2130static xtensa_operand_internal riuimm16x4_operand = {
2131 "r",
2132 '<',
2133 1,
2134 get_imm16_field,
2135 set_imm16_field,
2136 encode_uimm16x4,
2137 decode_uimm16x4,
2138 do_reloc_r,
2139 undo_reloc_r,
2140};
2141
2142static xtensa_operand_internal lisimm8_operand = {
2143 "l",
2144 '<',
2145 1,
2146 get_imm8_field,
2147 set_imm8_field,
2148 encode_simm8,
2149 decode_simm8,
2150 do_reloc_l,
2151 undo_reloc_l,
2152};
2153
2154static xtensa_operand_internal iilsi4x4_operand = {
2155 "i",
2156 '<',
2157 0,
2158 get_r_field,
2159 set_r_field,
2160 encode_lsi4x4,
2161 decode_lsi4x4,
2162 0,
2163 0
2164};
2165
2166static xtensa_operand_internal iiuimm8x2_operand = {
2167 "i",
2168 '<',
2169 0,
2170 get_imm8_field,
2171 set_imm8_field,
2172 encode_uimm8x2,
2173 decode_uimm8x2,
2174 0,
2175 0
2176};
2177
2178static xtensa_operand_internal iisimm4_operand = {
2179 "i",
2180 '<',
2181 0,
2182 get_mn_field,
2183 set_mn_field,
2184 encode_simm4,
2185 decode_simm4,
2186 0,
2187 0
2188};
2189
2190static xtensa_operand_internal iimsalp32_operand = {
2191 "i",
2192 '<',
2193 0,
2194 get_sal_field,
2195 set_sal_field,
2196 encode_msalp32,
2197 decode_msalp32,
2198 0,
2199 0
2200};
2201
2202static xtensa_operand_internal liuimm6_operand = {
2203 "l",
2204 '<',
2205 1,
2206 get_imm6_field,
2207 set_imm6_field,
2208 encode_uimm6,
2209 decode_uimm6,
2210 do_reloc_l,
2211 undo_reloc_l,
2212};
2213
2214static xtensa_operand_internal iiuimm8x4_operand = {
2215 "i",
2216 '<',
2217 0,
2218 get_imm8_field,
2219 set_imm8_field,
2220 encode_uimm8x4,
2221 decode_uimm8x4,
2222 0,
2223 0
2224};
2225
2226static xtensa_operand_internal lisoffset_operand = {
2227 "l",
2228 '<',
2229 1,
2230 get_offset_field,
2231 set_offset_field,
2232 encode_soffset,
2233 decode_soffset,
2234 do_reloc_l,
2235 undo_reloc_l,
2236};
2237
2238static xtensa_operand_internal iisimm7_operand = {
2239 "i",
2240 '<',
2241 0,
2242 get_imm7_field,
2243 set_imm7_field,
2244 encode_simm7,
2245 decode_simm7,
2246 0,
2247 0
2248};
2249
2250static xtensa_operand_internal ais_operand = {
2251 "a",
2252 '<',
2253 0,
2254 get_s_field,
2255 set_s_field,
2256 encode_s,
2257 decode_s,
2258 0,
2259 0
2260};
2261
2262static xtensa_operand_internal liuimm8_operand = {
2263 "l",
2264 '<',
2265 1,
2266 get_imm8_field,
2267 set_imm8_field,
2268 encode_uimm8,
2269 decode_uimm8,
2270 do_reloc_l,
2271 undo_reloc_l,
2272};
2273
2274static xtensa_operand_internal ait_operand = {
2275 "a",
2276 '<',
2277 0,
2278 get_t_field,
2279 set_t_field,
2280 encode_t,
2281 decode_t,
2282 0,
2283 0
2284};
2285
2286static xtensa_operand_internal iisimm8_operand = {
2287 "i",
2288 '<',
2289 0,
2290 get_imm8_field,
2291 set_imm8_field,
2292 encode_simm8,
2293 decode_simm8,
2294 0,
2295 0
2296};
2297
2298static xtensa_operand_internal aor_operand = {
2299 "a",
2300 '>',
2301 0,
2302 get_r_field,
2303 set_r_field,
2304 encode_r,
2305 decode_r,
2306 0,
2307 0
2308};
2309
2310static xtensa_operand_internal aos_operand = {
2311 "a",
2312 '>',
2313 0,
2314 get_s_field,
2315 set_s_field,
2316 encode_s,
2317 decode_s,
2318 0,
2319 0
2320};
2321
2322static xtensa_operand_internal aot_operand = {
2323 "a",
2324 '>',
2325 0,
2326 get_t_field,
2327 set_t_field,
2328 encode_t,
2329 decode_t,
2330 0,
2331 0
2332};
2333
2334static xtensa_iclass_internal nopn_iclass = {
2335 0,
2336 0
2337};
2338
2339static xtensa_operand_internal *movi_operand_list[] = {
2340 &aot_operand,
2341 &iisimm12b_operand
2342};
2343
2344static xtensa_iclass_internal movi_iclass = {
2345 2,
2346 &movi_operand_list[0]
2347};
2348
2349static xtensa_operand_internal *bsi8u_operand_list[] = {
2350 &ais_operand,
2351 &iib4constu_operand,
2352 &lisimm8_operand
2353};
2354
2355static xtensa_iclass_internal bsi8u_iclass = {
2356 3,
2357 &bsi8u_operand_list[0]
2358};
2359
2360static xtensa_operand_internal *itlb_operand_list[] = {
2361 &ais_operand
2362};
2363
2364static xtensa_iclass_internal itlb_iclass = {
2365 1,
2366 &itlb_operand_list[0]
2367};
2368
2369static xtensa_operand_internal *shiftst_operand_list[] = {
2370 &aor_operand,
2371 &ais_operand,
2372 &ait_operand
2373};
2374
2375static xtensa_iclass_internal shiftst_iclass = {
2376 3,
2377 &shiftst_operand_list[0]
2378};
2379
2380static xtensa_operand_internal *l32r_operand_list[] = {
2381 &aot_operand,
2382 &riuimm16x4_operand
2383};
2384
2385static xtensa_iclass_internal l32r_iclass = {
2386 2,
2387 &l32r_operand_list[0]
2388};
2389
2390static xtensa_iclass_internal rfe_iclass = {
2391 0,
2392 0
2393};
2394
2395static xtensa_operand_internal *wait_operand_list[] = {
2396 &iis_operand
2397};
2398
2399static xtensa_iclass_internal wait_iclass = {
2400 1,
2401 &wait_operand_list[0]
2402};
2403
2404static xtensa_operand_internal *rfi_operand_list[] = {
2405 &iis_operand
2406};
2407
2408static xtensa_iclass_internal rfi_iclass = {
2409 1,
2410 &rfi_operand_list[0]
2411};
2412
2413static xtensa_operand_internal *movz_operand_list[] = {
2414 &amr_operand,
2415 &ais_operand,
2416 &ait_operand
2417};
2418
2419static xtensa_iclass_internal movz_iclass = {
2420 3,
2421 &movz_operand_list[0]
2422};
2423
2424static xtensa_operand_internal *callx_operand_list[] = {
2425 &ais_operand
2426};
2427
2428static xtensa_iclass_internal callx_iclass = {
2429 1,
2430 &callx_operand_list[0]
2431};
2432
2433static xtensa_operand_internal *mov_n_operand_list[] = {
2434 &aot_operand,
2435 &ais_operand
2436};
2437
2438static xtensa_iclass_internal mov_n_iclass = {
2439 2,
2440 &mov_n_operand_list[0]
2441};
2442
2443static xtensa_operand_internal *loadi4_operand_list[] = {
2444 &aot_operand,
2445 &ais_operand,
2446 &iilsi4x4_operand
2447};
2448
2449static xtensa_iclass_internal loadi4_iclass = {
2450 3,
2451 &loadi4_operand_list[0]
2452};
2453
2454static xtensa_operand_internal *exti_operand_list[] = {
2455 &aor_operand,
2456 &ait_operand,
2457 &iisae_operand,
2458 &iiop2p1_operand
2459};
2460
2461static xtensa_iclass_internal exti_iclass = {
2462 4,
2463 &exti_operand_list[0]
2464};
2465
2466static xtensa_operand_internal *break_operand_list[] = {
2467 &iis_operand,
2468 &iit_operand
2469};
2470
2471static xtensa_iclass_internal break_iclass = {
2472 2,
2473 &break_operand_list[0]
2474};
2475
2476static xtensa_operand_internal *slli_operand_list[] = {
2477 &aor_operand,
2478 &ais_operand,
2479 &iimsalp32_operand
2480};
2481
2482static xtensa_iclass_internal slli_iclass = {
2483 3,
2484 &slli_operand_list[0]
2485};
2486
2487static xtensa_operand_internal *s16i_operand_list[] = {
2488 &ait_operand,
2489 &ais_operand,
2490 &iiuimm8x2_operand
2491};
2492
2493static xtensa_iclass_internal s16i_iclass = {
2494 3,
2495 &s16i_operand_list[0]
2496};
2497
2498static xtensa_operand_internal *call_operand_list[] = {
2499 &lisoffsetx4_operand
2500};
2501
2502static xtensa_iclass_internal call_iclass = {
2503 1,
2504 &call_operand_list[0]
2505};
2506
2507static xtensa_operand_internal *shifts_operand_list[] = {
2508 &aor_operand,
2509 &ais_operand
2510};
2511
2512static xtensa_iclass_internal shifts_iclass = {
2513 2,
2514 &shifts_operand_list[0]
2515};
2516
2517static xtensa_operand_internal *shiftt_operand_list[] = {
2518 &aor_operand,
2519 &ait_operand
2520};
2521
2522static xtensa_iclass_internal shiftt_iclass = {
2523 2,
2524 &shiftt_operand_list[0]
2525};
2526
2527static xtensa_operand_internal *rotw_operand_list[] = {
2528 &iisimm4_operand
2529};
2530
2531static xtensa_iclass_internal rotw_iclass = {
2532 1,
2533 &rotw_operand_list[0]
2534};
2535
2536static xtensa_operand_internal *addsub_operand_list[] = {
2537 &aor_operand,
2538 &ais_operand,
2539 &ait_operand
2540};
2541
2542static xtensa_iclass_internal addsub_iclass = {
2543 3,
2544 &addsub_operand_list[0]
2545};
2546
2547static xtensa_operand_internal *l8i_operand_list[] = {
2548 &aot_operand,
2549 &ais_operand,
2550 &iiuimm8_operand
2551};
2552
2553static xtensa_iclass_internal l8i_iclass = {
2554 3,
2555 &l8i_operand_list[0]
2556};
2557
2558static xtensa_operand_internal *sari_operand_list[] = {
2559 &iisas_operand
2560};
2561
2562static xtensa_iclass_internal sari_iclass = {
2563 1,
2564 &sari_operand_list[0]
2565};
2566
2567static xtensa_operand_internal *xsr_operand_list[] = {
2568 &abt_operand,
2569 &iisr_operand
2570};
2571
2572static xtensa_iclass_internal xsr_iclass = {
2573 2,
2574 &xsr_operand_list[0]
2575};
2576
2577static xtensa_operand_internal *rsil_operand_list[] = {
2578 &aot_operand,
2579 &iis_operand
2580};
2581
2582static xtensa_iclass_internal rsil_iclass = {
2583 2,
2584 &rsil_operand_list[0]
2585};
2586
2587static xtensa_operand_internal *bst8_operand_list[] = {
2588 &ais_operand,
2589 &ait_operand,
2590 &lisimm8_operand
2591};
2592
2593static xtensa_iclass_internal bst8_iclass = {
2594 3,
2595 &bst8_operand_list[0]
2596};
2597
2598static xtensa_operand_internal *addi_operand_list[] = {
2599 &aot_operand,
2600 &ais_operand,
2601 &iisimm8_operand
2602};
2603
2604static xtensa_iclass_internal addi_iclass = {
2605 3,
2606 &addi_operand_list[0]
2607};
2608
2609static xtensa_operand_internal *callx12_operand_list[] = {
2610 &ais_operand
2611};
2612
2613static xtensa_iclass_internal callx12_iclass = {
2614 1,
2615 &callx12_operand_list[0]
2616};
2617
2618static xtensa_operand_internal *bsi8_operand_list[] = {
2619 &ais_operand,
2620 &iib4const_operand,
2621 &lisimm8_operand
2622};
2623
2624static xtensa_iclass_internal bsi8_iclass = {
2625 3,
2626 &bsi8_operand_list[0]
2627};
2628
2629static xtensa_operand_internal *jumpx_operand_list[] = {
2630 &ais_operand
2631};
2632
2633static xtensa_iclass_internal jumpx_iclass = {
2634 1,
2635 &jumpx_operand_list[0]
2636};
2637
2638static xtensa_iclass_internal retn_iclass = {
2639 0,
2640 0
2641};
2642
2643static xtensa_operand_internal *nsa_operand_list[] = {
2644 &aot_operand,
2645 &ais_operand
2646};
2647
2648static xtensa_iclass_internal nsa_iclass = {
2649 2,
2650 &nsa_operand_list[0]
2651};
2652
2653static xtensa_operand_internal *storei4_operand_list[] = {
2654 &ait_operand,
2655 &ais_operand,
2656 &iilsi4x4_operand
2657};
2658
2659static xtensa_iclass_internal storei4_iclass = {
2660 3,
2661 &storei4_operand_list[0]
2662};
2663
2664static xtensa_operand_internal *wtlb_operand_list[] = {
2665 &ait_operand,
2666 &ais_operand
2667};
2668
2669static xtensa_iclass_internal wtlb_iclass = {
2670 2,
2671 &wtlb_operand_list[0]
2672};
2673
2674static xtensa_operand_internal *dce_operand_list[] = {
2675 &ais_operand,
2676 &iiuimm4x16_operand
2677};
2678
2679static xtensa_iclass_internal dce_iclass = {
2680 2,
2681 &dce_operand_list[0]
2682};
2683
2684static xtensa_operand_internal *l16i_operand_list[] = {
2685 &aot_operand,
2686 &ais_operand,
2687 &iiuimm8x2_operand
2688};
2689
2690static xtensa_iclass_internal l16i_iclass = {
2691 3,
2692 &l16i_operand_list[0]
2693};
2694
2695static xtensa_operand_internal *callx4_operand_list[] = {
2696 &ais_operand
2697};
2698
2699static xtensa_iclass_internal callx4_iclass = {
2700 1,
2701 &callx4_operand_list[0]
2702};
2703
2704static xtensa_operand_internal *callx8_operand_list[] = {
2705 &ais_operand
2706};
2707
2708static xtensa_iclass_internal callx8_iclass = {
2709 1,
2710 &callx8_operand_list[0]
2711};
2712
2713static xtensa_operand_internal *movsp_operand_list[] = {
2714 &aot_operand,
2715 &ais_operand
2716};
2717
2718static xtensa_iclass_internal movsp_iclass = {
2719 2,
2720 &movsp_operand_list[0]
2721};
2722
2723static xtensa_operand_internal *wsr_operand_list[] = {
2724 &ait_operand,
2725 &iisr_operand
2726};
2727
2728static xtensa_iclass_internal wsr_iclass = {
2729 2,
2730 &wsr_operand_list[0]
2731};
2732
2733static xtensa_operand_internal *call12_operand_list[] = {
2734 &lisoffsetx4_operand
2735};
2736
2737static xtensa_iclass_internal call12_iclass = {
2738 1,
2739 &call12_operand_list[0]
2740};
2741
2742static xtensa_operand_internal *call4_operand_list[] = {
2743 &lisoffsetx4_operand
2744};
2745
2746static xtensa_iclass_internal call4_iclass = {
2747 1,
2748 &call4_operand_list[0]
2749};
2750
2751static xtensa_operand_internal *addmi_operand_list[] = {
2752 &aot_operand,
2753 &ais_operand,
2754 &iisimm8x256_operand
2755};
2756
2757static xtensa_iclass_internal addmi_iclass = {
2758 3,
2759 &addmi_operand_list[0]
2760};
2761
2762static xtensa_operand_internal *bit_operand_list[] = {
2763 &aor_operand,
2764 &ais_operand,
2765 &ait_operand
2766};
2767
2768static xtensa_iclass_internal bit_iclass = {
2769 3,
2770 &bit_operand_list[0]
2771};
2772
2773static xtensa_operand_internal *call8_operand_list[] = {
2774 &lisoffsetx4_operand
2775};
2776
2777static xtensa_iclass_internal call8_iclass = {
2778 1,
2779 &call8_operand_list[0]
2780};
2781
2782static xtensa_iclass_internal itlba_iclass = {
2783 0,
2784 0
2785};
2786
2787static xtensa_operand_internal *break_n_operand_list[] = {
2788 &iis_operand
2789};
2790
2791static xtensa_iclass_internal break_n_iclass = {
2792 1,
2793 &break_n_operand_list[0]
2794};
2795
2796static xtensa_operand_internal *sar_operand_list[] = {
2797 &ais_operand
2798};
2799
2800static xtensa_iclass_internal sar_iclass = {
2801 1,
2802 &sar_operand_list[0]
2803};
2804
2805static xtensa_operand_internal *s32e_operand_list[] = {
2806 &ait_operand,
2807 &ais_operand,
2808 &iinimm4x2_operand
2809};
2810
2811static xtensa_iclass_internal s32e_iclass = {
2812 3,
2813 &s32e_operand_list[0]
2814};
2815
2816static xtensa_operand_internal *bz6_operand_list[] = {
2817 &ais_operand,
2818 &liuimm6_operand
2819};
2820
2821static xtensa_iclass_internal bz6_iclass = {
2822 2,
2823 &bz6_operand_list[0]
2824};
2825
2826static xtensa_operand_internal *loop_operand_list[] = {
2827 &ais_operand,
2828 &liuimm8_operand
2829};
2830
2831static xtensa_iclass_internal loop_iclass = {
2832 2,
2833 &loop_operand_list[0]
2834};
2835
2836static xtensa_operand_internal *rsr_operand_list[] = {
2837 &aot_operand,
2838 &iisr_operand
2839};
2840
2841static xtensa_iclass_internal rsr_iclass = {
2842 2,
2843 &rsr_operand_list[0]
2844};
2845
2846static xtensa_operand_internal *icache_operand_list[] = {
2847 &ais_operand,
2848 &iiuimm8x4_operand
2849};
2850
2851static xtensa_iclass_internal icache_iclass = {
2852 2,
2853 &icache_operand_list[0]
2854};
2855
2856static xtensa_operand_internal *s8i_operand_list[] = {
2857 &ait_operand,
2858 &ais_operand,
2859 &iiuimm8_operand
2860};
2861
2862static xtensa_iclass_internal s8i_iclass = {
2863 3,
2864 &s8i_operand_list[0]
2865};
2866
2867static xtensa_iclass_internal return_iclass = {
2868 0,
2869 0
2870};
2871
2872static xtensa_operand_internal *dcache_operand_list[] = {
2873 &ais_operand,
2874 &iiuimm8x4_operand
2875};
2876
2877static xtensa_iclass_internal dcache_iclass = {
2878 2,
2879 &dcache_operand_list[0]
2880};
2881
2882static xtensa_operand_internal *s32i_operand_list[] = {
2883 &ait_operand,
2884 &ais_operand,
2885 &iiuimm8x4_operand
2886};
2887
2888static xtensa_iclass_internal s32i_iclass = {
2889 3,
2890 &s32i_operand_list[0]
2891};
2892
2893static xtensa_operand_internal *jump_operand_list[] = {
2894 &lisoffset_operand
2895};
2896
2897static xtensa_iclass_internal jump_iclass = {
2898 1,
2899 &jump_operand_list[0]
2900};
2901
2902static xtensa_operand_internal *addi_n_operand_list[] = {
2903 &aor_operand,
2904 &ais_operand,
2905 &iiai4const_operand
2906};
2907
2908static xtensa_iclass_internal addi_n_iclass = {
2909 3,
2910 &addi_n_operand_list[0]
2911};
2912
2913static xtensa_iclass_internal sync_iclass = {
2914 0,
2915 0
2916};
2917
2918static xtensa_operand_internal *neg_operand_list[] = {
2919 &aor_operand,
2920 &ait_operand
2921};
2922
2923static xtensa_iclass_internal neg_iclass = {
2924 2,
2925 &neg_operand_list[0]
2926};
2927
2928static xtensa_iclass_internal syscall_iclass = {
2929 0,
2930 0
2931};
2932
2933static xtensa_operand_internal *bsz12_operand_list[] = {
2934 &ais_operand,
2935 &lisimm12_operand
2936};
2937
2938static xtensa_iclass_internal bsz12_iclass = {
2939 2,
2940 &bsz12_operand_list[0]
2941};
2942
2943static xtensa_iclass_internal excw_iclass = {
2944 0,
2945 0
2946};
2947
2948static xtensa_operand_internal *movi_n_operand_list[] = {
2949 &aos_operand,
2950 &iisimm7_operand
2951};
2952
2953static xtensa_iclass_internal movi_n_iclass = {
2954 2,
2955 &movi_n_operand_list[0]
2956};
2957
2958static xtensa_operand_internal *rtlb_operand_list[] = {
2959 &aot_operand,
2960 &ais_operand
2961};
2962
2963static xtensa_iclass_internal rtlb_iclass = {
2964 2,
2965 &rtlb_operand_list[0]
2966};
2967
2968static xtensa_operand_internal *actl_operand_list[] = {
2969 &aot_operand,
2970 &ais_operand
2971};
2972
2973static xtensa_iclass_internal actl_iclass = {
2974 2,
2975 &actl_operand_list[0]
2976};
2977
2978static xtensa_operand_internal *srli_operand_list[] = {
2979 &aor_operand,
2980 &ait_operand,
2981 &iis_operand
2982};
2983
2984static xtensa_iclass_internal srli_iclass = {
2985 3,
2986 &srli_operand_list[0]
2987};
2988
2989static xtensa_operand_internal *bsi8b_operand_list[] = {
2990 &ais_operand,
2991 &iibbi_operand,
2992 &lisimm8_operand
2993};
2994
2995static xtensa_iclass_internal bsi8b_iclass = {
2996 3,
2997 &bsi8b_operand_list[0]
2998};
2999
3000static xtensa_operand_internal *acts_operand_list[] = {
3001 &ait_operand,
3002 &ais_operand
3003};
3004
3005static xtensa_iclass_internal acts_iclass = {
3006 2,
3007 &acts_operand_list[0]
3008};
3009
3010static xtensa_operand_internal *add_n_operand_list[] = {
3011 &aor_operand,
3012 &ais_operand,
3013 &ait_operand
3014};
3015
3016static xtensa_iclass_internal add_n_iclass = {
3017 3,
3018 &add_n_operand_list[0]
3019};
3020
3021static xtensa_operand_internal *srai_operand_list[] = {
3022 &aor_operand,
3023 &ait_operand,
3024 &iisar_operand
3025};
3026
3027static xtensa_iclass_internal srai_iclass = {
3028 3,
3029 &srai_operand_list[0]
3030};
3031
3032static xtensa_operand_internal *entry_operand_list[] = {
3033 &abs_operand,
3034 &iiuimm12x8_operand
3035};
3036
3037static xtensa_iclass_internal entry_iclass = {
3038 2,
3039 &entry_operand_list[0]
3040};
3041
3042static xtensa_operand_internal *l32e_operand_list[] = {
3043 &aot_operand,
3044 &ais_operand,
3045 &iinimm4x2_operand
3046};
3047
3048static xtensa_iclass_internal l32e_iclass = {
3049 3,
3050 &l32e_operand_list[0]
3051};
3052
3053static xtensa_operand_internal *dpf_operand_list[] = {
3054 &ais_operand,
3055 &iiuimm8x4_operand
3056};
3057
3058static xtensa_iclass_internal dpf_iclass = {
3059 2,
3060 &dpf_operand_list[0]
3061};
3062
3063static xtensa_operand_internal *l32i_operand_list[] = {
3064 &aot_operand,
3065 &ais_operand,
3066 &iiuimm8x4_operand
3067};
3068
3069static xtensa_iclass_internal l32i_iclass = {
3070 3,
3071 &l32i_operand_list[0]
3072};
3073
3074static xtensa_insnbuf abs_template (void);
3075static xtensa_insnbuf add_template (void);
3076static xtensa_insnbuf add_n_template (void);
3077static xtensa_insnbuf addi_template (void);
3078static xtensa_insnbuf addi_n_template (void);
3079static xtensa_insnbuf addmi_template (void);
3080static xtensa_insnbuf addx2_template (void);
3081static xtensa_insnbuf addx4_template (void);
3082static xtensa_insnbuf addx8_template (void);
3083static xtensa_insnbuf and_template (void);
3084static xtensa_insnbuf ball_template (void);
3085static xtensa_insnbuf bany_template (void);
3086static xtensa_insnbuf bbc_template (void);
3087static xtensa_insnbuf bbci_template (void);
3088static xtensa_insnbuf bbs_template (void);
3089static xtensa_insnbuf bbsi_template (void);
3090static xtensa_insnbuf beq_template (void);
3091static xtensa_insnbuf beqi_template (void);
3092static xtensa_insnbuf beqz_template (void);
3093static xtensa_insnbuf beqz_n_template (void);
3094static xtensa_insnbuf bge_template (void);
3095static xtensa_insnbuf bgei_template (void);
3096static xtensa_insnbuf bgeu_template (void);
3097static xtensa_insnbuf bgeui_template (void);
3098static xtensa_insnbuf bgez_template (void);
3099static xtensa_insnbuf blt_template (void);
3100static xtensa_insnbuf blti_template (void);
3101static xtensa_insnbuf bltu_template (void);
3102static xtensa_insnbuf bltui_template (void);
3103static xtensa_insnbuf bltz_template (void);
3104static xtensa_insnbuf bnall_template (void);
3105static xtensa_insnbuf bne_template (void);
3106static xtensa_insnbuf bnei_template (void);
3107static xtensa_insnbuf bnez_template (void);
3108static xtensa_insnbuf bnez_n_template (void);
3109static xtensa_insnbuf bnone_template (void);
3110static xtensa_insnbuf break_template (void);
3111static xtensa_insnbuf break_n_template (void);
3112static xtensa_insnbuf call0_template (void);
3113static xtensa_insnbuf call12_template (void);
3114static xtensa_insnbuf call4_template (void);
3115static xtensa_insnbuf call8_template (void);
3116static xtensa_insnbuf callx0_template (void);
3117static xtensa_insnbuf callx12_template (void);
3118static xtensa_insnbuf callx4_template (void);
3119static xtensa_insnbuf callx8_template (void);
3120static xtensa_insnbuf dhi_template (void);
3121static xtensa_insnbuf dhwb_template (void);
3122static xtensa_insnbuf dhwbi_template (void);
3123static xtensa_insnbuf dii_template (void);
3124static xtensa_insnbuf diwb_template (void);
3125static xtensa_insnbuf diwbi_template (void);
3126static xtensa_insnbuf dpfr_template (void);
3127static xtensa_insnbuf dpfro_template (void);
3128static xtensa_insnbuf dpfw_template (void);
3129static xtensa_insnbuf dpfwo_template (void);
3130static xtensa_insnbuf dsync_template (void);
3131static xtensa_insnbuf entry_template (void);
3132static xtensa_insnbuf esync_template (void);
3133static xtensa_insnbuf excw_template (void);
3134static xtensa_insnbuf extui_template (void);
3135static xtensa_insnbuf idtlb_template (void);
3136static xtensa_insnbuf idtlba_template (void);
3137static xtensa_insnbuf ihi_template (void);
3138static xtensa_insnbuf iii_template (void);
3139static xtensa_insnbuf iitlb_template (void);
3140static xtensa_insnbuf iitlba_template (void);
3141static xtensa_insnbuf ipf_template (void);
3142static xtensa_insnbuf isync_template (void);
3143static xtensa_insnbuf j_template (void);
3144static xtensa_insnbuf jx_template (void);
3145static xtensa_insnbuf l16si_template (void);
3146static xtensa_insnbuf l16ui_template (void);
3147static xtensa_insnbuf l32e_template (void);
3148static xtensa_insnbuf l32i_template (void);
3149static xtensa_insnbuf l32i_n_template (void);
3150static xtensa_insnbuf l32r_template (void);
3151static xtensa_insnbuf l8ui_template (void);
3152static xtensa_insnbuf ldct_template (void);
3153static xtensa_insnbuf lict_template (void);
3154static xtensa_insnbuf licw_template (void);
3155static xtensa_insnbuf loop_template (void);
3156static xtensa_insnbuf loopgtz_template (void);
3157static xtensa_insnbuf loopnez_template (void);
3158static xtensa_insnbuf memw_template (void);
3159static xtensa_insnbuf mov_n_template (void);
3160static xtensa_insnbuf moveqz_template (void);
3161static xtensa_insnbuf movgez_template (void);
3162static xtensa_insnbuf movi_template (void);
3163static xtensa_insnbuf movi_n_template (void);
3164static xtensa_insnbuf movltz_template (void);
3165static xtensa_insnbuf movnez_template (void);
3166static xtensa_insnbuf movsp_template (void);
3167static xtensa_insnbuf neg_template (void);
3168static xtensa_insnbuf nop_n_template (void);
3169static xtensa_insnbuf nsa_template (void);
3170static xtensa_insnbuf nsau_template (void);
3171static xtensa_insnbuf or_template (void);
3172static xtensa_insnbuf pdtlb_template (void);
3173static xtensa_insnbuf pitlb_template (void);
3174static xtensa_insnbuf rdtlb0_template (void);
3175static xtensa_insnbuf rdtlb1_template (void);
3176static xtensa_insnbuf ret_template (void);
3177static xtensa_insnbuf ret_n_template (void);
3178static xtensa_insnbuf retw_template (void);
3179static xtensa_insnbuf retw_n_template (void);
3180static xtensa_insnbuf rfde_template (void);
3181static xtensa_insnbuf rfe_template (void);
3182static xtensa_insnbuf rfi_template (void);
3183static xtensa_insnbuf rfwo_template (void);
3184static xtensa_insnbuf rfwu_template (void);
3185static xtensa_insnbuf ritlb0_template (void);
3186static xtensa_insnbuf ritlb1_template (void);
3187static xtensa_insnbuf rotw_template (void);
3188static xtensa_insnbuf rsil_template (void);
3189static xtensa_insnbuf rsr_template (void);
3190static xtensa_insnbuf rsync_template (void);
3191static xtensa_insnbuf s16i_template (void);
3192static xtensa_insnbuf s32e_template (void);
3193static xtensa_insnbuf s32i_template (void);
3194static xtensa_insnbuf s32i_n_template (void);
3195static xtensa_insnbuf s8i_template (void);
3196static xtensa_insnbuf sdct_template (void);
3197static xtensa_insnbuf sict_template (void);
3198static xtensa_insnbuf sicw_template (void);
3199static xtensa_insnbuf simcall_template (void);
3200static xtensa_insnbuf sll_template (void);
3201static xtensa_insnbuf slli_template (void);
3202static xtensa_insnbuf sra_template (void);
3203static xtensa_insnbuf srai_template (void);
3204static xtensa_insnbuf src_template (void);
3205static xtensa_insnbuf srl_template (void);
3206static xtensa_insnbuf srli_template (void);
3207static xtensa_insnbuf ssa8b_template (void);
3208static xtensa_insnbuf ssa8l_template (void);
3209static xtensa_insnbuf ssai_template (void);
3210static xtensa_insnbuf ssl_template (void);
3211static xtensa_insnbuf ssr_template (void);
3212static xtensa_insnbuf sub_template (void);
3213static xtensa_insnbuf subx2_template (void);
3214static xtensa_insnbuf subx4_template (void);
3215static xtensa_insnbuf subx8_template (void);
3216static xtensa_insnbuf syscall_template (void);
3217static xtensa_insnbuf waiti_template (void);
3218static xtensa_insnbuf wdtlb_template (void);
3219static xtensa_insnbuf witlb_template (void);
3220static xtensa_insnbuf wsr_template (void);
3221static xtensa_insnbuf xor_template (void);
3222static xtensa_insnbuf xsr_template (void);
3223
3224static xtensa_insnbuf
3225abs_template (void)
3226{
3227 static xtensa_insnbuf_word template[] = { 0x00001006 };
3228 return &template[0];
3229}
3230
3231static xtensa_insnbuf
3232add_template (void)
3233{
3234 static xtensa_insnbuf_word template[] = { 0x00000008 };
3235 return &template[0];
3236}
3237
3238static xtensa_insnbuf
3239add_n_template (void)
3240{
3241 static xtensa_insnbuf_word template[] = { 0x00a00000 };
3242 return &template[0];
3243}
3244
3245static xtensa_insnbuf
3246addi_template (void)
3247{
3248 static xtensa_insnbuf_word template[] = { 0x00200c00 };
3249 return &template[0];
3250}
3251
3252static xtensa_insnbuf
3253addi_n_template (void)
3254{
3255 static xtensa_insnbuf_word template[] = { 0x00b00000 };
3256 return &template[0];
3257}
3258
3259static xtensa_insnbuf
3260addmi_template (void)
3261{
3262 static xtensa_insnbuf_word template[] = { 0x00200d00 };
3263 return &template[0];
3264}
3265
3266static xtensa_insnbuf
3267addx2_template (void)
3268{
3269 static xtensa_insnbuf_word template[] = { 0x00000009 };
3270 return &template[0];
3271}
3272
3273static xtensa_insnbuf
3274addx4_template (void)
3275{
3276 static xtensa_insnbuf_word template[] = { 0x0000000a };
3277 return &template[0];
3278}
3279
3280static xtensa_insnbuf
3281addx8_template (void)
3282{
3283 static xtensa_insnbuf_word template[] = { 0x0000000b };
3284 return &template[0];
3285}
3286
3287static xtensa_insnbuf
3288and_template (void)
3289{
3290 static xtensa_insnbuf_word template[] = { 0x00000001 };
3291 return &template[0];
3292}
3293
3294static xtensa_insnbuf
3295ball_template (void)
3296{
3297 static xtensa_insnbuf_word template[] = { 0x00700400 };
3298 return &template[0];
3299}
3300
3301static xtensa_insnbuf
3302bany_template (void)
3303{
3304 static xtensa_insnbuf_word template[] = { 0x00700800 };
3305 return &template[0];
3306}
3307
3308static xtensa_insnbuf
3309bbc_template (void)
3310{
3311 static xtensa_insnbuf_word template[] = { 0x00700500 };
3312 return &template[0];
3313}
3314
3315static xtensa_insnbuf
3316bbci_template (void)
3317{
3318 static xtensa_insnbuf_word template[] = { 0x00700600 };
3319 return &template[0];
3320}
3321
3322static xtensa_insnbuf
3323bbs_template (void)
3324{
3325 static xtensa_insnbuf_word template[] = { 0x00700d00 };
3326 return &template[0];
3327}
3328
3329static xtensa_insnbuf
3330bbsi_template (void)
3331{
3332 static xtensa_insnbuf_word template[] = { 0x00700e00 };
3333 return &template[0];
3334}
3335
3336static xtensa_insnbuf
3337beq_template (void)
3338{
3339 static xtensa_insnbuf_word template[] = { 0x00700100 };
3340 return &template[0];
3341}
3342
3343static xtensa_insnbuf
3344beqi_template (void)
3345{
3346 static xtensa_insnbuf_word template[] = { 0x00680000 };
3347 return &template[0];
3348}
3349
3350static xtensa_insnbuf
3351beqz_template (void)
3352{
3353 static xtensa_insnbuf_word template[] = { 0x00640000 };
3354 return &template[0];
3355}
3356
3357static xtensa_insnbuf
3358beqz_n_template (void)
3359{
3360 static xtensa_insnbuf_word template[] = { 0x00c80000 };
3361 return &template[0];
3362}
3363
3364static xtensa_insnbuf
3365bge_template (void)
3366{
3367 static xtensa_insnbuf_word template[] = { 0x00700a00 };
3368 return &template[0];
3369}
3370
3371static xtensa_insnbuf
3372bgei_template (void)
3373{
3374 static xtensa_insnbuf_word template[] = { 0x006b0000 };
3375 return &template[0];
3376}
3377
3378static xtensa_insnbuf
3379bgeu_template (void)
3380{
3381 static xtensa_insnbuf_word template[] = { 0x00700b00 };
3382 return &template[0];
3383}
3384
3385static xtensa_insnbuf
3386bgeui_template (void)
3387{
3388 static xtensa_insnbuf_word template[] = { 0x006f0000 };
3389 return &template[0];
3390}
3391
3392static xtensa_insnbuf
3393bgez_template (void)
3394{
3395 static xtensa_insnbuf_word template[] = { 0x00670000 };
3396 return &template[0];
3397}
3398
3399static xtensa_insnbuf
3400blt_template (void)
3401{
3402 static xtensa_insnbuf_word template[] = { 0x00700200 };
3403 return &template[0];
3404}
3405
3406static xtensa_insnbuf
3407blti_template (void)
3408{
3409 static xtensa_insnbuf_word template[] = { 0x006a0000 };
3410 return &template[0];
3411}
3412
3413static xtensa_insnbuf
3414bltu_template (void)
3415{
3416 static xtensa_insnbuf_word template[] = { 0x00700300 };
3417 return &template[0];
3418}
3419
3420static xtensa_insnbuf
3421bltui_template (void)
3422{
3423 static xtensa_insnbuf_word template[] = { 0x006e0000 };
3424 return &template[0];
3425}
3426
3427static xtensa_insnbuf
3428bltz_template (void)
3429{
3430 static xtensa_insnbuf_word template[] = { 0x00660000 };
3431 return &template[0];
3432}
3433
3434static xtensa_insnbuf
3435bnall_template (void)
3436{
3437 static xtensa_insnbuf_word template[] = { 0x00700c00 };
3438 return &template[0];
3439}
3440
3441static xtensa_insnbuf
3442bne_template (void)
3443{
3444 static xtensa_insnbuf_word template[] = { 0x00700900 };
3445 return &template[0];
3446}
3447
3448static xtensa_insnbuf
3449bnei_template (void)
3450{
3451 static xtensa_insnbuf_word template[] = { 0x00690000 };
3452 return &template[0];
3453}
3454
3455static xtensa_insnbuf
3456bnez_template (void)
3457{
3458 static xtensa_insnbuf_word template[] = { 0x00650000 };
3459 return &template[0];
3460}
3461
3462static xtensa_insnbuf
3463bnez_n_template (void)
3464{
3465 static xtensa_insnbuf_word template[] = { 0x00cc0000 };
3466 return &template[0];
3467}
3468
3469static xtensa_insnbuf
3470bnone_template (void)
3471{
3472 static xtensa_insnbuf_word template[] = { 0x00700000 };
3473 return &template[0];
3474}
3475
3476static xtensa_insnbuf
3477break_template (void)
3478{
3479 static xtensa_insnbuf_word template[] = { 0x00000400 };
3480 return &template[0];
3481}
3482
3483static xtensa_insnbuf
3484break_n_template (void)
3485{
3486 static xtensa_insnbuf_word template[] = { 0x00d20f00 };
3487 return &template[0];
3488}
3489
3490static xtensa_insnbuf
3491call0_template (void)
3492{
3493 static xtensa_insnbuf_word template[] = { 0x00500000 };
3494 return &template[0];
3495}
3496
3497static xtensa_insnbuf
3498call12_template (void)
3499{
3500 static xtensa_insnbuf_word template[] = { 0x005c0000 };
3501 return &template[0];
3502}
3503
3504static xtensa_insnbuf
3505call4_template (void)
3506{
3507 static xtensa_insnbuf_word template[] = { 0x00540000 };
3508 return &template[0];
3509}
3510
3511static xtensa_insnbuf
3512call8_template (void)
3513{
3514 static xtensa_insnbuf_word template[] = { 0x00580000 };
3515 return &template[0];
3516}
3517
3518static xtensa_insnbuf
3519callx0_template (void)
3520{
3521 static xtensa_insnbuf_word template[] = { 0x00030000 };
3522 return &template[0];
3523}
3524
3525static xtensa_insnbuf
3526callx12_template (void)
3527{
3528 static xtensa_insnbuf_word template[] = { 0x000f0000 };
3529 return &template[0];
3530}
3531
3532static xtensa_insnbuf
3533callx4_template (void)
3534{
3535 static xtensa_insnbuf_word template[] = { 0x00070000 };
3536 return &template[0];
3537}
3538
3539static xtensa_insnbuf
3540callx8_template (void)
3541{
3542 static xtensa_insnbuf_word template[] = { 0x000b0000 };
3543 return &template[0];
3544}
3545
3546static xtensa_insnbuf
3547dhi_template (void)
3548{
3549 static xtensa_insnbuf_word template[] = { 0x00260700 };
3550 return &template[0];
3551}
3552
3553static xtensa_insnbuf
3554dhwb_template (void)
3555{
3556 static xtensa_insnbuf_word template[] = { 0x00240700 };
3557 return &template[0];
3558}
3559
3560static xtensa_insnbuf
3561dhwbi_template (void)
3562{
3563 static xtensa_insnbuf_word template[] = { 0x00250700 };
3564 return &template[0];
3565}
3566
3567static xtensa_insnbuf
3568dii_template (void)
3569{
3570 static xtensa_insnbuf_word template[] = { 0x00270700 };
3571 return &template[0];
3572}
3573
3574static xtensa_insnbuf
3575diwb_template (void)
3576{
3577 static xtensa_insnbuf_word template[] = { 0x00280740 };
3578 return &template[0];
3579}
3580
3581static xtensa_insnbuf
3582diwbi_template (void)
3583{
3584 static xtensa_insnbuf_word template[] = { 0x00280750 };
3585 return &template[0];
3586}
3587
3588static xtensa_insnbuf
3589dpfr_template (void)
3590{
3591 static xtensa_insnbuf_word template[] = { 0x00200700 };
3592 return &template[0];
3593}
3594
3595static xtensa_insnbuf
3596dpfro_template (void)
3597{
3598 static xtensa_insnbuf_word template[] = { 0x00220700 };
3599 return &template[0];
3600}
3601
3602static xtensa_insnbuf
3603dpfw_template (void)
3604{
3605 static xtensa_insnbuf_word template[] = { 0x00210700 };
3606 return &template[0];
3607}
3608
3609static xtensa_insnbuf
3610dpfwo_template (void)
3611{
3612 static xtensa_insnbuf_word template[] = { 0x00230700 };
3613 return &template[0];
3614}
3615
3616static xtensa_insnbuf
3617dsync_template (void)
3618{
3619 static xtensa_insnbuf_word template[] = { 0x00030200 };
3620 return &template[0];
3621}
3622
3623static xtensa_insnbuf
3624entry_template (void)
3625{
3626 static xtensa_insnbuf_word template[] = { 0x006c0000 };
3627 return &template[0];
3628}
3629
3630static xtensa_insnbuf
3631esync_template (void)
3632{
3633 static xtensa_insnbuf_word template[] = { 0x00020200 };
3634 return &template[0];
3635}
3636
3637static xtensa_insnbuf
3638excw_template (void)
3639{
3640 static xtensa_insnbuf_word template[] = { 0x00080200 };
3641 return &template[0];
3642}
3643
3644static xtensa_insnbuf
3645extui_template (void)
3646{
3647 static xtensa_insnbuf_word template[] = { 0x00000040 };
3648 return &template[0];
3649}
3650
3651static xtensa_insnbuf
3652idtlb_template (void)
3653{
3654 static xtensa_insnbuf_word template[] = { 0x00000c05 };
3655 return &template[0];
3656}
3657
3658static xtensa_insnbuf
3659idtlba_template (void)
3660{
3661 static xtensa_insnbuf_word template[] = { 0x00000805 };
3662 return &template[0];
3663}
3664
3665static xtensa_insnbuf
3666ihi_template (void)
3667{
3668 static xtensa_insnbuf_word template[] = { 0x002e0700 };
3669 return &template[0];
3670}
3671
3672static xtensa_insnbuf
3673iii_template (void)
3674{
3675 static xtensa_insnbuf_word template[] = { 0x002f0700 };
3676 return &template[0];
3677}
3678
3679static xtensa_insnbuf
3680iitlb_template (void)
3681{
3682 static xtensa_insnbuf_word template[] = { 0x00000405 };
3683 return &template[0];
3684}
3685
3686static xtensa_insnbuf
3687iitlba_template (void)
3688{
3689 static xtensa_insnbuf_word template[] = { 0x00000005 };
3690 return &template[0];
3691}
3692
3693static xtensa_insnbuf
3694ipf_template (void)
3695{
3696 static xtensa_insnbuf_word template[] = { 0x002c0700 };
3697 return &template[0];
3698}
3699
3700static xtensa_insnbuf
3701isync_template (void)
3702{
3703 static xtensa_insnbuf_word template[] = { 0x00000200 };
3704 return &template[0];
3705}
3706
3707static xtensa_insnbuf
3708j_template (void)
3709{
3710 static xtensa_insnbuf_word template[] = { 0x00600000 };
3711 return &template[0];
3712}
3713
3714static xtensa_insnbuf
3715jx_template (void)
3716{
3717 static xtensa_insnbuf_word template[] = { 0x000a0000 };
3718 return &template[0];
3719}
3720
3721static xtensa_insnbuf
3722l16si_template (void)
3723{
3724 static xtensa_insnbuf_word template[] = { 0x00200900 };
3725 return &template[0];
3726}
3727
3728static xtensa_insnbuf
3729l16ui_template (void)
3730{
3731 static xtensa_insnbuf_word template[] = { 0x00200100 };
3732 return &template[0];
3733}
3734
3735static xtensa_insnbuf
3736l32e_template (void)
3737{
3738 static xtensa_insnbuf_word template[] = { 0x00000090 };
3739 return &template[0];
3740}
3741
3742static xtensa_insnbuf
3743l32i_template (void)
3744{
3745 static xtensa_insnbuf_word template[] = { 0x00200200 };
3746 return &template[0];
3747}
3748
3749static xtensa_insnbuf
3750l32i_n_template (void)
3751{
3752 static xtensa_insnbuf_word template[] = { 0x00800000 };
3753 return &template[0];
3754}
3755
3756static xtensa_insnbuf
3757l32r_template (void)
3758{
3759 static xtensa_insnbuf_word template[] = { 0x00100000 };
3760 return &template[0];
3761}
3762
3763static xtensa_insnbuf
3764l8ui_template (void)
3765{
3766 static xtensa_insnbuf_word template[] = { 0x00200000 };
3767 return &template[0];
3768}
3769
3770static xtensa_insnbuf
3771ldct_template (void)
3772{
3773 static xtensa_insnbuf_word template[] = { 0x0000081f };
3774 return &template[0];
3775}
3776
3777static xtensa_insnbuf
3778lict_template (void)
3779{
3780 static xtensa_insnbuf_word template[] = { 0x0000001f };
3781 return &template[0];
3782}
3783
3784static xtensa_insnbuf
3785licw_template (void)
3786{
3787 static xtensa_insnbuf_word template[] = { 0x0000021f };
3788 return &template[0];
3789}
3790
3791static xtensa_insnbuf
3792loop_template (void)
3793{
3794 static xtensa_insnbuf_word template[] = { 0x006d0800 };
3795 return &template[0];
3796}
3797
3798static xtensa_insnbuf
3799loopgtz_template (void)
3800{
3801 static xtensa_insnbuf_word template[] = { 0x006d0a00 };
3802 return &template[0];
3803}
3804
3805static xtensa_insnbuf
3806loopnez_template (void)
3807{
3808 static xtensa_insnbuf_word template[] = { 0x006d0900 };
3809 return &template[0];
3810}
3811
3812static xtensa_insnbuf
3813memw_template (void)
3814{
3815 static xtensa_insnbuf_word template[] = { 0x000c0200 };
3816 return &template[0];
3817}
3818
3819static xtensa_insnbuf
3820mov_n_template (void)
3821{
3822 static xtensa_insnbuf_word template[] = { 0x00d00000 };
3823 return &template[0];
3824}
3825
3826static xtensa_insnbuf
3827moveqz_template (void)
3828{
3829 static xtensa_insnbuf_word template[] = { 0x00000038 };
3830 return &template[0];
3831}
3832
3833static xtensa_insnbuf
3834movgez_template (void)
3835{
3836 static xtensa_insnbuf_word template[] = { 0x0000003b };
3837 return &template[0];
3838}
3839
3840static xtensa_insnbuf
3841movi_template (void)
3842{
3843 static xtensa_insnbuf_word template[] = { 0x00200a00 };
3844 return &template[0];
3845}
3846
3847static xtensa_insnbuf
3848movi_n_template (void)
3849{
3850 static xtensa_insnbuf_word template[] = { 0x00c00000 };
3851 return &template[0];
3852}
3853
3854static xtensa_insnbuf
3855movltz_template (void)
3856{
3857 static xtensa_insnbuf_word template[] = { 0x0000003a };
3858 return &template[0];
3859}
3860
3861static xtensa_insnbuf
3862movnez_template (void)
3863{
3864 static xtensa_insnbuf_word template[] = { 0x00000039 };
3865 return &template[0];
3866}
3867
3868static xtensa_insnbuf
3869movsp_template (void)
3870{
3871 static xtensa_insnbuf_word template[] = { 0x00000100 };
3872 return &template[0];
3873}
3874
3875static xtensa_insnbuf
3876neg_template (void)
3877{
3878 static xtensa_insnbuf_word template[] = { 0x00000006 };
3879 return &template[0];
3880}
3881
3882static xtensa_insnbuf
3883nop_n_template (void)
3884{
3885 static xtensa_insnbuf_word template[] = { 0x00d30f00 };
3886 return &template[0];
3887}
3888
3889static xtensa_insnbuf
3890nsa_template (void)
3891{
3892 static xtensa_insnbuf_word template[] = { 0x00000e04 };
3893 return &template[0];
3894}
3895
3896static xtensa_insnbuf
3897nsau_template (void)
3898{
3899 static xtensa_insnbuf_word template[] = { 0x00000f04 };
3900 return &template[0];
3901}
3902
3903static xtensa_insnbuf
3904or_template (void)
3905{
3906 static xtensa_insnbuf_word template[] = { 0x00000002 };
3907 return &template[0];
3908}
3909
3910static xtensa_insnbuf
3911pdtlb_template (void)
3912{
3913 static xtensa_insnbuf_word template[] = { 0x00000d05 };
3914 return &template[0];
3915}
3916
3917static xtensa_insnbuf
3918pitlb_template (void)
3919{
3920 static xtensa_insnbuf_word template[] = { 0x00000505 };
3921 return &template[0];
3922}
3923
3924static xtensa_insnbuf
3925rdtlb0_template (void)
3926{
3927 static xtensa_insnbuf_word template[] = { 0x00000b05 };
3928 return &template[0];
3929}
3930
3931static xtensa_insnbuf
3932rdtlb1_template (void)
3933{
3934 static xtensa_insnbuf_word template[] = { 0x00000f05 };
3935 return &template[0];
3936}
3937
3938static xtensa_insnbuf
3939ret_template (void)
3940{
3941 static xtensa_insnbuf_word template[] = { 0x00020000 };
3942 return &template[0];
3943}
3944
3945static xtensa_insnbuf
3946ret_n_template (void)
3947{
3948 static xtensa_insnbuf_word template[] = { 0x00d00f00 };
3949 return &template[0];
3950}
3951
3952static xtensa_insnbuf
3953retw_template (void)
3954{
3955 static xtensa_insnbuf_word template[] = { 0x00060000 };
3956 return &template[0];
3957}
3958
3959static xtensa_insnbuf
3960retw_n_template (void)
3961{
3962 static xtensa_insnbuf_word template[] = { 0x00d10f00 };
3963 return &template[0];
3964}
3965
3966static xtensa_insnbuf
3967rfde_template (void)
3968{
3969 static xtensa_insnbuf_word template[] = { 0x00002300 };
3970 return &template[0];
3971}
3972
3973static xtensa_insnbuf
3974rfe_template (void)
3975{
3976 static xtensa_insnbuf_word template[] = { 0x00000300 };
3977 return &template[0];
3978}
3979
3980static xtensa_insnbuf
3981rfi_template (void)
3982{
3983 static xtensa_insnbuf_word template[] = { 0x00010300 };
3984 return &template[0];
3985}
3986
3987static xtensa_insnbuf
3988rfwo_template (void)
3989{
3990 static xtensa_insnbuf_word template[] = { 0x00004300 };
3991 return &template[0];
3992}
3993
3994static xtensa_insnbuf
3995rfwu_template (void)
3996{
3997 static xtensa_insnbuf_word template[] = { 0x00005300 };
3998 return &template[0];
3999}
4000
4001static xtensa_insnbuf
4002ritlb0_template (void)
4003{
4004 static xtensa_insnbuf_word template[] = { 0x00000305 };
4005 return &template[0];
4006}
4007
4008static xtensa_insnbuf
4009ritlb1_template (void)
4010{
4011 static xtensa_insnbuf_word template[] = { 0x00000705 };
4012 return &template[0];
4013}
4014
4015static xtensa_insnbuf
4016rotw_template (void)
4017{
4018 static xtensa_insnbuf_word template[] = { 0x00000804 };
4019 return &template[0];
4020}
4021
4022static xtensa_insnbuf
4023rsil_template (void)
4024{
4025 static xtensa_insnbuf_word template[] = { 0x00000600 };
4026 return &template[0];
4027}
4028
4029static xtensa_insnbuf
4030rsr_template (void)
4031{
4032 static xtensa_insnbuf_word template[] = { 0x00000030 };
4033 return &template[0];
4034}
4035
4036static xtensa_insnbuf
4037rsync_template (void)
4038{
4039 static xtensa_insnbuf_word template[] = { 0x00010200 };
4040 return &template[0];
4041}
4042
4043static xtensa_insnbuf
4044s16i_template (void)
4045{
4046 static xtensa_insnbuf_word template[] = { 0x00200500 };
4047 return &template[0];
4048}
4049
4050static xtensa_insnbuf
4051s32e_template (void)
4052{
4053 static xtensa_insnbuf_word template[] = { 0x00000094 };
4054 return &template[0];
4055}
4056
4057static xtensa_insnbuf
4058s32i_template (void)
4059{
4060 static xtensa_insnbuf_word template[] = { 0x00200600 };
4061 return &template[0];
4062}
4063
4064static xtensa_insnbuf
4065s32i_n_template (void)
4066{
4067 static xtensa_insnbuf_word template[] = { 0x00900000 };
4068 return &template[0];
4069}
4070
4071static xtensa_insnbuf
4072s8i_template (void)
4073{
4074 static xtensa_insnbuf_word template[] = { 0x00200400 };
4075 return &template[0];
4076}
4077
4078static xtensa_insnbuf
4079sdct_template (void)
4080{
4081 static xtensa_insnbuf_word template[] = { 0x0000091f };
4082 return &template[0];
4083}
4084
4085static xtensa_insnbuf
4086sict_template (void)
4087{
4088 static xtensa_insnbuf_word template[] = { 0x0000011f };
4089 return &template[0];
4090}
4091
4092static xtensa_insnbuf
4093sicw_template (void)
4094{
4095 static xtensa_insnbuf_word template[] = { 0x0000031f };
4096 return &template[0];
4097}
4098
4099static xtensa_insnbuf
4100simcall_template (void)
4101{
4102 static xtensa_insnbuf_word template[] = { 0x00001500 };
4103 return &template[0];
4104}
4105
4106static xtensa_insnbuf
4107sll_template (void)
4108{
4109 static xtensa_insnbuf_word template[] = { 0x0000001a };
4110 return &template[0];
4111}
4112
4113static xtensa_insnbuf
4114slli_template (void)
4115{
4116 static xtensa_insnbuf_word template[] = { 0x00000010 };
4117 return &template[0];
4118}
4119
4120static xtensa_insnbuf
4121sra_template (void)
4122{
4123 static xtensa_insnbuf_word template[] = { 0x0000001b };
4124 return &template[0];
4125}
4126
4127static xtensa_insnbuf
4128srai_template (void)
4129{
4130 static xtensa_insnbuf_word template[] = { 0x00000012 };
4131 return &template[0];
4132}
4133
4134static xtensa_insnbuf
4135src_template (void)
4136{
4137 static xtensa_insnbuf_word template[] = { 0x00000018 };
4138 return &template[0];
4139}
4140
4141static xtensa_insnbuf
4142srl_template (void)
4143{
4144 static xtensa_insnbuf_word template[] = { 0x00000019 };
4145 return &template[0];
4146}
4147
4148static xtensa_insnbuf
4149srli_template (void)
4150{
4151 static xtensa_insnbuf_word template[] = { 0x00000014 };
4152 return &template[0];
4153}
4154
4155static xtensa_insnbuf
4156ssa8b_template (void)
4157{
4158 static xtensa_insnbuf_word template[] = { 0x00000304 };
4159 return &template[0];
4160}
4161
4162static xtensa_insnbuf
4163ssa8l_template (void)
4164{
4165 static xtensa_insnbuf_word template[] = { 0x00000204 };
4166 return &template[0];
4167}
4168
4169static xtensa_insnbuf
4170ssai_template (void)
4171{
4172 static xtensa_insnbuf_word template[] = { 0x00000404 };
4173 return &template[0];
4174}
4175
4176static xtensa_insnbuf
4177ssl_template (void)
4178{
4179 static xtensa_insnbuf_word template[] = { 0x00000104 };
4180 return &template[0];
4181}
4182
4183static xtensa_insnbuf
4184ssr_template (void)
4185{
4186 static xtensa_insnbuf_word template[] = { 0x00000004 };
4187 return &template[0];
4188}
4189
4190static xtensa_insnbuf
4191sub_template (void)
4192{
4193 static xtensa_insnbuf_word template[] = { 0x0000000c };
4194 return &template[0];
4195}
4196
4197static xtensa_insnbuf
4198subx2_template (void)
4199{
4200 static xtensa_insnbuf_word template[] = { 0x0000000d };
4201 return &template[0];
4202}
4203
4204static xtensa_insnbuf
4205subx4_template (void)
4206{
4207 static xtensa_insnbuf_word template[] = { 0x0000000e };
4208 return &template[0];
4209}
4210
4211static xtensa_insnbuf
4212subx8_template (void)
4213{
4214 static xtensa_insnbuf_word template[] = { 0x0000000f };
4215 return &template[0];
4216}
4217
4218static xtensa_insnbuf
4219syscall_template (void)
4220{
4221 static xtensa_insnbuf_word template[] = { 0x00000500 };
4222 return &template[0];
4223}
4224
4225static xtensa_insnbuf
4226waiti_template (void)
4227{
4228 static xtensa_insnbuf_word template[] = { 0x00000700 };
4229 return &template[0];
4230}
4231
4232static xtensa_insnbuf
4233wdtlb_template (void)
4234{
4235 static xtensa_insnbuf_word template[] = { 0x00000e05 };
4236 return &template[0];
4237}
4238
4239static xtensa_insnbuf
4240witlb_template (void)
4241{
4242 static xtensa_insnbuf_word template[] = { 0x00000605 };
4243 return &template[0];
4244}
4245
4246static xtensa_insnbuf
4247wsr_template (void)
4248{
4249 static xtensa_insnbuf_word template[] = { 0x00000031 };
4250 return &template[0];
4251}
4252
4253static xtensa_insnbuf
4254xor_template (void)
4255{
4256 static xtensa_insnbuf_word template[] = { 0x00000003 };
4257 return &template[0];
4258}
4259
4260static xtensa_insnbuf
4261xsr_template (void)
4262{
4263 static xtensa_insnbuf_word template[] = { 0x00000016 };
4264 return &template[0];
4265}
4266
4267static xtensa_opcode_internal abs_opcode = {
4268 "abs",
4269 3,
4270 abs_template,
4271 &neg_iclass
4272};
4273
4274static xtensa_opcode_internal add_opcode = {
4275 "add",
4276 3,
4277 add_template,
4278 &addsub_iclass
4279};
4280
4281static xtensa_opcode_internal add_n_opcode = {
4282 "add.n",
4283 2,
4284 add_n_template,
4285 &add_n_iclass
4286};
4287
4288static xtensa_opcode_internal addi_opcode = {
4289 "addi",
4290 3,
4291 addi_template,
4292 &addi_iclass
4293};
4294
4295static xtensa_opcode_internal addi_n_opcode = {
4296 "addi.n",
4297 2,
4298 addi_n_template,
4299 &addi_n_iclass
4300};
4301
4302static xtensa_opcode_internal addmi_opcode = {
4303 "addmi",
4304 3,
4305 addmi_template,
4306 &addmi_iclass
4307};
4308
4309static xtensa_opcode_internal addx2_opcode = {
4310 "addx2",
4311 3,
4312 addx2_template,
4313 &addsub_iclass
4314};
4315
4316static xtensa_opcode_internal addx4_opcode = {
4317 "addx4",
4318 3,
4319 addx4_template,
4320 &addsub_iclass
4321};
4322
4323static xtensa_opcode_internal addx8_opcode = {
4324 "addx8",
4325 3,
4326 addx8_template,
4327 &addsub_iclass
4328};
4329
4330static xtensa_opcode_internal and_opcode = {
4331 "and",
4332 3,
4333 and_template,
4334 &bit_iclass
4335};
4336
4337static xtensa_opcode_internal ball_opcode = {
4338 "ball",
4339 3,
4340 ball_template,
4341 &bst8_iclass
4342};
4343
4344static xtensa_opcode_internal bany_opcode = {
4345 "bany",
4346 3,
4347 bany_template,
4348 &bst8_iclass
4349};
4350
4351static xtensa_opcode_internal bbc_opcode = {
4352 "bbc",
4353 3,
4354 bbc_template,
4355 &bst8_iclass
4356};
4357
4358static xtensa_opcode_internal bbci_opcode = {
4359 "bbci",
4360 3,
4361 bbci_template,
4362 &bsi8b_iclass
4363};
4364
4365static xtensa_opcode_internal bbs_opcode = {
4366 "bbs",
4367 3,
4368 bbs_template,
4369 &bst8_iclass
4370};
4371
4372static xtensa_opcode_internal bbsi_opcode = {
4373 "bbsi",
4374 3,
4375 bbsi_template,
4376 &bsi8b_iclass
4377};
4378
4379static xtensa_opcode_internal beq_opcode = {
4380 "beq",
4381 3,
4382 beq_template,
4383 &bst8_iclass
4384};
4385
4386static xtensa_opcode_internal beqi_opcode = {
4387 "beqi",
4388 3,
4389 beqi_template,
4390 &bsi8_iclass
4391};
4392
4393static xtensa_opcode_internal beqz_opcode = {
4394 "beqz",
4395 3,
4396 beqz_template,
4397 &bsz12_iclass
4398};
4399
4400static xtensa_opcode_internal beqz_n_opcode = {
4401 "beqz.n",
4402 2,
4403 beqz_n_template,
4404 &bz6_iclass
4405};
4406
4407static xtensa_opcode_internal bge_opcode = {
4408 "bge",
4409 3,
4410 bge_template,
4411 &bst8_iclass
4412};
4413
4414static xtensa_opcode_internal bgei_opcode = {
4415 "bgei",
4416 3,
4417 bgei_template,
4418 &bsi8_iclass
4419};
4420
4421static xtensa_opcode_internal bgeu_opcode = {
4422 "bgeu",
4423 3,
4424 bgeu_template,
4425 &bst8_iclass
4426};
4427
4428static xtensa_opcode_internal bgeui_opcode = {
4429 "bgeui",
4430 3,
4431 bgeui_template,
4432 &bsi8u_iclass
4433};
4434
4435static xtensa_opcode_internal bgez_opcode = {
4436 "bgez",
4437 3,
4438 bgez_template,
4439 &bsz12_iclass
4440};
4441
4442static xtensa_opcode_internal blt_opcode = {
4443 "blt",
4444 3,
4445 blt_template,
4446 &bst8_iclass
4447};
4448
4449static xtensa_opcode_internal blti_opcode = {
4450 "blti",
4451 3,
4452 blti_template,
4453 &bsi8_iclass
4454};
4455
4456static xtensa_opcode_internal bltu_opcode = {
4457 "bltu",
4458 3,
4459 bltu_template,
4460 &bst8_iclass
4461};
4462
4463static xtensa_opcode_internal bltui_opcode = {
4464 "bltui",
4465 3,
4466 bltui_template,
4467 &bsi8u_iclass
4468};
4469
4470static xtensa_opcode_internal bltz_opcode = {
4471 "bltz",
4472 3,
4473 bltz_template,
4474 &bsz12_iclass
4475};
4476
4477static xtensa_opcode_internal bnall_opcode = {
4478 "bnall",
4479 3,
4480 bnall_template,
4481 &bst8_iclass
4482};
4483
4484static xtensa_opcode_internal bne_opcode = {
4485 "bne",
4486 3,
4487 bne_template,
4488 &bst8_iclass
4489};
4490
4491static xtensa_opcode_internal bnei_opcode = {
4492 "bnei",
4493 3,
4494 bnei_template,
4495 &bsi8_iclass
4496};
4497
4498static xtensa_opcode_internal bnez_opcode = {
4499 "bnez",
4500 3,
4501 bnez_template,
4502 &bsz12_iclass
4503};
4504
4505static xtensa_opcode_internal bnez_n_opcode = {
4506 "bnez.n",
4507 2,
4508 bnez_n_template,
4509 &bz6_iclass
4510};
4511
4512static xtensa_opcode_internal bnone_opcode = {
4513 "bnone",
4514 3,
4515 bnone_template,
4516 &bst8_iclass
4517};
4518
4519static xtensa_opcode_internal break_opcode = {
4520 "break",
4521 3,
4522 break_template,
4523 &break_iclass
4524};
4525
4526static xtensa_opcode_internal break_n_opcode = {
4527 "break.n",
4528 2,
4529 break_n_template,
4530 &break_n_iclass
4531};
4532
4533static xtensa_opcode_internal call0_opcode = {
4534 "call0",
4535 3,
4536 call0_template,
4537 &call_iclass
4538};
4539
4540static xtensa_opcode_internal call12_opcode = {
4541 "call12",
4542 3,
4543 call12_template,
4544 &call12_iclass
4545};
4546
4547static xtensa_opcode_internal call4_opcode = {
4548 "call4",
4549 3,
4550 call4_template,
4551 &call4_iclass
4552};
4553
4554static xtensa_opcode_internal call8_opcode = {
4555 "call8",
4556 3,
4557 call8_template,
4558 &call8_iclass
4559};
4560
4561static xtensa_opcode_internal callx0_opcode = {
4562 "callx0",
4563 3,
4564 callx0_template,
4565 &callx_iclass
4566};
4567
4568static xtensa_opcode_internal callx12_opcode = {
4569 "callx12",
4570 3,
4571 callx12_template,
4572 &callx12_iclass
4573};
4574
4575static xtensa_opcode_internal callx4_opcode = {
4576 "callx4",
4577 3,
4578 callx4_template,
4579 &callx4_iclass
4580};
4581
4582static xtensa_opcode_internal callx8_opcode = {
4583 "callx8",
4584 3,
4585 callx8_template,
4586 &callx8_iclass
4587};
4588
4589static xtensa_opcode_internal dhi_opcode = {
4590 "dhi",
4591 3,
4592 dhi_template,
4593 &dcache_iclass
4594};
4595
4596static xtensa_opcode_internal dhwb_opcode = {
4597 "dhwb",
4598 3,
4599 dhwb_template,
4600 &dcache_iclass
4601};
4602
4603static xtensa_opcode_internal dhwbi_opcode = {
4604 "dhwbi",
4605 3,
4606 dhwbi_template,
4607 &dcache_iclass
4608};
4609
4610static xtensa_opcode_internal dii_opcode = {
4611 "dii",
4612 3,
4613 dii_template,
4614 &dcache_iclass
4615};
4616
4617static xtensa_opcode_internal diwb_opcode = {
4618 "diwb",
4619 3,
4620 diwb_template,
4621 &dce_iclass
4622};
4623
4624static xtensa_opcode_internal diwbi_opcode = {
4625 "diwbi",
4626 3,
4627 diwbi_template,
4628 &dce_iclass
4629};
4630
4631static xtensa_opcode_internal dpfr_opcode = {
4632 "dpfr",
4633 3,
4634 dpfr_template,
4635 &dpf_iclass
4636};
4637
4638static xtensa_opcode_internal dpfro_opcode = {
4639 "dpfro",
4640 3,
4641 dpfro_template,
4642 &dpf_iclass
4643};
4644
4645static xtensa_opcode_internal dpfw_opcode = {
4646 "dpfw",
4647 3,
4648 dpfw_template,
4649 &dpf_iclass
4650};
4651
4652static xtensa_opcode_internal dpfwo_opcode = {
4653 "dpfwo",
4654 3,
4655 dpfwo_template,
4656 &dpf_iclass
4657};
4658
4659static xtensa_opcode_internal dsync_opcode = {
4660 "dsync",
4661 3,
4662 dsync_template,
4663 &sync_iclass
4664};
4665
4666static xtensa_opcode_internal entry_opcode = {
4667 "entry",
4668 3,
4669 entry_template,
4670 &entry_iclass
4671};
4672
4673static xtensa_opcode_internal esync_opcode = {
4674 "esync",
4675 3,
4676 esync_template,
4677 &sync_iclass
4678};
4679
4680static xtensa_opcode_internal excw_opcode = {
4681 "excw",
4682 3,
4683 excw_template,
4684 &excw_iclass
4685};
4686
4687static xtensa_opcode_internal extui_opcode = {
4688 "extui",
4689 3,
4690 extui_template,
4691 &exti_iclass
4692};
4693
4694static xtensa_opcode_internal idtlb_opcode = {
4695 "idtlb",
4696 3,
4697 idtlb_template,
4698 &itlb_iclass
4699};
4700
4701static xtensa_opcode_internal idtlba_opcode = {
4702 "idtlba",
4703 3,
4704 idtlba_template,
4705 &itlba_iclass
4706};
4707
4708static xtensa_opcode_internal ihi_opcode = {
4709 "ihi",
4710 3,
4711 ihi_template,
4712 &icache_iclass
4713};
4714
4715static xtensa_opcode_internal iii_opcode = {
4716 "iii",
4717 3,
4718 iii_template,
4719 &icache_iclass
4720};
4721
4722static xtensa_opcode_internal iitlb_opcode = {
4723 "iitlb",
4724 3,
4725 iitlb_template,
4726 &itlb_iclass
4727};
4728
4729static xtensa_opcode_internal iitlba_opcode = {
4730 "iitlba",
4731 3,
4732 iitlba_template,
4733 &itlba_iclass
4734};
4735
4736static xtensa_opcode_internal ipf_opcode = {
4737 "ipf",
4738 3,
4739 ipf_template,
4740 &icache_iclass
4741};
4742
4743static xtensa_opcode_internal isync_opcode = {
4744 "isync",
4745 3,
4746 isync_template,
4747 &sync_iclass
4748};
4749
4750static xtensa_opcode_internal j_opcode = {
4751 "j",
4752 3,
4753 j_template,
4754 &jump_iclass
4755};
4756
4757static xtensa_opcode_internal jx_opcode = {
4758 "jx",
4759 3,
4760 jx_template,
4761 &jumpx_iclass
4762};
4763
4764static xtensa_opcode_internal l16si_opcode = {
4765 "l16si",
4766 3,
4767 l16si_template,
4768 &l16i_iclass
4769};
4770
4771static xtensa_opcode_internal l16ui_opcode = {
4772 "l16ui",
4773 3,
4774 l16ui_template,
4775 &l16i_iclass
4776};
4777
4778static xtensa_opcode_internal l32e_opcode = {
4779 "l32e",
4780 3,
4781 l32e_template,
4782 &l32e_iclass
4783};
4784
4785static xtensa_opcode_internal l32i_opcode = {
4786 "l32i",
4787 3,
4788 l32i_template,
4789 &l32i_iclass
4790};
4791
4792static xtensa_opcode_internal l32i_n_opcode = {
4793 "l32i.n",
4794 2,
4795 l32i_n_template,
4796 &loadi4_iclass
4797};
4798
4799static xtensa_opcode_internal l32r_opcode = {
4800 "l32r",
4801 3,
4802 l32r_template,
4803 &l32r_iclass
4804};
4805
4806static xtensa_opcode_internal l8ui_opcode = {
4807 "l8ui",
4808 3,
4809 l8ui_template,
4810 &l8i_iclass
4811};
4812
4813static xtensa_opcode_internal ldct_opcode = {
4814 "ldct",
4815 3,
4816 ldct_template,
4817 &actl_iclass
4818};
4819
4820static xtensa_opcode_internal lict_opcode = {
4821 "lict",
4822 3,
4823 lict_template,
4824 &actl_iclass
4825};
4826
4827static xtensa_opcode_internal licw_opcode = {
4828 "licw",
4829 3,
4830 licw_template,
4831 &actl_iclass
4832};
4833
4834static xtensa_opcode_internal loop_opcode = {
4835 "loop",
4836 3,
4837 loop_template,
4838 &loop_iclass
4839};
4840
4841static xtensa_opcode_internal loopgtz_opcode = {
4842 "loopgtz",
4843 3,
4844 loopgtz_template,
4845 &loop_iclass
4846};
4847
4848static xtensa_opcode_internal loopnez_opcode = {
4849 "loopnez",
4850 3,
4851 loopnez_template,
4852 &loop_iclass
4853};
4854
4855static xtensa_opcode_internal memw_opcode = {
4856 "memw",
4857 3,
4858 memw_template,
4859 &sync_iclass
4860};
4861
4862static xtensa_opcode_internal mov_n_opcode = {
4863 "mov.n",
4864 2,
4865 mov_n_template,
4866 &mov_n_iclass
4867};
4868
4869static xtensa_opcode_internal moveqz_opcode = {
4870 "moveqz",
4871 3,
4872 moveqz_template,
4873 &movz_iclass
4874};
4875
4876static xtensa_opcode_internal movgez_opcode = {
4877 "movgez",
4878 3,
4879 movgez_template,
4880 &movz_iclass
4881};
4882
4883static xtensa_opcode_internal movi_opcode = {
4884 "movi",
4885 3,
4886 movi_template,
4887 &movi_iclass
4888};
4889
4890static xtensa_opcode_internal movi_n_opcode = {
4891 "movi.n",
4892 2,
4893 movi_n_template,
4894 &movi_n_iclass
4895};
4896
4897static xtensa_opcode_internal movltz_opcode = {
4898 "movltz",
4899 3,
4900 movltz_template,
4901 &movz_iclass
4902};
4903
4904static xtensa_opcode_internal movnez_opcode = {
4905 "movnez",
4906 3,
4907 movnez_template,
4908 &movz_iclass
4909};
4910
4911static xtensa_opcode_internal movsp_opcode = {
4912 "movsp",
4913 3,
4914 movsp_template,
4915 &movsp_iclass
4916};
4917
4918static xtensa_opcode_internal neg_opcode = {
4919 "neg",
4920 3,
4921 neg_template,
4922 &neg_iclass
4923};
4924
4925static xtensa_opcode_internal nop_n_opcode = {
4926 "nop.n",
4927 2,
4928 nop_n_template,
4929 &nopn_iclass
4930};
4931
4932static xtensa_opcode_internal nsa_opcode = {
4933 "nsa",
4934 3,
4935 nsa_template,
4936 &nsa_iclass
4937};
4938
4939static xtensa_opcode_internal nsau_opcode = {
4940 "nsau",
4941 3,
4942 nsau_template,
4943 &nsa_iclass
4944};
4945
4946static xtensa_opcode_internal or_opcode = {
4947 "or",
4948 3,
4949 or_template,
4950 &bit_iclass
4951};
4952
4953static xtensa_opcode_internal pdtlb_opcode = {
4954 "pdtlb",
4955 3,
4956 pdtlb_template,
4957 &rtlb_iclass
4958};
4959
4960static xtensa_opcode_internal pitlb_opcode = {
4961 "pitlb",
4962 3,
4963 pitlb_template,
4964 &rtlb_iclass
4965};
4966
4967static xtensa_opcode_internal rdtlb0_opcode = {
4968 "rdtlb0",
4969 3,
4970 rdtlb0_template,
4971 &rtlb_iclass
4972};
4973
4974static xtensa_opcode_internal rdtlb1_opcode = {
4975 "rdtlb1",
4976 3,
4977 rdtlb1_template,
4978 &rtlb_iclass
4979};
4980
4981static xtensa_opcode_internal ret_opcode = {
4982 "ret",
4983 3,
4984 ret_template,
4985 &return_iclass
4986};
4987
4988static xtensa_opcode_internal ret_n_opcode = {
4989 "ret.n",
4990 2,
4991 ret_n_template,
4992 &retn_iclass
4993};
4994
4995static xtensa_opcode_internal retw_opcode = {
4996 "retw",
4997 3,
4998 retw_template,
4999 &return_iclass
5000};
5001
5002static xtensa_opcode_internal retw_n_opcode = {
5003 "retw.n",
5004 2,
5005 retw_n_template,
5006 &retn_iclass
5007};
5008
5009static xtensa_opcode_internal rfde_opcode = {
5010 "rfde",
5011 3,
5012 rfde_template,
5013 &rfe_iclass
5014};
5015
5016static xtensa_opcode_internal rfe_opcode = {
5017 "rfe",
5018 3,
5019 rfe_template,
5020 &rfe_iclass
5021};
5022
5023static xtensa_opcode_internal rfi_opcode = {
5024 "rfi",
5025 3,
5026 rfi_template,
5027 &rfi_iclass
5028};
5029
5030static xtensa_opcode_internal rfwo_opcode = {
5031 "rfwo",
5032 3,
5033 rfwo_template,
5034 &rfe_iclass
5035};
5036
5037static xtensa_opcode_internal rfwu_opcode = {
5038 "rfwu",
5039 3,
5040 rfwu_template,
5041 &rfe_iclass
5042};
5043
5044static xtensa_opcode_internal ritlb0_opcode = {
5045 "ritlb0",
5046 3,
5047 ritlb0_template,
5048 &rtlb_iclass
5049};
5050
5051static xtensa_opcode_internal ritlb1_opcode = {
5052 "ritlb1",
5053 3,
5054 ritlb1_template,
5055 &rtlb_iclass
5056};
5057
5058static xtensa_opcode_internal rotw_opcode = {
5059 "rotw",
5060 3,
5061 rotw_template,
5062 &rotw_iclass
5063};
5064
5065static xtensa_opcode_internal rsil_opcode = {
5066 "rsil",
5067 3,
5068 rsil_template,
5069 &rsil_iclass
5070};
5071
5072static xtensa_opcode_internal rsr_opcode = {
5073 "rsr",
5074 3,
5075 rsr_template,
5076 &rsr_iclass
5077};
5078
5079static xtensa_opcode_internal rsync_opcode = {
5080 "rsync",
5081 3,
5082 rsync_template,
5083 &sync_iclass
5084};
5085
5086static xtensa_opcode_internal s16i_opcode = {
5087 "s16i",
5088 3,
5089 s16i_template,
5090 &s16i_iclass
5091};
5092
5093static xtensa_opcode_internal s32e_opcode = {
5094 "s32e",
5095 3,
5096 s32e_template,
5097 &s32e_iclass
5098};
5099
5100static xtensa_opcode_internal s32i_opcode = {
5101 "s32i",
5102 3,
5103 s32i_template,
5104 &s32i_iclass
5105};
5106
5107static xtensa_opcode_internal s32i_n_opcode = {
5108 "s32i.n",
5109 2,
5110 s32i_n_template,
5111 &storei4_iclass
5112};
5113
5114static xtensa_opcode_internal s8i_opcode = {
5115 "s8i",
5116 3,
5117 s8i_template,
5118 &s8i_iclass
5119};
5120
5121static xtensa_opcode_internal sdct_opcode = {
5122 "sdct",
5123 3,
5124 sdct_template,
5125 &acts_iclass
5126};
5127
5128static xtensa_opcode_internal sict_opcode = {
5129 "sict",
5130 3,
5131 sict_template,
5132 &acts_iclass
5133};
5134
5135static xtensa_opcode_internal sicw_opcode = {
5136 "sicw",
5137 3,
5138 sicw_template,
5139 &acts_iclass
5140};
5141
5142static xtensa_opcode_internal simcall_opcode = {
5143 "simcall",
5144 3,
5145 simcall_template,
5146 &syscall_iclass
5147};
5148
5149static xtensa_opcode_internal sll_opcode = {
5150 "sll",
5151 3,
5152 sll_template,
5153 &shifts_iclass
5154};
5155
5156static xtensa_opcode_internal slli_opcode = {
5157 "slli",
5158 3,
5159 slli_template,
5160 &slli_iclass
5161};
5162
5163static xtensa_opcode_internal sra_opcode = {
5164 "sra",
5165 3,
5166 sra_template,
5167 &shiftt_iclass
5168};
5169
5170static xtensa_opcode_internal srai_opcode = {
5171 "srai",
5172 3,
5173 srai_template,
5174 &srai_iclass
5175};
5176
5177static xtensa_opcode_internal src_opcode = {
5178 "src",
5179 3,
5180 src_template,
5181 &shiftst_iclass
5182};
5183
5184static xtensa_opcode_internal srl_opcode = {
5185 "srl",
5186 3,
5187 srl_template,
5188 &shiftt_iclass
5189};
5190
5191static xtensa_opcode_internal srli_opcode = {
5192 "srli",
5193 3,
5194 srli_template,
5195 &srli_iclass
5196};
5197
5198static xtensa_opcode_internal ssa8b_opcode = {
5199 "ssa8b",
5200 3,
5201 ssa8b_template,
5202 &sar_iclass
5203};
5204
5205static xtensa_opcode_internal ssa8l_opcode = {
5206 "ssa8l",
5207 3,
5208 ssa8l_template,
5209 &sar_iclass
5210};
5211
5212static xtensa_opcode_internal ssai_opcode = {
5213 "ssai",
5214 3,
5215 ssai_template,
5216 &sari_iclass
5217};
5218
5219static xtensa_opcode_internal ssl_opcode = {
5220 "ssl",
5221 3,
5222 ssl_template,
5223 &sar_iclass
5224};
5225
5226static xtensa_opcode_internal ssr_opcode = {
5227 "ssr",
5228 3,
5229 ssr_template,
5230 &sar_iclass
5231};
5232
5233static xtensa_opcode_internal sub_opcode = {
5234 "sub",
5235 3,
5236 sub_template,
5237 &addsub_iclass
5238};
5239
5240static xtensa_opcode_internal subx2_opcode = {
5241 "subx2",
5242 3,
5243 subx2_template,
5244 &addsub_iclass
5245};
5246
5247static xtensa_opcode_internal subx4_opcode = {
5248 "subx4",
5249 3,
5250 subx4_template,
5251 &addsub_iclass
5252};
5253
5254static xtensa_opcode_internal subx8_opcode = {
5255 "subx8",
5256 3,
5257 subx8_template,
5258 &addsub_iclass
5259};
5260
5261static xtensa_opcode_internal syscall_opcode = {
5262 "syscall",
5263 3,
5264 syscall_template,
5265 &syscall_iclass
5266};
5267
5268static xtensa_opcode_internal waiti_opcode = {
5269 "waiti",
5270 3,
5271 waiti_template,
5272 &wait_iclass
5273};
5274
5275static xtensa_opcode_internal wdtlb_opcode = {
5276 "wdtlb",
5277 3,
5278 wdtlb_template,
5279 &wtlb_iclass
5280};
5281
5282static xtensa_opcode_internal witlb_opcode = {
5283 "witlb",
5284 3,
5285 witlb_template,
5286 &wtlb_iclass
5287};
5288
5289static xtensa_opcode_internal wsr_opcode = {
5290 "wsr",
5291 3,
5292 wsr_template,
5293 &wsr_iclass
5294};
5295
5296static xtensa_opcode_internal xor_opcode = {
5297 "xor",
5298 3,
5299 xor_template,
5300 &bit_iclass
5301};
5302
5303static xtensa_opcode_internal xsr_opcode = {
5304 "xsr",
5305 3,
5306 xsr_template,
5307 &xsr_iclass
5308};
5309
5310static xtensa_opcode_internal * opcodes[149] = {
5311 &abs_opcode,
5312 &add_opcode,
5313 &add_n_opcode,
5314 &addi_opcode,
5315 &addi_n_opcode,
5316 &addmi_opcode,
5317 &addx2_opcode,
5318 &addx4_opcode,
5319 &addx8_opcode,
5320 &and_opcode,
5321 &ball_opcode,
5322 &bany_opcode,
5323 &bbc_opcode,
5324 &bbci_opcode,
5325 &bbs_opcode,
5326 &bbsi_opcode,
5327 &beq_opcode,
5328 &beqi_opcode,
5329 &beqz_opcode,
5330 &beqz_n_opcode,
5331 &bge_opcode,
5332 &bgei_opcode,
5333 &bgeu_opcode,
5334 &bgeui_opcode,
5335 &bgez_opcode,
5336 &blt_opcode,
5337 &blti_opcode,
5338 &bltu_opcode,
5339 &bltui_opcode,
5340 &bltz_opcode,
5341 &bnall_opcode,
5342 &bne_opcode,
5343 &bnei_opcode,
5344 &bnez_opcode,
5345 &bnez_n_opcode,
5346 &bnone_opcode,
5347 &break_opcode,
5348 &break_n_opcode,
5349 &call0_opcode,
5350 &call12_opcode,
5351 &call4_opcode,
5352 &call8_opcode,
5353 &callx0_opcode,
5354 &callx12_opcode,
5355 &callx4_opcode,
5356 &callx8_opcode,
5357 &dhi_opcode,
5358 &dhwb_opcode,
5359 &dhwbi_opcode,
5360 &dii_opcode,
5361 &diwb_opcode,
5362 &diwbi_opcode,
5363 &dpfr_opcode,
5364 &dpfro_opcode,
5365 &dpfw_opcode,
5366 &dpfwo_opcode,
5367 &dsync_opcode,
5368 &entry_opcode,
5369 &esync_opcode,
5370 &excw_opcode,
5371 &extui_opcode,
5372 &idtlb_opcode,
5373 &idtlba_opcode,
5374 &ihi_opcode,
5375 &iii_opcode,
5376 &iitlb_opcode,
5377 &iitlba_opcode,
5378 &ipf_opcode,
5379 &isync_opcode,
5380 &j_opcode,
5381 &jx_opcode,
5382 &l16si_opcode,
5383 &l16ui_opcode,
5384 &l32e_opcode,
5385 &l32i_opcode,
5386 &l32i_n_opcode,
5387 &l32r_opcode,
5388 &l8ui_opcode,
5389 &ldct_opcode,
5390 &lict_opcode,
5391 &licw_opcode,
5392 &loop_opcode,
5393 &loopgtz_opcode,
5394 &loopnez_opcode,
5395 &memw_opcode,
5396 &mov_n_opcode,
5397 &moveqz_opcode,
5398 &movgez_opcode,
5399 &movi_opcode,
5400 &movi_n_opcode,
5401 &movltz_opcode,
5402 &movnez_opcode,
5403 &movsp_opcode,
5404 &neg_opcode,
5405 &nop_n_opcode,
5406 &nsa_opcode,
5407 &nsau_opcode,
5408 &or_opcode,
5409 &pdtlb_opcode,
5410 &pitlb_opcode,
5411 &rdtlb0_opcode,
5412 &rdtlb1_opcode,
5413 &ret_opcode,
5414 &ret_n_opcode,
5415 &retw_opcode,
5416 &retw_n_opcode,
5417 &rfde_opcode,
5418 &rfe_opcode,
5419 &rfi_opcode,
5420 &rfwo_opcode,
5421 &rfwu_opcode,
5422 &ritlb0_opcode,
5423 &ritlb1_opcode,
5424 &rotw_opcode,
5425 &rsil_opcode,
5426 &rsr_opcode,
5427 &rsync_opcode,
5428 &s16i_opcode,
5429 &s32e_opcode,
5430 &s32i_opcode,
5431 &s32i_n_opcode,
5432 &s8i_opcode,
5433 &sdct_opcode,
5434 &sict_opcode,
5435 &sicw_opcode,
5436 &simcall_opcode,
5437 &sll_opcode,
5438 &slli_opcode,
5439 &sra_opcode,
5440 &srai_opcode,
5441 &src_opcode,
5442 &srl_opcode,
5443 &srli_opcode,
5444 &ssa8b_opcode,
5445 &ssa8l_opcode,
5446 &ssai_opcode,
5447 &ssl_opcode,
5448 &ssr_opcode,
5449 &sub_opcode,
5450 &subx2_opcode,
5451 &subx4_opcode,
5452 &subx8_opcode,
5453 &syscall_opcode,
5454 &waiti_opcode,
5455 &wdtlb_opcode,
5456 &witlb_opcode,
5457 &wsr_opcode,
5458 &xor_opcode,
5459 &xsr_opcode
5460};
5461
5462xtensa_opcode_internal **
5463get_opcodes (void)
5464{
5465 return &opcodes[0];
5466}
5467
5468const int
5469get_num_opcodes (void)
5470{
5471 return 149;
5472}
5473
5474#define xtensa_abs_op 0
5475#define xtensa_add_op 1
5476#define xtensa_add_n_op 2
5477#define xtensa_addi_op 3
5478#define xtensa_addi_n_op 4
5479#define xtensa_addmi_op 5
5480#define xtensa_addx2_op 6
5481#define xtensa_addx4_op 7
5482#define xtensa_addx8_op 8
5483#define xtensa_and_op 9
5484#define xtensa_ball_op 10
5485#define xtensa_bany_op 11
5486#define xtensa_bbc_op 12
5487#define xtensa_bbci_op 13
5488#define xtensa_bbs_op 14
5489#define xtensa_bbsi_op 15
5490#define xtensa_beq_op 16
5491#define xtensa_beqi_op 17
5492#define xtensa_beqz_op 18
5493#define xtensa_beqz_n_op 19
5494#define xtensa_bge_op 20
5495#define xtensa_bgei_op 21
5496#define xtensa_bgeu_op 22
5497#define xtensa_bgeui_op 23
5498#define xtensa_bgez_op 24
5499#define xtensa_blt_op 25
5500#define xtensa_blti_op 26
5501#define xtensa_bltu_op 27
5502#define xtensa_bltui_op 28
5503#define xtensa_bltz_op 29
5504#define xtensa_bnall_op 30
5505#define xtensa_bne_op 31
5506#define xtensa_bnei_op 32
5507#define xtensa_bnez_op 33
5508#define xtensa_bnez_n_op 34
5509#define xtensa_bnone_op 35
5510#define xtensa_break_op 36
5511#define xtensa_break_n_op 37
5512#define xtensa_call0_op 38
5513#define xtensa_call12_op 39
5514#define xtensa_call4_op 40
5515#define xtensa_call8_op 41
5516#define xtensa_callx0_op 42
5517#define xtensa_callx12_op 43
5518#define xtensa_callx4_op 44
5519#define xtensa_callx8_op 45
5520#define xtensa_dhi_op 46
5521#define xtensa_dhwb_op 47
5522#define xtensa_dhwbi_op 48
5523#define xtensa_dii_op 49
5524#define xtensa_diwb_op 50
5525#define xtensa_diwbi_op 51
5526#define xtensa_dpfr_op 52
5527#define xtensa_dpfro_op 53
5528#define xtensa_dpfw_op 54
5529#define xtensa_dpfwo_op 55
5530#define xtensa_dsync_op 56
5531#define xtensa_entry_op 57
5532#define xtensa_esync_op 58
5533#define xtensa_excw_op 59
5534#define xtensa_extui_op 60
5535#define xtensa_idtlb_op 61
5536#define xtensa_idtlba_op 62
5537#define xtensa_ihi_op 63
5538#define xtensa_iii_op 64
5539#define xtensa_iitlb_op 65
5540#define xtensa_iitlba_op 66
5541#define xtensa_ipf_op 67
5542#define xtensa_isync_op 68
5543#define xtensa_j_op 69
5544#define xtensa_jx_op 70
5545#define xtensa_l16si_op 71
5546#define xtensa_l16ui_op 72
5547#define xtensa_l32e_op 73
5548#define xtensa_l32i_op 74
5549#define xtensa_l32i_n_op 75
5550#define xtensa_l32r_op 76
5551#define xtensa_l8ui_op 77
5552#define xtensa_ldct_op 78
5553#define xtensa_lict_op 79
5554#define xtensa_licw_op 80
5555#define xtensa_loop_op 81
5556#define xtensa_loopgtz_op 82
5557#define xtensa_loopnez_op 83
5558#define xtensa_memw_op 84
5559#define xtensa_mov_n_op 85
5560#define xtensa_moveqz_op 86
5561#define xtensa_movgez_op 87
5562#define xtensa_movi_op 88
5563#define xtensa_movi_n_op 89
5564#define xtensa_movltz_op 90
5565#define xtensa_movnez_op 91
5566#define xtensa_movsp_op 92
5567#define xtensa_neg_op 93
5568#define xtensa_nop_n_op 94
5569#define xtensa_nsa_op 95
5570#define xtensa_nsau_op 96
5571#define xtensa_or_op 97
5572#define xtensa_pdtlb_op 98
5573#define xtensa_pitlb_op 99
5574#define xtensa_rdtlb0_op 100
5575#define xtensa_rdtlb1_op 101
5576#define xtensa_ret_op 102
5577#define xtensa_ret_n_op 103
5578#define xtensa_retw_op 104
5579#define xtensa_retw_n_op 105
5580#define xtensa_rfde_op 106
5581#define xtensa_rfe_op 107
5582#define xtensa_rfi_op 108
5583#define xtensa_rfwo_op 109
5584#define xtensa_rfwu_op 110
5585#define xtensa_ritlb0_op 111
5586#define xtensa_ritlb1_op 112
5587#define xtensa_rotw_op 113
5588#define xtensa_rsil_op 114
5589#define xtensa_rsr_op 115
5590#define xtensa_rsync_op 116
5591#define xtensa_s16i_op 117
5592#define xtensa_s32e_op 118
5593#define xtensa_s32i_op 119
5594#define xtensa_s32i_n_op 120
5595#define xtensa_s8i_op 121
5596#define xtensa_sdct_op 122
5597#define xtensa_sict_op 123
5598#define xtensa_sicw_op 124
5599#define xtensa_simcall_op 125
5600#define xtensa_sll_op 126
5601#define xtensa_slli_op 127
5602#define xtensa_sra_op 128
5603#define xtensa_srai_op 129
5604#define xtensa_src_op 130
5605#define xtensa_srl_op 131
5606#define xtensa_srli_op 132
5607#define xtensa_ssa8b_op 133
5608#define xtensa_ssa8l_op 134
5609#define xtensa_ssai_op 135
5610#define xtensa_ssl_op 136
5611#define xtensa_ssr_op 137
5612#define xtensa_sub_op 138
5613#define xtensa_subx2_op 139
5614#define xtensa_subx4_op 140
5615#define xtensa_subx8_op 141
5616#define xtensa_syscall_op 142
5617#define xtensa_waiti_op 143
5618#define xtensa_wdtlb_op 144
5619#define xtensa_witlb_op 145
5620#define xtensa_wsr_op 146
5621#define xtensa_xor_op 147
5622#define xtensa_xsr_op 148
5623
5624int
5625decode_insn (const xtensa_insnbuf insn)
5626{
5627 switch (get_op0_field (insn)) {
5628 case 0: /* QRST: op0=0000 */
5629 switch (get_op1_field (insn)) {
5630 case 3: /* RST3: op1=0011 */
5631 switch (get_op2_field (insn)) {
5632 case 8: /* MOVEQZ: op2=1000 */
5633 return xtensa_moveqz_op;
5634 case 9: /* MOVNEZ: op2=1001 */
5635 return xtensa_movnez_op;
5636 case 10: /* MOVLTZ: op2=1010 */
5637 return xtensa_movltz_op;
5638 case 11: /* MOVGEZ: op2=1011 */
5639 return xtensa_movgez_op;
5640 case 0: /* RSR: op2=0000 */
5641 return xtensa_rsr_op;
5642 case 1: /* WSR: op2=0001 */
5643 return xtensa_wsr_op;
5644 }
5645 break;
5646 case 9: /* LSI4: op1=1001 */
5647 switch (get_op2_field (insn)) {
5648 case 4: /* S32E: op2=0100 */
5649 return xtensa_s32e_op;
5650 case 0: /* L32E: op2=0000 */
5651 return xtensa_l32e_op;
5652 }
5653 break;
5654 case 4: /* EXTUI: op1=010x */
5655 case 5: /* EXTUI: op1=010x */
5656 return xtensa_extui_op;
5657 case 0: /* RST0: op1=0000 */
5658 switch (get_op2_field (insn)) {
5659 case 15: /* SUBX8: op2=1111 */
5660 return xtensa_subx8_op;
5661 case 0: /* ST0: op2=0000 */
5662 switch (get_r_field (insn)) {
5663 case 0: /* SNM0: r=0000 */
5664 switch (get_m_field (insn)) {
5665 case 2: /* JR: m=10 */
5666 switch (get_n_field (insn)) {
5667 case 0: /* RET: n=00 */
5668 return xtensa_ret_op;
5669 case 1: /* RETW: n=01 */
5670 return xtensa_retw_op;
5671 case 2: /* JX: n=10 */
5672 return xtensa_jx_op;
5673 }
5674 break;
5675 case 3: /* CALLX: m=11 */
5676 switch (get_n_field (insn)) {
5677 case 0: /* CALLX0: n=00 */
5678 return xtensa_callx0_op;
5679 case 1: /* CALLX4: n=01 */
5680 return xtensa_callx4_op;
5681 case 2: /* CALLX8: n=10 */
5682 return xtensa_callx8_op;
5683 case 3: /* CALLX12: n=11 */
5684 return xtensa_callx12_op;
5685 }
5686 break;
5687 }
5688 break;
5689 case 1: /* MOVSP: r=0001 */
5690 return xtensa_movsp_op;
5691 case 2: /* SYNC: r=0010 */
5692 switch (get_s_field (insn)) {
5693 case 0: /* SYNCT: s=0000 */
5694 switch (get_t_field (insn)) {
5695 case 2: /* ESYNC: t=0010 */
5696 return xtensa_esync_op;
5697 case 3: /* DSYNC: t=0011 */
5698 return xtensa_dsync_op;
5699 case 8: /* EXCW: t=1000 */
5700 return xtensa_excw_op;
5701 case 12: /* MEMW: t=1100 */
5702 return xtensa_memw_op;
5703 case 0: /* ISYNC: t=0000 */
5704 return xtensa_isync_op;
5705 case 1: /* RSYNC: t=0001 */
5706 return xtensa_rsync_op;
5707 }
5708 break;
5709 }
5710 break;
5711 case 4: /* BREAK: r=0100 */
5712 return xtensa_break_op;
5713 case 3: /* RFEI: r=0011 */
5714 switch (get_t_field (insn)) {
5715 case 0: /* RFET: t=0000 */
5716 switch (get_s_field (insn)) {
5717 case 2: /* RFDE: s=0010 */
5718 return xtensa_rfde_op;
5719 case 4: /* RFWO: s=0100 */
5720 return xtensa_rfwo_op;
5721 case 5: /* RFWU: s=0101 */
5722 return xtensa_rfwu_op;
5723 case 0: /* RFE: s=0000 */
5724 return xtensa_rfe_op;
5725 }
5726 break;
5727 case 1: /* RFI: t=0001 */
5728 return xtensa_rfi_op;
5729 }
5730 break;
5731 case 5: /* SCALL: r=0101 */
5732 switch (get_s_field (insn)) {
5733 case 0: /* SYSCALL: s=0000 */
5734 return xtensa_syscall_op;
5735 case 1: /* SIMCALL: s=0001 */
5736 return xtensa_simcall_op;
5737 }
5738 break;
5739 case 6: /* RSIL: r=0110 */
5740 return xtensa_rsil_op;
5741 case 7: /* WAITI: r=0111 */
5742 return xtensa_waiti_op;
5743 }
5744 break;
5745 case 1: /* AND: op2=0001 */
5746 return xtensa_and_op;
5747 case 2: /* OR: op2=0010 */
5748 return xtensa_or_op;
5749 case 3: /* XOR: op2=0011 */
5750 return xtensa_xor_op;
5751 case 4: /* ST1: op2=0100 */
5752 switch (get_r_field (insn)) {
5753 case 15: /* NSAU: r=1111 */
5754 return xtensa_nsau_op;
5755 case 0: /* SSR: r=0000 */
5756 return xtensa_ssr_op;
5757 case 1: /* SSL: r=0001 */
5758 return xtensa_ssl_op;
5759 case 2: /* SSA8L: r=0010 */
5760 return xtensa_ssa8l_op;
5761 case 3: /* SSA8B: r=0011 */
5762 return xtensa_ssa8b_op;
5763 case 4: /* SSAI: r=0100 */
5764 return xtensa_ssai_op;
5765 case 8: /* ROTW: r=1000 */
5766 return xtensa_rotw_op;
5767 case 14: /* NSA: r=1110 */
5768 return xtensa_nsa_op;
5769 }
5770 break;
5771 case 8: /* ADD: op2=1000 */
5772 return xtensa_add_op;
5773 case 5: /* ST4: op2=0101 */
5774 switch (get_r_field (insn)) {
5775 case 15: /* RDTLB1: r=1111 */
5776 return xtensa_rdtlb1_op;
5777 case 0: /* IITLBA: r=0000 */
5778 return xtensa_iitlba_op;
5779 case 3: /* RITLB0: r=0011 */
5780 return xtensa_ritlb0_op;
5781 case 4: /* IITLB: r=0100 */
5782 return xtensa_iitlb_op;
5783 case 8: /* IDTLBA: r=1000 */
5784 return xtensa_idtlba_op;
5785 case 5: /* PITLB: r=0101 */
5786 return xtensa_pitlb_op;
5787 case 6: /* WITLB: r=0110 */
5788 return xtensa_witlb_op;
5789 case 7: /* RITLB1: r=0111 */
5790 return xtensa_ritlb1_op;
5791 case 11: /* RDTLB0: r=1011 */
5792 return xtensa_rdtlb0_op;
5793 case 12: /* IDTLB: r=1100 */
5794 return xtensa_idtlb_op;
5795 case 13: /* PDTLB: r=1101 */
5796 return xtensa_pdtlb_op;
5797 case 14: /* WDTLB: r=1110 */
5798 return xtensa_wdtlb_op;
5799 }
5800 break;
5801 case 6: /* RT0: op2=0110 */
5802 switch (get_s_field (insn)) {
5803 case 0: /* NEG: s=0000 */
5804 return xtensa_neg_op;
5805 case 1: /* ABS: s=0001 */
5806 return xtensa_abs_op;
5807 }
5808 break;
5809 case 9: /* ADDX2: op2=1001 */
5810 return xtensa_addx2_op;
5811 case 10: /* ADDX4: op2=1010 */
5812 return xtensa_addx4_op;
5813 case 11: /* ADDX8: op2=1011 */
5814 return xtensa_addx8_op;
5815 case 12: /* SUB: op2=1100 */
5816 return xtensa_sub_op;
5817 case 13: /* SUBX2: op2=1101 */
5818 return xtensa_subx2_op;
5819 case 14: /* SUBX4: op2=1110 */
5820 return xtensa_subx4_op;
5821 }
5822 break;
5823 case 1: /* RST1: op1=0001 */
5824 switch (get_op2_field (insn)) {
5825 case 15: /* IMP: op2=1111 */
5826 switch (get_r_field (insn)) {
5827 case 0: /* LICT: r=0000 */
5828 return xtensa_lict_op;
5829 case 1: /* SICT: r=0001 */
5830 return xtensa_sict_op;
5831 case 2: /* LICW: r=0010 */
5832 return xtensa_licw_op;
5833 case 3: /* SICW: r=0011 */
5834 return xtensa_sicw_op;
5835 case 8: /* LDCT: r=1000 */
5836 return xtensa_ldct_op;
5837 case 9: /* SDCT: r=1001 */
5838 return xtensa_sdct_op;
5839 }
5840 break;
5841 case 0: /* SLLI: op2=000x */
5842 case 1: /* SLLI: op2=000x */
5843 return xtensa_slli_op;
5844 case 2: /* SRAI: op2=001x */
5845 case 3: /* SRAI: op2=001x */
5846 return xtensa_srai_op;
5847 case 4: /* SRLI: op2=0100 */
5848 return xtensa_srli_op;
5849 case 8: /* SRC: op2=1000 */
5850 return xtensa_src_op;
5851 case 9: /* SRL: op2=1001 */
5852 return xtensa_srl_op;
5853 case 6: /* XSR: op2=0110 */
5854 return xtensa_xsr_op;
5855 case 10: /* SLL: op2=1010 */
5856 return xtensa_sll_op;
5857 case 11: /* SRA: op2=1011 */
5858 return xtensa_sra_op;
5859 }
5860 break;
5861 }
5862 break;
5863 case 1: /* L32R: op0=0001 */
5864 return xtensa_l32r_op;
5865 case 2: /* LSAI: op0=0010 */
5866 switch (get_r_field (insn)) {
5867 case 0: /* L8UI: r=0000 */
5868 return xtensa_l8ui_op;
5869 case 1: /* L16UI: r=0001 */
5870 return xtensa_l16ui_op;
5871 case 2: /* L32I: r=0010 */
5872 return xtensa_l32i_op;
5873 case 4: /* S8I: r=0100 */
5874 return xtensa_s8i_op;
5875 case 5: /* S16I: r=0101 */
5876 return xtensa_s16i_op;
5877 case 9: /* L16SI: r=1001 */
5878 return xtensa_l16si_op;
5879 case 6: /* S32I: r=0110 */
5880 return xtensa_s32i_op;
5881 case 7: /* CACHE: r=0111 */
5882 switch (get_t_field (insn)) {
5883 case 15: /* III: t=1111 */
5884 return xtensa_iii_op;
5885 case 0: /* DPFR: t=0000 */
5886 return xtensa_dpfr_op;
5887 case 1: /* DPFW: t=0001 */
5888 return xtensa_dpfw_op;
5889 case 2: /* DPFRO: t=0010 */
5890 return xtensa_dpfro_op;
5891 case 4: /* DHWB: t=0100 */
5892 return xtensa_dhwb_op;
5893 case 3: /* DPFWO: t=0011 */
5894 return xtensa_dpfwo_op;
5895 case 8: /* DCE: t=1000 */
5896 switch (get_op1_field (insn)) {
5897 case 4: /* DIWB: op1=0100 */
5898 return xtensa_diwb_op;
5899 case 5: /* DIWBI: op1=0101 */
5900 return xtensa_diwbi_op;
5901 }
5902 break;
5903 case 5: /* DHWBI: t=0101 */
5904 return xtensa_dhwbi_op;
5905 case 6: /* DHI: t=0110 */
5906 return xtensa_dhi_op;
5907 case 7: /* DII: t=0111 */
5908 return xtensa_dii_op;
5909 case 12: /* IPF: t=1100 */
5910 return xtensa_ipf_op;
5911 case 14: /* IHI: t=1110 */
5912 return xtensa_ihi_op;
5913 }
5914 break;
5915 case 10: /* MOVI: r=1010 */
5916 return xtensa_movi_op;
5917 case 12: /* ADDI: r=1100 */
5918 return xtensa_addi_op;
5919 case 13: /* ADDMI: r=1101 */
5920 return xtensa_addmi_op;
5921 }
5922 break;
5923 case 8: /* L32I.N: op0=1000 */
5924 return xtensa_l32i_n_op;
5925 case 5: /* CALL: op0=0101 */
5926 switch (get_n_field (insn)) {
5927 case 0: /* CALL0: n=00 */
5928 return xtensa_call0_op;
5929 case 1: /* CALL4: n=01 */
5930 return xtensa_call4_op;
5931 case 2: /* CALL8: n=10 */
5932 return xtensa_call8_op;
5933 case 3: /* CALL12: n=11 */
5934 return xtensa_call12_op;
5935 }
5936 break;
5937 case 6: /* SI: op0=0110 */
5938 switch (get_n_field (insn)) {
5939 case 0: /* J: n=00 */
5940 return xtensa_j_op;
5941 case 1: /* BZ: n=01 */
5942 switch (get_m_field (insn)) {
5943 case 0: /* BEQZ: m=00 */
5944 return xtensa_beqz_op;
5945 case 1: /* BNEZ: m=01 */
5946 return xtensa_bnez_op;
5947 case 2: /* BLTZ: m=10 */
5948 return xtensa_bltz_op;
5949 case 3: /* BGEZ: m=11 */
5950 return xtensa_bgez_op;
5951 }
5952 break;
5953 case 2: /* BI0: n=10 */
5954 switch (get_m_field (insn)) {
5955 case 0: /* BEQI: m=00 */
5956 return xtensa_beqi_op;
5957 case 1: /* BNEI: m=01 */
5958 return xtensa_bnei_op;
5959 case 2: /* BLTI: m=10 */
5960 return xtensa_blti_op;
5961 case 3: /* BGEI: m=11 */
5962 return xtensa_bgei_op;
5963 }
5964 break;
5965 case 3: /* BI1: n=11 */
5966 switch (get_m_field (insn)) {
5967 case 0: /* ENTRY: m=00 */
5968 return xtensa_entry_op;
5969 case 1: /* B1: m=01 */
5970 switch (get_r_field (insn)) {
5971 case 8: /* LOOP: r=1000 */
5972 return xtensa_loop_op;
5973 case 9: /* LOOPNEZ: r=1001 */
5974 return xtensa_loopnez_op;
5975 case 10: /* LOOPGTZ: r=1010 */
5976 return xtensa_loopgtz_op;
5977 }
5978 break;
5979 case 2: /* BLTUI: m=10 */
5980 return xtensa_bltui_op;
5981 case 3: /* BGEUI: m=11 */
5982 return xtensa_bgeui_op;
5983 }
5984 break;
5985 }
5986 break;
5987 case 9: /* S32I.N: op0=1001 */
5988 return xtensa_s32i_n_op;
5989 case 10: /* ADD.N: op0=1010 */
5990 return xtensa_add_n_op;
5991 case 7: /* B: op0=0111 */
5992 switch (get_r_field (insn)) {
5993 case 6: /* BBCI: r=011x */
5994 case 7: /* BBCI: r=011x */
5995 return xtensa_bbci_op;
5996 case 0: /* BNONE: r=0000 */
5997 return xtensa_bnone_op;
5998 case 1: /* BEQ: r=0001 */
5999 return xtensa_beq_op;
6000 case 2: /* BLT: r=0010 */
6001 return xtensa_blt_op;
6002 case 4: /* BALL: r=0100 */
6003 return xtensa_ball_op;
6004 case 14: /* BBSI: r=111x */
6005 case 15: /* BBSI: r=111x */
6006 return xtensa_bbsi_op;
6007 case 3: /* BLTU: r=0011 */
6008 return xtensa_bltu_op;
6009 case 5: /* BBC: r=0101 */
6010 return xtensa_bbc_op;
6011 case 8: /* BANY: r=1000 */
6012 return xtensa_bany_op;
6013 case 9: /* BNE: r=1001 */
6014 return xtensa_bne_op;
6015 case 10: /* BGE: r=1010 */
6016 return xtensa_bge_op;
6017 case 11: /* BGEU: r=1011 */
6018 return xtensa_bgeu_op;
6019 case 12: /* BNALL: r=1100 */
6020 return xtensa_bnall_op;
6021 case 13: /* BBS: r=1101 */
6022 return xtensa_bbs_op;
6023 }
6024 break;
6025 case 11: /* ADDI.N: op0=1011 */
6026 return xtensa_addi_n_op;
6027 case 12: /* ST2: op0=1100 */
6028 switch (get_i_field (insn)) {
6029 case 0: /* MOVI.N: i=0 */
6030 return xtensa_movi_n_op;
6031 case 1: /* BZ6: i=1 */
6032 switch (get_z_field (insn)) {
6033 case 0: /* BEQZ.N: z=0 */
6034 return xtensa_beqz_n_op;
6035 case 1: /* BNEZ.N: z=1 */
6036 return xtensa_bnez_n_op;
6037 }
6038 break;
6039 }
6040 break;
6041 case 13: /* ST3: op0=1101 */
6042 switch (get_r_field (insn)) {
6043 case 15: /* S3: r=1111 */
6044 switch (get_t_field (insn)) {
6045 case 0: /* RET.N: t=0000 */
6046 return xtensa_ret_n_op;
6047 case 1: /* RETW.N: t=0001 */
6048 return xtensa_retw_n_op;
6049 case 2: /* BREAK.N: t=0010 */
6050 return xtensa_break_n_op;
6051 case 3: /* NOP.N: t=0011 */
6052 return xtensa_nop_n_op;
6053 }
6054 break;
6055 case 0: /* MOV.N: r=0000 */
6056 return xtensa_mov_n_op;
6057 }
6058 break;
6059 }
6060 return XTENSA_UNDEFINED;
6061}
6062
6063int
6064interface_version (void)
6065{
6066 return 3;
6067}
6068
6069static struct config_struct config_table[] = {
6070 {"IsaMemoryOrder", "BigEndian"},
6071 {"PIFReadDataBits", "128"},
6072 {"PIFWriteDataBits", "128"},
6073 {"IsaCoprocessorCount", "0"},
6074 {"IsaUseBooleans", "0"},
6075 {"IsaUseDensityInstruction", "1"},
6076 {0, 0}
6077};
6078
6079struct config_struct * get_config_table (void);
6080
6081struct config_struct *
6082get_config_table (void)
6083{
6084 return config_table;
6085}
6086
6087xtensa_isa_module xtensa_isa_modules[] = {
6088 { get_num_opcodes, get_opcodes, decode_insn, get_config_table },
6089 { 0, 0, 0, 0 }
6090};
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