[binutils.git] / opcodes / mn10300-opc.c

/* Assemble Matsushita MN10300 instructions.
   Copyright (C) 1996 Free Software Foundation, Inc.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#include "ansidecl.h"
#include "opcode/mn10300.h"

\f
const struct mn10300_operand mn10300_operands[] = {
#define UNUSED	0
  {0, 0, 0}, 

#define DN0      (UNUSED+1)
  {2, 0, MN10300_OPERAND_DREG},

#define DN1      (DN0+1)
  {2, 2, MN10300_OPERAND_DREG},

#define DM0      (DN1+1)
  {2, 0, MN10300_OPERAND_DREG},

#define DM1      (DM0+1)
  {2, 2, MN10300_OPERAND_DREG},

#define AN0      (DM1+1)
  {2, 0, MN10300_OPERAND_AREG},

#define AN1      (AN0+1)
  {2, 2, MN10300_OPERAND_AREG},

#define AM0      (AN1+1)
  {2, 0, MN10300_OPERAND_AREG},

#define AM1      (AM0+1)
  {2, 2, MN10300_OPERAND_AREG},

#define IMM8    (AM1+1)
  {8, 0, MN10300_OPERAND_PROMOTE},

#define IMM16    (IMM8+1)
  {16, 0, MN10300_OPERAND_PROMOTE},

#define IMM32    (IMM16+1)
  {32, 0, 0},

#define D8    (IMM32+1)
  {8, 0, MN10300_OPERAND_PROMOTE},

#define D16    (D8+1)
  {16, 0, MN10300_OPERAND_PROMOTE},

#define D32    (D16+1)
  {32, 0, 0},

#define SP    (D32+1)
  {8, 0, MN10300_OPERAND_SP},

#define PSW    (SP+1)
  {0, 0, MN10300_OPERAND_PSW},

#define MDR    (PSW+1)
  {0, 0, MN10300_OPERAND_MDR},

#define ABS16 (MDR+1)
  {16, 0, MN10300_OPERAND_PROMOTE},

#define ABS32 (ABS16+1)
  {32, 0, 0},

#define DI (ABS32+1)
  {2, 0, MN10300_OPERAND_DREG},

#define SD8    (DI+1)
  {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define SD16    (SD8+1)
  {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define SD8N    (SD16+1)
  {8, 0, MN10300_OPERAND_SIGNED},

#define SIMM8    (SD8N+1)
  {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define SIMM16    (SIMM8+1)
  {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define PAREN	(SIMM16+1)
  {0, 0, MN10300_OPERAND_PAREN}, 
} ; 

#define MEM(ADDR) PAREN, ADDR, PAREN 
#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN 
\f
/* The opcode table.

   The format of the opcode table is:

   NAME		OPCODE		MASK		{ OPERANDS }

   NAME is the name of the instruction.
   OPCODE is the instruction opcode.
   MASK is the opcode mask; this is used to tell the disassembler
     which bits in the actual opcode must match OPCODE.
   OPERANDS is the list of operands.

   The disassembler reads the table in order and prints the first
   instruction which matches, so this table is sorted to put more
   specific instructions before more general instructions.  It is also
   sorted by major opcode.  */

const struct mn10300_opcode mn10300_opcodes[] = {
{ "mov",	0x8000,		0xf000,		FMT_S1, {SIMM8, DN0}},
{ "mov",	0x80,		0xf0,		FMT_S0, {DM1, DN0}},
{ "mov",	0xf1e0,		0xfff0,		FMT_D0, {DM1, AN0}},
{ "mov",	0xf1d0,		0xfff0,		FMT_D0, {AM1, DN0}},
{ "mov",	0x9000,		0xf000,		FMT_S1, {IMM8, AN0}},
{ "mov",	0x90,		0xf0,		FMT_S0, {AM1, AN0}},
{ "mov",	0x3c,		0xfc,		FMT_S0, {SP, AN0}},
{ "mov",	0xf2f0,		0xfff3,		FMT_D0, {AM1, SP}},
{ "mov",	0xf2e4,		0xfffc,		FMT_D0, {PSW, DN0}},
{ "mov",	0xf2f3,		0xfff3,		FMT_D0, {DM1, PSW}},
{ "mov",	0xf2e0,		0xfffc,		FMT_D0, {MDR, DN0}},
{ "mov",	0xf2f2,		0xfff3,		FMT_D0, {DM1, MDR}},
{ "mov",	0x70,		0xf0,		FMT_S0, {MEM(AM0), DN1}},
{ "mov",	0xf80000,	0xfff000,	FMT_D1, {MEM2(SD8, AM0), DN1}},
{ "mov",	0xfa000000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), DN1}},
{ "mov",	0xfc000000,	0xfff00000,	FMT_D4, {MEM2(D32, AM0), DN1}},
{ "mov",	0x5800,		0xfc00,		FMT_S1, {MEM2(D8, SP), DN0}},
{ "mov",	0xfab40000,	0xfffc0000,	FMT_D2, {MEM2(D16, SP), DN0}},
{ "mov",	0xfcb40000,	0xfffc0000,	FMT_D4, {MEM2(D32, SP), DN0}},
{ "mov",	0xf300,		0xffc0,		FMT_D0, {MEM2(DI, AM0), DN0}},
{ "mov",	0x300000,	0xfc0000,	FMT_S2, {MEM(ABS16), DN0}},
{ "mov",	0xfca40000,	0xfffc0000,	FMT_D4, {MEM(ABS32), DN0}},
{ "mov",	0xf000,		0xfff0,		FMT_D0, {MEM(AM0), AN1}},
{ "mov",	0xf82000,	0xfff000,	FMT_D1, {MEM2(D8, AM0), AN1}},
{ "mov",	0xfa200000,	0xfff00000,	FMT_D2, {MEM2(D16, AM0), AN1}},
{ "mov",	0xfc200000,	0xfff00000,	FMT_D4, {MEM2(D32, AM0), AN1}},
{ "mov",	0x5c00,		0xfc00,		FMT_S1, {MEM2(D8, SP), AN0}},
{ "mov",	0xfab00000,	0xfffc0000,	FMT_D2, {MEM2(D16, SP), AN0}},
{ "mov",	0xfcb00000,	0xfffc0000,	FMT_D4, {MEM2(D32, SP), AN0}},
{ "mov",	0xf380,		0xffc0,		FMT_D0, {MEM2(DI, AM0), AN0}},
{ "mov",	0xfaa00000,	0xfffc0000,	FMT_D2, {MEM(ABS16), AN0}},
{ "mov",	0xfca00000,	0xfffc0000,	FMT_D4, {MEM(ABS32), AN0}},
{ "mov",	0xf8f000,	0xfffc00,	FMT_D1, {MEM2(SD8N, AM0), SP}},
{ "mov",	0x60,		0xf0,		FMT_S0, {DM1, MEM(AN0)}},
{ "mov",	0xf81000,	0xfff000,	FMT_D1, {DM1, MEM2(SD8, AN0)}},
{ "mov",	0xfa100000,	0xfff00000,	FMT_D2, {DM1, MEM2(SD16, AN0)}},
{ "mov",	0xfc100000,	0xfff00000,	FMT_D4, {DM1, MEM2(D32, AN0)}},
{ "mov",	0x4200,		0xf300,		FMT_S1, {DM1, MEM2(D8, SP)}},
{ "mov",	0xfa910000,	0xfff30000,	FMT_D2, {DM1, MEM2(D16, SP)}},
{ "mov",	0xfc910000,	0xfff30000,	FMT_D4, {DM1, MEM2(D32, SP)}},
{ "mov",	0xf340,		0xffc0,		FMT_D0, {DM0, MEM2(DI, AN0)}},
{ "mov",	0x010000,	0xf30000,	FMT_S2, {DM1, MEM(ABS16)}},
{ "mov",	0xfc810000,	0xfff30000,	FMT_D4, {DM1, MEM(ABS32)}},
{ "mov",	0xf010,		0xfff0,		FMT_D0, {AM1, MEM(AN0)}},
{ "mov",	0xf83000,	0xfff000,	FMT_D1, {AM1, MEM2(SD8, AN0)}},
{ "mov",	0xfa300000,	0xfff00000,	FMT_D2, {AM1, MEM2(SD16, AN0)}},
{ "mov",	0xfc300000,	0xfff00000,	FMT_D4, {AM1, MEM2(D32, AN0)}},
{ "mov",	0x4300,		0xf300,		FMT_S1, {AM1, MEM2(D8, SP)}},
{ "mov",	0xfa900000,	0xfff30000,	FMT_D2, {AM1, MEM2(D16, SP)}},
{ "mov",	0xfc900000,	0xfc930000,	FMT_D4, {AM1, MEM2(D32, SP)}},
{ "mov",	0xf3c0,		0xffc0,		FMT_D0, {AM0, MEM2(DI, AN0)}},
{ "mov",	0xfa800000,	0xfff30000,	FMT_D2, {AM1, MEM(ABS16)}},
{ "mov",	0xfc800000,	0xfff30000,	FMT_D4, {AM1, MEM(ABS32)}},
{ "mov",	0xf8f400,	0xfffc00,	FMT_D1, {SP, MEM2(SD8N, AN0)}},
{ "mov",	0x2c0000,	0xfc0000,	FMT_S2, {SIMM16, DN0}},
{ "mov",	0xfcdc0000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "mov",	0x240000,	0xfc0000,	FMT_S2, {IMM16, AN0}},
{ "mov",	0xfcdc0000,	0xfffc0000,	FMT_D4, {IMM32, AN0}},

{ "movbu",	0xf040,		0xfff0,		FMT_D0, {MEM(AM0), DN1}},
{ "movbu",	0xf84000,	0xfff000,	FMT_D1, {MEM2(SD8, AM0), DN1}},
{ "movbu",	0xfa400000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), DN1}},
{ "movbu",	0xfc400000,	0xfff00000,	FMT_D4, {MEM2(D32, AM0), DN1}},
{ "movbu",	0xf8b800,	0xfffc00,	FMT_D1, {MEM2(D8, SP), DN0}},
{ "movbu",	0xfab80000,	0xfffc0000,	FMT_D2, {MEM2(D16, SP), DN0}},
{ "movbu",	0xfcb80000,	0xfffc0000,	FMT_D4, {MEM2(D32, SP), DN0}},
{ "movbu",	0xf400,		0xffc0,		FMT_D0, {MEM2(DI, AM0), DN0}},
{ "movbu",	0x340000,	0xfc0000,	FMT_S2, {MEM(ABS16), DN0}},
{ "movbu",	0xfca80000,	0xfffc0000,	FMT_D4, {MEM(ABS32), DN0}},
{ "movbu",	0xf050,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
{ "movbu",	0xf85000,	0xfff000,	FMT_D1, {DM1, MEM2(SD8, AN0)}},
{ "movbu",	0xfa500000,	0xfff00000,	FMT_D2, {DM1, MEM2(SD16, AN0)}},
{ "movbu",	0xfc500000,	0xfff00000,	FMT_D4, {DM1, MEM2(D32, AN0)}},
{ "movbu",	0xf89200,	0xfff300,	FMT_D1, {DM1, MEM2(D8, SP)}},
{ "movbu",	0xfa920000,	0xfff30000,	FMT_D2, {DM1, MEM2(D16, SP)}},
{ "movbu",	0xfc920000,	0xfff30000,	FMT_D4, {DM1, MEM2(D32, SP)}},
{ "movbu",	0xf440,		0xffc0,		FMT_D0, {DM0, MEM2(DI, AN0)}},
{ "movbu",	0x020000,	0xf30000,	FMT_S2, {DM1, MEM(ABS16)}},
{ "movbu",	0xfc820000,	0xfff30000,	FMT_D4, {DM1, MEM(ABS32)}},

{ "movhu",	0xf060,		0xfff0,		FMT_D0, {MEM(AM0), DN1}},
{ "movhu",	0xf86000,	0xfff000,	FMT_D1, {MEM2(SD8, AM0), DN1}},
{ "movhu",	0xfa600000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), DN1}},
{ "movhu",	0xfc600000,	0xfff00000,	FMT_D4, {MEM2(D32, AM0), DN1}},
{ "movhu",	0xf8bc00,	0xfffc00,	FMT_D1, {MEM2(D8, SP), DN0}},
{ "movhu",	0xfabc0000,	0xfffc0000,	FMT_D2, {MEM2(D16, SP), DN0}},
{ "movhu",	0xfcbc0000,	0xfffc0000,	FMT_D4, {MEM2(D32, SP), DN0}},
{ "movhu",	0xf480,		0xffc0,		FMT_D0, {MEM2(DI, AM0), DN0}},
{ "movhu",	0xc80000,	0xfc0000,	FMT_S2, {MEM(ABS16), DN0}},
{ "movhu",	0xfcac0000,	0xfffc0000,	FMT_D4, {MEM(ABS32), DN0}},
{ "movhu",	0xf070,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
{ "movhu",	0xf87000,	0xfff000,	FMT_D1, {DM1, MEM2(SD8, AN0)}},
{ "movhu",	0xfa700000,	0xfff00000,	FMT_D2, {DM1, MEM2(SD16, AN0)}},
{ "movhu",	0xfc700000,	0xfff00000,	FMT_D4, {DM1, MEM2(D32, AN0)}},
{ "movhu",	0xf89300,	0xfff300,	FMT_D1, {DM1, MEM2(D8, SP)}},
{ "movhu",	0xfa930000,	0xfff30000,	FMT_D2, {DM1, MEM2(D16, SP)}},
{ "movhu",	0xfc930000,	0xfff30000,	FMT_D4, {DM1, MEM2(D32, SP)}},
{ "movhu",	0xf4c0,		0xffc0,		FMT_D0, {DM0, MEM2(DI, AN0)}},
{ "movhu",	0x030000,	0xf30000,	FMT_S2, {DM1, MEM(ABS16)}},
{ "movhu",	0xfc830000,	0xfff30000,	FMT_D4, {DM1, MEM(ABS32)}},

{ "ext",	0xf2d0,		0xfffc,		FMT_D0, {DN0}},
{ "extb",	0x10, 		0xfc,		FMT_S0, {DN0}},
{ "extbu",	0x14,		0xfc,		FMT_S0, {DN0}},
{ "exth",	0x18,		0xfc,		FMT_S0, {DN0}},
{ "exthu",	0x1c,		0xfc,		FMT_S0, {DN0}},

{ "movm",	0xce00,		0xff00,		FMT_S1, {MEM(SP), IMM8}},
{ "movm",	0xcf00,		0xff00,		FMT_S1, {IMM8, MEM(SP)}},

{ "clr",	0x00,		0xf3,		FMT_S0, {DN1}},

{ "add",	0xe0,		0xf0,		FMT_S0, {DM1, DN0}},
{ "add",	0xf160,		0xfff0,		FMT_D0, {DM1, AN0}},
{ "add",	0xf150,		0xfff0,		FMT_D0, {AM1, DN0}},
{ "add",	0xf170,		0xfff0,		FMT_D0, {AM1, AN0}},
{ "add",	0x2800,		0xfc00,		FMT_S1, {SIMM8, DN0}},
{ "add",	0xfac00000,	0xfffc0000,	FMT_D2, {SIMM16, DN0}},
{ "add",	0xfcc00000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "add",	0x2000,		0xfc00,		FMT_S1, {SIMM8, AN0}},
{ "add",	0xfad00000,	0xfffc0000,	FMT_D2, {SIMM16, AN0}},
{ "add",	0xfcd00000,	0xfffc0000,	FMT_D4, {IMM32, AN0}},
{ "add",	0xf8fe00,	0xffff00,	FMT_D1, {SIMM8, SP}},
{ "add",	0xfafe0000,	0xfffc0000,	FMT_D2, {SIMM16, SP}},
{ "add",	0xfcfe0000,	0xfff0000,	FMT_D4, {IMM32, SP}},
{ "addc",	0xf140,		0xfff0,		FMT_D0, {DM1, DN0}},

{ "sub",	0xf100,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "sub",	0xf120,		0xfff0,		FMT_D0, {DM1, AN0}},
{ "sub",	0xf110,		0xfff0,		FMT_D0, {AM1, DN0}},
{ "sub",	0xf130,		0xfff0,		FMT_D0, {AM1, AN0}},
{ "sub",	0xfcc40000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "sub",	0xfcd40000,	0xfffc0000,	FMT_D4, {IMM32, AN0}},
{ "subc",	0xf180,		0xfff0,		FMT_D0, {DM1, DN0}},

{ "mul",	0xf240,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "mulu",	0xf250,		0xfff0,		FMT_D0, {DM1, DN0}},

{ "div",	0xf260,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "divu",	0xf270,		0xfff0,		FMT_D0, {DM1, DN0}},

{ "inc",	0x40,		0xf3,		FMT_S0, {DN1}},
{ "inc",	0x41,		0xf3,		FMT_S0, {AN1}},
{ "inc4",	0x50,		0xfc,		FMT_S0, {AN0}},

{ "cmp",	0xa000,		0xf000,		FMT_S1, {SIMM8, DN0}},
{ "cmp",	0xa0,		0xf0,		FMT_S0, {DM1, DN0}},
{ "cmp",	0xf1a0,		0xfff0,		FMT_D0, {DM1, AN0}},
{ "cmp",	0xf190,		0xfff0,		FMT_D0, {AM1, DN0}},
{ "cmp",	0xb000,		0xf000,		FMT_S1, {IMM8, AN0}},
{ "cmp",	0xb0,		0xf0,		FMT_S0, {AM1, AN0}},
{ "cmp",	0xfac80000,	0xfffc0000,	FMT_D2, {SIMM16, DN0}},
{ "cmp",	0xfcc80000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "cmp",	0xfad80000,	0xfffc0000,	FMT_D2, {IMM16, AN0}},
{ "cmp",	0xfcd80000,	0xfffc0000,	FMT_D4, {IMM32, AN0}},

{ "and",	0xf200,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "and",	0xf8e000,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "and",	0xfae00000,	0xfffc0000,	FMT_D2, {IMM16, DN0}},
{ "and",	0xfce00000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "and",	0xfafc0000,	0xfffc0000,	FMT_D2, {IMM16, PSW}},
{ "or",		0xf210,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "or",		0xf8e400,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "or",		0xfae40000,	0xfffc0000,	FMT_D2, {IMM16, DN0}},
{ "or",		0xfce40000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "or",		0xfafd0000,	0xfffc0000,	FMT_D2, {IMM16, PSW}},
{ "xor",	0xf220,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "xor",	0xfae80000,	0xfffc0000,	FMT_D2, {IMM16, DN0}},
{ "xor",	0xfce80000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "not",	0xf230,		0xfffc,		FMT_D0, {DN0}},

{ "btst",	0xf8ec00,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "btst",	0xfaec0000,	0xfffc0000,	FMT_D2, {IMM16, DN0}},
{ "btst",	0xfcec0000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "btst",	0xfe020000,	0xffff0000,	FMT_D5, {IMM8, MEM(ABS32)}},
{ "btst",	0xfaf80000,	0xfffc0000,	FMT_D2, {IMM8, MEM2(SD8N,AN0)}},
{ "bset",	0xf080,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
{ "bset",	0xfe000000,	0xffff0000,	FMT_D5, {IMM8, MEM(ABS32)}},
{ "bset",	0xfaf00000,	0xfffc0000,	FMT_D2, {IMM8, MEM2(SD8N,AN0)}},
{ "bclr",	0xf090,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
{ "bclr",	0xfe010000,	0xffff0000,	FMT_D5, {IMM8, MEM(ABS32)}},
{ "bclr",	0xfaf40000,	0xfffc0000,	FMT_D2, {IMM8, MEM2(SD8N,AN0)}},

{ "asr",	0xf2b0,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "asr",	0xf8c800,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "lsr",	0xf2a0,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "lsr",	0xf8c400,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "asl",	0xf290,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "asl",	0xf8c000,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "asl2",	0x54,		0xfc,		FMT_S0, {DN0}},
{ "ror",	0xf284,		0xfffc,		FMT_D0, {DN0}},
{ "rol",	0xf280,		0xfffc,		FMT_D0, {DN0}},

{ "beq",	0xc800,		0xff00,		FMT_S1, {SD8N}},
{ "bne",	0xc900,		0xff00,		FMT_S1, {SD8N}},
{ "bgt",	0xc100,		0xff00,		FMT_S1, {SD8N}},
{ "bge",	0xc200,		0xff00,		FMT_S1, {SD8N}},
{ "ble",	0xc300,		0xff00,		FMT_S1, {SD8N}},
{ "blt",	0xc000,		0xff00,		FMT_S1, {SD8N}},
{ "bhi",	0xc500,		0xff00,		FMT_S1, {SD8N}},
{ "bcc",	0xc600,		0xff00,		FMT_S1, {SD8N}},
{ "bls",	0xc700,		0xff00,		FMT_S1, {SD8N}},
{ "bcs",	0xc400,		0xff00,		FMT_S1, {SD8N}},
{ "bvc",	0xf8e800,	0xffff00,	FMT_D1, {SD8N}},
{ "bvs",	0xf8e900,	0xffff00,	FMT_D1, {SD8N}},
{ "bnc",	0xf8ea00,	0xffff00,	FMT_D1, {SD8N}},
{ "bns",	0xf8eb00,	0xffff00,	FMT_D1, {SD8N}},
{ "bra",	0xca00,		0xff00,		FMT_S1, {SD8N}},

{ "leq",	0xd8,		0xff,		FMT_S0, {UNUSED}},
{ "lne",	0xd9,		0xff,		FMT_S0, {UNUSED}},
{ "lgt",	0xd1,		0xff,		FMT_S0, {UNUSED}},
{ "lge",	0xd2,		0xff,		FMT_S0, {UNUSED}},
{ "lle",	0xd3,		0xff,		FMT_S0, {UNUSED}},
{ "llt",	0xd0,		0xff,		FMT_S0, {UNUSED}},
{ "lhi",	0xd5,		0xff,		FMT_S0, {UNUSED}},
{ "lcc",	0xd6,		0xff,		FMT_S0, {UNUSED}},
{ "lls",	0xd7,		0xff,		FMT_S0, {UNUSED}},
{ "lcs",	0xd4,		0xff,		FMT_S0, {UNUSED}},
{ "lra",	0xda,		0xff,		FMT_S0, {UNUSED}},
{ "lcc",	0xd6,		0xff,		FMT_S0, {UNUSED}},
{ "setlb",	0xdb,		0xff,	 	FMT_S0, {UNUSED}},

{ "jmp",	0xf0f4,		0xfffc,		FMT_D0, {AN0}},
{ "jmp",	0xcc0000,	0xff0000,	FMT_S2, {D16}},
{ "jmp",	0xdc0000,	0xff0000,	FMT_S4, {D32}},
{ "call",	0xcd000000,	0xff000000,	FMT_S4, {D16,IMM8,IMM8}},
{ "call",	0xdd000000,	0xff000000,	FMT_S6, {D32,IMM8,IMM8}},
{ "calls",	0xf0f0,		0xfffc,		FMT_D0, {AN0}},
{ "calls",	0xfaff0000,	0xffff0000,	FMT_D2, {D16}},
{ "calls",	0xfcff0000,	0xffff0000,	FMT_D4, {D32}},

{ "ret",	0xdf0000,	0xff00000,	FMT_S2, {IMM8, IMM8}},
{ "retf",	0xde0000,	0xff00000,	FMT_S2, {IMM8, IMM8}},
{ "rets",	0xf0fc,		0xffff,		FMT_D0, {UNUSED}},
{ "rti",	0xf0fd,		0xffff,		FMT_D0, {UNUSED}},
{ "trap",	0xf0fe,		0xffff,		FMT_D0, {UNUSED}},
{ "rtm",	0xf0ff,		0xffff,		FMT_D0, {UNUSED}},
{ "nop",	0xcb,		0xff,		FMT_S0, {UNUSED}},
/* { "udf", 0, 0, {0}},  */

{ "putx",	0xf500,		0xfff0,		FMT_D0, {DM0}},
{ "getx",	0xf6f0,		0xfff0,		FMT_D0, {DN0}},
{ "mulq",	0xf600,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "mulq",	0xf90000,	0xfffc00,	FMT_D1, {SIMM8, DN0}},
{ "mulq",	0xfb000000,	0xfffc0000,	FMT_D2, {SIMM16, DN0}},
{ "mulq",	0xfd000000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "mulqu",	0xf610,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "mulqu",	0xf90400,	0xfffc00,	FMT_D1, {SIMM8, DN0}},
{ "mulqu",	0xfb040000,	0xfffc0000,	FMT_D2, {SIMM16, DN0}},
{ "mulqu",	0xfd040000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "sat16",	0xf640,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "sat24",	0xf650,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "bsch",	0xf670,		0xfff0,		FMT_D0, {DM1, DN0}},
{ 0, 0, 0, 0, {0}},

} ;

const int mn10300_num_opcodes =
  sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);

\f
Commit	Line	Data
ae1b99e4	1	/* Assemble Matsushita MN10300 instructions.
e7c50cef JL	2	Copyright (C) 1996 Free Software Foundation, Inc.
	3
	4	This program is free software; you can redistribute it and/or modify
	5	it under the terms of the GNU General Public License as published by
	6	the Free Software Foundation; either version 2 of the License, or
	7	(at your option) any later version.
	8
	9	This program is distributed in the hope that it will be useful,
	10	but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	GNU General Public License for more details.
	13
	14	You should have received a copy of the GNU General Public License
	15	along with this program; if not, write to the Free Software
	16	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	17
	18	#include "ansidecl.h"
ae1b99e4	19	#include "opcode/mn10300.h"
e7c50cef JL	20
e7c50cef JL	21	\f
ae1b99e4	22	const struct mn10300_operand mn10300_operands[] = {
e7c50cef	23	#define UNUSED 0
5ab7bce6 JL	24	{0, 0, 0},
5ab7bce6 JL	25
36b34aa4	26	#define DN0 (UNUSED+1)
5ab7bce6 JL	27	{2, 0, MN10300_OPERAND_DREG},
5ab7bce6 JL	28
36b34aa4 JL	29	#define DN1 (DN0+1)
	30	{2, 2, MN10300_OPERAND_DREG},
	31
	32	#define DM0 (DN1+1)
5ab7bce6 JL	33	{2, 0, MN10300_OPERAND_DREG},
5ab7bce6 JL	34
36b34aa4 JL	35	#define DM1 (DM0+1)
	36	{2, 2, MN10300_OPERAND_DREG},
	37
	38	#define AN0 (DM1+1)
5ab7bce6 JL	39	{2, 0, MN10300_OPERAND_AREG},
5ab7bce6 JL	40
36b34aa4 JL	41	#define AN1 (AN0+1)
	42	{2, 2, MN10300_OPERAND_AREG},
	43
	44	#define AM0 (AN1+1)
5ab7bce6 JL	45	{2, 0, MN10300_OPERAND_AREG},
5ab7bce6 JL	46
36b34aa4 JL	47	#define AM1 (AM0+1)
	48	{2, 2, MN10300_OPERAND_AREG},
	49
	50	#define IMM8 (AM1+1)
5ab7bce6 JL	51	{8, 0, MN10300_OPERAND_PROMOTE},
	52
	53	#define IMM16 (IMM8+1)
	54	{16, 0, MN10300_OPERAND_PROMOTE},
	55
	56	#define IMM32 (IMM16+1)
	57	{32, 0, 0},
	58
	59	#define D8 (IMM32+1)
	60	{8, 0, MN10300_OPERAND_PROMOTE},
	61
	62	#define D16 (D8+1)
	63	{16, 0, MN10300_OPERAND_PROMOTE},
	64
	65	#define D32 (D16+1)
	66	{32, 0, 0},
	67
	68	#define SP (D32+1)
	69	{8, 0, MN10300_OPERAND_SP},
	70
	71	#define PSW (SP+1)
	72	{0, 0, MN10300_OPERAND_PSW},
	73
	74	#define MDR (PSW+1)
	75	{0, 0, MN10300_OPERAND_MDR},
	76
	77	#define ABS16 (MDR+1)
	78	{16, 0, MN10300_OPERAND_PROMOTE},
	79
	80	#define ABS32 (ABS16+1)
	81	{32, 0, 0},
	82
	83	#define DI (ABS32+1)
	84	{2, 0, MN10300_OPERAND_DREG},
	85
db229054	86	#define SD8 (DI+1)
5ab7bce6 JL	87	{8, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
	88
	89	#define SD16 (SD8+1)
	90	{16, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
	91
	92	#define SD8N (SD16+1)
	93	{8, 0, MN10300_OPERAND_SIGNED},
	94
	95	#define SIMM8 (SD8N+1)
	96	{8, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
	97
	98	#define SIMM16 (SIMM8+1)
	99	{16, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
db229054 JL	100
	101	#define PAREN (SIMM16+1)
	102	{0, 0, MN10300_OPERAND_PAREN},
e7c50cef JL	103	} ;
e7c50cef JL	104
db229054 JL	105	#define MEM(ADDR) PAREN, ADDR, PAREN
db229054 JL	106	#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
e7c50cef JL	107	\f
	108	/* The opcode table.
	109
	110	The format of the opcode table is:
	111
	112	NAME OPCODE MASK { OPERANDS }
	113
	114	NAME is the name of the instruction.
	115	OPCODE is the instruction opcode.
	116	MASK is the opcode mask; this is used to tell the disassembler
	117	which bits in the actual opcode must match OPCODE.
	118	OPERANDS is the list of operands.
	119
	120	The disassembler reads the table in order and prints the first
	121	instruction which matches, so this table is sorted to put more
	122	specific instructions before more general instructions. It is also
	123	sorted by major opcode. */
	124
ae1b99e4	125	const struct mn10300_opcode mn10300_opcodes[] = {
36b34aa4 JL	126	{ "mov", 0x8000, 0xf000, FMT_S1, {SIMM8, DN0}},
	127	{ "mov", 0x80, 0xf0, FMT_S0, {DM1, DN0}},
	128	{ "mov", 0xf1e0, 0xfff0, FMT_D0, {DM1, AN0}},
	129	{ "mov", 0xf1d0, 0xfff0, FMT_D0, {AM1, DN0}},
	130	{ "mov", 0x9000, 0xf000, FMT_S1, {IMM8, AN0}},
	131	{ "mov", 0x90, 0xf0, FMT_S0, {AM1, AN0}},
	132	{ "mov", 0x3c, 0xfc, FMT_S0, {SP, AN0}},
	133	{ "mov", 0xf2f0, 0xfff3, FMT_D0, {AM1, SP}},
	134	{ "mov", 0xf2e4, 0xfffc, FMT_D0, {PSW, DN0}},
	135	{ "mov", 0xf2f3, 0xfff3, FMT_D0, {DM1, PSW}},
	136	{ "mov", 0xf2e0, 0xfffc, FMT_D0, {MDR, DN0}},
	137	{ "mov", 0xf2f2, 0xfff3, FMT_D0, {DM1, MDR}},
	138	{ "mov", 0x70, 0xf0, FMT_S0, {MEM(AM0), DN1}},
	139	{ "mov", 0xf80000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
	140	{ "mov", 0xfa000000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
	141	{ "mov", 0xfc000000, 0xfff00000, FMT_D4, {MEM2(D32, AM0), DN1}},
	142	{ "mov", 0x5800, 0xfc00, FMT_S1, {MEM2(D8, SP), DN0}},
	143	{ "mov", 0xfab40000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), DN0}},
	144	{ "mov", 0xfcb40000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), DN0}},
	145	{ "mov", 0xf300, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN0}},
	146	{ "mov", 0x300000, 0xfc0000, FMT_S2, {MEM(ABS16), DN0}},
	147	{ "mov", 0xfca40000, 0xfffc0000, FMT_D4, {MEM(ABS32), DN0}},
	148	{ "mov", 0xf000, 0xfff0, FMT_D0, {MEM(AM0), AN1}},
	149	{ "mov", 0xf82000, 0xfff000, FMT_D1, {MEM2(D8, AM0), AN1}},
	150	{ "mov", 0xfa200000, 0xfff00000, FMT_D2, {MEM2(D16, AM0), AN1}},
	151	{ "mov", 0xfc200000, 0xfff00000, FMT_D4, {MEM2(D32, AM0), AN1}},
	152	{ "mov", 0x5c00, 0xfc00, FMT_S1, {MEM2(D8, SP), AN0}},
	153	{ "mov", 0xfab00000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), AN0}},
	154	{ "mov", 0xfcb00000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), AN0}},
	155	{ "mov", 0xf380, 0xffc0, FMT_D0, {MEM2(DI, AM0), AN0}},
	156	{ "mov", 0xfaa00000, 0xfffc0000, FMT_D2, {MEM(ABS16), AN0}},
	157	{ "mov", 0xfca00000, 0xfffc0000, FMT_D4, {MEM(ABS32), AN0}},
	158	{ "mov", 0xf8f000, 0xfffc00, FMT_D1, {MEM2(SD8N, AM0), SP}},
	159	{ "mov", 0x60, 0xf0, FMT_S0, {DM1, MEM(AN0)}},
	160	{ "mov", 0xf81000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
	161	{ "mov", 0xfa100000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
	162	{ "mov", 0xfc100000, 0xfff00000, FMT_D4, {DM1, MEM2(D32, AN0)}},
	163	{ "mov", 0x4200, 0xf300, FMT_S1, {DM1, MEM2(D8, SP)}},
	164	{ "mov", 0xfa910000, 0xfff30000, FMT_D2, {DM1, MEM2(D16, SP)}},
	165	{ "mov", 0xfc910000, 0xfff30000, FMT_D4, {DM1, MEM2(D32, SP)}},
	166	{ "mov", 0xf340, 0xffc0, FMT_D0, {DM0, MEM2(DI, AN0)}},
	167	{ "mov", 0x010000, 0xf30000, FMT_S2, {DM1, MEM(ABS16)}},
	168	{ "mov", 0xfc810000, 0xfff30000, FMT_D4, {DM1, MEM(ABS32)}},
	169	{ "mov", 0xf010, 0xfff0, FMT_D0, {AM1, MEM(AN0)}},
	170	{ "mov", 0xf83000, 0xfff000, FMT_D1, {AM1, MEM2(SD8, AN0)}},
	171	{ "mov", 0xfa300000, 0xfff00000, FMT_D2, {AM1, MEM2(SD16, AN0)}},
	172	{ "mov", 0xfc300000, 0xfff00000, FMT_D4, {AM1, MEM2(D32, AN0)}},
	173	{ "mov", 0x4300, 0xf300, FMT_S1, {AM1, MEM2(D8, SP)}},
	174	{ "mov", 0xfa900000, 0xfff30000, FMT_D2, {AM1, MEM2(D16, SP)}},
	175	{ "mov", 0xfc900000, 0xfc930000, FMT_D4, {AM1, MEM2(D32, SP)}},
	176	{ "mov", 0xf3c0, 0xffc0, FMT_D0, {AM0, MEM2(DI, AN0)}},
	177	{ "mov", 0xfa800000, 0xfff30000, FMT_D2, {AM1, MEM(ABS16)}},
	178	{ "mov", 0xfc800000, 0xfff30000, FMT_D4, {AM1, MEM(ABS32)}},
	179	{ "mov", 0xf8f400, 0xfffc00, FMT_D1, {SP, MEM2(SD8N, AN0)}},
	180	{ "mov", 0x2c0000, 0xfc0000, FMT_S2, {SIMM16, DN0}},
	181	{ "mov", 0xfcdc0000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	182	{ "mov", 0x240000, 0xfc0000, FMT_S2, {IMM16, AN0}},
	183	{ "mov", 0xfcdc0000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
	184
	185	{ "movbu", 0xf040, 0xfff0, FMT_D0, {MEM(AM0), DN1}},
	186	{ "movbu", 0xf84000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
	187	{ "movbu", 0xfa400000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
	188	{ "movbu", 0xfc400000, 0xfff00000, FMT_D4, {MEM2(D32, AM0), DN1}},
	189	{ "movbu", 0xf8b800, 0xfffc00, FMT_D1, {MEM2(D8, SP), DN0}},
190	{ "movbu", 0xfab80000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), DN0}},
191	{ "movbu", 0xfcb80000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), DN0}},
192	{ "movbu", 0xf400, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN0}},
193	{ "movbu", 0x340000, 0xfc0000, FMT_S2, {MEM(ABS16), DN0}},
194	{ "movbu", 0xfca80000, 0xfffc0000, FMT_D4, {MEM(ABS32), DN0}},
195	{ "movbu", 0xf050, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
196	{ "movbu", 0xf85000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
197	{ "movbu", 0xfa500000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
198	{ "movbu", 0xfc500000, 0xfff00000, FMT_D4, {DM1, MEM2(D32, AN0)}},
199	{ "movbu", 0xf89200, 0xfff300, FMT_D1, {DM1, MEM2(D8, SP)}},
200	{ "movbu", 0xfa920000, 0xfff30000, FMT_D2, {DM1, MEM2(D16, SP)}},
201	{ "movbu", 0xfc920000, 0xfff30000, FMT_D4, {DM1, MEM2(D32, SP)}},
202	{ "movbu", 0xf440, 0xffc0, FMT_D0, {DM0, MEM2(DI, AN0)}},
203	{ "movbu", 0x020000, 0xf30000, FMT_S2, {DM1, MEM(ABS16)}},
204	{ "movbu", 0xfc820000, 0xfff30000, FMT_D4, {DM1, MEM(ABS32)}},
205
206	{ "movhu", 0xf060, 0xfff0, FMT_D0, {MEM(AM0), DN1}},
207	{ "movhu", 0xf86000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
208	{ "movhu", 0xfa600000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
209	{ "movhu", 0xfc600000, 0xfff00000, FMT_D4, {MEM2(D32, AM0), DN1}},
210	{ "movhu", 0xf8bc00, 0xfffc00, FMT_D1, {MEM2(D8, SP), DN0}},
211	{ "movhu", 0xfabc0000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), DN0}},
212	{ "movhu", 0xfcbc0000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), DN0}},
213	{ "movhu", 0xf480, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN0}},
214	{ "movhu", 0xc80000, 0xfc0000, FMT_S2, {MEM(ABS16), DN0}},
215	{ "movhu", 0xfcac0000, 0xfffc0000, FMT_D4, {MEM(ABS32), DN0}},
216	{ "movhu", 0xf070, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
217	{ "movhu", 0xf87000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
218	{ "movhu", 0xfa700000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
219	{ "movhu", 0xfc700000, 0xfff00000, FMT_D4, {DM1, MEM2(D32, AN0)}},
220	{ "movhu", 0xf89300, 0xfff300, FMT_D1, {DM1, MEM2(D8, SP)}},
221	{ "movhu", 0xfa930000, 0xfff30000, FMT_D2, {DM1, MEM2(D16, SP)}},
222	{ "movhu", 0xfc930000, 0xfff30000, FMT_D4, {DM1, MEM2(D32, SP)}},
223	{ "movhu", 0xf4c0, 0xffc0, FMT_D0, {DM0, MEM2(DI, AN0)}},
224	{ "movhu", 0x030000, 0xf30000, FMT_S2, {DM1, MEM(ABS16)}},
225	{ "movhu", 0xfc830000, 0xfff30000, FMT_D4, {DM1, MEM(ABS32)}},
226
227	{ "ext", 0xf2d0, 0xfffc, FMT_D0, {DN0}},
228	{ "extb", 0x10, 0xfc, FMT_S0, {DN0}},
229	{ "extbu", 0x14, 0xfc, FMT_S0, {DN0}},
230	{ "exth", 0x18, 0xfc, FMT_S0, {DN0}},
231	{ "exthu", 0x1c, 0xfc, FMT_S0, {DN0}},
db229054 JL	232
	233	{ "movm", 0xce00, 0xff00, FMT_S1, {MEM(SP), IMM8}},
	234	{ "movm", 0xcf00, 0xff00, FMT_S1, {IMM8, MEM(SP)}},
	235
36b34aa4 JL	236	{ "clr", 0x00, 0xf3, FMT_S0, {DN1}},
	237
	238	{ "add", 0xe0, 0xf0, FMT_S0, {DM1, DN0}},
	239	{ "add", 0xf160, 0xfff0, FMT_D0, {DM1, AN0}},
	240	{ "add", 0xf150, 0xfff0, FMT_D0, {AM1, DN0}},
	241	{ "add", 0xf170, 0xfff0, FMT_D0, {AM1, AN0}},
	242	{ "add", 0x2800, 0xfc00, FMT_S1, {SIMM8, DN0}},
	243	{ "add", 0xfac00000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
	244	{ "add", 0xfcc00000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	245	{ "add", 0x2000, 0xfc00, FMT_S1, {SIMM8, AN0}},
	246	{ "add", 0xfad00000, 0xfffc0000, FMT_D2, {SIMM16, AN0}},
	247	{ "add", 0xfcd00000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
db229054 JL	248	{ "add", 0xf8fe00, 0xffff00, FMT_D1, {SIMM8, SP}},
	249	{ "add", 0xfafe0000, 0xfffc0000, FMT_D2, {SIMM16, SP}},
	250	{ "add", 0xfcfe0000, 0xfff0000, FMT_D4, {IMM32, SP}},
36b34aa4 JL	251	{ "addc", 0xf140, 0xfff0, FMT_D0, {DM1, DN0}},
	252
	253	{ "sub", 0xf100, 0xfff0, FMT_D0, {DM1, DN0}},
	254	{ "sub", 0xf120, 0xfff0, FMT_D0, {DM1, AN0}},
	255	{ "sub", 0xf110, 0xfff0, FMT_D0, {AM1, DN0}},
	256	{ "sub", 0xf130, 0xfff0, FMT_D0, {AM1, AN0}},
	257	{ "sub", 0xfcc40000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	258	{ "sub", 0xfcd40000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
	259	{ "subc", 0xf180, 0xfff0, FMT_D0, {DM1, DN0}},
	260
	261	{ "mul", 0xf240, 0xfff0, FMT_D0, {DM1, DN0}},
	262	{ "mulu", 0xf250, 0xfff0, FMT_D0, {DM1, DN0}},
	263
	264	{ "div", 0xf260, 0xfff0, FMT_D0, {DM1, DN0}},
	265	{ "divu", 0xf270, 0xfff0, FMT_D0, {DM1, DN0}},
	266
	267	{ "inc", 0x40, 0xf3, FMT_S0, {DN1}},
	268	{ "inc", 0x41, 0xf3, FMT_S0, {AN1}},
	269	{ "inc4", 0x50, 0xfc, FMT_S0, {AN0}},
	270
	271	{ "cmp", 0xa000, 0xf000, FMT_S1, {SIMM8, DN0}},
	272	{ "cmp", 0xa0, 0xf0, FMT_S0, {DM1, DN0}},
	273	{ "cmp", 0xf1a0, 0xfff0, FMT_D0, {DM1, AN0}},
	274	{ "cmp", 0xf190, 0xfff0, FMT_D0, {AM1, DN0}},
	275	{ "cmp", 0xb000, 0xf000, FMT_S1, {IMM8, AN0}},
	276	{ "cmp", 0xb0, 0xf0, FMT_S0, {AM1, AN0}},
	277	{ "cmp", 0xfac80000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
	278	{ "cmp", 0xfcc80000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	279	{ "cmp", 0xfad80000, 0xfffc0000, FMT_D2, {IMM16, AN0}},
	280	{ "cmp", 0xfcd80000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
	281
	282	{ "and", 0xf200, 0xfff0, FMT_D0, {DM1, DN0}},
	283	{ "and", 0xf8e000, 0xfffc00, FMT_D1, {IMM8, DN0}},
	284	{ "and", 0xfae00000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
	285	{ "and", 0xfce00000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
db229054	286	{ "and", 0xfafc0000, 0xfffc0000, FMT_D2, {IMM16, PSW}},
36b34aa4 JL	287	{ "or", 0xf210, 0xfff0, FMT_D0, {DM1, DN0}},
	288	{ "or", 0xf8e400, 0xfffc00, FMT_D1, {IMM8, DN0}},
	289	{ "or", 0xfae40000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
	290	{ "or", 0xfce40000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
db229054	291	{ "or", 0xfafd0000, 0xfffc0000, FMT_D2, {IMM16, PSW}},
36b34aa4 JL	292	{ "xor", 0xf220, 0xfff0, FMT_D0, {DM1, DN0}},
	293	{ "xor", 0xfae80000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
	294	{ "xor", 0xfce80000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	295	{ "not", 0xf230, 0xfffc, FMT_D0, {DN0}},
	296
	297	{ "btst", 0xf8ec00, 0xfffc00, FMT_D1, {IMM8, DN0}},
	298	{ "btst", 0xfaec0000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
	299	{ "btst", 0xfcec0000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
db229054	300	{ "btst", 0xfe020000, 0xffff0000, FMT_D5, {IMM8, MEM(ABS32)}},
36b34aa4 JL	301	{ "btst", 0xfaf80000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N,AN0)}},
36b34aa4 JL	302	{ "bset", 0xf080, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
db229054	303	{ "bset", 0xfe000000, 0xffff0000, FMT_D5, {IMM8, MEM(ABS32)}},
36b34aa4 JL	304	{ "bset", 0xfaf00000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N,AN0)}},
36b34aa4 JL	305	{ "bclr", 0xf090, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
db229054	306	{ "bclr", 0xfe010000, 0xffff0000, FMT_D5, {IMM8, MEM(ABS32)}},
36b34aa4 JL	307	{ "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N,AN0)}},
36b34aa4 JL	308
1e5ddd3b	309	{ "asr", 0xf2b0, 0xfff0, FMT_D0, {DM1, DN0}},
36b34aa4	310	{ "asr", 0xf8c800, 0xfffc00, FMT_D1, {IMM8, DN0}},
1e5ddd3b	311	{ "lsr", 0xf2a0, 0xfff0, FMT_D0, {DM1, DN0}},
36b34aa4	312	{ "lsr", 0xf8c400, 0xfffc00, FMT_D1, {IMM8, DN0}},
1e5ddd3b	313	{ "asl", 0xf290, 0xfff0, FMT_D0, {DM1, DN0}},
36b34aa4 JL	314	{ "asl", 0xf8c000, 0xfffc00, FMT_D1, {IMM8, DN0}},
	315	{ "asl2", 0x54, 0xfc, FMT_S0, {DN0}},
	316	{ "ror", 0xf284, 0xfffc, FMT_D0, {DN0}},
	317	{ "rol", 0xf280, 0xfffc, FMT_D0, {DN0}},
db229054 JL	318
	319	{ "beq", 0xc800, 0xff00, FMT_S1, {SD8N}},
	320	{ "bne", 0xc900, 0xff00, FMT_S1, {SD8N}},
	321	{ "bgt", 0xc100, 0xff00, FMT_S1, {SD8N}},
	322	{ "bge", 0xc200, 0xff00, FMT_S1, {SD8N}},
	323	{ "ble", 0xc300, 0xff00, FMT_S1, {SD8N}},
	324	{ "blt", 0xc000, 0xff00, FMT_S1, {SD8N}},
	325	{ "bhi", 0xc500, 0xff00, FMT_S1, {SD8N}},
	326	{ "bcc", 0xc600, 0xff00, FMT_S1, {SD8N}},
	327	{ "bls", 0xc700, 0xff00, FMT_S1, {SD8N}},
	328	{ "bcs", 0xc400, 0xff00, FMT_S1, {SD8N}},
	329	{ "bvc", 0xf8e800, 0xffff00, FMT_D1, {SD8N}},
	330	{ "bvs", 0xf8e900, 0xffff00, FMT_D1, {SD8N}},
	331	{ "bnc", 0xf8ea00, 0xffff00, FMT_D1, {SD8N}},
	332	{ "bns", 0xf8eb00, 0xffff00, FMT_D1, {SD8N}},
	333	{ "bra", 0xca00, 0xff00, FMT_S1, {SD8N}},
	334
	335	{ "leq", 0xd8, 0xff, FMT_S0, {UNUSED}},
	336	{ "lne", 0xd9, 0xff, FMT_S0, {UNUSED}},
	337	{ "lgt", 0xd1, 0xff, FMT_S0, {UNUSED}},
	338	{ "lge", 0xd2, 0xff, FMT_S0, {UNUSED}},
	339	{ "lle", 0xd3, 0xff, FMT_S0, {UNUSED}},
	340	{ "llt", 0xd0, 0xff, FMT_S0, {UNUSED}},
	341	{ "lhi", 0xd5, 0xff, FMT_S0, {UNUSED}},
	342	{ "lcc", 0xd6, 0xff, FMT_S0, {UNUSED}},
	343	{ "lls", 0xd7, 0xff, FMT_S0, {UNUSED}},
	344	{ "lcs", 0xd4, 0xff, FMT_S0, {UNUSED}},
	345	{ "lra", 0xda, 0xff, FMT_S0, {UNUSED}},
	346	{ "lcc", 0xd6, 0xff, FMT_S0, {UNUSED}},
	347	{ "setlb", 0xdb, 0xff, FMT_S0, {UNUSED}},
	348
36b34aa4	349	{ "jmp", 0xf0f4, 0xfffc, FMT_D0, {AN0}},
db229054 JL	350	{ "jmp", 0xcc0000, 0xff0000, FMT_S2, {D16}},
	351	{ "jmp", 0xdc0000, 0xff0000, FMT_S4, {D32}},
	352	{ "call", 0xcd000000, 0xff000000, FMT_S4, {D16,IMM8,IMM8}},
	353	{ "call", 0xdd000000, 0xff000000, FMT_S6, {D32,IMM8,IMM8}},
36b34aa4	354	{ "calls", 0xf0f0, 0xfffc, FMT_D0, {AN0}},
db229054 JL	355	{ "calls", 0xfaff0000, 0xffff0000, FMT_D2, {D16}},
	356	{ "calls", 0xfcff0000, 0xffff0000, FMT_D4, {D32}},
	357
	358	{ "ret", 0xdf0000, 0xff00000, FMT_S2, {IMM8, IMM8}},
	359	{ "retf", 0xde0000, 0xff00000, FMT_S2, {IMM8, IMM8}},
	360	{ "rets", 0xf0fc, 0xffff, FMT_D0, {UNUSED}},
	361	{ "rti", 0xf0fd, 0xffff, FMT_D0, {UNUSED}},
	362	{ "trap", 0xf0fe, 0xffff, FMT_D0, {UNUSED}},
	363	{ "rtm", 0xf0ff, 0xffff, FMT_D0, {UNUSED}},
	364	{ "nop", 0xcb, 0xff, FMT_S0, {UNUSED}},
	365	/* { "udf", 0, 0, {0}}, */
344d6417	366
36b34aa4 JL	367	{ "putx", 0xf500, 0xfff0, FMT_D0, {DM0}},
	368	{ "getx", 0xf6f0, 0xfff0, FMT_D0, {DN0}},
	369	{ "mulq", 0xf600, 0xfff0, FMT_D0, {DM1, DN0}},
	370	{ "mulq", 0xf90000, 0xfffc00, FMT_D1, {SIMM8, DN0}},
	371	{ "mulq", 0xfb000000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
	372	{ "mulq", 0xfd000000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	373	{ "mulqu", 0xf610, 0xfff0, FMT_D0, {DM1, DN0}},
	374	{ "mulqu", 0xf90400, 0xfffc00, FMT_D1, {SIMM8, DN0}},
	375	{ "mulqu", 0xfb040000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
	376	{ "mulqu", 0xfd040000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	377	{ "sat16", 0xf640, 0xfff0, FMT_D0, {DM1, DN0}},
	378	{ "sat24", 0xf650, 0xfff0, FMT_D0, {DM1, DN0}},
	379	{ "bsch", 0xf670, 0xfff0, FMT_D0, {DM1, DN0}},
db229054	380	{ 0, 0, 0, 0, {0}},
5ab7bce6	381
cd8a9026	382	} ;
e7c50cef	383
ae1b99e4 JL	384	const int mn10300_num_opcodes =
ae1b99e4 JL	385	sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
e7c50cef JL	386
e7c50cef JL	387	\f