[binutils.git] / opcodes / mn10300-opc.c

/* Assemble Matsushita MN10300 instructions.
   Copyright (C) 1996 Free Software Foundation, Inc.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#include "ansidecl.h"
#include "opcode/mn10300.h"

/* Formats.  Right now we don't use this.  We probably will later for
   the size of the instruction and other random stuff.  */
#define FMT_S0 1
#define FMT_S1 2
#define FMT_S2 3
#define FMT_S4 4
#define FMT_S6 5
#define FMT_D0 6
#define FMT_D1 7
#define FMT_D2 8
#define FMT_D4 9
#define FMT_D5 10

/* Operands currently used.  This is temporary.  */

\f
const struct mn10300_operand mn10300_operands[] = {
#define UNUSED	0
  {0, 0, 0}, 

#define DN      (UNUSED+1)
  {2, 0, MN10300_OPERAND_DREG},

#define DM      (DN+1)
  {2, 0, MN10300_OPERAND_DREG},

#define AN      (DM+1)
  {2, 0, MN10300_OPERAND_AREG},

#define AM      (AN+1)
  {2, 0, MN10300_OPERAND_AREG},

#define IMM8    (AM+1)
  {8, 0, MN10300_OPERAND_PROMOTE},

#define IMM16    (IMM8+1)
  {16, 0, MN10300_OPERAND_PROMOTE},

#define IMM32    (IMM16+1)
  {32, 0, 0},

#define D8    (IMM32+1)
  {8, 0, MN10300_OPERAND_PROMOTE},

#define D16    (D8+1)
  {16, 0, MN10300_OPERAND_PROMOTE},

#define D32    (D16+1)
  {32, 0, 0},

#define SP    (D32+1)
  {8, 0, MN10300_OPERAND_SP},

#define PSW    (SP+1)
  {0, 0, MN10300_OPERAND_PSW},

#define MDR    (PSW+1)
  {0, 0, MN10300_OPERAND_MDR},

#define ABS16 (MDR+1)
  {16, 0, MN10300_OPERAND_PROMOTE},

#define ABS32 (ABS16+1)
  {32, 0, 0},

#define DI (ABS32+1)
  {2, 0, MN10300_OPERAND_DREG},

#define SD8    (DI+1)
  {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define SD16    (SD8+1)
  {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define SD8N    (SD16+1)
  {8, 0, MN10300_OPERAND_SIGNED},

#define SIMM8    (SD8N+1)
  {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define SIMM16    (SIMM8+1)
  {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define PAREN	(SIMM16+1)
  {0, 0, MN10300_OPERAND_PAREN}, 
} ; 

#define MEM(ADDR) PAREN, ADDR, PAREN 
#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN 
\f
/* The opcode table.

   The format of the opcode table is:

   NAME		OPCODE		MASK		{ OPERANDS }

   NAME is the name of the instruction.
   OPCODE is the instruction opcode.
   MASK is the opcode mask; this is used to tell the disassembler
     which bits in the actual opcode must match OPCODE.
   OPERANDS is the list of operands.

   The disassembler reads the table in order and prints the first
   instruction which matches, so this table is sorted to put more
   specific instructions before more general instructions.  It is also
   sorted by major opcode.  */

const struct mn10300_opcode mn10300_opcodes[] = {
{ "mov",	0x8000,		0xf000,		FMT_S1, {SIMM8, DN}},
{ "mov",	0x80,		0xf0,		FMT_S0, {DM, DN}},
{ "mov",	0xf1e0,		0xfff0,		FMT_D0, {DM, AN}},
{ "mov",	0xf1d0,		0xfff0,		FMT_D0, {AM, DN}},
{ "mov",	0x9000,		0xf000,		FMT_S1, {IMM8, AN}},
{ "mov",	0x90,		0xf0,		FMT_S0, {AM, AN}},
{ "mov",	0x3c,		0xfc,		FMT_S0, {SP, AN}},
{ "mov",	0xf2f0,		0xfff3,		FMT_D0, {AM, SP}},
{ "mov",	0xf2e4,		0xfffc,		FMT_D0, {PSW, DN}},
{ "mov",	0xf2f3,		0xfff3,		FMT_D0, {DM, PSW}},
{ "mov",	0xf2e0,		0xfffc,		FMT_D0, {MDR, DN}},
{ "mov",	0xf2f2,		0xfff3,		FMT_D0, {DM, MDR}},
{ "mov",	0x70,		0xf0,		FMT_S0, {MEM(AM), DN}},
{ "mov",	0xf80000,	0xfff000,	FMT_D1, {MEM2(SD8, AM), DN}},
{ "mov",	0xfa000000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM), DN}},
{ "mov",	0xfc000000,	0xfff00000,	FMT_D4, {MEM2(D32, AM), DN}},
{ "mov",	0x5800,		0xfc00,		FMT_S1, {MEM2(D8, SP), DN}},
{ "mov",	0xfab40000,	0xfffc0000,	FMT_D2, {MEM2(D16, SP), DN}},
{ "mov",	0xfcb40000,	0xfffc0000,	FMT_D4, {MEM2(D32, SP), DN}},
{ "mov",	0xf300,		0xffc0,		FMT_D0, {MEM2(DI, AM), DN}},
{ "mov",	0x300000,	0xfc0000,	FMT_S2, {MEM(ABS16), DN}},
{ "mov",	0xfca40000,	0xfffc0000,	FMT_D4, {MEM(ABS32), DN}},
{ "mov",	0xf000,		0xfff0,		FMT_D0, {MEM(AM), AN}},
{ "mov",	0xf82000,	0xfff000,	FMT_D1, {MEM2(D8, AM), AN}},
{ "mov",	0xfa200000,	0xfff00000,	FMT_D2, {MEM2(D16, AM), AN}},
{ "mov",	0xfc200000,	0xfff00000,	FMT_D4, {MEM2(D32, AM), AN}},
{ "mov",	0x5c00,		0xfc00,		FMT_S1, {MEM2(D8, SP), AN}},
{ "mov",	0xfab00000,	0xfffc0000,	FMT_D2, {MEM2(D16, SP), AN}},
{ "mov",	0xfcb00000,	0xfffc0000,	FMT_D4, {MEM2(D32, SP), AN}},
{ "mov",	0xf380,		0xffc0,		FMT_D0, {MEM2(DI, AM), AN}},
{ "mov",	0xfaa00000,	0xfffc0000,	FMT_D2, {MEM(ABS16), AN}},
{ "mov",	0xfca00000,	0xfffc0000,	FMT_D4, {MEM(ABS32), AN}},
{ "mov",	0xf8f000,	0xfffc00,	FMT_D1, {MEM2(SD8N, AM), SP}},
{ "mov",	0x60,		0xf0,		FMT_S0, {DM, MEM(AN)}},
{ "mov",	0xf81000,	0xfff000,	FMT_D1, {DM, MEM2(SD8, AN)}},
{ "mov",	0xfa100000,	0xfff00000,	FMT_D2, {DM, MEM2(SD16, AN)}},
{ "mov",	0xfc100000,	0xfff00000,	FMT_D4, {DM, MEM2(D32, AN)}},
{ "mov",	0x4200,		0xf300,		FMT_S1, {DM, MEM2(D8, SP)}},
{ "mov",	0xfa910000,	0xfff30000,	FMT_D2, {DM, MEM2(D16, SP)}},
{ "mov",	0xfc910000,	0xfff30000,	FMT_D4, {DM, MEM2(D32, SP)}},
{ "mov",	0xf340,		0xffc0,		FMT_D0, {DM, MEM2(DI, AN)}},
{ "mov",	0x010000,	0xf30000,	FMT_S2, {DM, MEM(ABS16)}},
{ "mov",	0xfc810000,	0xfff30000,	FMT_D4, {DM, MEM(ABS32)}},
{ "mov",	0xf010,		0xfff0,		FMT_D0, {AM, MEM(AN)}},
{ "mov",	0xf83000,	0xfff000,	FMT_D1, {AM, MEM2(SD8, AN)}},
{ "mov",	0xfa300000,	0xfff00000,	FMT_D2, {AM, MEM2(SD16, AN)}},
{ "mov",	0xfc300000,	0xfff00000,	FMT_D4, {AM, MEM2(D32, AN)}},
{ "mov",	0x4300,		0xf300,		FMT_S1, {AM, MEM2(D8, SP)}},
{ "mov",	0xfa900000,	0xfff30000,	FMT_D2, {AM, MEM2(D16, SP)}},
{ "mov",	0xfc900000,	0xfc930000,	FMT_D4, {AM, MEM2(D32, SP)}},
{ "mov",	0xf3c0,		0xffc0,		FMT_D0, {AM, MEM2(DI, AN)}},
{ "mov",	0xfa800000,	0xfff30000,	FMT_D2, {AM, MEM(ABS16)}},
{ "mov",	0xfc800000,	0xfff30000,	FMT_D4, {AM, MEM(ABS32)}},
{ "mov",	0xf8f400,	0xfffc00,	FMT_D1, {SP, MEM2(SD8N, AN)}},
{ "mov",	0x2c0000,	0xfc0000,	FMT_S2, {SIMM16, DN}},
{ "mov",	0xfcdc0000,	0xfffc0000,	FMT_D4, {IMM32, DN}},
{ "mov",	0x240000,	0xfc0000,	FMT_S2, {IMM16, AN}},
{ "mov",	0xfcdc0000,	0xfffc0000,	FMT_D4, {IMM32, AN}},

{ "movbu",	0xf040,		0xfff0,		FMT_D0, {MEM(AM), DN}},
{ "movbu",	0xf84000,	0xfff000,	FMT_D1, {MEM2(SD8, AM), DN}},
{ "movbu",	0xfa400000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM), DN}},
{ "movbu",	0xfc400000,	0xfff00000,	FMT_D4, {MEM2(D32, AM), DN}},
{ "movbu",	0xf8b800,	0xfffc00,	FMT_D1, {MEM2(D8, SP), DN}},
{ "movbu",	0xfab80000,	0xfffc0000,	FMT_D2, {MEM2(D16, SP), DN}},
{ "movbu",	0xfcb80000,	0xfffc0000,	FMT_D4, {MEM2(D32, SP), DN}},
{ "movbu",	0xf400,		0xffc0,		FMT_D0, {MEM2(DI, AM), DN}},
{ "movbu",	0x340000,	0xfc0000,	FMT_S2, {MEM(ABS16), DN}},
{ "movbu",	0xfca80000,	0xfffc0000,	FMT_D4, {MEM(ABS32), DN}},
{ "movbu",	0xf050,		0xfff0,		FMT_D0, {DM, MEM(AN)}},
{ "movbu",	0xf85000,	0xfff000,	FMT_D1, {DM, MEM2(SD8, AN)}},
{ "movbu",	0xfa500000,	0xfff00000,	FMT_D2, {DM, MEM2(SD16, AN)}},
{ "movbu",	0xfc500000,	0xfff00000,	FMT_D4, {DM, MEM2(D32, AN)}},
{ "movbu",	0xf89200,	0xfff300,	FMT_D1, {DM, MEM2(D8, SP)}},
{ "movbu",	0xfa920000,	0xfff30000,	FMT_D2, {DM, MEM2(D16, SP)}},
{ "movbu",	0xfc920000,	0xfff30000,	FMT_D4, {DM, MEM2(D32, SP)}},
{ "movbu",	0xf440,		0xffc0,		FMT_D0, {DM, MEM2(DI, AN)}},
{ "movbu",	0x020000,	0xf30000,	FMT_S2, {DM, MEM(ABS16)}},
{ "movbu",	0xfc820000,	0xfff30000,	FMT_D4, {DM, MEM(ABS32)}},

{ "movhu",	0xf060,		0xfff0,		FMT_D0, {MEM(AM), DN}},
{ "movhu",	0xf86000,	0xfff000,	FMT_D1, {MEM2(SD8, AM), DN}},
{ "movhu",	0xfa600000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM), DN}},
{ "movhu",	0xfc600000,	0xfff00000,	FMT_D4, {MEM2(D32, AM), DN}},
{ "movhu",	0xf8bc00,	0xfffc00,	FMT_D1, {MEM2(D8, SP), DN}},
{ "movhu",	0xfabc0000,	0xfffc0000,	FMT_D2, {MEM2(D16, SP), DN}},
{ "movhu",	0xfcbc0000,	0xfffc0000,	FMT_D4, {MEM2(D32, SP), DN}},
{ "movhu",	0xf480,		0xffc0,		FMT_D0, {MEM2(DI, AM), DN}},
{ "movhu",	0xc80000,	0xfc0000,	FMT_S2, {MEM(ABS16), DN}},
{ "movhu",	0xfcac0000,	0xfffc0000,	FMT_D4, {MEM(ABS32), DN}},
{ "movhu",	0xf070,		0xfff0,		FMT_D0, {DM, MEM(AN)}},
{ "movhu",	0xf87000,	0xfff000,	FMT_D1, {DM, MEM2(SD8, AN)}},
{ "movhu",	0xfa700000,	0xfff00000,	FMT_D2, {DM, MEM2(SD16, AN)}},
{ "movhu",	0xfc700000,	0xfff00000,	FMT_D4, {DM, MEM2(D32, AN)}},
{ "movhu",	0xf89300,	0xfff300,	FMT_D1, {DM, MEM2(D8, SP)}},
{ "movhu",	0xfa930000,	0xfff30000,	FMT_D2, {DM, MEM2(D16, SP)}},
{ "movhu",	0xfc930000,	0xfff30000,	FMT_D4, {DM, MEM2(D32, SP)}},
{ "movhu",	0xf4c0,		0xffc0,		FMT_D0, {DM, MEM2(DI, AN)}},
{ "movhu",	0x030000,	0xf30000,	FMT_S2, {DM, MEM(ABS16)}},
{ "movhu",	0xfc830000,	0xfff30000,	FMT_D4, {DM, MEM(ABS32)}},

{ "ext",	0xf2d0,		0xfffc,		FMT_D0, {DN}},
{ "extb",	0x10, 		0xfc,		FMT_S0, {DN}},
{ "extbu",	0x14,		0xfc,		FMT_S0, {DN}},
{ "exth",	0x18,		0xfc,		FMT_S0, {DN}},
{ "exthu",	0x1c,		0xfc,		FMT_S0, {DN}},

{ "movm",	0xce00,		0xff00,		FMT_S1, {MEM(SP), IMM8}},
{ "movm",	0xcf00,		0xff00,		FMT_S1, {IMM8, MEM(SP)}},

{ "clr",	0x00,		0xf3,		FMT_S0, {DN}},

{ "add",	0xe0,		0xf0,		FMT_S0, {DM, DN}},
{ "add",	0xf160,		0xfff0,		FMT_D0, {DM, AN}},
{ "add",	0xf150,		0xfff0,		FMT_D0, {AM, DN}},
{ "add",	0xf170,		0xfff0,		FMT_D0, {AM, AN}},
{ "add",	0x2800,		0xfc00,		FMT_S1, {SIMM8, DN}},
{ "add",	0xfac00000,	0xfffc0000,	FMT_D2, {SIMM16, DN}},
{ "add",	0xfcc00000,	0xfffc0000,	FMT_D4, {IMM32, DN}},
{ "add",	0x2000,		0xfc00,		FMT_S1, {SIMM8, AN}},
{ "add",	0xfad00000,	0xfffc0000,	FMT_D2, {SIMM16, AN}},
{ "add",	0xfcd00000,	0xfffc0000,	FMT_D4, {IMM32, AN}},
{ "add",	0xf8fe00,	0xffff00,	FMT_D1, {SIMM8, SP}},
{ "add",	0xfafe0000,	0xfffc0000,	FMT_D2, {SIMM16, SP}},
{ "add",	0xfcfe0000,	0xfff0000,	FMT_D4, {IMM32, SP}},
{ "addc",	0xf140,		0xfff0,		FMT_D0, {DM, DN}},

{ "sub",	0xf100,		0xfff0,		FMT_D0, {DM, DN}},
{ "sub",	0xf120,		0xfff0,		FMT_D0, {DM, AN}},
{ "sub",	0xf110,		0xfff0,		FMT_D0, {AM, DN}},
{ "sub",	0xf130,		0xfff0,		FMT_D0, {AM, AN}},
{ "sub",	0xfcc40000,	0xfffc0000,	FMT_D4, {IMM32, DN}},
{ "sub",	0xfcd40000,	0xfffc0000,	FMT_D4, {IMM32, AN}},
{ "subc",	0xf180,		0xfff0,		FMT_D0, {DM, DN}},

{ "mul",	0xf240,		0xfff0,		FMT_D0, {DM, DN}},
{ "mulu",	0xf250,		0xfff0,		FMT_D0, {DM, DN}},

{ "div",	0xf260,		0xfff0,		FMT_D0, {DM, DN}},
{ "divu",	0xf270,		0xfff0,		FMT_D0, {DM, DN}},

{ "inc",	0x40,		0xf3,		FMT_S0, {DN}},
{ "inc",	0x41,		0xf3,		FMT_S0, {AN}},
{ "inc4",	0x50,		0xfc,		FMT_S0, {AN}},

{ "cmp",	0xa000,		0xf000,		FMT_S1, {SIMM8, DN}},
{ "cmp",	0xa0,		0xf0,		FMT_S0, {DM, DN}},
{ "cmp",	0xf1a0,		0xfff0,		FMT_D0, {DM, AN}},
{ "cmp",	0xf190,		0xfff0,		FMT_D0, {AM, DN}},
{ "cmp",	0xb000,		0xf000,		FMT_S1, {IMM8, AN}},
{ "cmp",	0xb0,		0xf0,		FMT_S0, {AM, AN}},
{ "cmp",	0xfac80000,	0xfffc0000,	FMT_D2, {SIMM16, DN}},
{ "cmp",	0xfcc80000,	0xfffc0000,	FMT_D4, {IMM32, DN}},
{ "cmp",	0xfad80000,	0xfffc0000,	FMT_D2, {IMM16, AN}},
{ "cmp",	0xfcd80000,	0xfffc0000,	FMT_D4, {IMM32, AN}},

{ "and",	0xf200,		0xfff0,		FMT_D0, {DM, DN}},
{ "and",	0xf8e000,	0xfffc00,	FMT_D1, {IMM8, DN}},
{ "and",	0xfae00000,	0xfffc0000,	FMT_D2, {IMM16, DN}},
{ "and",	0xfce00000,	0xfffc0000,	FMT_D4, {IMM32, DN}},
{ "and",	0xfafc0000,	0xfffc0000,	FMT_D2, {IMM16, PSW}},
{ "or",		0xf210,		0xfff0,		FMT_D0, {DM, DN}},
{ "or",		0xf8e400,	0xfffc00,	FMT_D1, {IMM8, DN}},
{ "or",		0xfae40000,	0xfffc0000,	FMT_D2, {IMM16, DN}},
{ "or",		0xfce40000,	0xfffc0000,	FMT_D4, {IMM32, DN}},
{ "or",		0xfafd0000,	0xfffc0000,	FMT_D2, {IMM16, PSW}},
{ "xor",	0xf220,		0xfff0,		FMT_D0, {DM, DN}},
{ "xor",	0xfae80000,	0xfffc0000,	FMT_D2, {IMM16, DN}},
{ "xor",	0xfce80000,	0xfffc0000,	FMT_D4, {IMM32, DN}},
{ "not",	0xf230,		0xfffc,		FMT_D0, {DN}},

{ "btst",	0xf8ec00,	0xfffc00,	FMT_D1, {IMM8, DN}},
{ "btst",	0xfaec0000,	0xfffc0000,	FMT_D2, {IMM16, DN}},
{ "btst",	0xfcec0000,	0xfffc0000,	FMT_D4, {IMM32, DN}},
{ "btst",	0xfe020000,	0xffff0000,	FMT_D5, {IMM8, MEM(ABS32)}},
{ "btst",	0xfaf80000,	0xfffc0000,	FMT_D2, {IMM8, MEM2(SD8N, AN)}},
{ "bset",	0xf080,		0xfff0,		FMT_D0, {DM, MEM(AN)}},
{ "bset",	0xfe000000,	0xffff0000,	FMT_D5, {IMM8, MEM(ABS32)}},
{ "bset",	0xfaf00000,	0xfffc0000,	FMT_D2, {IMM8, MEM2(SD8N, AN)}},
{ "bclr",	0xf090,		0xfff0,		FMT_D0, {DM, MEM(AN)}},
{ "bclr",	0xfe010000,	0xffff0000,	FMT_D5, {IMM8, MEM(ABS32)}},
{ "bclr",	0xfaf40000,	0xfffc0000,	FMT_D2, {IMM8, MEM2(SD8N, AN)}},

{ "asr",	0xf2b0,		0xfff0,		FMT_D0, {DM, DN}},
{ "asr",	0xf8c800,	0xfffc00,	FMT_D1, {IMM8, DN}},
{ "lsr",	0xf2a0,		0xfff0,		FMT_D0, {DM, DN}},
{ "lsr",	0xf8c400,	0xfffc00,	FMT_D1, {IMM8, DN}},
{ "asl",	0xf290,		0xfff0,		FMT_D0, {DM, DN}},
{ "asl",	0xf8c000,	0xfffc00,	FMT_D1, {IMM8, DN}},
{ "asl2",	0x54,		0xfc,		FMT_S0, {DN}},
{ "ror",	0xf284,		0xfffc,		FMT_D0, {DN}},
{ "rol",	0xf280,		0xfffc,		FMT_D0, {DN}},

{ "beq",	0xc800,		0xff00,		FMT_S1, {SD8N}},
{ "bne",	0xc900,		0xff00,		FMT_S1, {SD8N}},
{ "bgt",	0xc100,		0xff00,		FMT_S1, {SD8N}},
{ "bge",	0xc200,		0xff00,		FMT_S1, {SD8N}},
{ "ble",	0xc300,		0xff00,		FMT_S1, {SD8N}},
{ "blt",	0xc000,		0xff00,		FMT_S1, {SD8N}},
{ "bhi",	0xc500,		0xff00,		FMT_S1, {SD8N}},
{ "bcc",	0xc600,		0xff00,		FMT_S1, {SD8N}},
{ "bls",	0xc700,		0xff00,		FMT_S1, {SD8N}},
{ "bcs",	0xc400,		0xff00,		FMT_S1, {SD8N}},
{ "bvc",	0xf8e800,	0xffff00,	FMT_D1, {SD8N}},
{ "bvs",	0xf8e900,	0xffff00,	FMT_D1, {SD8N}},
{ "bnc",	0xf8ea00,	0xffff00,	FMT_D1, {SD8N}},
{ "bns",	0xf8eb00,	0xffff00,	FMT_D1, {SD8N}},
{ "bra",	0xca00,		0xff00,		FMT_S1, {SD8N}},

{ "leq",	0xd8,		0xff,		FMT_S0, {UNUSED}},
{ "lne",	0xd9,		0xff,		FMT_S0, {UNUSED}},
{ "lgt",	0xd1,		0xff,		FMT_S0, {UNUSED}},
{ "lge",	0xd2,		0xff,		FMT_S0, {UNUSED}},
{ "lle",	0xd3,		0xff,		FMT_S0, {UNUSED}},
{ "llt",	0xd0,		0xff,		FMT_S0, {UNUSED}},
{ "lhi",	0xd5,		0xff,		FMT_S0, {UNUSED}},
{ "lcc",	0xd6,		0xff,		FMT_S0, {UNUSED}},
{ "lls",	0xd7,		0xff,		FMT_S0, {UNUSED}},
{ "lcs",	0xd4,		0xff,		FMT_S0, {UNUSED}},
{ "lra",	0xda,		0xff,		FMT_S0, {UNUSED}},
{ "lcc",	0xd6,		0xff,		FMT_S0, {UNUSED}},
{ "setlb",	0xdb,		0xff,	 	FMT_S0, {UNUSED}},

{ "jmp",	0xf0f4,		0xfffc,		FMT_D0, {AN}},
{ "jmp",	0xcc0000,	0xff0000,	FMT_S2, {D16}},
{ "jmp",	0xdc0000,	0xff0000,	FMT_S4, {D32}},
{ "call",	0xcd000000,	0xff000000,	FMT_S4, {D16,IMM8,IMM8}},
{ "call",	0xdd000000,	0xff000000,	FMT_S6, {D32,IMM8,IMM8}},
{ "calls",	0xf0f0,		0xfffc,		FMT_D0, {AN}},
{ "calls",	0xfaff0000,	0xffff0000,	FMT_D2, {D16}},
{ "calls",	0xfcff0000,	0xffff0000,	FMT_D4, {D32}},

{ "ret",	0xdf0000,	0xff00000,	FMT_S2, {IMM8, IMM8}},
{ "retf",	0xde0000,	0xff00000,	FMT_S2, {IMM8, IMM8}},
{ "rets",	0xf0fc,		0xffff,		FMT_D0, {UNUSED}},
{ "rti",	0xf0fd,		0xffff,		FMT_D0, {UNUSED}},
{ "trap",	0xf0fe,		0xffff,		FMT_D0, {UNUSED}},
{ "rtm",	0xf0ff,		0xffff,		FMT_D0, {UNUSED}},
{ "nop",	0xcb,		0xff,		FMT_S0, {UNUSED}},
/* { "udf", 0, 0, {0}},  */

{ "putx",	0xf500,		0xfff0,		FMT_D0, {DM}},
{ "getx",	0xf6f0,		0xfff0,		FMT_D0, {DN}},
{ "mulq",	0xf600,		0xfff0,		FMT_D0, {DM, DN}},
{ "mulq",	0xf90000,	0xfffc00,	FMT_D1, {SIMM8, DN}},
{ "mulq",	0xfb000000,	0xfffc0000,	FMT_D2, {SIMM16, DN}},
{ "mulq",	0xfd000000,	0xfffc0000,	FMT_D4, {IMM32, DN}},
{ "mulqu",	0xf610,		0xfff0,		FMT_D0, {DM, DN}},
{ "mulqu",	0xf90400,	0xfffc00,	FMT_D1, {SIMM8, DN}},
{ "mulqu",	0xfb040000,	0xfffc0000,	FMT_D2, {SIMM16, DN}},
{ "mulqu",	0xfd040000,	0xfffc0000,	FMT_D4, {IMM32, DN}},
{ "sat16",	0xf640,		0xfff0,		FMT_D0, {DM, DN}},
{ "sat24",	0xf650,		0xfff0,		FMT_D0, {DM, DN}},
{ "bsch",	0xf670,		0xfff0,		FMT_D0, {DM, DN}},
{ 0, 0, 0, 0, {0}},

} ;

const int mn10300_num_opcodes =
  sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);

\f
Commit	Line	Data
ae1b99e4	1	/* Assemble Matsushita MN10300 instructions.
e7c50cef JL	2	Copyright (C) 1996 Free Software Foundation, Inc.
	3
	4	This program is free software; you can redistribute it and/or modify
	5	it under the terms of the GNU General Public License as published by
	6	the Free Software Foundation; either version 2 of the License, or
	7	(at your option) any later version.
	8
	9	This program is distributed in the hope that it will be useful,
	10	but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	GNU General Public License for more details.
	13
	14	You should have received a copy of the GNU General Public License
	15	along with this program; if not, write to the Free Software
	16	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	17
	18	#include "ansidecl.h"
ae1b99e4	19	#include "opcode/mn10300.h"
e7c50cef	20
99777c0b JL	21	/* Formats. Right now we don't use this. We probably will later for
99777c0b JL	22	the size of the instruction and other random stuff. */
5ab7bce6 JL	23	#define FMT_S0 1
	24	#define FMT_S1 2
	25	#define FMT_S2 3
	26	#define FMT_S4 4
	27	#define FMT_S6 5
	28	#define FMT_D0 6
	29	#define FMT_D1 7
	30	#define FMT_D2 8
	31	#define FMT_D4 9
	32	#define FMT_D5 10
99777c0b JL	33
99777c0b JL	34	/* Operands currently used. This is temporary. */
99777c0b	35
e7c50cef	36	\f
ae1b99e4	37	const struct mn10300_operand mn10300_operands[] = {
e7c50cef	38	#define UNUSED 0
5ab7bce6 JL	39	{0, 0, 0},
	40
	41	#define DN (UNUSED+1)
	42	{2, 0, MN10300_OPERAND_DREG},
	43
	44	#define DM (DN+1)
	45	{2, 0, MN10300_OPERAND_DREG},
	46
	47	#define AN (DM+1)
	48	{2, 0, MN10300_OPERAND_AREG},
	49
	50	#define AM (AN+1)
	51	{2, 0, MN10300_OPERAND_AREG},
	52
	53	#define IMM8 (AM+1)
	54	{8, 0, MN10300_OPERAND_PROMOTE},
	55
	56	#define IMM16 (IMM8+1)
	57	{16, 0, MN10300_OPERAND_PROMOTE},
	58
	59	#define IMM32 (IMM16+1)
	60	{32, 0, 0},
	61
	62	#define D8 (IMM32+1)
	63	{8, 0, MN10300_OPERAND_PROMOTE},
	64
	65	#define D16 (D8+1)
	66	{16, 0, MN10300_OPERAND_PROMOTE},
	67
	68	#define D32 (D16+1)
	69	{32, 0, 0},
	70
	71	#define SP (D32+1)
	72	{8, 0, MN10300_OPERAND_SP},
	73
	74	#define PSW (SP+1)
	75	{0, 0, MN10300_OPERAND_PSW},
	76
	77	#define MDR (PSW+1)
	78	{0, 0, MN10300_OPERAND_MDR},
	79
	80	#define ABS16 (MDR+1)
	81	{16, 0, MN10300_OPERAND_PROMOTE},
	82
	83	#define ABS32 (ABS16+1)
	84	{32, 0, 0},
	85
	86	#define DI (ABS32+1)
	87	{2, 0, MN10300_OPERAND_DREG},
	88
db229054	89	#define SD8 (DI+1)
5ab7bce6 JL	90	{8, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
	91
	92	#define SD16 (SD8+1)
	93	{16, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
	94
	95	#define SD8N (SD16+1)
	96	{8, 0, MN10300_OPERAND_SIGNED},
	97
	98	#define SIMM8 (SD8N+1)
	99	{8, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
	100
	101	#define SIMM16 (SIMM8+1)
	102	{16, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
db229054 JL	103
	104	#define PAREN (SIMM16+1)
	105	{0, 0, MN10300_OPERAND_PAREN},
e7c50cef JL	106	} ;
e7c50cef JL	107
db229054 JL	108	#define MEM(ADDR) PAREN, ADDR, PAREN
db229054 JL	109	#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
e7c50cef JL	110	\f
	111	/* The opcode table.
	112
	113	The format of the opcode table is:
	114
	115	NAME OPCODE MASK { OPERANDS }
	116
	117	NAME is the name of the instruction.
	118	OPCODE is the instruction opcode.
	119	MASK is the opcode mask; this is used to tell the disassembler
	120	which bits in the actual opcode must match OPCODE.
	121	OPERANDS is the list of operands.
	122
	123	The disassembler reads the table in order and prints the first
	124	instruction which matches, so this table is sorted to put more
	125	specific instructions before more general instructions. It is also
	126	sorted by major opcode. */
	127
ae1b99e4	128	const struct mn10300_opcode mn10300_opcodes[] = {
db229054 JL	129	{ "mov", 0x8000, 0xf000, FMT_S1, {SIMM8, DN}},
	130	{ "mov", 0x80, 0xf0, FMT_S0, {DM, DN}},
	131	{ "mov", 0xf1e0, 0xfff0, FMT_D0, {DM, AN}},
	132	{ "mov", 0xf1d0, 0xfff0, FMT_D0, {AM, DN}},
	133	{ "mov", 0x9000, 0xf000, FMT_S1, {IMM8, AN}},
	134	{ "mov", 0x90, 0xf0, FMT_S0, {AM, AN}},
	135	{ "mov", 0x3c, 0xfc, FMT_S0, {SP, AN}},
	136	{ "mov", 0xf2f0, 0xfff3, FMT_D0, {AM, SP}},
	137	{ "mov", 0xf2e4, 0xfffc, FMT_D0, {PSW, DN}},
	138	{ "mov", 0xf2f3, 0xfff3, FMT_D0, {DM, PSW}},
	139	{ "mov", 0xf2e0, 0xfffc, FMT_D0, {MDR, DN}},
	140	{ "mov", 0xf2f2, 0xfff3, FMT_D0, {DM, MDR}},
	141	{ "mov", 0x70, 0xf0, FMT_S0, {MEM(AM), DN}},
	142	{ "mov", 0xf80000, 0xfff000, FMT_D1, {MEM2(SD8, AM), DN}},
	143	{ "mov", 0xfa000000, 0xfff00000, FMT_D2, {MEM2(SD16, AM), DN}},
	144	{ "mov", 0xfc000000, 0xfff00000, FMT_D4, {MEM2(D32, AM), DN}},
	145	{ "mov", 0x5800, 0xfc00, FMT_S1, {MEM2(D8, SP), DN}},
	146	{ "mov", 0xfab40000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), DN}},
	147	{ "mov", 0xfcb40000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), DN}},
	148	{ "mov", 0xf300, 0xffc0, FMT_D0, {MEM2(DI, AM), DN}},
	149	{ "mov", 0x300000, 0xfc0000, FMT_S2, {MEM(ABS16), DN}},
	150	{ "mov", 0xfca40000, 0xfffc0000, FMT_D4, {MEM(ABS32), DN}},
	151	{ "mov", 0xf000, 0xfff0, FMT_D0, {MEM(AM), AN}},
	152	{ "mov", 0xf82000, 0xfff000, FMT_D1, {MEM2(D8, AM), AN}},
	153	{ "mov", 0xfa200000, 0xfff00000, FMT_D2, {MEM2(D16, AM), AN}},
	154	{ "mov", 0xfc200000, 0xfff00000, FMT_D4, {MEM2(D32, AM), AN}},
	155	{ "mov", 0x5c00, 0xfc00, FMT_S1, {MEM2(D8, SP), AN}},
	156	{ "mov", 0xfab00000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), AN}},
	157	{ "mov", 0xfcb00000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), AN}},
	158	{ "mov", 0xf380, 0xffc0, FMT_D0, {MEM2(DI, AM), AN}},
	159	{ "mov", 0xfaa00000, 0xfffc0000, FMT_D2, {MEM(ABS16), AN}},
	160	{ "mov", 0xfca00000, 0xfffc0000, FMT_D4, {MEM(ABS32), AN}},
	161	{ "mov", 0xf8f000, 0xfffc00, FMT_D1, {MEM2(SD8N, AM), SP}},
	162	{ "mov", 0x60, 0xf0, FMT_S0, {DM, MEM(AN)}},
	163	{ "mov", 0xf81000, 0xfff000, FMT_D1, {DM, MEM2(SD8, AN)}},
	164	{ "mov", 0xfa100000, 0xfff00000, FMT_D2, {DM, MEM2(SD16, AN)}},
	165	{ "mov", 0xfc100000, 0xfff00000, FMT_D4, {DM, MEM2(D32, AN)}},
	166	{ "mov", 0x4200, 0xf300, FMT_S1, {DM, MEM2(D8, SP)}},
	167	{ "mov", 0xfa910000, 0xfff30000, FMT_D2, {DM, MEM2(D16, SP)}},
	168	{ "mov", 0xfc910000, 0xfff30000, FMT_D4, {DM, MEM2(D32, SP)}},
	169	{ "mov", 0xf340, 0xffc0, FMT_D0, {DM, MEM2(DI, AN)}},
	170	{ "mov", 0x010000, 0xf30000, FMT_S2, {DM, MEM(ABS16)}},
	171	{ "mov", 0xfc810000, 0xfff30000, FMT_D4, {DM, MEM(ABS32)}},
	172	{ "mov", 0xf010, 0xfff0, FMT_D0, {AM, MEM(AN)}},
	173	{ "mov", 0xf83000, 0xfff000, FMT_D1, {AM, MEM2(SD8, AN)}},
	174	{ "mov", 0xfa300000, 0xfff00000, FMT_D2, {AM, MEM2(SD16, AN)}},
	175	{ "mov", 0xfc300000, 0xfff00000, FMT_D4, {AM, MEM2(D32, AN)}},
	176	{ "mov", 0x4300, 0xf300, FMT_S1, {AM, MEM2(D8, SP)}},
	177	{ "mov", 0xfa900000, 0xfff30000, FMT_D2, {AM, MEM2(D16, SP)}},
	178	{ "mov", 0xfc900000, 0xfc930000, FMT_D4, {AM, MEM2(D32, SP)}},
	179	{ "mov", 0xf3c0, 0xffc0, FMT_D0, {AM, MEM2(DI, AN)}},
	180	{ "mov", 0xfa800000, 0xfff30000, FMT_D2, {AM, MEM(ABS16)}},
	181	{ "mov", 0xfc800000, 0xfff30000, FMT_D4, {AM, MEM(ABS32)}},
	182	{ "mov", 0xf8f400, 0xfffc00, FMT_D1, {SP, MEM2(SD8N, AN)}},
	183	{ "mov", 0x2c0000, 0xfc0000, FMT_S2, {SIMM16, DN}},
	184	{ "mov", 0xfcdc0000, 0xfffc0000, FMT_D4, {IMM32, DN}},
	185	{ "mov", 0x240000, 0xfc0000, FMT_S2, {IMM16, AN}},
	186	{ "mov", 0xfcdc0000, 0xfffc0000, FMT_D4, {IMM32, AN}},
	187
	188	{ "movbu", 0xf040, 0xfff0, FMT_D0, {MEM(AM), DN}},
	189	{ "movbu", 0xf84000, 0xfff000, FMT_D1, {MEM2(SD8, AM), DN}},
	190	{ "movbu", 0xfa400000, 0xfff00000, FMT_D2, {MEM2(SD16, AM), DN}},
	191	{ "movbu", 0xfc400000, 0xfff00000, FMT_D4, {MEM2(D32, AM), DN}},
	192	{ "movbu", 0xf8b800, 0xfffc00, FMT_D1, {MEM2(D8, SP), DN}},
193	{ "movbu", 0xfab80000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), DN}},
194	{ "movbu", 0xfcb80000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), DN}},
195	{ "movbu", 0xf400, 0xffc0, FMT_D0, {MEM2(DI, AM), DN}},
196	{ "movbu", 0x340000, 0xfc0000, FMT_S2, {MEM(ABS16), DN}},
197	{ "movbu", 0xfca80000, 0xfffc0000, FMT_D4, {MEM(ABS32), DN}},
198	{ "movbu", 0xf050, 0xfff0, FMT_D0, {DM, MEM(AN)}},
199	{ "movbu", 0xf85000, 0xfff000, FMT_D1, {DM, MEM2(SD8, AN)}},
200	{ "movbu", 0xfa500000, 0xfff00000, FMT_D2, {DM, MEM2(SD16, AN)}},
201	{ "movbu", 0xfc500000, 0xfff00000, FMT_D4, {DM, MEM2(D32, AN)}},
202	{ "movbu", 0xf89200, 0xfff300, FMT_D1, {DM, MEM2(D8, SP)}},
203	{ "movbu", 0xfa920000, 0xfff30000, FMT_D2, {DM, MEM2(D16, SP)}},
204	{ "movbu", 0xfc920000, 0xfff30000, FMT_D4, {DM, MEM2(D32, SP)}},
205	{ "movbu", 0xf440, 0xffc0, FMT_D0, {DM, MEM2(DI, AN)}},
206	{ "movbu", 0x020000, 0xf30000, FMT_S2, {DM, MEM(ABS16)}},
207	{ "movbu", 0xfc820000, 0xfff30000, FMT_D4, {DM, MEM(ABS32)}},
208
209	{ "movhu", 0xf060, 0xfff0, FMT_D0, {MEM(AM), DN}},
210	{ "movhu", 0xf86000, 0xfff000, FMT_D1, {MEM2(SD8, AM), DN}},
211	{ "movhu", 0xfa600000, 0xfff00000, FMT_D2, {MEM2(SD16, AM), DN}},
212	{ "movhu", 0xfc600000, 0xfff00000, FMT_D4, {MEM2(D32, AM), DN}},
213	{ "movhu", 0xf8bc00, 0xfffc00, FMT_D1, {MEM2(D8, SP), DN}},
214	{ "movhu", 0xfabc0000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), DN}},
215	{ "movhu", 0xfcbc0000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), DN}},
216	{ "movhu", 0xf480, 0xffc0, FMT_D0, {MEM2(DI, AM), DN}},
217	{ "movhu", 0xc80000, 0xfc0000, FMT_S2, {MEM(ABS16), DN}},
218	{ "movhu", 0xfcac0000, 0xfffc0000, FMT_D4, {MEM(ABS32), DN}},
219	{ "movhu", 0xf070, 0xfff0, FMT_D0, {DM, MEM(AN)}},
220	{ "movhu", 0xf87000, 0xfff000, FMT_D1, {DM, MEM2(SD8, AN)}},
221	{ "movhu", 0xfa700000, 0xfff00000, FMT_D2, {DM, MEM2(SD16, AN)}},
222	{ "movhu", 0xfc700000, 0xfff00000, FMT_D4, {DM, MEM2(D32, AN)}},
223	{ "movhu", 0xf89300, 0xfff300, FMT_D1, {DM, MEM2(D8, SP)}},
224	{ "movhu", 0xfa930000, 0xfff30000, FMT_D2, {DM, MEM2(D16, SP)}},
225	{ "movhu", 0xfc930000, 0xfff30000, FMT_D4, {DM, MEM2(D32, SP)}},
226	{ "movhu", 0xf4c0, 0xffc0, FMT_D0, {DM, MEM2(DI, AN)}},
227	{ "movhu", 0x030000, 0xf30000, FMT_S2, {DM, MEM(ABS16)}},
228	{ "movhu", 0xfc830000, 0xfff30000, FMT_D4, {DM, MEM(ABS32)}},
229
230	{ "ext", 0xf2d0, 0xfffc, FMT_D0, {DN}},
231	{ "extb", 0x10, 0xfc, FMT_S0, {DN}},
232	{ "extbu", 0x14, 0xfc, FMT_S0, {DN}},
233	{ "exth", 0x18, 0xfc, FMT_S0, {DN}},
234	{ "exthu", 0x1c, 0xfc, FMT_S0, {DN}},
235
236	{ "movm", 0xce00, 0xff00, FMT_S1, {MEM(SP), IMM8}},
237	{ "movm", 0xcf00, 0xff00, FMT_S1, {IMM8, MEM(SP)}},
238
239	{ "clr", 0x00, 0xf3, FMT_S0, {DN}},
240
241	{ "add", 0xe0, 0xf0, FMT_S0, {DM, DN}},
242	{ "add", 0xf160, 0xfff0, FMT_D0, {DM, AN}},
243	{ "add", 0xf150, 0xfff0, FMT_D0, {AM, DN}},
244	{ "add", 0xf170, 0xfff0, FMT_D0, {AM, AN}},
245	{ "add", 0x2800, 0xfc00, FMT_S1, {SIMM8, DN}},
246	{ "add", 0xfac00000, 0xfffc0000, FMT_D2, {SIMM16, DN}},
247	{ "add", 0xfcc00000, 0xfffc0000, FMT_D4, {IMM32, DN}},
248	{ "add", 0x2000, 0xfc00, FMT_S1, {SIMM8, AN}},
249	{ "add", 0xfad00000, 0xfffc0000, FMT_D2, {SIMM16, AN}},
250	{ "add", 0xfcd00000, 0xfffc0000, FMT_D4, {IMM32, AN}},
251	{ "add", 0xf8fe00, 0xffff00, FMT_D1, {SIMM8, SP}},
252	{ "add", 0xfafe0000, 0xfffc0000, FMT_D2, {SIMM16, SP}},
253	{ "add", 0xfcfe0000, 0xfff0000, FMT_D4, {IMM32, SP}},
254	{ "addc", 0xf140, 0xfff0, FMT_D0, {DM, DN}},
255
256	{ "sub", 0xf100, 0xfff0, FMT_D0, {DM, DN}},
257	{ "sub", 0xf120, 0xfff0, FMT_D0, {DM, AN}},
258	{ "sub", 0xf110, 0xfff0, FMT_D0, {AM, DN}},
259	{ "sub", 0xf130, 0xfff0, FMT_D0, {AM, AN}},
260	{ "sub", 0xfcc40000, 0xfffc0000, FMT_D4, {IMM32, DN}},
261	{ "sub", 0xfcd40000, 0xfffc0000, FMT_D4, {IMM32, AN}},
262	{ "subc", 0xf180, 0xfff0, FMT_D0, {DM, DN}},
263
264	{ "mul", 0xf240, 0xfff0, FMT_D0, {DM, DN}},
265	{ "mulu", 0xf250, 0xfff0, FMT_D0, {DM, DN}},
266
267	{ "div", 0xf260, 0xfff0, FMT_D0, {DM, DN}},
268	{ "divu", 0xf270, 0xfff0, FMT_D0, {DM, DN}},
269
270	{ "inc", 0x40, 0xf3, FMT_S0, {DN}},
271	{ "inc", 0x41, 0xf3, FMT_S0, {AN}},
272	{ "inc4", 0x50, 0xfc, FMT_S0, {AN}},
273
274	{ "cmp", 0xa000, 0xf000, FMT_S1, {SIMM8, DN}},
275	{ "cmp", 0xa0, 0xf0, FMT_S0, {DM, DN}},
276	{ "cmp", 0xf1a0, 0xfff0, FMT_D0, {DM, AN}},
277	{ "cmp", 0xf190, 0xfff0, FMT_D0, {AM, DN}},
278	{ "cmp", 0xb000, 0xf000, FMT_S1, {IMM8, AN}},
279	{ "cmp", 0xb0, 0xf0, FMT_S0, {AM, AN}},
280	{ "cmp", 0xfac80000, 0xfffc0000, FMT_D2, {SIMM16, DN}},
281	{ "cmp", 0xfcc80000, 0xfffc0000, FMT_D4, {IMM32, DN}},
282	{ "cmp", 0xfad80000, 0xfffc0000, FMT_D2, {IMM16, AN}},
283	{ "cmp", 0xfcd80000, 0xfffc0000, FMT_D4, {IMM32, AN}},
284
285	{ "and", 0xf200, 0xfff0, FMT_D0, {DM, DN}},
286	{ "and", 0xf8e000, 0xfffc00, FMT_D1, {IMM8, DN}},
287	{ "and", 0xfae00000, 0xfffc0000, FMT_D2, {IMM16, DN}},
288	{ "and", 0xfce00000, 0xfffc0000, FMT_D4, {IMM32, DN}},
289	{ "and", 0xfafc0000, 0xfffc0000, FMT_D2, {IMM16, PSW}},
290	{ "or", 0xf210, 0xfff0, FMT_D0, {DM, DN}},
291	{ "or", 0xf8e400, 0xfffc00, FMT_D1, {IMM8, DN}},
292	{ "or", 0xfae40000, 0xfffc0000, FMT_D2, {IMM16, DN}},
293	{ "or", 0xfce40000, 0xfffc0000, FMT_D4, {IMM32, DN}},
294	{ "or", 0xfafd0000, 0xfffc0000, FMT_D2, {IMM16, PSW}},
295	{ "xor", 0xf220, 0xfff0, FMT_D0, {DM, DN}},
296	{ "xor", 0xfae80000, 0xfffc0000, FMT_D2, {IMM16, DN}},
297	{ "xor", 0xfce80000, 0xfffc0000, FMT_D4, {IMM32, DN}},
298	{ "not", 0xf230, 0xfffc, FMT_D0, {DN}},
299
300	{ "btst", 0xf8ec00, 0xfffc00, FMT_D1, {IMM8, DN}},
301	{ "btst", 0xfaec0000, 0xfffc0000, FMT_D2, {IMM16, DN}},
302	{ "btst", 0xfcec0000, 0xfffc0000, FMT_D4, {IMM32, DN}},
303	{ "btst", 0xfe020000, 0xffff0000, FMT_D5, {IMM8, MEM(ABS32)}},
304	{ "btst", 0xfaf80000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N, AN)}},
305	{ "bset", 0xf080, 0xfff0, FMT_D0, {DM, MEM(AN)}},
306	{ "bset", 0xfe000000, 0xffff0000, FMT_D5, {IMM8, MEM(ABS32)}},
307	{ "bset", 0xfaf00000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N, AN)}},
308	{ "bclr", 0xf090, 0xfff0, FMT_D0, {DM, MEM(AN)}},
309	{ "bclr", 0xfe010000, 0xffff0000, FMT_D5, {IMM8, MEM(ABS32)}},
310	{ "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N, AN)}},
311
312	{ "asr", 0xf2b0, 0xfff0, FMT_D0, {DM, DN}},
313	{ "asr", 0xf8c800, 0xfffc00, FMT_D1, {IMM8, DN}},
314	{ "lsr", 0xf2a0, 0xfff0, FMT_D0, {DM, DN}},
315	{ "lsr", 0xf8c400, 0xfffc00, FMT_D1, {IMM8, DN}},
316	{ "asl", 0xf290, 0xfff0, FMT_D0, {DM, DN}},
317	{ "asl", 0xf8c000, 0xfffc00, FMT_D1, {IMM8, DN}},
318	{ "asl2", 0x54, 0xfc, FMT_S0, {DN}},
319	{ "ror", 0xf284, 0xfffc, FMT_D0, {DN}},
320	{ "rol", 0xf280, 0xfffc, FMT_D0, {DN}},
321
322	{ "beq", 0xc800, 0xff00, FMT_S1, {SD8N}},
323	{ "bne", 0xc900, 0xff00, FMT_S1, {SD8N}},
324	{ "bgt", 0xc100, 0xff00, FMT_S1, {SD8N}},
325	{ "bge", 0xc200, 0xff00, FMT_S1, {SD8N}},
326	{ "ble", 0xc300, 0xff00, FMT_S1, {SD8N}},
327	{ "blt", 0xc000, 0xff00, FMT_S1, {SD8N}},
328	{ "bhi", 0xc500, 0xff00, FMT_S1, {SD8N}},
329	{ "bcc", 0xc600, 0xff00, FMT_S1, {SD8N}},
330	{ "bls", 0xc700, 0xff00, FMT_S1, {SD8N}},
331	{ "bcs", 0xc400, 0xff00, FMT_S1, {SD8N}},
332	{ "bvc", 0xf8e800, 0xffff00, FMT_D1, {SD8N}},
333	{ "bvs", 0xf8e900, 0xffff00, FMT_D1, {SD8N}},
334	{ "bnc", 0xf8ea00, 0xffff00, FMT_D1, {SD8N}},
335	{ "bns", 0xf8eb00, 0xffff00, FMT_D1, {SD8N}},
336	{ "bra", 0xca00, 0xff00, FMT_S1, {SD8N}},
337
338	{ "leq", 0xd8, 0xff, FMT_S0, {UNUSED}},
339	{ "lne", 0xd9, 0xff, FMT_S0, {UNUSED}},
340	{ "lgt", 0xd1, 0xff, FMT_S0, {UNUSED}},
341	{ "lge", 0xd2, 0xff, FMT_S0, {UNUSED}},
342	{ "lle", 0xd3, 0xff, FMT_S0, {UNUSED}},
343	{ "llt", 0xd0, 0xff, FMT_S0, {UNUSED}},
344	{ "lhi", 0xd5, 0xff, FMT_S0, {UNUSED}},
345	{ "lcc", 0xd6, 0xff, FMT_S0, {UNUSED}},
346	{ "lls", 0xd7, 0xff, FMT_S0, {UNUSED}},
347	{ "lcs", 0xd4, 0xff, FMT_S0, {UNUSED}},
348	{ "lra", 0xda, 0xff, FMT_S0, {UNUSED}},
349	{ "lcc", 0xd6, 0xff, FMT_S0, {UNUSED}},
350	{ "setlb", 0xdb, 0xff, FMT_S0, {UNUSED}},
351
352	{ "jmp", 0xf0f4, 0xfffc, FMT_D0, {AN}},
353	{ "jmp", 0xcc0000, 0xff0000, FMT_S2, {D16}},
354	{ "jmp", 0xdc0000, 0xff0000, FMT_S4, {D32}},
355	{ "call", 0xcd000000, 0xff000000, FMT_S4, {D16,IMM8,IMM8}},
356	{ "call", 0xdd000000, 0xff000000, FMT_S6, {D32,IMM8,IMM8}},
357	{ "calls", 0xf0f0, 0xfffc, FMT_D0, {AN}},
358	{ "calls", 0xfaff0000, 0xffff0000, FMT_D2, {D16}},
359	{ "calls", 0xfcff0000, 0xffff0000, FMT_D4, {D32}},
360
361	{ "ret", 0xdf0000, 0xff00000, FMT_S2, {IMM8, IMM8}},
362	{ "retf", 0xde0000, 0xff00000, FMT_S2, {IMM8, IMM8}},
363	{ "rets", 0xf0fc, 0xffff, FMT_D0, {UNUSED}},
364	{ "rti", 0xf0fd, 0xffff, FMT_D0, {UNUSED}},
365	{ "trap", 0xf0fe, 0xffff, FMT_D0, {UNUSED}},
366	{ "rtm", 0xf0ff, 0xffff, FMT_D0, {UNUSED}},
367	{ "nop", 0xcb, 0xff, FMT_S0, {UNUSED}},
368	/* { "udf", 0, 0, {0}}, */
344d6417 JL	369
	370	{ "putx", 0xf500, 0xfff0, FMT_D0, {DM}},
	371	{ "getx", 0xf6f0, 0xfff0, FMT_D0, {DN}},
	372	{ "mulq", 0xf600, 0xfff0, FMT_D0, {DM, DN}},
	373	{ "mulq", 0xf90000, 0xfffc00, FMT_D1, {SIMM8, DN}},
	374	{ "mulq", 0xfb000000, 0xfffc0000, FMT_D2, {SIMM16, DN}},
	375	{ "mulq", 0xfd000000, 0xfffc0000, FMT_D4, {IMM32, DN}},
	376	{ "mulqu", 0xf610, 0xfff0, FMT_D0, {DM, DN}},
	377	{ "mulqu", 0xf90400, 0xfffc00, FMT_D1, {SIMM8, DN}},
	378	{ "mulqu", 0xfb040000, 0xfffc0000, FMT_D2, {SIMM16, DN}},
	379	{ "mulqu", 0xfd040000, 0xfffc0000, FMT_D4, {IMM32, DN}},
	380	{ "sat16", 0xf640, 0xfff0, FMT_D0, {DM, DN}},
	381	{ "sat24", 0xf650, 0xfff0, FMT_D0, {DM, DN}},
	382	{ "bsch", 0xf670, 0xfff0, FMT_D0, {DM, DN}},
db229054	383	{ 0, 0, 0, 0, {0}},
5ab7bce6	384
cd8a9026	385	} ;
e7c50cef	386
ae1b99e4 JL	387	const int mn10300_num_opcodes =
ae1b99e4 JL	388	sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
e7c50cef JL	389
e7c50cef JL	390	\f