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[binutils.git] / bfd / xtensa-modules.c
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e0001a05 1/* Xtensa configuration-specific ISA information.
aa820537 2 Copyright 2003, 2004, 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
e0001a05
NC		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
43cd72b9
BW		 6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License as
cd123cb7 8 published by the Free Software Foundation; either version 3 of the
43cd72b9 9 License, or (at your option) any later version.
e0001a05
NC		 10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
43cd72b9
BW		 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
e0001a05
NC		 15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
3e110533 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
53e09e0a 19 02110-1301, USA. */
e0001a05 20
43cd72b9 21#include "ansidecl.h"
e0001a05
NC		 22#include <xtensa-isa.h>
23#include "xtensa-isa-internal.h"
e0001a05 24
43cd72b9
BW		 25\f
26/* Sysregs. */
27
28static xtensa_sysreg_internal sysregs[] = {
29 { "LBEG", 0, 0 },
30 { "LEND", 1, 0 },
31 { "LCOUNT", 2, 0 },
074f5109 32 { "PTEVADDR", 83, 0 },
33430bd0 33 { "MMID", 89, 0 },
43cd72b9
BW		 34 { "DDR", 104, 0 },
35 { "176", 176, 0 },
36 { "208", 208, 0 },
37 { "INTERRUPT", 226, 0 },
38 { "INTCLEAR", 227, 0 },
39 { "CCOUNT", 234, 0 },
40 { "PRID", 235, 0 },
41 { "ICOUNT", 236, 0 },
42 { "CCOMPARE0", 240, 0 },
43 { "CCOMPARE1", 241, 0 },
44 { "CCOMPARE2", 242, 0 },
33430bd0 45 { "VECBASE", 231, 0 },
43cd72b9
BW		 46 { "EPC1", 177, 0 },
47 { "EPC2", 178, 0 },
48 { "EPC3", 179, 0 },
49 { "EPC4", 180, 0 },
33430bd0
BW		 50 { "EPC5", 181, 0 },
51 { "EPC6", 182, 0 },
52 { "EPC7", 183, 0 },
43cd72b9
BW		 53 { "EXCSAVE1", 209, 0 },
54 { "EXCSAVE2", 210, 0 },
55 { "EXCSAVE3", 211, 0 },
56 { "EXCSAVE4", 212, 0 },
33430bd0
BW		 57 { "EXCSAVE5", 213, 0 },
58 { "EXCSAVE6", 214, 0 },
59 { "EXCSAVE7", 215, 0 },
43cd72b9
BW		 60 { "EPS2", 194, 0 },
61 { "EPS3", 195, 0 },
62 { "EPS4", 196, 0 },
33430bd0
BW		 63 { "EPS5", 197, 0 },
64 { "EPS6", 198, 0 },
65 { "EPS7", 199, 0 },
43cd72b9
BW		 66 { "EXCCAUSE", 232, 0 },
67 { "DEPC", 192, 0 },
68 { "EXCVADDR", 238, 0 },
69 { "WINDOWBASE", 72, 0 },
70 { "WINDOWSTART", 73, 0 },
71 { "SAR", 3, 0 },
72 { "LITBASE", 5, 0 },
73 { "PS", 230, 0 },
74 { "MISC0", 244, 0 },
75 { "MISC1", 245, 0 },
76 { "INTENABLE", 228, 0 },
77 { "DBREAKA0", 144, 0 },
78 { "DBREAKC0", 160, 0 },
79 { "DBREAKA1", 145, 0 },
80 { "DBREAKC1", 161, 0 },
81 { "IBREAKA0", 128, 0 },
82 { "IBREAKA1", 129, 0 },
83 { "IBREAKENABLE", 96, 0 },
84 { "ICOUNTLEVEL", 237, 0 },
074f5109
BW		 85 { "DEBUGCAUSE", 233, 0 },
86 { "RASID", 90, 0 },
87 { "ITLBCFG", 91, 0 },
33430bd0
BW		 88 { "DTLBCFG", 92, 0 },
89 { "CPENABLE", 224, 0 },
90 { "SCOMPARE1", 12, 0 },
91 { "THREADPTR", 231, 1 }
43cd72b9
BW		 92};
93
33430bd0 94#define NUM_SYSREGS 63
43cd72b9 95#define MAX_SPECIAL_REG 245
33430bd0 96#define MAX_USER_REG 231
43cd72b9
BW		 97
98\f
99/* Processor states. */
100
101static xtensa_state_internal states[] = {
102 { "LCOUNT", 32, 0 },
103 { "PC", 32, 0 },
104 { "ICOUNT", 32, 0 },
105 { "DDR", 32, 0 },
33430bd0 106 { "INTERRUPT", 22, 0 },
43cd72b9
BW		 107 { "CCOUNT", 32, 0 },
108 { "XTSYNC", 1, 0 },
33430bd0 109 { "VECBASE", 22, 0 },
43cd72b9
BW		 110 { "EPC1", 32, 0 },
111 { "EPC2", 32, 0 },
112 { "EPC3", 32, 0 },
113 { "EPC4", 32, 0 },
33430bd0
BW		 114 { "EPC5", 32, 0 },
115 { "EPC6", 32, 0 },
116 { "EPC7", 32, 0 },
43cd72b9
BW		 117 { "EXCSAVE1", 32, 0 },
118 { "EXCSAVE2", 32, 0 },
119 { "EXCSAVE3", 32, 0 },
120 { "EXCSAVE4", 32, 0 },
33430bd0
BW		 121 { "EXCSAVE5", 32, 0 },
122 { "EXCSAVE6", 32, 0 },
123 { "EXCSAVE7", 32, 0 },
074f5109
BW		 124 { "EPS2", 15, 0 },
125 { "EPS3", 15, 0 },
126 { "EPS4", 15, 0 },
33430bd0
BW		 127 { "EPS5", 15, 0 },
128 { "EPS6", 15, 0 },
129 { "EPS7", 15, 0 },
43cd72b9
BW		 130 { "EXCCAUSE", 6, 0 },
131 { "PSINTLEVEL", 4, 0 },
132 { "PSUM", 1, 0 },
133 { "PSWOE", 1, 0 },
074f5109 134 { "PSRING", 2, 0 },
43cd72b9
BW		 135 { "PSEXCM", 1, 0 },
136 { "DEPC", 32, 0 },
137 { "EXCVADDR", 32, 0 },
33430bd0
BW		 138 { "WindowBase", 3, 0 },
139 { "WindowStart", 8, 0 },
43cd72b9
BW		 140 { "PSCALLINC", 2, 0 },
141 { "PSOWB", 4, 0 },
142 { "LBEG", 32, 0 },
143 { "LEND", 32, 0 },
144 { "SAR", 6, 0 },
33430bd0 145 { "THREADPTR", 32, 0 },
43cd72b9
BW		 146 { "LITBADDR", 20, 0 },
147 { "LITBEN", 1, 0 },
148 { "MISC0", 32, 0 },
149 { "MISC1", 32, 0 },
150 { "InOCDMode", 1, 0 },
33430bd0 151 { "INTENABLE", 22, 0 },
43cd72b9
BW		 152 { "DBREAKA0", 32, 0 },
153 { "DBREAKC0", 8, 0 },
154 { "DBREAKA1", 32, 0 },
155 { "DBREAKC1", 8, 0 },
156 { "IBREAKA0", 32, 0 },
157 { "IBREAKA1", 32, 0 },
158 { "IBREAKENABLE", 2, 0 },
159 { "ICOUNTLEVEL", 4, 0 },
160 { "DEBUGCAUSE", 6, 0 },
161 { "DBNUM", 4, 0 },
162 { "CCOMPARE0", 32, 0 },
163 { "CCOMPARE1", 32, 0 },
074f5109
BW		 164 { "CCOMPARE2", 32, 0 },
165 { "ASID3", 8, 0 },
166 { "ASID2", 8, 0 },
167 { "ASID1", 8, 0 },
168 { "INSTPGSZID4", 2, 0 },
169 { "DATAPGSZID4", 2, 0 },
33430bd0
BW		 170 { "PTBASE", 10, 0 },
171 { "CPENABLE", 8, 0 },
172 { "SCOMPARE1", 32, 0 }
43cd72b9
BW		 173};
174
33430bd0 175#define NUM_STATES 71
43cd72b9 176
af4bed4b
BW		 177enum xtensa_state_id {
178 STATE_LCOUNT,
179 STATE_PC,
180 STATE_ICOUNT,
181 STATE_DDR,
182 STATE_INTERRUPT,
183 STATE_CCOUNT,
184 STATE_XTSYNC,
33430bd0 185 STATE_VECBASE,
af4bed4b
BW		 186 STATE_EPC1,
187 STATE_EPC2,
188 STATE_EPC3,
189 STATE_EPC4,
33430bd0
BW		 190 STATE_EPC5,
191 STATE_EPC6,
192 STATE_EPC7,
af4bed4b
BW		 193 STATE_EXCSAVE1,
194 STATE_EXCSAVE2,
195 STATE_EXCSAVE3,
196 STATE_EXCSAVE4,
33430bd0
BW		 197 STATE_EXCSAVE5,
198 STATE_EXCSAVE6,
199 STATE_EXCSAVE7,
af4bed4b
BW		 200 STATE_EPS2,
201 STATE_EPS3,
202 STATE_EPS4,
33430bd0
BW		 203 STATE_EPS5,
204 STATE_EPS6,
205 STATE_EPS7,
af4bed4b
BW		 206 STATE_EXCCAUSE,
207 STATE_PSINTLEVEL,
208 STATE_PSUM,
209 STATE_PSWOE,
210 STATE_PSRING,
211 STATE_PSEXCM,
212 STATE_DEPC,
213 STATE_EXCVADDR,
214 STATE_WindowBase,
215 STATE_WindowStart,
216 STATE_PSCALLINC,
217 STATE_PSOWB,
218 STATE_LBEG,
219 STATE_LEND,
220 STATE_SAR,
33430bd0 221 STATE_THREADPTR,
af4bed4b
BW		 222 STATE_LITBADDR,
223 STATE_LITBEN,
224 STATE_MISC0,
225 STATE_MISC1,
226 STATE_InOCDMode,
227 STATE_INTENABLE,
228 STATE_DBREAKA0,
229 STATE_DBREAKC0,
230 STATE_DBREAKA1,
231 STATE_DBREAKC1,
232 STATE_IBREAKA0,
233 STATE_IBREAKA1,
234 STATE_IBREAKENABLE,
235 STATE_ICOUNTLEVEL,
236 STATE_DEBUGCAUSE,
237 STATE_DBNUM,
238 STATE_CCOMPARE0,
239 STATE_CCOMPARE1,
240 STATE_CCOMPARE2,
241 STATE_ASID3,
242 STATE_ASID2,
243 STATE_ASID1,
244 STATE_INSTPGSZID4,
245 STATE_DATAPGSZID4,
33430bd0
BW		 246 STATE_PTBASE,
247 STATE_CPENABLE,
248 STATE_SCOMPARE1
af4bed4b 249};
43cd72b9
BW		 250
251\f
252/* Field definitions. */
253
254static unsigned
255Field_t_Slot_inst_get (const xtensa_insnbuf insn)
256{
257 unsigned tie_t = 0;
258 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
259 return tie_t;
260}
261
262static void
263Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
264{
265 uint32 tie_t;
266 tie_t = (val << 28) >> 28;
267 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
268}
269
270static unsigned
56fb3749 271Field_s_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 272{
43cd72b9 273 unsigned tie_t = 0;
56fb3749 274 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
43cd72b9 275 return tie_t;
e0001a05
NC		 276}
277
43cd72b9 278static void
56fb3749 279Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 280{
43cd72b9
BW		 281 uint32 tie_t;
282 tie_t = (val << 28) >> 28;
56fb3749 283 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
e0001a05
NC		 284}
285
43cd72b9 286static unsigned
56fb3749 287Field_r_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 288{
43cd72b9 289 unsigned tie_t = 0;
658ff993 290 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
43cd72b9 291 return tie_t;
e0001a05
NC		 292}
293
43cd72b9 294static void
56fb3749 295Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 296{
43cd72b9
BW		 297 uint32 tie_t;
298 tie_t = (val << 28) >> 28;
658ff993 299 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
e0001a05
NC		 300}
301
43cd72b9 302static unsigned
56fb3749 303Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 304{
43cd72b9 305 unsigned tie_t = 0;
56fb3749 306 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
43cd72b9 307 return tie_t;
e0001a05
NC		 308}
309
43cd72b9 310static void
56fb3749 311Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 312{
43cd72b9 313 uint32 tie_t;
56fb3749
SA		 314 tie_t = (val << 28) >> 28;
315 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
e0001a05
NC		 316}
317
43cd72b9 318static unsigned
56fb3749 319Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 320{
43cd72b9 321 unsigned tie_t = 0;
56fb3749 322 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
43cd72b9 323 return tie_t;
e0001a05
NC		 324}
325
43cd72b9 326static void
56fb3749 327Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 328{
43cd72b9
BW		 329 uint32 tie_t;
330 tie_t = (val << 28) >> 28;
56fb3749 331 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
e0001a05
NC		 332}
333
43cd72b9 334static unsigned
56fb3749 335Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 336{
43cd72b9 337 unsigned tie_t = 0;
56fb3749 338 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
43cd72b9 339 return tie_t;
e0001a05
NC		 340}
341
43cd72b9 342static void
56fb3749 343Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 344{
43cd72b9 345 uint32 tie_t;
56fb3749
SA		 346 tie_t = (val << 28) >> 28;
347 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
e0001a05
NC		 348}
349
43cd72b9 350static unsigned
56fb3749 351Field_n_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 352{
43cd72b9 353 unsigned tie_t = 0;
56fb3749 354 tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
43cd72b9 355 return tie_t;
e0001a05
NC		 356}
357
43cd72b9 358static void
56fb3749 359Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 360{
43cd72b9 361 uint32 tie_t;
56fb3749
SA		 362 tie_t = (val << 30) >> 30;
363 insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
e0001a05
NC		 364}
365
43cd72b9 366static unsigned
56fb3749
SA		 367Field_m_Slot_inst_get (const xtensa_insnbuf insn)
368{
369 unsigned tie_t = 0;
370 tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
371 return tie_t;
372}
373
374static void
375Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
376{
377 uint32 tie_t;
378 tie_t = (val << 30) >> 30;
379 insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
380}
381
382static unsigned
383Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 384{
43cd72b9
BW		 385 unsigned tie_t = 0;
386 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
56fb3749 387 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
43cd72b9 388 return tie_t;
e0001a05
NC		 389}
390
43cd72b9 391static void
56fb3749 392Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 393{
43cd72b9
BW		 394 uint32 tie_t;
395 tie_t = (val << 28) >> 28;
56fb3749
SA		 396 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
397 tie_t = (val << 24) >> 28;
43cd72b9 398 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
e0001a05
NC		 399}
400
33430bd0 401static unsigned
56fb3749 402Field_st_Slot_inst_get (const xtensa_insnbuf insn)
33430bd0
BW		 403{
404 unsigned tie_t = 0;
56fb3749
SA		 405 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
406 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
33430bd0
BW		 407 return tie_t;
408}
409
410static void
56fb3749 411Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
33430bd0
BW		 412{
413 uint32 tie_t;
414 tie_t = (val << 28) >> 28;
56fb3749
SA		 415 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
416 tie_t = (val << 24) >> 28;
417 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
33430bd0
BW		 418}
419
43cd72b9 420static unsigned
56fb3749 421Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 422{
43cd72b9 423 unsigned tie_t = 0;
56fb3749 424 tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
43cd72b9 425 return tie_t;
e0001a05
NC		 426}
427
43cd72b9 428static void
56fb3749 429Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 430{
43cd72b9 431 uint32 tie_t;
56fb3749
SA		 432 tie_t = (val << 29) >> 29;
433 insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
e0001a05
NC		 434}
435
43cd72b9 436static unsigned
56fb3749 437Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 438{
43cd72b9
BW		 439 unsigned tie_t = 0;
440 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
441 return tie_t;
e0001a05
NC		 442}
443
43cd72b9 444static void
56fb3749 445Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 446{
43cd72b9 447 uint32 tie_t;
56fb3749 448 tie_t = (val << 28) >> 28;
43cd72b9 449 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
e0001a05
NC		 450}
451
43cd72b9 452static unsigned
56fb3749 453Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 454{
43cd72b9 455 unsigned tie_t = 0;
56fb3749 456 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
43cd72b9 457 return tie_t;
e0001a05
NC		 458}
459
43cd72b9 460static void
56fb3749 461Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 462{
43cd72b9 463 uint32 tie_t;
56fb3749
SA		 464 tie_t = (val << 28) >> 28;
465 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
e0001a05
NC		 466}
467
43cd72b9 468static unsigned
56fb3749 469Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 470{
43cd72b9 471 unsigned tie_t = 0;
56fb3749 472 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
43cd72b9 473 return tie_t;
e0001a05
NC		 474}
475
43cd72b9 476static void
56fb3749 477Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 478{
43cd72b9 479 uint32 tie_t;
56fb3749
SA		 480 tie_t = (val << 28) >> 28;
481 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
e0001a05
NC		 482}
483
43cd72b9 484static unsigned
56fb3749 485Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 486{
43cd72b9 487 unsigned tie_t = 0;
56fb3749 488 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
43cd72b9 489 return tie_t;
e0001a05
NC		 490}
491
43cd72b9 492static void
56fb3749 493Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 494{
43cd72b9 495 uint32 tie_t;
56fb3749
SA		 496 tie_t = (val << 28) >> 28;
497 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
e0001a05
NC		 498}
499
43cd72b9 500static unsigned
56fb3749 501Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 502{
43cd72b9 503 unsigned tie_t = 0;
56fb3749 504 tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
43cd72b9 505 return tie_t;
e0001a05
NC		 506}
507
43cd72b9 508static void
56fb3749 509Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 510{
43cd72b9 511 uint32 tie_t;
56fb3749
SA		 512 tie_t = (val << 31) >> 31;
513 insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
e0001a05
NC		 514}
515
43cd72b9 516static unsigned
56fb3749 517Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 518{
43cd72b9 519 unsigned tie_t = 0;
56fb3749 520 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
43cd72b9 521 return tie_t;
e0001a05
NC		 522}
523
43cd72b9 524static void
56fb3749
SA		 525Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
526{
527 uint32 tie_t;
528 tie_t = (val << 31) >> 31;
529 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
530}
531
532static unsigned
533Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
534{
535 unsigned tie_t = 0;
536 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
537 return tie_t;
538}
539
540static void
541Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 542{
43cd72b9
BW		 543 uint32 tie_t;
544 tie_t = (val << 28) >> 28;
56fb3749 545 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
e0001a05
NC		 546}
547
43cd72b9 548static unsigned
56fb3749 549Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 550{
43cd72b9 551 unsigned tie_t = 0;
56fb3749 552 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
43cd72b9 553 return tie_t;
e0001a05
NC		 554}
555
43cd72b9 556static void
56fb3749 557Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 558{
43cd72b9
BW		 559 uint32 tie_t;
560 tie_t = (val << 28) >> 28;
56fb3749 561 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
e0001a05
NC		 562}
563
43cd72b9 564static unsigned
56fb3749 565Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 566{
43cd72b9 567 unsigned tie_t = 0;
56fb3749 568 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
43cd72b9 569 return tie_t;
e0001a05
NC		 570}
571
43cd72b9 572static void
56fb3749
SA		 573Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
574{
575 uint32 tie_t;
576 tie_t = (val << 31) >> 31;
577 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
578}
579
580static unsigned
581Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
582{
583 unsigned tie_t = 0;
584 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
585 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
586 return tie_t;
587}
588
589static void
590Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 591{
43cd72b9
BW		 592 uint32 tie_t;
593 tie_t = (val << 28) >> 28;
56fb3749
SA		 594 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
595 tie_t = (val << 27) >> 31;
596 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
e0001a05
NC		 597}
598
43cd72b9 599static unsigned
56fb3749
SA		 600Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
601{
602 unsigned tie_t = 0;
603 tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20);
604 return tie_t;
605}
606
607static void
608Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
609{
610 uint32 tie_t;
611 tie_t = (val << 20) >> 20;
612 insn[0] = (insn[0] & ~0xfff) | (tie_t << 0);
613}
614
615static unsigned
616Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
617{
618 unsigned tie_t = 0;
619 tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
620 return tie_t;
621}
622
623static void
624Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
625{
626 uint32 tie_t;
627 tie_t = (val << 24) >> 24;
628 insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
629}
630
631static unsigned
632Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 633{
43cd72b9
BW		 634 unsigned tie_t = 0;
635 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
636 return tie_t;
e0001a05
NC		 637}
638
43cd72b9 639static void
56fb3749 640Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 641{
43cd72b9
BW		 642 uint32 tie_t;
643 tie_t = (val << 28) >> 28;
644 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
e0001a05
NC		 645}
646
43cd72b9 647static unsigned
56fb3749 648Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 649{
43cd72b9 650 unsigned tie_t = 0;
56fb3749
SA		 651 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
652 tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
43cd72b9 653 return tie_t;
e0001a05
NC		 654}
655
43cd72b9 656static void
56fb3749 657Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 658{
43cd72b9 659 uint32 tie_t;
56fb3749
SA		 660 tie_t = (val << 24) >> 24;
661 insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
662 tie_t = (val << 20) >> 28;
663 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
e0001a05
NC		 664}
665
43cd72b9 666static unsigned
56fb3749 667Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 668{
43cd72b9 669 unsigned tie_t = 0;
56fb3749 670 tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16);
43cd72b9 671 return tie_t;
e0001a05
NC		 672}
673
43cd72b9 674static void
56fb3749 675Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 676{
43cd72b9 677 uint32 tie_t;
56fb3749
SA		 678 tie_t = (val << 16) >> 16;
679 insn[0] = (insn[0] & ~0xffff) | (tie_t << 0);
e0001a05
NC		 680}
681
43cd72b9 682static unsigned
56fb3749 683Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 684{
43cd72b9 685 unsigned tie_t = 0;
56fb3749 686 tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
43cd72b9 687 return tie_t;
e0001a05
NC		 688}
689
43cd72b9 690static void
56fb3749 691Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 692{
43cd72b9 693 uint32 tie_t;
56fb3749
SA		 694 tie_t = (val << 14) >> 14;
695 insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
e0001a05
NC		 696}
697
43cd72b9 698static unsigned
56fb3749 699Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 700{
43cd72b9
BW		 701 unsigned tie_t = 0;
702 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
703 return tie_t;
e0001a05
NC		 704}
705
43cd72b9 706static void
56fb3749 707Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 708{
43cd72b9
BW		 709 uint32 tie_t;
710 tie_t = (val << 28) >> 28;
711 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
e0001a05
NC		 712}
713
43cd72b9
BW		 714static unsigned
715Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 716{
43cd72b9
BW		 717 unsigned tie_t = 0;
718 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
719 return tie_t;
e0001a05
NC		 720}
721
43cd72b9
BW		 722static void
723Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 724{
43cd72b9
BW		 725 uint32 tie_t;
726 tie_t = (val << 31) >> 31;
727 insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
e0001a05
NC		 728}
729
43cd72b9
BW		 730static unsigned
731Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 732{
43cd72b9
BW		 733 unsigned tie_t = 0;
734 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
735 return tie_t;
e0001a05
NC		 736}
737
43cd72b9
BW		 738static void
739Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 740{
43cd72b9
BW		 741 uint32 tie_t;
742 tie_t = (val << 31) >> 31;
743 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
e0001a05
NC		 744}
745
43cd72b9
BW		 746static unsigned
747Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 748{
43cd72b9
BW		 749 unsigned tie_t = 0;
750 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
751 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
752 return tie_t;
e0001a05
NC		 753}
754
43cd72b9
BW		 755static void
756Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 757{
43cd72b9
BW		 758 uint32 tie_t;
759 tie_t = (val << 28) >> 28;
760 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
761 tie_t = (val << 27) >> 31;
762 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
e0001a05
NC		 763}
764
43cd72b9
BW		 765static unsigned
766Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 767{
43cd72b9
BW		 768 unsigned tie_t = 0;
769 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
770 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
771 return tie_t;
e0001a05
NC		 772}
773
43cd72b9
BW		 774static void
775Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 776{
43cd72b9
BW		 777 uint32 tie_t;
778 tie_t = (val << 28) >> 28;
779 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
780 tie_t = (val << 27) >> 31;
781 insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
e0001a05
NC		 782}
783
43cd72b9
BW		 784static unsigned
785Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 786{
43cd72b9
BW		 787 unsigned tie_t = 0;
788 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
789 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
790 return tie_t;
e0001a05
NC		 791}
792
43cd72b9
BW		 793static void
794Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 795{
43cd72b9
BW		 796 uint32 tie_t;
797 tie_t = (val << 28) >> 28;
798 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
799 tie_t = (val << 27) >> 31;
800 insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
e0001a05
NC		 801}
802
43cd72b9
BW		 803static unsigned
804Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 805{
43cd72b9
BW		 806 unsigned tie_t = 0;
807 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
808 return tie_t;
e0001a05
NC		 809}
810
43cd72b9
BW		 811static void
812Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 813{
43cd72b9
BW		 814 uint32 tie_t;
815 tie_t = (val << 31) >> 31;
816 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
e0001a05
NC		 817}
818
43cd72b9
BW		 819static unsigned
820Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 821{
43cd72b9
BW		 822 unsigned tie_t = 0;
823 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
824 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
825 return tie_t;
e0001a05
NC		 826}
827
43cd72b9
BW		 828static void
829Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 830{
43cd72b9
BW		 831 uint32 tie_t;
832 tie_t = (val << 28) >> 28;
833 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
834 tie_t = (val << 27) >> 31;
835 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
e0001a05
NC		 836}
837
43cd72b9
BW		 838static unsigned
839Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 840{
43cd72b9
BW		 841 unsigned tie_t = 0;
842 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
843 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
844 return tie_t;
e0001a05
NC		 845}
846
43cd72b9
BW		 847static void
848Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 849{
43cd72b9
BW		 850 uint32 tie_t;
851 tie_t = (val << 28) >> 28;
852 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
853 tie_t = (val << 24) >> 28;
854 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
e0001a05
NC		 855}
856
43cd72b9
BW		 857static unsigned
858Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 859{
43cd72b9
BW		 860 unsigned tie_t = 0;
861 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
862 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
863 return tie_t;
e0001a05
NC		 864}
865
43cd72b9
BW		 866static void
867Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
868{
869 uint32 tie_t;
870 tie_t = (val << 28) >> 28;
871 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
872 tie_t = (val << 24) >> 28;
873 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
874}
e0001a05 875
43cd72b9
BW		 876static unsigned
877Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 878{
43cd72b9
BW		 879 unsigned tie_t = 0;
880 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
881 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
882 return tie_t;
e0001a05
NC		 883}
884
43cd72b9
BW		 885static void
886Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 887{
43cd72b9
BW		 888 uint32 tie_t;
889 tie_t = (val << 28) >> 28;
890 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
891 tie_t = (val << 24) >> 28;
892 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
e0001a05
NC		 893}
894
43cd72b9
BW		 895static unsigned
896Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 897{
43cd72b9
BW		 898 unsigned tie_t = 0;
899 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
900 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
901 return tie_t;
e0001a05
NC		 902}
903
43cd72b9
BW		 904static void
905Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 906{
43cd72b9
BW		 907 uint32 tie_t;
908 tie_t = (val << 28) >> 28;
909 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
910 tie_t = (val << 24) >> 28;
911 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
e0001a05
NC		 912}
913
43cd72b9
BW		 914static unsigned
915Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 916{
43cd72b9
BW		 917 unsigned tie_t = 0;
918 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
919 return tie_t;
e0001a05
NC		 920}
921
43cd72b9
BW		 922static void
923Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 924{
43cd72b9
BW		 925 uint32 tie_t;
926 tie_t = (val << 28) >> 28;
927 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
e0001a05
NC		 928}
929
43cd72b9
BW		 930static unsigned
931Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 932{
43cd72b9
BW		 933 unsigned tie_t = 0;
934 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
935 return tie_t;
e0001a05
NC		 936}
937
43cd72b9
BW		 938static void
939Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 940{
43cd72b9
BW		 941 uint32 tie_t;
942 tie_t = (val << 28) >> 28;
943 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
e0001a05
NC		 944}
945
43cd72b9
BW		 946static unsigned
947Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 948{
43cd72b9
BW		 949 unsigned tie_t = 0;
950 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
951 return tie_t;
e0001a05
NC		 952}
953
43cd72b9
BW		 954static void
955Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 956{
43cd72b9
BW		 957 uint32 tie_t;
958 tie_t = (val << 28) >> 28;
959 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
e0001a05
NC		 960}
961
43cd72b9
BW		 962static unsigned
963Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 964{
43cd72b9
BW		 965 unsigned tie_t = 0;
966 tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
967 tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
968 return tie_t;
e0001a05
NC		 969}
970
43cd72b9
BW		 971static void
972Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 973{
43cd72b9
BW		 974 uint32 tie_t;
975 tie_t = (val << 30) >> 30;
976 insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
977 tie_t = (val << 28) >> 30;
978 insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
e0001a05
NC		 979}
980
43cd72b9
BW		 981static unsigned
982Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 983{
43cd72b9
BW		 984 unsigned tie_t = 0;
985 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
986 return tie_t;
e0001a05
NC		 987}
988
43cd72b9
BW		 989static void
990Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 991{
43cd72b9
BW		 992 uint32 tie_t;
993 tie_t = (val << 31) >> 31;
994 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
e0001a05
NC		 995}
996
43cd72b9
BW		 997static unsigned
998Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 999{
43cd72b9
BW		 1000 unsigned tie_t = 0;
1001 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1002 return tie_t;
e0001a05
NC		 1003}
1004
43cd72b9
BW		 1005static void
1006Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1007{
43cd72b9
BW		 1008 uint32 tie_t;
1009 tie_t = (val << 28) >> 28;
1010 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
e0001a05
NC		 1011}
1012
43cd72b9
BW		 1013static unsigned
1014Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 1015{
43cd72b9
BW		 1016 unsigned tie_t = 0;
1017 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1018 return tie_t;
e0001a05
NC		 1019}
1020
43cd72b9
BW		 1021static void
1022Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1023{
43cd72b9
BW		 1024 uint32 tie_t;
1025 tie_t = (val << 28) >> 28;
1026 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
e0001a05
NC		 1027}
1028
43cd72b9
BW		 1029static unsigned
1030Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1031{
1032 unsigned tie_t = 0;
1033 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1034 return tie_t;
1035}
e0001a05 1036
43cd72b9
BW		 1037static void
1038Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1039{
43cd72b9
BW		 1040 uint32 tie_t;
1041 tie_t = (val << 30) >> 30;
1042 insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
e0001a05
NC		 1043}
1044
43cd72b9
BW		 1045static unsigned
1046Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 1047{
43cd72b9
BW		 1048 unsigned tie_t = 0;
1049 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1050 return tie_t;
e0001a05
NC		 1051}
1052
43cd72b9
BW		 1053static void
1054Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1055{
43cd72b9
BW		 1056 uint32 tie_t;
1057 tie_t = (val << 30) >> 30;
1058 insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
e0001a05
NC		 1059}
1060
43cd72b9
BW		 1061static unsigned
1062Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 1063{
43cd72b9
BW		 1064 unsigned tie_t = 0;
1065 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1066 return tie_t;
e0001a05
NC		 1067}
1068
43cd72b9
BW		 1069static void
1070Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1071{
43cd72b9
BW		 1072 uint32 tie_t;
1073 tie_t = (val << 28) >> 28;
1074 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
e0001a05
NC		 1075}
1076
43cd72b9
BW		 1077static unsigned
1078Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 1079{
43cd72b9
BW		 1080 unsigned tie_t = 0;
1081 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1082 return tie_t;
e0001a05
NC		 1083}
1084
43cd72b9
BW		 1085static void
1086Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1087{
43cd72b9
BW		 1088 uint32 tie_t;
1089 tie_t = (val << 28) >> 28;
1090 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
e0001a05
NC		 1091}
1092
43cd72b9
BW		 1093static unsigned
1094Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 1095{
43cd72b9
BW		 1096 unsigned tie_t = 0;
1097 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1098 return tie_t;
e0001a05
NC		 1099}
1100
43cd72b9
BW		 1101static void
1102Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1103{
43cd72b9
BW		 1104 uint32 tie_t;
1105 tie_t = (val << 29) >> 29;
1106 insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
e0001a05
NC		 1107}
1108
43cd72b9
BW		 1109static unsigned
1110Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 1111{
43cd72b9
BW		 1112 unsigned tie_t = 0;
1113 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1114 return tie_t;
e0001a05
NC		 1115}
1116
43cd72b9
BW		 1117static void
1118Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1119{
43cd72b9
BW		 1120 uint32 tie_t;
1121 tie_t = (val << 29) >> 29;
1122 insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
e0001a05
NC		 1123}
1124
43cd72b9
BW		 1125static unsigned
1126Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 1127{
43cd72b9
BW		 1128 unsigned tie_t = 0;
1129 tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
1130 return tie_t;
e0001a05
NC		 1131}
1132
43cd72b9
BW		 1133static void
1134Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1135{
43cd72b9
BW		 1136 uint32 tie_t;
1137 tie_t = (val << 31) >> 31;
1138 insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
e0001a05
NC		 1139}
1140
43cd72b9
BW		 1141static unsigned
1142Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 1143{
43cd72b9
BW		 1144 unsigned tie_t = 0;
1145 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1146 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1147 return tie_t;
e0001a05
NC		 1148}
1149
43cd72b9
BW		 1150static void
1151Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1152{
43cd72b9
BW		 1153 uint32 tie_t;
1154 tie_t = (val << 28) >> 28;
1155 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1156 tie_t = (val << 26) >> 30;
1157 insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
e0001a05
NC		 1158}
1159
43cd72b9
BW		 1160static unsigned
1161Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 1162{
43cd72b9
BW		 1163 unsigned tie_t = 0;
1164 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1165 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1166 return tie_t;
e0001a05
NC		 1167}
1168
43cd72b9
BW		 1169static void
1170Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1171{
43cd72b9
BW		 1172 uint32 tie_t;
1173 tie_t = (val << 28) >> 28;
1174 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1175 tie_t = (val << 26) >> 30;
1176 insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
e0001a05
NC		 1177}
1178
43cd72b9
BW		 1179static unsigned
1180Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 1181{
43cd72b9
BW		 1182 unsigned tie_t = 0;
1183 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1184 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1185 return tie_t;
e0001a05
NC		 1186}
1187
43cd72b9
BW		 1188static void
1189Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1190{
43cd72b9
BW		 1191 uint32 tie_t;
1192 tie_t = (val << 28) >> 28;
1193 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1194 tie_t = (val << 25) >> 29;
1195 insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
e0001a05
NC		 1196}
1197
43cd72b9
BW		 1198static unsigned
1199Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 1200{
43cd72b9
BW		 1201 unsigned tie_t = 0;
1202 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1203 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1204 return tie_t;
e0001a05
NC		 1205}
1206
43cd72b9
BW		 1207static void
1208Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1209{
43cd72b9
BW		 1210 uint32 tie_t;
1211 tie_t = (val << 28) >> 28;
1212 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1213 tie_t = (val << 25) >> 29;
1214 insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
e0001a05
NC		 1215}
1216
33430bd0
BW		 1217static unsigned
1218Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
1219{
1220 unsigned tie_t = 0;
1221 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1222 return tie_t;
1223}
1224
1225static void
1226Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1227{
1228 uint32 tie_t;
1229 tie_t = (val << 17) >> 17;
1230 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1231}
1232
1233static unsigned
1234Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
1235{
1236 unsigned tie_t = 0;
1237 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1238 return tie_t;
1239}
1240
1241static void
1242Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1243{
1244 uint32 tie_t;
1245 tie_t = (val << 14) >> 14;
1246 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1247}
1248
43cd72b9
BW		 1249static void
1250Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
1251 uint32 val ATTRIBUTE_UNUSED)
e0001a05 1252{
43cd72b9 1253 /* Do nothing. */
e0001a05
NC		 1254}
1255
43cd72b9
BW		 1256static unsigned
1257Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
e0001a05 1258{
43cd72b9 1259 return 0;
e0001a05
NC		 1260}
1261
43cd72b9
BW		 1262static unsigned
1263Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
e0001a05 1264{
43cd72b9 1265 return 4;
e0001a05
NC		 1266}
1267
43cd72b9
BW		 1268static unsigned
1269Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
e0001a05 1270{
43cd72b9 1271 return 8;
e0001a05
NC		 1272}
1273
43cd72b9
BW		 1274static unsigned
1275Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
e0001a05 1276{
43cd72b9 1277 return 12;
e0001a05
NC		 1278}
1279
56fb3749
SA		 1280enum xtensa_field_id {
1281 FIELD_t,
1282 FIELD_bbi4,
1283 FIELD_bbi,
1284 FIELD_imm12,
1285 FIELD_imm8,
1286 FIELD_s,
1287 FIELD_imm12b,
1288 FIELD_imm16,
1289 FIELD_m,
1290 FIELD_n,
1291 FIELD_offset,
1292 FIELD_op0,
1293 FIELD_op1,
1294 FIELD_op2,
1295 FIELD_r,
1296 FIELD_sa4,
1297 FIELD_sae4,
1298 FIELD_sae,
1299 FIELD_sal,
1300 FIELD_sargt,
1301 FIELD_sas4,
1302 FIELD_sas,
1303 FIELD_sr,
1304 FIELD_st,
1305 FIELD_thi3,
1306 FIELD_imm4,
1307 FIELD_mn,
1308 FIELD_i,
1309 FIELD_imm6lo,
1310 FIELD_imm6hi,
1311 FIELD_imm7lo,
1312 FIELD_imm7hi,
1313 FIELD_z,
1314 FIELD_imm6,
1315 FIELD_imm7,
1316 FIELD_xt_wbr15_imm,
1317 FIELD_xt_wbr18_imm,
1318 FIELD__ar0,
1319 FIELD__ar4,
1320 FIELD__ar8,
1321 FIELD__ar12
1322};
1323
43cd72b9
BW		 1324\f
1325/* Functional units. */
1326
1327static xtensa_funcUnit_internal funcUnits[] = {
1328
1329};
1330
1331\f
1332/* Register files. */
1333
56fb3749
SA		 1334enum xtensa_regfile_id {
1335 REGFILE_AR
1336};
1337
43cd72b9 1338static xtensa_regfile_internal regfiles[] = {
56fb3749 1339 { "AR", "a", REGFILE_AR, 32, 32 }
43cd72b9
BW		 1340};
1341
1342\f
1343/* Interfaces. */
1344
1345static xtensa_interface_internal interfaces[] = {
1346
1347};
1348
1349\f
1350/* Constant tables. */
1351
1352/* constant table ai4c */
1353static const unsigned CONST_TBL_ai4c_0[] = {
1354 0xffffffff,
1355 0x1,
1356 0x2,
1357 0x3,
1358 0x4,
1359 0x5,
1360 0x6,
1361 0x7,
1362 0x8,
1363 0x9,
1364 0xa,
1365 0xb,
1366 0xc,
1367 0xd,
1368 0xe,
1369 0xf,
1370 0
1371};
1372
1373/* constant table b4c */
1374static const unsigned CONST_TBL_b4c_0[] = {
1375 0xffffffff,
1376 0x1,
1377 0x2,
1378 0x3,
1379 0x4,
1380 0x5,
1381 0x6,
1382 0x7,
1383 0x8,
1384 0xa,
1385 0xc,
1386 0x10,
1387 0x20,
1388 0x40,
1389 0x80,
1390 0x100,
1391 0
1392};
1393
1394/* constant table b4cu */
1395static const unsigned CONST_TBL_b4cu_0[] = {
1396 0x8000,
1397 0x10000,
1398 0x2,
1399 0x3,
1400 0x4,
1401 0x5,
1402 0x6,
1403 0x7,
1404 0x8,
1405 0xa,
1406 0xc,
1407 0x10,
1408 0x20,
1409 0x40,
1410 0x80,
1411 0x100,
1412 0
1413};
1414
1415\f
1416/* Instruction operands. */
1417
1418static int
1419Operand_soffsetx4_decode (uint32 *valp)
e0001a05 1420{
43cd72b9
BW		 1421 unsigned soffsetx4_0, offset_0;
1422 offset_0 = *valp & 0x3ffff;
1423 soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
1424 *valp = soffsetx4_0;
1425 return 0;
e0001a05
NC		 1426}
1427
43cd72b9
BW		 1428static int
1429Operand_soffsetx4_encode (uint32 *valp)
e0001a05 1430{
43cd72b9
BW		 1431 unsigned offset_0, soffsetx4_0;
1432 soffsetx4_0 = *valp;
1433 offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
1434 *valp = offset_0;
1435 return 0;
e0001a05
NC		 1436}
1437
43cd72b9
BW		 1438static int
1439Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
e0001a05 1440{
43cd72b9
BW		 1441 *valp -= (pc & ~0x3);
1442 return 0;
e0001a05
NC		 1443}
1444
43cd72b9
BW		 1445static int
1446Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
e0001a05 1447{
43cd72b9
BW		 1448 *valp += (pc & ~0x3);
1449 return 0;
e0001a05
NC		 1450}
1451
43cd72b9
BW		 1452static int
1453Operand_uimm12x8_decode (uint32 *valp)
e0001a05 1454{
43cd72b9
BW		 1455 unsigned uimm12x8_0, imm12_0;
1456 imm12_0 = *valp & 0xfff;
1457 uimm12x8_0 = imm12_0 << 3;
1458 *valp = uimm12x8_0;
1459 return 0;
e0001a05
NC		 1460}
1461
43cd72b9
BW		 1462static int
1463Operand_uimm12x8_encode (uint32 *valp)
e0001a05 1464{
43cd72b9
BW		 1465 unsigned imm12_0, uimm12x8_0;
1466 uimm12x8_0 = *valp;
1467 imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
1468 *valp = imm12_0;
1469 return 0;
e0001a05
NC		 1470}
1471
43cd72b9
BW		 1472static int
1473Operand_simm4_decode (uint32 *valp)
e0001a05 1474{
43cd72b9
BW		 1475 unsigned simm4_0, mn_0;
1476 mn_0 = *valp & 0xf;
1477 simm4_0 = ((int) mn_0 << 28) >> 28;
1478 *valp = simm4_0;
1479 return 0;
e0001a05
NC		 1480}
1481
43cd72b9
BW		 1482static int
1483Operand_simm4_encode (uint32 *valp)
e0001a05 1484{
43cd72b9
BW		 1485 unsigned mn_0, simm4_0;
1486 simm4_0 = *valp;
1487 mn_0 = (simm4_0 & 0xf);
1488 *valp = mn_0;
1489 return 0;
e0001a05
NC		 1490}
1491
43cd72b9
BW		 1492static int
1493Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
e0001a05 1494{
43cd72b9 1495 return 0;
e0001a05
NC		 1496}
1497
43cd72b9
BW		 1498static int
1499Operand_arr_encode (uint32 *valp)
e0001a05 1500{
43cd72b9
BW		 1501 int error;
1502 error = (*valp & ~0xf) != 0;
1503 return error;
e0001a05
NC		 1504}
1505
43cd72b9
BW		 1506static int
1507Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
e0001a05 1508{
43cd72b9 1509 return 0;
e0001a05
NC		 1510}
1511
43cd72b9
BW		 1512static int
1513Operand_ars_encode (uint32 *valp)
e0001a05 1514{
43cd72b9
BW		 1515 int error;
1516 error = (*valp & ~0xf) != 0;
1517 return error;
e0001a05
NC		 1518}
1519
43cd72b9
BW		 1520static int
1521Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
1522{
1523 return 0;
1524}
e0001a05 1525
43cd72b9
BW		 1526static int
1527Operand_art_encode (uint32 *valp)
e0001a05 1528{
43cd72b9
BW		 1529 int error;
1530 error = (*valp & ~0xf) != 0;
1531 return error;
e0001a05
NC		 1532}
1533
43cd72b9
BW		 1534static int
1535Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
e0001a05 1536{
43cd72b9 1537 return 0;
e0001a05
NC		 1538}
1539
43cd72b9
BW		 1540static int
1541Operand_ar0_encode (uint32 *valp)
e0001a05 1542{
43cd72b9 1543 int error;
33430bd0 1544 error = (*valp & ~0x1f) != 0;
43cd72b9 1545 return error;
e0001a05
NC		 1546}
1547
43cd72b9
BW		 1548static int
1549Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
e0001a05 1550{
43cd72b9 1551 return 0;
e0001a05
NC		 1552}
1553
43cd72b9
BW		 1554static int
1555Operand_ar4_encode (uint32 *valp)
1556{
1557 int error;
33430bd0 1558 error = (*valp & ~0x1f) != 0;
43cd72b9 1559 return error;
e0001a05
NC		 1560}
1561
43cd72b9
BW		 1562static int
1563Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
e0001a05 1564{
43cd72b9 1565 return 0;
e0001a05
NC		 1566}
1567
43cd72b9
BW		 1568static int
1569Operand_ar8_encode (uint32 *valp)
e0001a05 1570{
43cd72b9 1571 int error;
33430bd0 1572 error = (*valp & ~0x1f) != 0;
43cd72b9 1573 return error;
e0001a05
NC		 1574}
1575
43cd72b9
BW		 1576static int
1577Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
e0001a05 1578{
43cd72b9 1579 return 0;
e0001a05
NC		 1580}
1581
43cd72b9
BW		 1582static int
1583Operand_ar12_encode (uint32 *valp)
e0001a05 1584{
43cd72b9 1585 int error;
33430bd0 1586 error = (*valp & ~0x1f) != 0;
43cd72b9 1587 return error;
e0001a05
NC		 1588}
1589
43cd72b9
BW		 1590static int
1591Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
1592{
1593 return 0;
1594}
e0001a05 1595
43cd72b9
BW		 1596static int
1597Operand_ars_entry_encode (uint32 *valp)
e0001a05 1598{
43cd72b9 1599 int error;
33430bd0 1600 error = (*valp & ~0x1f) != 0;
43cd72b9 1601 return error;
e0001a05
NC		 1602}
1603
43cd72b9
BW		 1604static int
1605Operand_immrx4_decode (uint32 *valp)
e0001a05 1606{
43cd72b9
BW		 1607 unsigned immrx4_0, r_0;
1608 r_0 = *valp & 0xf;
af4bed4b 1609 immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
43cd72b9
BW		 1610 *valp = immrx4_0;
1611 return 0;
e0001a05
NC		 1612}
1613
43cd72b9
BW		 1614static int
1615Operand_immrx4_encode (uint32 *valp)
e0001a05 1616{
43cd72b9
BW		 1617 unsigned r_0, immrx4_0;
1618 immrx4_0 = *valp;
1619 r_0 = ((immrx4_0 >> 2) & 0xf);
1620 *valp = r_0;
1621 return 0;
e0001a05
NC		 1622}
1623
43cd72b9
BW		 1624static int
1625Operand_lsi4x4_decode (uint32 *valp)
e0001a05 1626{
43cd72b9
BW		 1627 unsigned lsi4x4_0, r_0;
1628 r_0 = *valp & 0xf;
1629 lsi4x4_0 = r_0 << 2;
1630 *valp = lsi4x4_0;
1631 return 0;
e0001a05
NC		 1632}
1633
43cd72b9
BW		 1634static int
1635Operand_lsi4x4_encode (uint32 *valp)
e0001a05 1636{
43cd72b9
BW		 1637 unsigned r_0, lsi4x4_0;
1638 lsi4x4_0 = *valp;
1639 r_0 = ((lsi4x4_0 >> 2) & 0xf);
1640 *valp = r_0;
1641 return 0;
e0001a05
NC		 1642}
1643
43cd72b9
BW		 1644static int
1645Operand_simm7_decode (uint32 *valp)
e0001a05 1646{
43cd72b9
BW		 1647 unsigned simm7_0, imm7_0;
1648 imm7_0 = *valp & 0x7f;
1649 simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
1650 *valp = simm7_0;
1651 return 0;
e0001a05
NC		 1652}
1653
43cd72b9
BW		 1654static int
1655Operand_simm7_encode (uint32 *valp)
e0001a05 1656{
43cd72b9
BW		 1657 unsigned imm7_0, simm7_0;
1658 simm7_0 = *valp;
1659 imm7_0 = (simm7_0 & 0x7f);
1660 *valp = imm7_0;
1661 return 0;
e0001a05
NC		 1662}
1663
43cd72b9
BW		 1664static int
1665Operand_uimm6_decode (uint32 *valp)
e0001a05 1666{
43cd72b9
BW		 1667 unsigned uimm6_0, imm6_0;
1668 imm6_0 = *valp & 0x3f;
af4bed4b 1669 uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
43cd72b9
BW		 1670 *valp = uimm6_0;
1671 return 0;
e0001a05
NC		 1672}
1673
43cd72b9
BW		 1674static int
1675Operand_uimm6_encode (uint32 *valp)
e0001a05 1676{
43cd72b9
BW		 1677 unsigned imm6_0, uimm6_0;
1678 uimm6_0 = *valp;
1679 imm6_0 = (uimm6_0 - 0x4) & 0x3f;
1680 *valp = imm6_0;
1681 return 0;
e0001a05
NC		 1682}
1683
43cd72b9
BW		 1684static int
1685Operand_uimm6_ator (uint32 *valp, uint32 pc)
e0001a05 1686{
43cd72b9
BW		 1687 *valp -= pc;
1688 return 0;
e0001a05
NC		 1689}
1690
43cd72b9
BW		 1691static int
1692Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
e0001a05 1693{
43cd72b9
BW		 1694 *valp += pc;
1695 return 0;
e0001a05
NC		 1696}
1697
43cd72b9
BW		 1698static int
1699Operand_ai4const_decode (uint32 *valp)
e0001a05 1700{
43cd72b9
BW		 1701 unsigned ai4const_0, t_0;
1702 t_0 = *valp & 0xf;
1703 ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
1704 *valp = ai4const_0;
1705 return 0;
e0001a05
NC		 1706}
1707
43cd72b9
BW		 1708static int
1709Operand_ai4const_encode (uint32 *valp)
e0001a05 1710{
43cd72b9
BW		 1711 unsigned t_0, ai4const_0;
1712 ai4const_0 = *valp;
1713 switch (ai4const_0)
1714 {
1715 case 0xffffffff: t_0 = 0; break;
1716 case 0x1: t_0 = 0x1; break;
1717 case 0x2: t_0 = 0x2; break;
1718 case 0x3: t_0 = 0x3; break;
1719 case 0x4: t_0 = 0x4; break;
1720 case 0x5: t_0 = 0x5; break;
1721 case 0x6: t_0 = 0x6; break;
1722 case 0x7: t_0 = 0x7; break;
1723 case 0x8: t_0 = 0x8; break;
1724 case 0x9: t_0 = 0x9; break;
1725 case 0xa: t_0 = 0xa; break;
1726 case 0xb: t_0 = 0xb; break;
1727 case 0xc: t_0 = 0xc; break;
1728 case 0xd: t_0 = 0xd; break;
1729 case 0xe: t_0 = 0xe; break;
1730 default: t_0 = 0xf; break;
1731 }
1732 *valp = t_0;
1733 return 0;
e0001a05
NC		 1734}
1735
43cd72b9
BW		 1736static int
1737Operand_b4const_decode (uint32 *valp)
e0001a05 1738{
43cd72b9
BW		 1739 unsigned b4const_0, r_0;
1740 r_0 = *valp & 0xf;
1741 b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
1742 *valp = b4const_0;
1743 return 0;
e0001a05
NC		 1744}
1745
43cd72b9
BW		 1746static int
1747Operand_b4const_encode (uint32 *valp)
e0001a05 1748{
43cd72b9
BW		 1749 unsigned r_0, b4const_0;
1750 b4const_0 = *valp;
1751 switch (b4const_0)
1752 {
1753 case 0xffffffff: r_0 = 0; break;
1754 case 0x1: r_0 = 0x1; break;
1755 case 0x2: r_0 = 0x2; break;
1756 case 0x3: r_0 = 0x3; break;
1757 case 0x4: r_0 = 0x4; break;
1758 case 0x5: r_0 = 0x5; break;
1759 case 0x6: r_0 = 0x6; break;
1760 case 0x7: r_0 = 0x7; break;
1761 case 0x8: r_0 = 0x8; break;
1762 case 0xa: r_0 = 0x9; break;
1763 case 0xc: r_0 = 0xa; break;
1764 case 0x10: r_0 = 0xb; break;
1765 case 0x20: r_0 = 0xc; break;
1766 case 0x40: r_0 = 0xd; break;
1767 case 0x80: r_0 = 0xe; break;
1768 default: r_0 = 0xf; break;
1769 }
1770 *valp = r_0;
1771 return 0;
e0001a05
NC		 1772}
1773
43cd72b9
BW		 1774static int
1775Operand_b4constu_decode (uint32 *valp)
e0001a05 1776{
43cd72b9
BW		 1777 unsigned b4constu_0, r_0;
1778 r_0 = *valp & 0xf;
1779 b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
1780 *valp = b4constu_0;
1781 return 0;
e0001a05
NC		 1782}
1783
43cd72b9
BW		 1784static int
1785Operand_b4constu_encode (uint32 *valp)
e0001a05 1786{
43cd72b9
BW		 1787 unsigned r_0, b4constu_0;
1788 b4constu_0 = *valp;
1789 switch (b4constu_0)
1790 {
1791 case 0x8000: r_0 = 0; break;
1792 case 0x10000: r_0 = 0x1; break;
1793 case 0x2: r_0 = 0x2; break;
1794 case 0x3: r_0 = 0x3; break;
1795 case 0x4: r_0 = 0x4; break;
1796 case 0x5: r_0 = 0x5; break;
1797 case 0x6: r_0 = 0x6; break;
1798 case 0x7: r_0 = 0x7; break;
1799 case 0x8: r_0 = 0x8; break;
1800 case 0xa: r_0 = 0x9; break;
1801 case 0xc: r_0 = 0xa; break;
1802 case 0x10: r_0 = 0xb; break;
1803 case 0x20: r_0 = 0xc; break;
1804 case 0x40: r_0 = 0xd; break;
1805 case 0x80: r_0 = 0xe; break;
1806 default: r_0 = 0xf; break;
1807 }
1808 *valp = r_0;
1809 return 0;
e0001a05
NC		 1810}
1811
43cd72b9
BW		 1812static int
1813Operand_uimm8_decode (uint32 *valp)
e0001a05 1814{
43cd72b9
BW		 1815 unsigned uimm8_0, imm8_0;
1816 imm8_0 = *valp & 0xff;
1817 uimm8_0 = imm8_0;
1818 *valp = uimm8_0;
1819 return 0;
e0001a05
NC		 1820}
1821
43cd72b9
BW		 1822static int
1823Operand_uimm8_encode (uint32 *valp)
e0001a05 1824{
43cd72b9
BW		 1825 unsigned imm8_0, uimm8_0;
1826 uimm8_0 = *valp;
1827 imm8_0 = (uimm8_0 & 0xff);
1828 *valp = imm8_0;
1829 return 0;
e0001a05
NC		 1830}
1831
43cd72b9
BW		 1832static int
1833Operand_uimm8x2_decode (uint32 *valp)
e0001a05 1834{
43cd72b9
BW		 1835 unsigned uimm8x2_0, imm8_0;
1836 imm8_0 = *valp & 0xff;
1837 uimm8x2_0 = imm8_0 << 1;
1838 *valp = uimm8x2_0;
1839 return 0;
e0001a05
NC		 1840}
1841
43cd72b9
BW		 1842static int
1843Operand_uimm8x2_encode (uint32 *valp)
e0001a05 1844{
43cd72b9
BW		 1845 unsigned imm8_0, uimm8x2_0;
1846 uimm8x2_0 = *valp;
1847 imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
1848 *valp = imm8_0;
1849 return 0;
e0001a05
NC		 1850}
1851
43cd72b9
BW		 1852static int
1853Operand_uimm8x4_decode (uint32 *valp)
e0001a05 1854{
43cd72b9
BW		 1855 unsigned uimm8x4_0, imm8_0;
1856 imm8_0 = *valp & 0xff;
1857 uimm8x4_0 = imm8_0 << 2;
1858 *valp = uimm8x4_0;
1859 return 0;
e0001a05
NC		 1860}
1861
43cd72b9
BW		 1862static int
1863Operand_uimm8x4_encode (uint32 *valp)
e0001a05 1864{
43cd72b9
BW		 1865 unsigned imm8_0, uimm8x4_0;
1866 uimm8x4_0 = *valp;
1867 imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
1868 *valp = imm8_0;
1869 return 0;
e0001a05
NC		 1870}
1871
43cd72b9
BW		 1872static int
1873Operand_uimm4x16_decode (uint32 *valp)
e0001a05 1874{
43cd72b9
BW		 1875 unsigned uimm4x16_0, op2_0;
1876 op2_0 = *valp & 0xf;
1877 uimm4x16_0 = op2_0 << 4;
1878 *valp = uimm4x16_0;
1879 return 0;
e0001a05
NC		 1880}
1881
43cd72b9
BW		 1882static int
1883Operand_uimm4x16_encode (uint32 *valp)
e0001a05 1884{
43cd72b9
BW		 1885 unsigned op2_0, uimm4x16_0;
1886 uimm4x16_0 = *valp;
1887 op2_0 = ((uimm4x16_0 >> 4) & 0xf);
1888 *valp = op2_0;
1889 return 0;
e0001a05
NC		 1890}
1891
43cd72b9
BW		 1892static int
1893Operand_simm8_decode (uint32 *valp)
e0001a05 1894{
43cd72b9
BW		 1895 unsigned simm8_0, imm8_0;
1896 imm8_0 = *valp & 0xff;
1897 simm8_0 = ((int) imm8_0 << 24) >> 24;
1898 *valp = simm8_0;
1899 return 0;
e0001a05
NC		 1900}
1901
43cd72b9
BW		 1902static int
1903Operand_simm8_encode (uint32 *valp)
e0001a05 1904{
43cd72b9
BW		 1905 unsigned imm8_0, simm8_0;
1906 simm8_0 = *valp;
1907 imm8_0 = (simm8_0 & 0xff);
1908 *valp = imm8_0;
1909 return 0;
e0001a05
NC		 1910}
1911
43cd72b9
BW		 1912static int
1913Operand_simm8x256_decode (uint32 *valp)
e0001a05 1914{
43cd72b9
BW		 1915 unsigned simm8x256_0, imm8_0;
1916 imm8_0 = *valp & 0xff;
1917 simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
1918 *valp = simm8x256_0;
1919 return 0;
e0001a05
NC		 1920}
1921
43cd72b9
BW		 1922static int
1923Operand_simm8x256_encode (uint32 *valp)
e0001a05 1924{
43cd72b9
BW		 1925 unsigned imm8_0, simm8x256_0;
1926 simm8x256_0 = *valp;
1927 imm8_0 = ((simm8x256_0 >> 8) & 0xff);
1928 *valp = imm8_0;
1929 return 0;
e0001a05
NC		 1930}
1931
43cd72b9
BW		 1932static int
1933Operand_simm12b_decode (uint32 *valp)
e0001a05 1934{
43cd72b9
BW		 1935 unsigned simm12b_0, imm12b_0;
1936 imm12b_0 = *valp & 0xfff;
1937 simm12b_0 = ((int) imm12b_0 << 20) >> 20;
1938 *valp = simm12b_0;
1939 return 0;
e0001a05
NC		 1940}
1941
43cd72b9
BW		 1942static int
1943Operand_simm12b_encode (uint32 *valp)
e0001a05 1944{
43cd72b9
BW		 1945 unsigned imm12b_0, simm12b_0;
1946 simm12b_0 = *valp;
1947 imm12b_0 = (simm12b_0 & 0xfff);
1948 *valp = imm12b_0;
1949 return 0;
e0001a05
NC		 1950}
1951
43cd72b9
BW		 1952static int
1953Operand_msalp32_decode (uint32 *valp)
e0001a05 1954{
43cd72b9
BW		 1955 unsigned msalp32_0, sal_0;
1956 sal_0 = *valp & 0x1f;
1957 msalp32_0 = 0x20 - sal_0;
1958 *valp = msalp32_0;
1959 return 0;
e0001a05
NC		 1960}
1961
43cd72b9
BW		 1962static int
1963Operand_msalp32_encode (uint32 *valp)
e0001a05 1964{
43cd72b9
BW		 1965 unsigned sal_0, msalp32_0;
1966 msalp32_0 = *valp;
1967 sal_0 = (0x20 - msalp32_0) & 0x1f;
1968 *valp = sal_0;
1969 return 0;
e0001a05
NC		 1970}
1971
43cd72b9
BW		 1972static int
1973Operand_op2p1_decode (uint32 *valp)
e0001a05 1974{
43cd72b9
BW		 1975 unsigned op2p1_0, op2_0;
1976 op2_0 = *valp & 0xf;
1977 op2p1_0 = op2_0 + 0x1;
1978 *valp = op2p1_0;
1979 return 0;
e0001a05
NC		 1980}
1981
43cd72b9
BW		 1982static int
1983Operand_op2p1_encode (uint32 *valp)
e0001a05 1984{
43cd72b9
BW		 1985 unsigned op2_0, op2p1_0;
1986 op2p1_0 = *valp;
1987 op2_0 = (op2p1_0 - 0x1) & 0xf;
1988 *valp = op2_0;
1989 return 0;
e0001a05
NC		 1990}
1991
43cd72b9
BW		 1992static int
1993Operand_label8_decode (uint32 *valp)
e0001a05 1994{
43cd72b9
BW		 1995 unsigned label8_0, imm8_0;
1996 imm8_0 = *valp & 0xff;
1997 label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
1998 *valp = label8_0;
1999 return 0;
e0001a05
NC		 2000}
2001
43cd72b9
BW		 2002static int
2003Operand_label8_encode (uint32 *valp)
e0001a05 2004{
43cd72b9
BW		 2005 unsigned imm8_0, label8_0;
2006 label8_0 = *valp;
2007 imm8_0 = (label8_0 - 0x4) & 0xff;
2008 *valp = imm8_0;
2009 return 0;
e0001a05
NC		 2010}
2011
43cd72b9
BW		 2012static int
2013Operand_label8_ator (uint32 *valp, uint32 pc)
e0001a05 2014{
43cd72b9
BW		 2015 *valp -= pc;
2016 return 0;
e0001a05
NC		 2017}
2018
43cd72b9
BW		 2019static int
2020Operand_label8_rtoa (uint32 *valp, uint32 pc)
e0001a05 2021{
43cd72b9
BW		 2022 *valp += pc;
2023 return 0;
e0001a05
NC		 2024}
2025
43cd72b9
BW		 2026static int
2027Operand_ulabel8_decode (uint32 *valp)
e0001a05 2028{
43cd72b9
BW		 2029 unsigned ulabel8_0, imm8_0;
2030 imm8_0 = *valp & 0xff;
af4bed4b 2031 ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
43cd72b9
BW		 2032 *valp = ulabel8_0;
2033 return 0;
e0001a05
NC		 2034}
2035
43cd72b9
BW		 2036static int
2037Operand_ulabel8_encode (uint32 *valp)
e0001a05 2038{
43cd72b9
BW		 2039 unsigned imm8_0, ulabel8_0;
2040 ulabel8_0 = *valp;
2041 imm8_0 = (ulabel8_0 - 0x4) & 0xff;
2042 *valp = imm8_0;
2043 return 0;
e0001a05
NC		 2044}
2045
43cd72b9
BW		 2046static int
2047Operand_ulabel8_ator (uint32 *valp, uint32 pc)
e0001a05 2048{
43cd72b9
BW		 2049 *valp -= pc;
2050 return 0;
e0001a05
NC		 2051}
2052
43cd72b9
BW		 2053static int
2054Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
e0001a05 2055{
43cd72b9
BW		 2056 *valp += pc;
2057 return 0;
e0001a05
NC		 2058}
2059
43cd72b9
BW		 2060static int
2061Operand_label12_decode (uint32 *valp)
e0001a05 2062{
43cd72b9
BW		 2063 unsigned label12_0, imm12_0;
2064 imm12_0 = *valp & 0xfff;
2065 label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
2066 *valp = label12_0;
2067 return 0;
e0001a05
NC		 2068}
2069
43cd72b9
BW		 2070static int
2071Operand_label12_encode (uint32 *valp)
2072{
2073 unsigned imm12_0, label12_0;
2074 label12_0 = *valp;
2075 imm12_0 = (label12_0 - 0x4) & 0xfff;
2076 *valp = imm12_0;
2077 return 0;
2078}
e0001a05 2079
43cd72b9
BW		 2080static int
2081Operand_label12_ator (uint32 *valp, uint32 pc)
2082{
2083 *valp -= pc;
2084 return 0;
2085}
e0001a05 2086
43cd72b9
BW		 2087static int
2088Operand_label12_rtoa (uint32 *valp, uint32 pc)
2089{
2090 *valp += pc;
2091 return 0;
2092}
e0001a05 2093
43cd72b9
BW		 2094static int
2095Operand_soffset_decode (uint32 *valp)
2096{
2097 unsigned soffset_0, offset_0;
2098 offset_0 = *valp & 0x3ffff;
2099 soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
2100 *valp = soffset_0;
2101 return 0;
2102}
e0001a05 2103
43cd72b9
BW		 2104static int
2105Operand_soffset_encode (uint32 *valp)
e0001a05 2106{
43cd72b9
BW		 2107 unsigned offset_0, soffset_0;
2108 soffset_0 = *valp;
2109 offset_0 = (soffset_0 - 0x4) & 0x3ffff;
2110 *valp = offset_0;
2111 return 0;
e0001a05
NC		 2112}
2113
43cd72b9
BW		 2114static int
2115Operand_soffset_ator (uint32 *valp, uint32 pc)
e0001a05 2116{
43cd72b9
BW		 2117 *valp -= pc;
2118 return 0;
e0001a05
NC		 2119}
2120
43cd72b9
BW		 2121static int
2122Operand_soffset_rtoa (uint32 *valp, uint32 pc)
e0001a05 2123{
43cd72b9
BW		 2124 *valp += pc;
2125 return 0;
e0001a05
NC		 2126}
2127
43cd72b9
BW		 2128static int
2129Operand_uimm16x4_decode (uint32 *valp)
e0001a05 2130{
43cd72b9
BW		 2131 unsigned uimm16x4_0, imm16_0;
2132 imm16_0 = *valp & 0xffff;
af4bed4b 2133 uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
43cd72b9
BW		 2134 *valp = uimm16x4_0;
2135 return 0;
e0001a05
NC		 2136}
2137
43cd72b9
BW		 2138static int
2139Operand_uimm16x4_encode (uint32 *valp)
e0001a05 2140{
43cd72b9
BW		 2141 unsigned imm16_0, uimm16x4_0;
2142 uimm16x4_0 = *valp;
2143 imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
2144 *valp = imm16_0;
2145 return 0;
e0001a05
NC		 2146}
2147
43cd72b9
BW		 2148static int
2149Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
e0001a05 2150{
43cd72b9
BW		 2151 *valp -= ((pc + 3) & ~0x3);
2152 return 0;
e0001a05
NC		 2153}
2154
43cd72b9
BW		 2155static int
2156Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
2157{
2158 *valp += ((pc + 3) & ~0x3);
2159 return 0;
2160}
2161
2162static int
2163Operand_immt_decode (uint32 *valp)
2164{
2165 unsigned immt_0, t_0;
2166 t_0 = *valp & 0xf;
2167 immt_0 = t_0;
2168 *valp = immt_0;
2169 return 0;
2170}
2171
2172static int
2173Operand_immt_encode (uint32 *valp)
2174{
2175 unsigned t_0, immt_0;
2176 immt_0 = *valp;
2177 t_0 = immt_0 & 0xf;
2178 *valp = t_0;
2179 return 0;
2180}
2181
2182static int
2183Operand_imms_decode (uint32 *valp)
2184{
2185 unsigned imms_0, s_0;
2186 s_0 = *valp & 0xf;
2187 imms_0 = s_0;
2188 *valp = imms_0;
2189 return 0;
2190}
2191
2192static int
2193Operand_imms_encode (uint32 *valp)
2194{
2195 unsigned s_0, imms_0;
2196 imms_0 = *valp;
2197 s_0 = imms_0 & 0xf;
2198 *valp = s_0;
2199 return 0;
2200}
2201
33430bd0
BW		 2202static int
2203Operand_tp7_decode (uint32 *valp)
2204{
2205 unsigned tp7_0, t_0;
2206 t_0 = *valp & 0xf;
2207 tp7_0 = t_0 + 0x7;
2208 *valp = tp7_0;
2209 return 0;
2210}
2211
2212static int
2213Operand_tp7_encode (uint32 *valp)
2214{
2215 unsigned t_0, tp7_0;
2216 tp7_0 = *valp;
2217 t_0 = (tp7_0 - 0x7) & 0xf;
2218 *valp = t_0;
2219 return 0;
2220}
2221
2222static int
2223Operand_xt_wbr15_label_decode (uint32 *valp)
2224{
2225 unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
2226 xt_wbr15_imm_0 = *valp & 0x7fff;
2227 xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
2228 *valp = xt_wbr15_label_0;
2229 return 0;
2230}
2231
2232static int
2233Operand_xt_wbr15_label_encode (uint32 *valp)
2234{
2235 unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
2236 xt_wbr15_label_0 = *valp;
2237 xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
2238 *valp = xt_wbr15_imm_0;
2239 return 0;
2240}
2241
2242static int
2243Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
2244{
2245 *valp -= pc;
2246 return 0;
2247}
2248
2249static int
2250Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
2251{
2252 *valp += pc;
2253 return 0;
2254}
2255
2256static int
2257Operand_xt_wbr18_label_decode (uint32 *valp)
2258{
2259 unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
2260 xt_wbr18_imm_0 = *valp & 0x3ffff;
2261 xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
2262 *valp = xt_wbr18_label_0;
2263 return 0;
2264}
2265
2266static int
2267Operand_xt_wbr18_label_encode (uint32 *valp)
2268{
2269 unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
2270 xt_wbr18_label_0 = *valp;
2271 xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
2272 *valp = xt_wbr18_imm_0;
2273 return 0;
2274}
2275
2276static int
2277Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
2278{
2279 *valp -= pc;
2280 return 0;
2281}
2282
2283static int
2284Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
2285{
2286 *valp += pc;
2287 return 0;
2288}
2289
43cd72b9 2290static xtensa_operand_internal operands[] = {
56fb3749 2291 { "soffsetx4", FIELD_offset, -1, 0,
43cd72b9
BW		 2292 XTENSA_OPERAND_IS_PCRELATIVE,
2293 Operand_soffsetx4_encode, Operand_soffsetx4_decode,
2294 Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
56fb3749 2295 { "uimm12x8", FIELD_imm12, -1, 0,
43cd72b9
BW		 2296 0,
2297 Operand_uimm12x8_encode, Operand_uimm12x8_decode,
2298 0, 0 },
56fb3749 2299 { "simm4", FIELD_mn, -1, 0,
43cd72b9
BW		 2300 0,
2301 Operand_simm4_encode, Operand_simm4_decode,
2302 0, 0 },
56fb3749 2303 { "arr", FIELD_r, REGFILE_AR, 1,
43cd72b9
BW		 2304 XTENSA_OPERAND_IS_REGISTER,
2305 Operand_arr_encode, Operand_arr_decode,
2306 0, 0 },
56fb3749 2307 { "ars", FIELD_s, REGFILE_AR, 1,
43cd72b9
BW		 2308 XTENSA_OPERAND_IS_REGISTER,
2309 Operand_ars_encode, Operand_ars_decode,
2310 0, 0 },
56fb3749 2311 { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
43cd72b9
BW		 2312 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2313 Operand_ars_encode, Operand_ars_decode,
2314 0, 0 },
56fb3749 2315 { "art", FIELD_t, REGFILE_AR, 1,
43cd72b9
BW		 2316 XTENSA_OPERAND_IS_REGISTER,
2317 Operand_art_encode, Operand_art_decode,
2318 0, 0 },
56fb3749 2319 { "ar0", FIELD__ar0, REGFILE_AR, 1,
43cd72b9
BW		 2320 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2321 Operand_ar0_encode, Operand_ar0_decode,
2322 0, 0 },
56fb3749 2323 { "ar4", FIELD__ar4, REGFILE_AR, 1,
43cd72b9
BW		 2324 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2325 Operand_ar4_encode, Operand_ar4_decode,
2326 0, 0 },
56fb3749 2327 { "ar8", FIELD__ar8, REGFILE_AR, 1,
43cd72b9
BW		 2328 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2329 Operand_ar8_encode, Operand_ar8_decode,
2330 0, 0 },
56fb3749 2331 { "ar12", FIELD__ar12, REGFILE_AR, 1,
43cd72b9
BW		 2332 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2333 Operand_ar12_encode, Operand_ar12_decode,
2334 0, 0 },
56fb3749 2335 { "ars_entry", FIELD_s, REGFILE_AR, 1,
43cd72b9
BW		 2336 XTENSA_OPERAND_IS_REGISTER,
2337 Operand_ars_entry_encode, Operand_ars_entry_decode,
2338 0, 0 },
56fb3749 2339 { "immrx4", FIELD_r, -1, 0,
43cd72b9
BW		 2340 0,
2341 Operand_immrx4_encode, Operand_immrx4_decode,
2342 0, 0 },
56fb3749 2343 { "lsi4x4", FIELD_r, -1, 0,
43cd72b9
BW		 2344 0,
2345 Operand_lsi4x4_encode, Operand_lsi4x4_decode,
2346 0, 0 },
56fb3749 2347 { "simm7", FIELD_imm7, -1, 0,
43cd72b9
BW		 2348 0,
2349 Operand_simm7_encode, Operand_simm7_decode,
2350 0, 0 },
56fb3749 2351 { "uimm6", FIELD_imm6, -1, 0,
43cd72b9
BW		 2352 XTENSA_OPERAND_IS_PCRELATIVE,
2353 Operand_uimm6_encode, Operand_uimm6_decode,
2354 Operand_uimm6_ator, Operand_uimm6_rtoa },
56fb3749 2355 { "ai4const", FIELD_t, -1, 0,
43cd72b9
BW		 2356 0,
2357 Operand_ai4const_encode, Operand_ai4const_decode,
2358 0, 0 },
56fb3749 2359 { "b4const", FIELD_r, -1, 0,
43cd72b9
BW		 2360 0,
2361 Operand_b4const_encode, Operand_b4const_decode,
2362 0, 0 },
56fb3749 2363 { "b4constu", FIELD_r, -1, 0,
43cd72b9
BW		 2364 0,
2365 Operand_b4constu_encode, Operand_b4constu_decode,
2366 0, 0 },
56fb3749 2367 { "uimm8", FIELD_imm8, -1, 0,
43cd72b9
BW		 2368 0,
2369 Operand_uimm8_encode, Operand_uimm8_decode,
2370 0, 0 },
56fb3749 2371 { "uimm8x2", FIELD_imm8, -1, 0,
43cd72b9
BW		 2372 0,
2373 Operand_uimm8x2_encode, Operand_uimm8x2_decode,
2374 0, 0 },
56fb3749 2375 { "uimm8x4", FIELD_imm8, -1, 0,
43cd72b9
BW		 2376 0,
2377 Operand_uimm8x4_encode, Operand_uimm8x4_decode,
2378 0, 0 },
56fb3749 2379 { "uimm4x16", FIELD_op2, -1, 0,
43cd72b9
BW		 2380 0,
2381 Operand_uimm4x16_encode, Operand_uimm4x16_decode,
2382 0, 0 },
56fb3749 2383 { "simm8", FIELD_imm8, -1, 0,
43cd72b9
BW		 2384 0,
2385 Operand_simm8_encode, Operand_simm8_decode,
2386 0, 0 },
56fb3749 2387 { "simm8x256", FIELD_imm8, -1, 0,
43cd72b9
BW		 2388 0,
2389 Operand_simm8x256_encode, Operand_simm8x256_decode,
2390 0, 0 },
56fb3749 2391 { "simm12b", FIELD_imm12b, -1, 0,
43cd72b9
BW		 2392 0,
2393 Operand_simm12b_encode, Operand_simm12b_decode,
2394 0, 0 },
56fb3749 2395 { "msalp32", FIELD_sal, -1, 0,
43cd72b9
BW		 2396 0,
2397 Operand_msalp32_encode, Operand_msalp32_decode,
2398 0, 0 },
56fb3749 2399 { "op2p1", FIELD_op2, -1, 0,
43cd72b9
BW		 2400 0,
2401 Operand_op2p1_encode, Operand_op2p1_decode,
2402 0, 0 },
56fb3749 2403 { "label8", FIELD_imm8, -1, 0,
43cd72b9
BW		 2404 XTENSA_OPERAND_IS_PCRELATIVE,
2405 Operand_label8_encode, Operand_label8_decode,
2406 Operand_label8_ator, Operand_label8_rtoa },
56fb3749 2407 { "ulabel8", FIELD_imm8, -1, 0,
43cd72b9
BW		 2408 XTENSA_OPERAND_IS_PCRELATIVE,
2409 Operand_ulabel8_encode, Operand_ulabel8_decode,
2410 Operand_ulabel8_ator, Operand_ulabel8_rtoa },
56fb3749 2411 { "label12", FIELD_imm12, -1, 0,
43cd72b9
BW		 2412 XTENSA_OPERAND_IS_PCRELATIVE,
2413 Operand_label12_encode, Operand_label12_decode,
2414 Operand_label12_ator, Operand_label12_rtoa },
56fb3749 2415 { "soffset", FIELD_offset, -1, 0,
43cd72b9
BW		 2416 XTENSA_OPERAND_IS_PCRELATIVE,
2417 Operand_soffset_encode, Operand_soffset_decode,
2418 Operand_soffset_ator, Operand_soffset_rtoa },
56fb3749 2419 { "uimm16x4", FIELD_imm16, -1, 0,
43cd72b9
BW		 2420 XTENSA_OPERAND_IS_PCRELATIVE,
2421 Operand_uimm16x4_encode, Operand_uimm16x4_decode,
2422 Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
56fb3749 2423 { "immt", FIELD_t, -1, 0,
43cd72b9
BW		 2424 0,
2425 Operand_immt_encode, Operand_immt_decode,
2426 0, 0 },
56fb3749 2427 { "imms", FIELD_s, -1, 0,
43cd72b9
BW		 2428 0,
2429 Operand_imms_encode, Operand_imms_decode,
2430 0, 0 },
56fb3749 2431 { "tp7", FIELD_t, -1, 0,
33430bd0
BW		 2432 0,
2433 Operand_tp7_encode, Operand_tp7_decode,
2434 0, 0 },
56fb3749 2435 { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
33430bd0
BW		 2436 XTENSA_OPERAND_IS_PCRELATIVE,
2437 Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
2438 Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
56fb3749 2439 { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
33430bd0
BW		 2440 XTENSA_OPERAND_IS_PCRELATIVE,
2441 Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
2442 Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
56fb3749
SA		 2443 { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
2444 { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
2445 { "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 },
2446 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
2447 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
2448 { "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 },
2449 { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
2450 { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
2451 { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
2452 { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
2453 { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
2454 { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
2455 { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
2456 { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
2457 { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
2458 { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
2459 { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
2460 { "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 },
2461 { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
2462 { "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 },
2463 { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
2464 { "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 },
2465 { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
2466 { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
2467 { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
2468 { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
2469 { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
2470 { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
2471 { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
2472 { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
2473 { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
2474 { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
2475 { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
2476 { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
2477 { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
2478 { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
2479 { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }
2480};
2481
2482enum xtensa_operand_id {
2483 OPERAND_soffsetx4,
2484 OPERAND_uimm12x8,
2485 OPERAND_simm4,
2486 OPERAND_arr,
2487 OPERAND_ars,
2488 OPERAND__ars_invisible,
2489 OPERAND_art,
2490 OPERAND_ar0,
2491 OPERAND_ar4,
2492 OPERAND_ar8,
2493 OPERAND_ar12,
2494 OPERAND_ars_entry,
2495 OPERAND_immrx4,
2496 OPERAND_lsi4x4,
2497 OPERAND_simm7,
2498 OPERAND_uimm6,
2499 OPERAND_ai4const,
2500 OPERAND_b4const,
2501 OPERAND_b4constu,
2502 OPERAND_uimm8,
2503 OPERAND_uimm8x2,
2504 OPERAND_uimm8x4,
2505 OPERAND_uimm4x16,
2506 OPERAND_simm8,
2507 OPERAND_simm8x256,
2508 OPERAND_simm12b,
2509 OPERAND_msalp32,
2510 OPERAND_op2p1,
2511 OPERAND_label8,
2512 OPERAND_ulabel8,
2513 OPERAND_label12,
2514 OPERAND_soffset,
2515 OPERAND_uimm16x4,
2516 OPERAND_immt,
2517 OPERAND_imms,
2518 OPERAND_tp7,
2519 OPERAND_xt_wbr15_label,
2520 OPERAND_xt_wbr18_label,
2521 OPERAND_t,
2522 OPERAND_bbi4,
2523 OPERAND_bbi,
2524 OPERAND_imm12,
2525 OPERAND_imm8,
2526 OPERAND_s,
2527 OPERAND_imm12b,
2528 OPERAND_imm16,
2529 OPERAND_m,
2530 OPERAND_n,
2531 OPERAND_offset,
2532 OPERAND_op0,
2533 OPERAND_op1,
2534 OPERAND_op2,
2535 OPERAND_r,
2536 OPERAND_sa4,
2537 OPERAND_sae4,
2538 OPERAND_sae,
2539 OPERAND_sal,
2540 OPERAND_sargt,
2541 OPERAND_sas4,
2542 OPERAND_sas,
2543 OPERAND_sr,
2544 OPERAND_st,
2545 OPERAND_thi3,
2546 OPERAND_imm4,
2547 OPERAND_mn,
2548 OPERAND_i,
2549 OPERAND_imm6lo,
2550 OPERAND_imm6hi,
2551 OPERAND_imm7lo,
2552 OPERAND_imm7hi,
2553 OPERAND_z,
2554 OPERAND_imm6,
2555 OPERAND_imm7,
2556 OPERAND_xt_wbr15_imm,
2557 OPERAND_xt_wbr18_imm
43cd72b9
BW		 2558};
2559
2560\f
2561/* Iclass table. */
2562
2563static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
074f5109
BW		 2564 { { STATE_PSRING }, 'i' },
2565 { { STATE_PSEXCM }, 'm' },
43cd72b9
BW		 2566 { { STATE_EPC1 }, 'i' }
2567};
2568
2569static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
074f5109
BW		 2570 { { STATE_PSEXCM }, 'i' },
2571 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 2572 { { STATE_DEPC }, 'i' }
2573};
2574
2575static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
56fb3749
SA		 2576 { { OPERAND_soffsetx4 }, 'i' },
2577 { { OPERAND_ar12 }, 'o' }
43cd72b9
BW		 2578};
2579
2580static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
2581 { { STATE_PSCALLINC }, 'o' }
2582};
2583
2584static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
56fb3749
SA		 2585 { { OPERAND_soffsetx4 }, 'i' },
2586 { { OPERAND_ar8 }, 'o' }
e0001a05
NC		 2587};
2588
43cd72b9
BW		 2589static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
2590 { { STATE_PSCALLINC }, 'o' }
e0001a05
NC		 2591};
2592
43cd72b9 2593static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
56fb3749
SA		 2594 { { OPERAND_soffsetx4 }, 'i' },
2595 { { OPERAND_ar4 }, 'o' }
e0001a05
NC		 2596};
2597
43cd72b9
BW		 2598static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
2599 { { STATE_PSCALLINC }, 'o' }
e0001a05
NC		 2600};
2601
43cd72b9 2602static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
56fb3749
SA		 2603 { { OPERAND_ars }, 'i' },
2604 { { OPERAND_ar12 }, 'o' }
e0001a05
NC		 2605};
2606
43cd72b9
BW		 2607static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
2608 { { STATE_PSCALLINC }, 'o' }
e0001a05
NC		 2609};
2610
43cd72b9 2611static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
56fb3749
SA		 2612 { { OPERAND_ars }, 'i' },
2613 { { OPERAND_ar8 }, 'o' }
e0001a05
NC		 2614};
2615
43cd72b9
BW		 2616static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
2617 { { STATE_PSCALLINC }, 'o' }
e0001a05
NC		 2618};
2619
43cd72b9 2620static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
56fb3749
SA		 2621 { { OPERAND_ars }, 'i' },
2622 { { OPERAND_ar4 }, 'o' }
e0001a05
NC		 2623};
2624
43cd72b9
BW		 2625static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
2626 { { STATE_PSCALLINC }, 'o' }
e0001a05
NC		 2627};
2628
43cd72b9 2629static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
56fb3749
SA		 2630 { { OPERAND_ars_entry }, 's' },
2631 { { OPERAND_ars }, 'i' },
2632 { { OPERAND_uimm12x8 }, 'i' }
e0001a05
NC		 2633};
2634
43cd72b9
BW		 2635static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
2636 { { STATE_PSCALLINC }, 'i' },
2637 { { STATE_PSEXCM }, 'i' },
2638 { { STATE_PSWOE }, 'i' },
2639 { { STATE_WindowBase }, 'm' },
2640 { { STATE_WindowStart }, 'm' }
e0001a05
NC		 2641};
2642
43cd72b9 2643static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
56fb3749
SA		 2644 { { OPERAND_art }, 'o' },
2645 { { OPERAND_ars }, 'i' }
e0001a05
NC		 2646};
2647
43cd72b9
BW		 2648static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
2649 { { STATE_WindowBase }, 'i' },
2650 { { STATE_WindowStart }, 'i' }
e0001a05
NC		 2651};
2652
43cd72b9 2653static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
56fb3749 2654 { { OPERAND_simm4 }, 'i' }
e0001a05
NC		 2655};
2656
43cd72b9 2657static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
074f5109
BW		 2658 { { STATE_PSEXCM }, 'i' },
2659 { { STATE_PSRING }, 'i' },
43cd72b9 2660 { { STATE_WindowBase }, 'm' }
e0001a05
NC		 2661};
2662
43cd72b9 2663static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
56fb3749 2664 { { OPERAND__ars_invisible }, 'i' }
e0001a05
NC		 2665};
2666
43cd72b9
BW		 2667static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
2668 { { STATE_WindowBase }, 'm' },
2669 { { STATE_WindowStart }, 'm' },
2670 { { STATE_PSEXCM }, 'i' },
2671 { { STATE_PSWOE }, 'i' }
e0001a05
NC		 2672};
2673
43cd72b9
BW		 2674static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
2675 { { STATE_EPC1 }, 'i' },
074f5109
BW		 2676 { { STATE_PSEXCM }, 'm' },
2677 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 2678 { { STATE_WindowBase }, 'm' },
2679 { { STATE_WindowStart }, 'm' },
2680 { { STATE_PSOWB }, 'i' }
e0001a05
NC		 2681};
2682
43cd72b9 2683static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
56fb3749
SA		 2684 { { OPERAND_art }, 'o' },
2685 { { OPERAND_ars }, 'i' },
2686 { { OPERAND_immrx4 }, 'i' }
e0001a05
NC		 2687};
2688
074f5109
BW		 2689static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
2690 { { STATE_PSEXCM }, 'i' },
2691 { { STATE_PSRING }, 'i' }
2692};
2693
43cd72b9 2694static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
56fb3749
SA		 2695 { { OPERAND_art }, 'i' },
2696 { { OPERAND_ars }, 'i' },
2697 { { OPERAND_immrx4 }, 'i' }
e0001a05
NC		 2698};
2699
074f5109
BW		 2700static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
2701 { { STATE_PSEXCM }, 'i' },
2702 { { STATE_PSRING }, 'i' }
2703};
2704
43cd72b9 2705static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
56fb3749 2706 { { OPERAND_art }, 'o' }
e0001a05
NC		 2707};
2708
43cd72b9 2709static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
074f5109
BW		 2710 { { STATE_PSEXCM }, 'i' },
2711 { { STATE_PSRING }, 'i' },
43cd72b9 2712 { { STATE_WindowBase }, 'i' }
e0001a05
NC		 2713};
2714
43cd72b9 2715static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
56fb3749 2716 { { OPERAND_art }, 'i' }
e0001a05
NC		 2717};
2718
43cd72b9 2719static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
074f5109
BW		 2720 { { STATE_PSEXCM }, 'i' },
2721 { { STATE_PSRING }, 'i' },
43cd72b9 2722 { { STATE_WindowBase }, 'o' }
e0001a05
NC		 2723};
2724
43cd72b9 2725static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
56fb3749 2726 { { OPERAND_art }, 'm' }
e0001a05
NC		 2727};
2728
43cd72b9 2729static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
074f5109
BW		 2730 { { STATE_PSEXCM }, 'i' },
2731 { { STATE_PSRING }, 'i' },
43cd72b9 2732 { { STATE_WindowBase }, 'm' }
e0001a05
NC		 2733};
2734
43cd72b9 2735static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
56fb3749 2736 { { OPERAND_art }, 'o' }
e0001a05
NC		 2737};
2738
43cd72b9 2739static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
074f5109
BW		 2740 { { STATE_PSEXCM }, 'i' },
2741 { { STATE_PSRING }, 'i' },
43cd72b9 2742 { { STATE_WindowStart }, 'i' }
e0001a05
NC		 2743};
2744
43cd72b9 2745static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
56fb3749 2746 { { OPERAND_art }, 'i' }
e0001a05
NC		 2747};
2748
43cd72b9 2749static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
074f5109
BW		 2750 { { STATE_PSEXCM }, 'i' },
2751 { { STATE_PSRING }, 'i' },
43cd72b9 2752 { { STATE_WindowStart }, 'o' }
e0001a05
NC		 2753};
2754
43cd72b9 2755static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
56fb3749 2756 { { OPERAND_art }, 'm' }
e0001a05
NC		 2757};
2758
43cd72b9 2759static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
074f5109
BW		 2760 { { STATE_PSEXCM }, 'i' },
2761 { { STATE_PSRING }, 'i' },
43cd72b9 2762 { { STATE_WindowStart }, 'm' }
e0001a05
NC		 2763};
2764
43cd72b9 2765static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
56fb3749
SA		 2766 { { OPERAND_arr }, 'o' },
2767 { { OPERAND_ars }, 'i' },
2768 { { OPERAND_art }, 'i' }
e0001a05
NC		 2769};
2770
43cd72b9 2771static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
56fb3749
SA		 2772 { { OPERAND_arr }, 'o' },
2773 { { OPERAND_ars }, 'i' },
2774 { { OPERAND_ai4const }, 'i' }
e0001a05
NC		 2775};
2776
43cd72b9 2777static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
56fb3749
SA		 2778 { { OPERAND_ars }, 'i' },
2779 { { OPERAND_uimm6 }, 'i' }
e0001a05
NC		 2780};
2781
43cd72b9 2782static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
56fb3749
SA		 2783 { { OPERAND_art }, 'o' },
2784 { { OPERAND_ars }, 'i' },
2785 { { OPERAND_lsi4x4 }, 'i' }
e0001a05
NC		 2786};
2787
43cd72b9 2788static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
56fb3749
SA		 2789 { { OPERAND_art }, 'o' },
2790 { { OPERAND_ars }, 'i' }
e0001a05
NC		 2791};
2792
43cd72b9 2793static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
56fb3749
SA		 2794 { { OPERAND_ars }, 'o' },
2795 { { OPERAND_simm7 }, 'i' }
e0001a05
NC		 2796};
2797
43cd72b9 2798static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
56fb3749 2799 { { OPERAND__ars_invisible }, 'i' }
e0001a05
NC		 2800};
2801
43cd72b9 2802static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
56fb3749
SA		 2803 { { OPERAND_art }, 'i' },
2804 { { OPERAND_ars }, 'i' },
2805 { { OPERAND_lsi4x4 }, 'i' }
e0001a05
NC		 2806};
2807
33430bd0 2808static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
56fb3749 2809 { { OPERAND_arr }, 'o' }
33430bd0
BW		 2810};
2811
2812static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
2813 { { STATE_THREADPTR }, 'i' }
2814};
2815
2816static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
56fb3749 2817 { { OPERAND_art }, 'i' }
33430bd0
BW		 2818};
2819
2820static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
2821 { { STATE_THREADPTR }, 'o' }
2822};
2823
43cd72b9 2824static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
56fb3749
SA		 2825 { { OPERAND_art }, 'o' },
2826 { { OPERAND_ars }, 'i' },
2827 { { OPERAND_simm8 }, 'i' }
e0001a05
NC		 2828};
2829
43cd72b9 2830static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
56fb3749
SA		 2831 { { OPERAND_art }, 'o' },
2832 { { OPERAND_ars }, 'i' },
2833 { { OPERAND_simm8x256 }, 'i' }
e0001a05
NC		 2834};
2835
43cd72b9 2836static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
56fb3749
SA		 2837 { { OPERAND_arr }, 'o' },
2838 { { OPERAND_ars }, 'i' },
2839 { { OPERAND_art }, 'i' }
e0001a05
NC		 2840};
2841
43cd72b9 2842static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
56fb3749
SA		 2843 { { OPERAND_arr }, 'o' },
2844 { { OPERAND_ars }, 'i' },
2845 { { OPERAND_art }, 'i' }
e0001a05
NC		 2846};
2847
43cd72b9 2848static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
56fb3749
SA		 2849 { { OPERAND_ars }, 'i' },
2850 { { OPERAND_b4const }, 'i' },
2851 { { OPERAND_label8 }, 'i' }
e0001a05
NC		 2852};
2853
43cd72b9 2854static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
56fb3749
SA		 2855 { { OPERAND_ars }, 'i' },
2856 { { OPERAND_bbi }, 'i' },
2857 { { OPERAND_label8 }, 'i' }
e0001a05
NC		 2858};
2859
43cd72b9 2860static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
56fb3749
SA		 2861 { { OPERAND_ars }, 'i' },
2862 { { OPERAND_b4constu }, 'i' },
2863 { { OPERAND_label8 }, 'i' }
e0001a05
NC		 2864};
2865
43cd72b9 2866static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
56fb3749
SA		 2867 { { OPERAND_ars }, 'i' },
2868 { { OPERAND_art }, 'i' },
2869 { { OPERAND_label8 }, 'i' }
e0001a05
NC		 2870};
2871
43cd72b9 2872static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
56fb3749
SA		 2873 { { OPERAND_ars }, 'i' },
2874 { { OPERAND_label12 }, 'i' }
e0001a05
NC		 2875};
2876
43cd72b9 2877static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
56fb3749
SA		 2878 { { OPERAND_soffsetx4 }, 'i' },
2879 { { OPERAND_ar0 }, 'o' }
e0001a05
NC		 2880};
2881
43cd72b9 2882static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
56fb3749
SA		 2883 { { OPERAND_ars }, 'i' },
2884 { { OPERAND_ar0 }, 'o' }
e0001a05
NC		 2885};
2886
43cd72b9 2887static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
56fb3749
SA		 2888 { { OPERAND_arr }, 'o' },
2889 { { OPERAND_art }, 'i' },
2890 { { OPERAND_sae }, 'i' },
2891 { { OPERAND_op2p1 }, 'i' }
e0001a05
NC		 2892};
2893
43cd72b9 2894static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
56fb3749 2895 { { OPERAND_soffset }, 'i' }
e0001a05
NC		 2896};
2897
43cd72b9 2898static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
56fb3749 2899 { { OPERAND_ars }, 'i' }
e0001a05
NC		 2900};
2901
43cd72b9 2902static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
56fb3749
SA		 2903 { { OPERAND_art }, 'o' },
2904 { { OPERAND_ars }, 'i' },
2905 { { OPERAND_uimm8x2 }, 'i' }
e0001a05
NC		 2906};
2907
43cd72b9 2908static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
56fb3749
SA		 2909 { { OPERAND_art }, 'o' },
2910 { { OPERAND_ars }, 'i' },
2911 { { OPERAND_uimm8x2 }, 'i' }
e0001a05
NC		 2912};
2913
43cd72b9 2914static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
56fb3749
SA		 2915 { { OPERAND_art }, 'o' },
2916 { { OPERAND_ars }, 'i' },
2917 { { OPERAND_uimm8x4 }, 'i' }
e0001a05
NC		 2918};
2919
43cd72b9 2920static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
56fb3749
SA		 2921 { { OPERAND_art }, 'o' },
2922 { { OPERAND_uimm16x4 }, 'i' }
e0001a05
NC		 2923};
2924
43cd72b9
BW		 2925static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
2926 { { STATE_LITBADDR }, 'i' },
2927 { { STATE_LITBEN }, 'i' }
e0001a05
NC		 2928};
2929
43cd72b9 2930static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
56fb3749
SA		 2931 { { OPERAND_art }, 'o' },
2932 { { OPERAND_ars }, 'i' },
2933 { { OPERAND_uimm8 }, 'i' }
e0001a05
NC		 2934};
2935
43cd72b9 2936static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
56fb3749
SA		 2937 { { OPERAND_ars }, 'i' },
2938 { { OPERAND_ulabel8 }, 'i' }
e0001a05
NC		 2939};
2940
43cd72b9
BW		 2941static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
2942 { { STATE_LBEG }, 'o' },
2943 { { STATE_LEND }, 'o' },
2944 { { STATE_LCOUNT }, 'o' }
e0001a05
NC		 2945};
2946
43cd72b9 2947static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
56fb3749
SA		 2948 { { OPERAND_ars }, 'i' },
2949 { { OPERAND_ulabel8 }, 'i' }
e0001a05
NC		 2950};
2951
43cd72b9
BW		 2952static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
2953 { { STATE_LBEG }, 'o' },
2954 { { STATE_LEND }, 'o' },
2955 { { STATE_LCOUNT }, 'o' }
e0001a05
NC		 2956};
2957
43cd72b9 2958static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
56fb3749
SA		 2959 { { OPERAND_art }, 'o' },
2960 { { OPERAND_simm12b }, 'i' }
e0001a05
NC		 2961};
2962
43cd72b9 2963static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
56fb3749
SA		 2964 { { OPERAND_arr }, 'm' },
2965 { { OPERAND_ars }, 'i' },
2966 { { OPERAND_art }, 'i' }
e0001a05
NC		 2967};
2968
43cd72b9 2969static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
56fb3749
SA		 2970 { { OPERAND_arr }, 'o' },
2971 { { OPERAND_art }, 'i' }
e0001a05
NC		 2972};
2973
43cd72b9 2974static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
56fb3749 2975 { { OPERAND__ars_invisible }, 'i' }
e0001a05
NC		 2976};
2977
43cd72b9 2978static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
56fb3749
SA		 2979 { { OPERAND_art }, 'i' },
2980 { { OPERAND_ars }, 'i' },
2981 { { OPERAND_uimm8x2 }, 'i' }
e0001a05
NC		 2982};
2983
43cd72b9 2984static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
56fb3749
SA		 2985 { { OPERAND_art }, 'i' },
2986 { { OPERAND_ars }, 'i' },
2987 { { OPERAND_uimm8x4 }, 'i' }
e0001a05
NC		 2988};
2989
43cd72b9 2990static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
56fb3749
SA		 2991 { { OPERAND_art }, 'i' },
2992 { { OPERAND_ars }, 'i' },
2993 { { OPERAND_uimm8 }, 'i' }
e0001a05
NC		 2994};
2995
43cd72b9 2996static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
56fb3749 2997 { { OPERAND_ars }, 'i' }
e0001a05
NC		 2998};
2999
43cd72b9
BW		 3000static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
3001 { { STATE_SAR }, 'o' }
e0001a05
NC		 3002};
3003
43cd72b9 3004static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
56fb3749 3005 { { OPERAND_sas }, 'i' }
e0001a05
NC		 3006};
3007
43cd72b9
BW		 3008static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
3009 { { STATE_SAR }, 'o' }
e0001a05
NC		 3010};
3011
43cd72b9 3012static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
56fb3749
SA		 3013 { { OPERAND_arr }, 'o' },
3014 { { OPERAND_ars }, 'i' }
e0001a05
NC		 3015};
3016
43cd72b9
BW		 3017static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
3018 { { STATE_SAR }, 'i' }
e0001a05
NC		 3019};
3020
43cd72b9 3021static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
56fb3749
SA		 3022 { { OPERAND_arr }, 'o' },
3023 { { OPERAND_ars }, 'i' },
3024 { { OPERAND_art }, 'i' }
e0001a05
NC		 3025};
3026
43cd72b9
BW		 3027static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
3028 { { STATE_SAR }, 'i' }
e0001a05
NC		 3029};
3030
43cd72b9 3031static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
56fb3749
SA		 3032 { { OPERAND_arr }, 'o' },
3033 { { OPERAND_art }, 'i' }
e0001a05
NC		 3034};
3035
43cd72b9
BW		 3036static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
3037 { { STATE_SAR }, 'i' }
e0001a05
NC		 3038};
3039
43cd72b9 3040static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
56fb3749
SA		 3041 { { OPERAND_arr }, 'o' },
3042 { { OPERAND_ars }, 'i' },
3043 { { OPERAND_msalp32 }, 'i' }
e0001a05
NC		 3044};
3045
43cd72b9 3046static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
56fb3749
SA		 3047 { { OPERAND_arr }, 'o' },
3048 { { OPERAND_art }, 'i' },
3049 { { OPERAND_sargt }, 'i' }
e0001a05
NC		 3050};
3051
43cd72b9 3052static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
56fb3749
SA		 3053 { { OPERAND_arr }, 'o' },
3054 { { OPERAND_art }, 'i' },
3055 { { OPERAND_s }, 'i' }
e0001a05
NC		 3056};
3057
43cd72b9
BW		 3058static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
3059 { { STATE_XTSYNC }, 'i' }
e0001a05
NC		 3060};
3061
43cd72b9 3062static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
56fb3749
SA		 3063 { { OPERAND_art }, 'o' },
3064 { { OPERAND_s }, 'i' }
e0001a05
NC		 3065};
3066
43cd72b9
BW		 3067static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
3068 { { STATE_PSWOE }, 'i' },
3069 { { STATE_PSCALLINC }, 'i' },
3070 { { STATE_PSOWB }, 'i' },
074f5109 3071 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 3072 { { STATE_PSUM }, 'i' },
3073 { { STATE_PSEXCM }, 'i' },
3074 { { STATE_PSINTLEVEL }, 'm' }
e0001a05
NC		 3075};
3076
43cd72b9 3077static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
56fb3749 3078 { { OPERAND_art }, 'o' }
e0001a05
NC		 3079};
3080
43cd72b9
BW		 3081static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
3082 { { STATE_LEND }, 'i' }
e0001a05
NC		 3083};
3084
43cd72b9 3085static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
56fb3749 3086 { { OPERAND_art }, 'i' }
e0001a05
NC		 3087};
3088
43cd72b9
BW		 3089static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
3090 { { STATE_LEND }, 'o' }
e0001a05
NC		 3091};
3092
43cd72b9 3093static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
56fb3749 3094 { { OPERAND_art }, 'm' }
e0001a05
NC		 3095};
3096
43cd72b9
BW		 3097static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
3098 { { STATE_LEND }, 'm' }
e0001a05
NC		 3099};
3100
43cd72b9 3101static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
56fb3749 3102 { { OPERAND_art }, 'o' }
e0001a05
NC		 3103};
3104
43cd72b9
BW		 3105static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
3106 { { STATE_LCOUNT }, 'i' }
e0001a05
NC		 3107};
3108
43cd72b9 3109static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
56fb3749 3110 { { OPERAND_art }, 'i' }
e0001a05
NC		 3111};
3112
43cd72b9
BW		 3113static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
3114 { { STATE_XTSYNC }, 'o' },
3115 { { STATE_LCOUNT }, 'o' }
e0001a05
NC		 3116};
3117
43cd72b9 3118static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
56fb3749 3119 { { OPERAND_art }, 'm' }
e0001a05
NC		 3120};
3121
43cd72b9
BW		 3122static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
3123 { { STATE_XTSYNC }, 'o' },
3124 { { STATE_LCOUNT }, 'm' }
e0001a05
NC		 3125};
3126
43cd72b9 3127static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
56fb3749 3128 { { OPERAND_art }, 'o' }
e0001a05
NC		 3129};
3130
43cd72b9
BW		 3131static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
3132 { { STATE_LBEG }, 'i' }
e0001a05
NC		 3133};
3134
43cd72b9 3135static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
56fb3749 3136 { { OPERAND_art }, 'i' }
e0001a05
NC		 3137};
3138
43cd72b9
BW		 3139static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
3140 { { STATE_LBEG }, 'o' }
e0001a05
NC		 3141};
3142
43cd72b9 3143static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
56fb3749 3144 { { OPERAND_art }, 'm' }
e0001a05
NC		 3145};
3146
43cd72b9
BW		 3147static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
3148 { { STATE_LBEG }, 'm' }
e0001a05
NC		 3149};
3150
43cd72b9 3151static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
56fb3749 3152 { { OPERAND_art }, 'o' }
e0001a05
NC		 3153};
3154
43cd72b9
BW		 3155static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
3156 { { STATE_SAR }, 'i' }
e0001a05
NC		 3157};
3158
43cd72b9 3159static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
56fb3749 3160 { { OPERAND_art }, 'i' }
e0001a05
NC		 3161};
3162
43cd72b9
BW		 3163static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
3164 { { STATE_SAR }, 'o' },
3165 { { STATE_XTSYNC }, 'o' }
e0001a05
NC		 3166};
3167
43cd72b9 3168static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
56fb3749 3169 { { OPERAND_art }, 'm' }
e0001a05
NC		 3170};
3171
43cd72b9
BW		 3172static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
3173 { { STATE_SAR }, 'm' }
e0001a05
NC		 3174};
3175
43cd72b9 3176static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
56fb3749 3177 { { OPERAND_art }, 'o' }
e0001a05
NC		 3178};
3179
43cd72b9
BW		 3180static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
3181 { { STATE_LITBADDR }, 'i' },
3182 { { STATE_LITBEN }, 'i' }
e0001a05
NC		 3183};
3184
43cd72b9 3185static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
56fb3749 3186 { { OPERAND_art }, 'i' }
e0001a05
NC		 3187};
3188
43cd72b9
BW		 3189static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
3190 { { STATE_LITBADDR }, 'o' },
3191 { { STATE_LITBEN }, 'o' }
e0001a05
NC		 3192};
3193
43cd72b9 3194static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
56fb3749 3195 { { OPERAND_art }, 'm' }
e0001a05
NC		 3196};
3197
43cd72b9
BW		 3198static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
3199 { { STATE_LITBADDR }, 'm' },
3200 { { STATE_LITBEN }, 'm' }
e0001a05
NC		 3201};
3202
43cd72b9 3203static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
56fb3749 3204 { { OPERAND_art }, 'o' }
e0001a05
NC		 3205};
3206
074f5109
BW		 3207static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
3208 { { STATE_PSEXCM }, 'i' },
3209 { { STATE_PSRING }, 'i' }
3210};
3211
33430bd0 3212static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = {
56fb3749 3213 { { OPERAND_art }, 'i' }
33430bd0
BW		 3214};
3215
3216static xtensa_arg_internal Iclass_xt_iclass_wsr_176_stateArgs[] = {
3217 { { STATE_PSEXCM }, 'i' },
3218 { { STATE_PSRING }, 'i' }
3219};
3220
43cd72b9 3221static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
56fb3749 3222 { { OPERAND_art }, 'o' }
e0001a05
NC		 3223};
3224
074f5109
BW		 3225static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
3226 { { STATE_PSEXCM }, 'i' },
3227 { { STATE_PSRING }, 'i' }
3228};
3229
43cd72b9 3230static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
56fb3749 3231 { { OPERAND_art }, 'o' }
e0001a05
NC		 3232};
3233
43cd72b9
BW		 3234static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
3235 { { STATE_PSWOE }, 'i' },
3236 { { STATE_PSCALLINC }, 'i' },
3237 { { STATE_PSOWB }, 'i' },
074f5109 3238 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 3239 { { STATE_PSUM }, 'i' },
3240 { { STATE_PSEXCM }, 'i' },
3241 { { STATE_PSINTLEVEL }, 'i' }
e0001a05
NC		 3242};
3243
43cd72b9 3244static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
56fb3749 3245 { { OPERAND_art }, 'i' }
e0001a05
NC		 3246};
3247
43cd72b9
BW		 3248static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
3249 { { STATE_PSWOE }, 'o' },
3250 { { STATE_PSCALLINC }, 'o' },
3251 { { STATE_PSOWB }, 'o' },
074f5109 3252 { { STATE_PSRING }, 'm' },
43cd72b9 3253 { { STATE_PSUM }, 'o' },
074f5109 3254 { { STATE_PSEXCM }, 'm' },
43cd72b9 3255 { { STATE_PSINTLEVEL }, 'o' }
e0001a05
NC		 3256};
3257
43cd72b9 3258static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
56fb3749 3259 { { OPERAND_art }, 'm' }
e0001a05
NC		 3260};
3261
43cd72b9
BW		 3262static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
3263 { { STATE_PSWOE }, 'm' },
3264 { { STATE_PSCALLINC }, 'm' },
3265 { { STATE_PSOWB }, 'm' },
074f5109 3266 { { STATE_PSRING }, 'm' },
43cd72b9
BW		 3267 { { STATE_PSUM }, 'm' },
3268 { { STATE_PSEXCM }, 'm' },
3269 { { STATE_PSINTLEVEL }, 'm' }
e0001a05
NC		 3270};
3271
43cd72b9 3272static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
56fb3749 3273 { { OPERAND_art }, 'o' }
e0001a05
NC		 3274};
3275
43cd72b9 3276static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
074f5109
BW		 3277 { { STATE_PSEXCM }, 'i' },
3278 { { STATE_PSRING }, 'i' },
43cd72b9 3279 { { STATE_EPC1 }, 'i' }
e0001a05
NC		 3280};
3281
43cd72b9 3282static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
56fb3749 3283 { { OPERAND_art }, 'i' }
e0001a05
NC		 3284};
3285
43cd72b9 3286static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
074f5109
BW		 3287 { { STATE_PSEXCM }, 'i' },
3288 { { STATE_PSRING }, 'i' },
43cd72b9 3289 { { STATE_EPC1 }, 'o' }
e0001a05
NC		 3290};
3291
43cd72b9 3292static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
56fb3749 3293 { { OPERAND_art }, 'm' }
e0001a05
NC		 3294};
3295
43cd72b9 3296static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
074f5109
BW		 3297 { { STATE_PSEXCM }, 'i' },
3298 { { STATE_PSRING }, 'i' },
43cd72b9 3299 { { STATE_EPC1 }, 'm' }
e0001a05
NC		 3300};
3301
43cd72b9 3302static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
56fb3749 3303 { { OPERAND_art }, 'o' }
e0001a05
NC		 3304};
3305
43cd72b9 3306static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
074f5109
BW		 3307 { { STATE_PSEXCM }, 'i' },
3308 { { STATE_PSRING }, 'i' },
43cd72b9 3309 { { STATE_EXCSAVE1 }, 'i' }
e0001a05
NC		 3310};
3311
43cd72b9 3312static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
56fb3749 3313 { { OPERAND_art }, 'i' }
e0001a05
NC		 3314};
3315
43cd72b9 3316static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
074f5109
BW		 3317 { { STATE_PSEXCM }, 'i' },
3318 { { STATE_PSRING }, 'i' },
43cd72b9 3319 { { STATE_EXCSAVE1 }, 'o' }
e0001a05
NC		 3320};
3321
43cd72b9 3322static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
56fb3749 3323 { { OPERAND_art }, 'm' }
e0001a05
NC		 3324};
3325
43cd72b9 3326static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
074f5109
BW		 3327 { { STATE_PSEXCM }, 'i' },
3328 { { STATE_PSRING }, 'i' },
43cd72b9 3329 { { STATE_EXCSAVE1 }, 'm' }
e0001a05
NC		 3330};
3331
43cd72b9 3332static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
56fb3749 3333 { { OPERAND_art }, 'o' }
e0001a05
NC		 3334};
3335
43cd72b9 3336static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
074f5109
BW		 3337 { { STATE_PSEXCM }, 'i' },
3338 { { STATE_PSRING }, 'i' },
43cd72b9 3339 { { STATE_EPC2 }, 'i' }
e0001a05
NC		 3340};
3341
43cd72b9 3342static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
56fb3749 3343 { { OPERAND_art }, 'i' }
e0001a05
NC		 3344};
3345
43cd72b9 3346static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
074f5109
BW		 3347 { { STATE_PSEXCM }, 'i' },
3348 { { STATE_PSRING }, 'i' },
43cd72b9 3349 { { STATE_EPC2 }, 'o' }
e0001a05
NC		 3350};
3351
43cd72b9 3352static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
56fb3749 3353 { { OPERAND_art }, 'm' }
e0001a05
NC		 3354};
3355
43cd72b9 3356static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
074f5109
BW		 3357 { { STATE_PSEXCM }, 'i' },
3358 { { STATE_PSRING }, 'i' },
43cd72b9 3359 { { STATE_EPC2 }, 'm' }
e0001a05
NC		 3360};
3361
43cd72b9 3362static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
56fb3749 3363 { { OPERAND_art }, 'o' }
e0001a05
NC		 3364};
3365
43cd72b9 3366static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
074f5109
BW		 3367 { { STATE_PSEXCM }, 'i' },
3368 { { STATE_PSRING }, 'i' },
43cd72b9 3369 { { STATE_EXCSAVE2 }, 'i' }
e0001a05
NC		 3370};
3371
43cd72b9 3372static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
56fb3749 3373 { { OPERAND_art }, 'i' }
e0001a05
NC		 3374};
3375
43cd72b9 3376static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
074f5109
BW		 3377 { { STATE_PSEXCM }, 'i' },
3378 { { STATE_PSRING }, 'i' },
43cd72b9 3379 { { STATE_EXCSAVE2 }, 'o' }
e0001a05
NC		 3380};
3381
43cd72b9 3382static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
56fb3749 3383 { { OPERAND_art }, 'm' }
e0001a05
NC		 3384};
3385
43cd72b9 3386static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
074f5109
BW		 3387 { { STATE_PSEXCM }, 'i' },
3388 { { STATE_PSRING }, 'i' },
43cd72b9 3389 { { STATE_EXCSAVE2 }, 'm' }
e0001a05
NC		 3390};
3391
43cd72b9 3392static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
56fb3749 3393 { { OPERAND_art }, 'o' }
e0001a05
NC		 3394};
3395
43cd72b9 3396static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
074f5109
BW		 3397 { { STATE_PSEXCM }, 'i' },
3398 { { STATE_PSRING }, 'i' },
43cd72b9 3399 { { STATE_EPC3 }, 'i' }
e0001a05
NC		 3400};
3401
43cd72b9 3402static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
56fb3749 3403 { { OPERAND_art }, 'i' }
e0001a05
NC		 3404};
3405
43cd72b9 3406static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
074f5109
BW		 3407 { { STATE_PSEXCM }, 'i' },
3408 { { STATE_PSRING }, 'i' },
43cd72b9 3409 { { STATE_EPC3 }, 'o' }
e0001a05
NC		 3410};
3411
43cd72b9 3412static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
56fb3749 3413 { { OPERAND_art }, 'm' }
e0001a05
NC		 3414};
3415
43cd72b9 3416static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
074f5109
BW		 3417 { { STATE_PSEXCM }, 'i' },
3418 { { STATE_PSRING }, 'i' },
43cd72b9 3419 { { STATE_EPC3 }, 'm' }
e0001a05
NC		 3420};
3421
43cd72b9 3422static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
56fb3749 3423 { { OPERAND_art }, 'o' }
e0001a05
NC		 3424};
3425
43cd72b9 3426static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
074f5109
BW		 3427 { { STATE_PSEXCM }, 'i' },
3428 { { STATE_PSRING }, 'i' },
43cd72b9 3429 { { STATE_EXCSAVE3 }, 'i' }
e0001a05
NC		 3430};
3431
43cd72b9 3432static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
56fb3749 3433 { { OPERAND_art }, 'i' }
e0001a05
NC		 3434};
3435
43cd72b9 3436static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
074f5109
BW		 3437 { { STATE_PSEXCM }, 'i' },
3438 { { STATE_PSRING }, 'i' },
43cd72b9 3439 { { STATE_EXCSAVE3 }, 'o' }
e0001a05
NC		 3440};
3441
43cd72b9 3442static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
56fb3749 3443 { { OPERAND_art }, 'm' }
e0001a05
NC		 3444};
3445
43cd72b9 3446static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
074f5109
BW		 3447 { { STATE_PSEXCM }, 'i' },
3448 { { STATE_PSRING }, 'i' },
43cd72b9 3449 { { STATE_EXCSAVE3 }, 'm' }
e0001a05
NC		 3450};
3451
43cd72b9 3452static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
56fb3749 3453 { { OPERAND_art }, 'o' }
e0001a05
NC		 3454};
3455
43cd72b9 3456static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
074f5109
BW		 3457 { { STATE_PSEXCM }, 'i' },
3458 { { STATE_PSRING }, 'i' },
43cd72b9 3459 { { STATE_EPC4 }, 'i' }
e0001a05
NC		 3460};
3461
43cd72b9 3462static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
56fb3749 3463 { { OPERAND_art }, 'i' }
e0001a05
NC		 3464};
3465
43cd72b9 3466static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
074f5109
BW		 3467 { { STATE_PSEXCM }, 'i' },
3468 { { STATE_PSRING }, 'i' },
43cd72b9 3469 { { STATE_EPC4 }, 'o' }
e0001a05
NC		 3470};
3471
43cd72b9 3472static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
56fb3749 3473 { { OPERAND_art }, 'm' }
e0001a05
NC		 3474};
3475
43cd72b9 3476static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
074f5109
BW		 3477 { { STATE_PSEXCM }, 'i' },
3478 { { STATE_PSRING }, 'i' },
43cd72b9 3479 { { STATE_EPC4 }, 'm' }
e0001a05
NC		 3480};
3481
43cd72b9 3482static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
56fb3749 3483 { { OPERAND_art }, 'o' }
e0001a05
NC		 3484};
3485
43cd72b9 3486static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
074f5109
BW		 3487 { { STATE_PSEXCM }, 'i' },
3488 { { STATE_PSRING }, 'i' },
43cd72b9 3489 { { STATE_EXCSAVE4 }, 'i' }
e0001a05
NC		 3490};
3491
43cd72b9 3492static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
56fb3749 3493 { { OPERAND_art }, 'i' }
e0001a05
NC		 3494};
3495
43cd72b9 3496static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
074f5109
BW		 3497 { { STATE_PSEXCM }, 'i' },
3498 { { STATE_PSRING }, 'i' },
43cd72b9 3499 { { STATE_EXCSAVE4 }, 'o' }
e0001a05
NC		 3500};
3501
43cd72b9 3502static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
56fb3749 3503 { { OPERAND_art }, 'm' }
e0001a05
NC		 3504};
3505
43cd72b9 3506static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
074f5109
BW		 3507 { { STATE_PSEXCM }, 'i' },
3508 { { STATE_PSRING }, 'i' },
43cd72b9 3509 { { STATE_EXCSAVE4 }, 'm' }
e0001a05
NC		 3510};
3511
33430bd0 3512static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
56fb3749 3513 { { OPERAND_art }, 'o' }
e0001a05
NC		 3514};
3515
33430bd0 3516static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
074f5109
BW		 3517 { { STATE_PSEXCM }, 'i' },
3518 { { STATE_PSRING }, 'i' },
33430bd0 3519 { { STATE_EPC5 }, 'i' }
e0001a05
NC		 3520};
3521
33430bd0 3522static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
56fb3749 3523 { { OPERAND_art }, 'i' }
e0001a05
NC		 3524};
3525
33430bd0 3526static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
074f5109
BW		 3527 { { STATE_PSEXCM }, 'i' },
3528 { { STATE_PSRING }, 'i' },
33430bd0 3529 { { STATE_EPC5 }, 'o' }
e0001a05
NC		 3530};
3531
33430bd0 3532static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
56fb3749 3533 { { OPERAND_art }, 'm' }
e0001a05
NC		 3534};
3535
33430bd0 3536static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
074f5109
BW		 3537 { { STATE_PSEXCM }, 'i' },
3538 { { STATE_PSRING }, 'i' },
33430bd0 3539 { { STATE_EPC5 }, 'm' }
e0001a05
NC		 3540};
3541
33430bd0 3542static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
56fb3749 3543 { { OPERAND_art }, 'o' }
e0001a05
NC		 3544};
3545
33430bd0 3546static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
074f5109
BW		 3547 { { STATE_PSEXCM }, 'i' },
3548 { { STATE_PSRING }, 'i' },
33430bd0 3549 { { STATE_EXCSAVE5 }, 'i' }
e0001a05
NC		 3550};
3551
33430bd0 3552static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
56fb3749 3553 { { OPERAND_art }, 'i' }
43cd72b9 3554};
e0001a05 3555
33430bd0 3556static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
074f5109
BW		 3557 { { STATE_PSEXCM }, 'i' },
3558 { { STATE_PSRING }, 'i' },
33430bd0 3559 { { STATE_EXCSAVE5 }, 'o' }
43cd72b9 3560};
e0001a05 3561
33430bd0 3562static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
56fb3749 3563 { { OPERAND_art }, 'm' }
43cd72b9 3564};
e0001a05 3565
33430bd0 3566static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
074f5109
BW		 3567 { { STATE_PSEXCM }, 'i' },
3568 { { STATE_PSRING }, 'i' },
33430bd0 3569 { { STATE_EXCSAVE5 }, 'm' }
43cd72b9
BW		 3570};
3571
33430bd0 3572static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
56fb3749 3573 { { OPERAND_art }, 'o' }
43cd72b9
BW		 3574};
3575
33430bd0 3576static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
074f5109
BW		 3577 { { STATE_PSEXCM }, 'i' },
3578 { { STATE_PSRING }, 'i' },
33430bd0 3579 { { STATE_EPC6 }, 'i' }
43cd72b9
BW		 3580};
3581
33430bd0 3582static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
56fb3749 3583 { { OPERAND_art }, 'i' }
43cd72b9
BW		 3584};
3585
33430bd0 3586static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
074f5109
BW		 3587 { { STATE_PSEXCM }, 'i' },
3588 { { STATE_PSRING }, 'i' },
33430bd0 3589 { { STATE_EPC6 }, 'o' }
43cd72b9
BW		 3590};
3591
33430bd0 3592static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
56fb3749 3593 { { OPERAND_art }, 'm' }
43cd72b9
BW		 3594};
3595
33430bd0 3596static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
074f5109
BW		 3597 { { STATE_PSEXCM }, 'i' },
3598 { { STATE_PSRING }, 'i' },
33430bd0 3599 { { STATE_EPC6 }, 'm' }
43cd72b9
BW		 3600};
3601
33430bd0 3602static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
56fb3749 3603 { { OPERAND_art }, 'o' }
43cd72b9
BW		 3604};
3605
33430bd0 3606static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
074f5109
BW		 3607 { { STATE_PSEXCM }, 'i' },
3608 { { STATE_PSRING }, 'i' },
33430bd0 3609 { { STATE_EXCSAVE6 }, 'i' }
43cd72b9
BW		 3610};
3611
33430bd0 3612static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
56fb3749 3613 { { OPERAND_art }, 'i' }
43cd72b9
BW		 3614};
3615
33430bd0 3616static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
074f5109
BW		 3617 { { STATE_PSEXCM }, 'i' },
3618 { { STATE_PSRING }, 'i' },
33430bd0 3619 { { STATE_EXCSAVE6 }, 'o' }
43cd72b9
BW		 3620};
3621
33430bd0 3622static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
56fb3749 3623 { { OPERAND_art }, 'm' }
43cd72b9
BW		 3624};
3625
33430bd0 3626static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
074f5109
BW		 3627 { { STATE_PSEXCM }, 'i' },
3628 { { STATE_PSRING }, 'i' },
33430bd0 3629 { { STATE_EXCSAVE6 }, 'm' }
43cd72b9
BW		 3630};
3631
33430bd0 3632static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
56fb3749 3633 { { OPERAND_art }, 'o' }
43cd72b9
BW		 3634};
3635
33430bd0 3636static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
074f5109
BW		 3637 { { STATE_PSEXCM }, 'i' },
3638 { { STATE_PSRING }, 'i' },
33430bd0 3639 { { STATE_EPC7 }, 'i' }
43cd72b9
BW		 3640};
3641
33430bd0 3642static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
56fb3749 3643 { { OPERAND_art }, 'i' }
43cd72b9
BW		 3644};
3645
33430bd0 3646static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
074f5109
BW		 3647 { { STATE_PSEXCM }, 'i' },
3648 { { STATE_PSRING }, 'i' },
33430bd0 3649 { { STATE_EPC7 }, 'o' }
43cd72b9
BW		 3650};
3651
33430bd0 3652static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
56fb3749 3653 { { OPERAND_art }, 'm' }
43cd72b9
BW		 3654};
3655
33430bd0 3656static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
074f5109
BW		 3657 { { STATE_PSEXCM }, 'i' },
3658 { { STATE_PSRING }, 'i' },
33430bd0 3659 { { STATE_EPC7 }, 'm' }
43cd72b9
BW		 3660};
3661
33430bd0 3662static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
56fb3749 3663 { { OPERAND_art }, 'o' }
43cd72b9
BW		 3664};
3665
33430bd0 3666static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
074f5109
BW		 3667 { { STATE_PSEXCM }, 'i' },
3668 { { STATE_PSRING }, 'i' },
33430bd0 3669 { { STATE_EXCSAVE7 }, 'i' }
43cd72b9
BW		 3670};
3671
33430bd0 3672static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
56fb3749 3673 { { OPERAND_art }, 'i' }
43cd72b9
BW		 3674};
3675
33430bd0 3676static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
074f5109
BW		 3677 { { STATE_PSEXCM }, 'i' },
3678 { { STATE_PSRING }, 'i' },
33430bd0 3679 { { STATE_EXCSAVE7 }, 'o' }
43cd72b9
BW		 3680};
3681
33430bd0 3682static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
56fb3749 3683 { { OPERAND_art }, 'm' }
43cd72b9
BW		 3684};
3685
33430bd0 3686static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
074f5109
BW		 3687 { { STATE_PSEXCM }, 'i' },
3688 { { STATE_PSRING }, 'i' },
33430bd0 3689 { { STATE_EXCSAVE7 }, 'm' }
43cd72b9
BW		 3690};
3691
33430bd0 3692static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
56fb3749 3693 { { OPERAND_art }, 'o' }
43cd72b9
BW		 3694};
3695
33430bd0 3696static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
074f5109
BW		 3697 { { STATE_PSEXCM }, 'i' },
3698 { { STATE_PSRING }, 'i' },
33430bd0 3699 { { STATE_EPS2 }, 'i' }
43cd72b9
BW		 3700};
3701
33430bd0 3702static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
56fb3749 3703 { { OPERAND_art }, 'i' }
43cd72b9
BW		 3704};
3705
33430bd0 3706static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
074f5109
BW		 3707 { { STATE_PSEXCM }, 'i' },
3708 { { STATE_PSRING }, 'i' },
33430bd0 3709 { { STATE_EPS2 }, 'o' }
43cd72b9
BW		 3710};
3711
33430bd0 3712static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
56fb3749 3713 { { OPERAND_art }, 'm' }
43cd72b9
BW		 3714};
3715
33430bd0 3716static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
074f5109
BW		 3717 { { STATE_PSEXCM }, 'i' },
3718 { { STATE_PSRING }, 'i' },
33430bd0 3719 { { STATE_EPS2 }, 'm' }
43cd72b9
BW		 3720};
3721
33430bd0 3722static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
56fb3749 3723 { { OPERAND_art }, 'o' }
43cd72b9
BW		 3724};
3725
33430bd0 3726static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
074f5109
BW		 3727 { { STATE_PSEXCM }, 'i' },
3728 { { STATE_PSRING }, 'i' },
33430bd0 3729 { { STATE_EPS3 }, 'i' }
43cd72b9
BW		 3730};
3731
33430bd0 3732static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
56fb3749 3733 { { OPERAND_art }, 'i' }
43cd72b9
BW		 3734};
3735
33430bd0 3736static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
074f5109
BW		 3737 { { STATE_PSEXCM }, 'i' },
3738 { { STATE_PSRING }, 'i' },
33430bd0 3739 { { STATE_EPS3 }, 'o' }
43cd72b9
BW		 3740};
3741
33430bd0 3742static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
56fb3749 3743 { { OPERAND_art }, 'm' }
43cd72b9
BW		 3744};
3745
33430bd0 3746static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
074f5109
BW		 3747 { { STATE_PSEXCM }, 'i' },
3748 { { STATE_PSRING }, 'i' },
33430bd0 3749 { { STATE_EPS3 }, 'm' }
43cd72b9
BW		 3750};
3751
33430bd0 3752static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
56fb3749 3753 { { OPERAND_art }, 'o' }
43cd72b9
BW		 3754};
3755
33430bd0 3756static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
074f5109 3757 { { STATE_PSEXCM }, 'i' },
33430bd0
BW		 3758 { { STATE_PSRING }, 'i' },
3759 { { STATE_EPS4 }, 'i' }
074f5109
BW		 3760};
3761
33430bd0 3762static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
56fb3749 3763 { { OPERAND_art }, 'i' }
43cd72b9
BW		 3764};
3765
33430bd0
BW		 3766static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
3767 { { STATE_PSEXCM }, 'i' },
3768 { { STATE_PSRING }, 'i' },
3769 { { STATE_EPS4 }, 'o' }
3770};
3771
3772static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
56fb3749 3773 { { OPERAND_art }, 'm' }
33430bd0
BW		 3774};
3775
3776static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
3777 { { STATE_PSEXCM }, 'i' },
3778 { { STATE_PSRING }, 'i' },
3779 { { STATE_EPS4 }, 'm' }
3780};
3781
3782static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
56fb3749 3783 { { OPERAND_art }, 'o' }
33430bd0
BW		 3784};
3785
3786static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
3787 { { STATE_PSEXCM }, 'i' },
3788 { { STATE_PSRING }, 'i' },
3789 { { STATE_EPS5 }, 'i' }
3790};
3791
3792static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
56fb3749 3793 { { OPERAND_art }, 'i' }
33430bd0
BW		 3794};
3795
3796static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
3797 { { STATE_PSEXCM }, 'i' },
3798 { { STATE_PSRING }, 'i' },
3799 { { STATE_EPS5 }, 'o' }
3800};
3801
3802static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
56fb3749 3803 { { OPERAND_art }, 'm' }
33430bd0
BW		 3804};
3805
3806static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
3807 { { STATE_PSEXCM }, 'i' },
3808 { { STATE_PSRING }, 'i' },
3809 { { STATE_EPS5 }, 'm' }
3810};
3811
3812static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
56fb3749 3813 { { OPERAND_art }, 'o' }
33430bd0
BW		 3814};
3815
3816static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
3817 { { STATE_PSEXCM }, 'i' },
3818 { { STATE_PSRING }, 'i' },
3819 { { STATE_EPS6 }, 'i' }
3820};
3821
3822static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
56fb3749 3823 { { OPERAND_art }, 'i' }
33430bd0
BW		 3824};
3825
3826static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
3827 { { STATE_PSEXCM }, 'i' },
3828 { { STATE_PSRING }, 'i' },
3829 { { STATE_EPS6 }, 'o' }
3830};
3831
3832static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
56fb3749 3833 { { OPERAND_art }, 'm' }
33430bd0
BW		 3834};
3835
3836static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
3837 { { STATE_PSEXCM }, 'i' },
3838 { { STATE_PSRING }, 'i' },
3839 { { STATE_EPS6 }, 'm' }
3840};
3841
3842static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
56fb3749 3843 { { OPERAND_art }, 'o' }
33430bd0
BW		 3844};
3845
3846static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
3847 { { STATE_PSEXCM }, 'i' },
3848 { { STATE_PSRING }, 'i' },
3849 { { STATE_EPS7 }, 'i' }
3850};
3851
3852static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
56fb3749 3853 { { OPERAND_art }, 'i' }
33430bd0
BW		 3854};
3855
3856static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
3857 { { STATE_PSEXCM }, 'i' },
3858 { { STATE_PSRING }, 'i' },
3859 { { STATE_EPS7 }, 'o' }
3860};
3861
3862static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
56fb3749 3863 { { OPERAND_art }, 'm' }
33430bd0
BW		 3864};
3865
3866static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
3867 { { STATE_PSEXCM }, 'i' },
3868 { { STATE_PSRING }, 'i' },
3869 { { STATE_EPS7 }, 'm' }
3870};
3871
3872static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
56fb3749 3873 { { OPERAND_art }, 'o' }
33430bd0
BW		 3874};
3875
3876static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
3877 { { STATE_PSEXCM }, 'i' },
3878 { { STATE_PSRING }, 'i' },
3879 { { STATE_EXCVADDR }, 'i' }
3880};
3881
3882static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
56fb3749 3883 { { OPERAND_art }, 'i' }
33430bd0
BW		 3884};
3885
3886static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
3887 { { STATE_PSEXCM }, 'i' },
3888 { { STATE_PSRING }, 'i' },
3889 { { STATE_EXCVADDR }, 'o' }
3890};
3891
3892static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
56fb3749 3893 { { OPERAND_art }, 'm' }
33430bd0
BW		 3894};
3895
3896static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
3897 { { STATE_PSEXCM }, 'i' },
3898 { { STATE_PSRING }, 'i' },
3899 { { STATE_EXCVADDR }, 'm' }
3900};
3901
3902static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
56fb3749 3903 { { OPERAND_art }, 'o' }
33430bd0
BW		 3904};
3905
3906static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
3907 { { STATE_PSEXCM }, 'i' },
3908 { { STATE_PSRING }, 'i' },
3909 { { STATE_DEPC }, 'i' }
3910};
3911
3912static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
56fb3749 3913 { { OPERAND_art }, 'i' }
33430bd0
BW		 3914};
3915
3916static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
3917 { { STATE_PSEXCM }, 'i' },
3918 { { STATE_PSRING }, 'i' },
3919 { { STATE_DEPC }, 'o' }
3920};
3921
3922static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
56fb3749 3923 { { OPERAND_art }, 'm' }
33430bd0
BW		 3924};
3925
3926static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
3927 { { STATE_PSEXCM }, 'i' },
3928 { { STATE_PSRING }, 'i' },
3929 { { STATE_DEPC }, 'm' }
3930};
3931
3932static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
56fb3749 3933 { { OPERAND_art }, 'o' }
33430bd0
BW		 3934};
3935
3936static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
3937 { { STATE_PSEXCM }, 'i' },
3938 { { STATE_PSRING }, 'i' },
3939 { { STATE_EXCCAUSE }, 'i' },
3940 { { STATE_XTSYNC }, 'i' }
3941};
3942
3943static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
56fb3749 3944 { { OPERAND_art }, 'i' }
33430bd0
BW		 3945};
3946
3947static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
3948 { { STATE_PSEXCM }, 'i' },
3949 { { STATE_PSRING }, 'i' },
3950 { { STATE_EXCCAUSE }, 'o' }
3951};
3952
3953static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
56fb3749 3954 { { OPERAND_art }, 'm' }
33430bd0
BW		 3955};
3956
3957static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
3958 { { STATE_PSEXCM }, 'i' },
3959 { { STATE_PSRING }, 'i' },
3960 { { STATE_EXCCAUSE }, 'm' }
3961};
3962
3963static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
56fb3749 3964 { { OPERAND_art }, 'o' }
33430bd0
BW		 3965};
3966
3967static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
3968 { { STATE_PSEXCM }, 'i' },
3969 { { STATE_PSRING }, 'i' },
3970 { { STATE_MISC0 }, 'i' }
3971};
3972
3973static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
56fb3749 3974 { { OPERAND_art }, 'i' }
33430bd0
BW		 3975};
3976
3977static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
3978 { { STATE_PSEXCM }, 'i' },
3979 { { STATE_PSRING }, 'i' },
3980 { { STATE_MISC0 }, 'o' }
3981};
3982
3983static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
56fb3749 3984 { { OPERAND_art }, 'm' }
33430bd0
BW		 3985};
3986
3987static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
3988 { { STATE_PSEXCM }, 'i' },
3989 { { STATE_PSRING }, 'i' },
3990 { { STATE_MISC0 }, 'm' }
3991};
3992
3993static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
56fb3749 3994 { { OPERAND_art }, 'o' }
33430bd0
BW		 3995};
3996
3997static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
3998 { { STATE_PSEXCM }, 'i' },
3999 { { STATE_PSRING }, 'i' },
4000 { { STATE_MISC1 }, 'i' }
4001};
4002
4003static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
56fb3749 4004 { { OPERAND_art }, 'i' }
33430bd0
BW		 4005};
4006
4007static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
4008 { { STATE_PSEXCM }, 'i' },
4009 { { STATE_PSRING }, 'i' },
4010 { { STATE_MISC1 }, 'o' }
4011};
4012
4013static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
56fb3749 4014 { { OPERAND_art }, 'm' }
33430bd0
BW		 4015};
4016
4017static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
4018 { { STATE_PSEXCM }, 'i' },
4019 { { STATE_PSRING }, 'i' },
4020 { { STATE_MISC1 }, 'm' }
4021};
4022
4023static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
56fb3749 4024 { { OPERAND_art }, 'o' }
33430bd0
BW		 4025};
4026
4027static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
4028 { { STATE_PSEXCM }, 'i' },
4029 { { STATE_PSRING }, 'i' }
4030};
4031
4032static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
56fb3749 4033 { { OPERAND_art }, 'o' }
33430bd0
BW		 4034};
4035
4036static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
4037 { { STATE_PSEXCM }, 'i' },
4038 { { STATE_PSRING }, 'i' },
4039 { { STATE_VECBASE }, 'i' }
4040};
4041
4042static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
56fb3749 4043 { { OPERAND_art }, 'i' }
33430bd0
BW		 4044};
4045
4046static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
4047 { { STATE_PSEXCM }, 'i' },
4048 { { STATE_PSRING }, 'i' },
4049 { { STATE_VECBASE }, 'o' }
4050};
4051
4052static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
56fb3749 4053 { { OPERAND_art }, 'm' }
33430bd0
BW		 4054};
4055
4056static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
4057 { { STATE_PSEXCM }, 'i' },
4058 { { STATE_PSRING }, 'i' },
4059 { { STATE_VECBASE }, 'm' }
4060};
4061
4062static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = {
56fb3749
SA		 4063 { { OPERAND_arr }, 'o' },
4064 { { OPERAND_ars }, 'i' },
4065 { { OPERAND_art }, 'i' }
33430bd0
BW		 4066};
4067
4068static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
56fb3749 4069 { { OPERAND_s }, 'i' }
33430bd0
BW		 4070};
4071
4072static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
4073 { { STATE_PSWOE }, 'o' },
4074 { { STATE_PSCALLINC }, 'o' },
4075 { { STATE_PSOWB }, 'o' },
4076 { { STATE_PSRING }, 'm' },
4077 { { STATE_PSUM }, 'o' },
4078 { { STATE_PSEXCM }, 'm' },
4079 { { STATE_PSINTLEVEL }, 'o' },
4080 { { STATE_EPC1 }, 'i' },
4081 { { STATE_EPC2 }, 'i' },
4082 { { STATE_EPC3 }, 'i' },
4083 { { STATE_EPC4 }, 'i' },
4084 { { STATE_EPC5 }, 'i' },
4085 { { STATE_EPC6 }, 'i' },
4086 { { STATE_EPC7 }, 'i' },
4087 { { STATE_EPS2 }, 'i' },
4088 { { STATE_EPS3 }, 'i' },
4089 { { STATE_EPS4 }, 'i' },
4090 { { STATE_EPS5 }, 'i' },
4091 { { STATE_EPS6 }, 'i' },
4092 { { STATE_EPS7 }, 'i' },
4093 { { STATE_InOCDMode }, 'm' }
4094};
43cd72b9
BW		 4095
4096static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
56fb3749 4097 { { OPERAND_s }, 'i' }
43cd72b9
BW		 4098};
4099
4100static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
074f5109
BW		 4101 { { STATE_PSEXCM }, 'i' },
4102 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4103 { { STATE_PSINTLEVEL }, 'o' }
4104};
4105
4106static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
56fb3749 4107 { { OPERAND_art }, 'o' }
43cd72b9
BW		 4108};
4109
4110static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
074f5109
BW		 4111 { { STATE_PSEXCM }, 'i' },
4112 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4113 { { STATE_INTERRUPT }, 'i' }
4114};
4115
4116static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
56fb3749 4117 { { OPERAND_art }, 'i' }
43cd72b9
BW		 4118};
4119
4120static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
074f5109
BW		 4121 { { STATE_PSEXCM }, 'i' },
4122 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4123 { { STATE_XTSYNC }, 'o' },
4124 { { STATE_INTERRUPT }, 'm' }
4125};
4126
4127static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
56fb3749 4128 { { OPERAND_art }, 'i' }
43cd72b9
BW		 4129};
4130
4131static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
074f5109
BW		 4132 { { STATE_PSEXCM }, 'i' },
4133 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4134 { { STATE_XTSYNC }, 'o' },
4135 { { STATE_INTERRUPT }, 'm' }
4136};
4137
4138static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
56fb3749 4139 { { OPERAND_art }, 'o' }
43cd72b9
BW		 4140};
4141
4142static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
074f5109
BW		 4143 { { STATE_PSEXCM }, 'i' },
4144 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4145 { { STATE_INTENABLE }, 'i' }
4146};
4147
4148static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
56fb3749 4149 { { OPERAND_art }, 'i' }
43cd72b9
BW		 4150};
4151
4152static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
074f5109
BW		 4153 { { STATE_PSEXCM }, 'i' },
4154 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4155 { { STATE_INTENABLE }, 'o' }
4156};
4157
4158static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
56fb3749 4159 { { OPERAND_art }, 'm' }
43cd72b9
BW		 4160};
4161
4162static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
074f5109
BW		 4163 { { STATE_PSEXCM }, 'i' },
4164 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4165 { { STATE_INTENABLE }, 'm' }
4166};
4167
4168static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
56fb3749
SA		 4169 { { OPERAND_imms }, 'i' },
4170 { { OPERAND_immt }, 'i' }
43cd72b9
BW		 4171};
4172
4173static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
4174 { { STATE_PSEXCM }, 'i' },
4175 { { STATE_PSINTLEVEL }, 'i' }
4176};
4177
4178static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
56fb3749 4179 { { OPERAND_imms }, 'i' }
43cd72b9
BW		 4180};
4181
4182static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
4183 { { STATE_PSEXCM }, 'i' },
4184 { { STATE_PSINTLEVEL }, 'i' }
4185};
4186
4187static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
56fb3749 4188 { { OPERAND_art }, 'o' }
43cd72b9
BW		 4189};
4190
4191static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
074f5109
BW		 4192 { { STATE_PSEXCM }, 'i' },
4193 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4194 { { STATE_DBREAKA0 }, 'i' }
4195};
4196
4197static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
56fb3749 4198 { { OPERAND_art }, 'i' }
43cd72b9
BW		 4199};
4200
4201static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
074f5109
BW		 4202 { { STATE_PSEXCM }, 'i' },
4203 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4204 { { STATE_DBREAKA0 }, 'o' },
4205 { { STATE_XTSYNC }, 'o' }
4206};
4207
4208static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
56fb3749 4209 { { OPERAND_art }, 'm' }
43cd72b9
BW		 4210};
4211
4212static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
074f5109
BW		 4213 { { STATE_PSEXCM }, 'i' },
4214 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4215 { { STATE_DBREAKA0 }, 'm' },
4216 { { STATE_XTSYNC }, 'o' }
4217};
4218
4219static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
56fb3749 4220 { { OPERAND_art }, 'o' }
43cd72b9
BW		 4221};
4222
4223static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
074f5109
BW		 4224 { { STATE_PSEXCM }, 'i' },
4225 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4226 { { STATE_DBREAKC0 }, 'i' }
4227};
4228
4229static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
56fb3749 4230 { { OPERAND_art }, 'i' }
43cd72b9
BW		 4231};
4232
4233static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
074f5109
BW		 4234 { { STATE_PSEXCM }, 'i' },
4235 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4236 { { STATE_DBREAKC0 }, 'o' },
4237 { { STATE_XTSYNC }, 'o' }
4238};
4239
4240static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
56fb3749 4241 { { OPERAND_art }, 'm' }
43cd72b9
BW		 4242};
4243
4244static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
074f5109
BW		 4245 { { STATE_PSEXCM }, 'i' },
4246 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4247 { { STATE_DBREAKC0 }, 'm' },
4248 { { STATE_XTSYNC }, 'o' }
4249};
4250
4251static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
56fb3749 4252 { { OPERAND_art }, 'o' }
43cd72b9
BW		 4253};
4254
4255static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
074f5109
BW		 4256 { { STATE_PSEXCM }, 'i' },
4257 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4258 { { STATE_DBREAKA1 }, 'i' }
4259};
4260
4261static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
56fb3749 4262 { { OPERAND_art }, 'i' }
43cd72b9
BW		 4263};
4264
4265static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
074f5109
BW		 4266 { { STATE_PSEXCM }, 'i' },
4267 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4268 { { STATE_DBREAKA1 }, 'o' },
4269 { { STATE_XTSYNC }, 'o' }
4270};
4271
4272static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
56fb3749 4273 { { OPERAND_art }, 'm' }
43cd72b9
BW		 4274};
4275
4276static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
074f5109
BW		 4277 { { STATE_PSEXCM }, 'i' },
4278 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4279 { { STATE_DBREAKA1 }, 'm' },
4280 { { STATE_XTSYNC }, 'o' }
4281};
4282
4283static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
56fb3749 4284 { { OPERAND_art }, 'o' }
43cd72b9
BW		 4285};
4286
4287static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
074f5109
BW		 4288 { { STATE_PSEXCM }, 'i' },
4289 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4290 { { STATE_DBREAKC1 }, 'i' }
4291};
4292
4293static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
56fb3749 4294 { { OPERAND_art }, 'i' }
43cd72b9
BW		 4295};
4296
4297static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
074f5109
BW		 4298 { { STATE_PSEXCM }, 'i' },
4299 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4300 { { STATE_DBREAKC1 }, 'o' },
4301 { { STATE_XTSYNC }, 'o' }
4302};
4303
4304static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
56fb3749 4305 { { OPERAND_art }, 'm' }
43cd72b9
BW		 4306};
4307
4308static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
074f5109
BW		 4309 { { STATE_PSEXCM }, 'i' },
4310 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4311 { { STATE_DBREAKC1 }, 'm' },
4312 { { STATE_XTSYNC }, 'o' }
4313};
4314
4315static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
56fb3749 4316 { { OPERAND_art }, 'o' }
43cd72b9
BW		 4317};
4318
4319static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
074f5109
BW		 4320 { { STATE_PSEXCM }, 'i' },
4321 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4322 { { STATE_IBREAKA0 }, 'i' }
4323};
4324
4325static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
56fb3749 4326 { { OPERAND_art }, 'i' }
43cd72b9
BW		 4327};
4328
4329static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
074f5109
BW		 4330 { { STATE_PSEXCM }, 'i' },
4331 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4332 { { STATE_IBREAKA0 }, 'o' }
4333};
4334
4335static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
56fb3749 4336 { { OPERAND_art }, 'm' }
43cd72b9
BW		 4337};
4338
4339static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
074f5109
BW		 4340 { { STATE_PSEXCM }, 'i' },
4341 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4342 { { STATE_IBREAKA0 }, 'm' }
4343};
4344
4345static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
56fb3749 4346 { { OPERAND_art }, 'o' }
43cd72b9
BW		 4347};
4348
4349static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
074f5109
BW		 4350 { { STATE_PSEXCM }, 'i' },
4351 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4352 { { STATE_IBREAKA1 }, 'i' }
4353};
4354
4355static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
56fb3749 4356 { { OPERAND_art }, 'i' }
43cd72b9
BW		 4357};
4358
4359static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
074f5109
BW		 4360 { { STATE_PSEXCM }, 'i' },
4361 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4362 { { STATE_IBREAKA1 }, 'o' }
4363};
4364
4365static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
56fb3749 4366 { { OPERAND_art }, 'm' }
43cd72b9
BW		 4367};
4368
4369static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
074f5109
BW		 4370 { { STATE_PSEXCM }, 'i' },
4371 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4372 { { STATE_IBREAKA1 }, 'm' }
4373};
4374
4375static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
56fb3749 4376 { { OPERAND_art }, 'o' }
43cd72b9
BW		 4377};
4378
4379static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
074f5109
BW		 4380 { { STATE_PSEXCM }, 'i' },
4381 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4382 { { STATE_IBREAKENABLE }, 'i' }
4383};
4384
4385static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
56fb3749 4386 { { OPERAND_art }, 'i' }
43cd72b9
BW		 4387};
4388
4389static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
074f5109
BW		 4390 { { STATE_PSEXCM }, 'i' },
4391 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4392 { { STATE_IBREAKENABLE }, 'o' }
4393};
4394
4395static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
56fb3749 4396 { { OPERAND_art }, 'm' }
43cd72b9
BW		 4397};
4398
4399static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
074f5109
BW		 4400 { { STATE_PSEXCM }, 'i' },
4401 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4402 { { STATE_IBREAKENABLE }, 'm' }
4403};
4404
4405static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
56fb3749 4406 { { OPERAND_art }, 'o' }
43cd72b9
BW		 4407};
4408
4409static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
074f5109
BW		 4410 { { STATE_PSEXCM }, 'i' },
4411 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4412 { { STATE_DEBUGCAUSE }, 'i' },
4413 { { STATE_DBNUM }, 'i' }
4414};
4415
4416static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
56fb3749 4417 { { OPERAND_art }, 'i' }
43cd72b9
BW		 4418};
4419
4420static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
074f5109
BW		 4421 { { STATE_PSEXCM }, 'i' },
4422 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4423 { { STATE_DEBUGCAUSE }, 'o' },
4424 { { STATE_DBNUM }, 'o' }
4425};
4426
4427static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
56fb3749 4428 { { OPERAND_art }, 'm' }
43cd72b9
BW		 4429};
4430
4431static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
074f5109
BW		 4432 { { STATE_PSEXCM }, 'i' },
4433 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4434 { { STATE_DEBUGCAUSE }, 'm' },
4435 { { STATE_DBNUM }, 'm' }
4436};
4437
4438static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
56fb3749 4439 { { OPERAND_art }, 'o' }
43cd72b9
BW		 4440};
4441
4442static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
074f5109
BW		 4443 { { STATE_PSEXCM }, 'i' },
4444 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4445 { { STATE_ICOUNT }, 'i' }
4446};
4447
4448static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
56fb3749 4449 { { OPERAND_art }, 'i' }
43cd72b9
BW		 4450};
4451
4452static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
074f5109
BW		 4453 { { STATE_PSEXCM }, 'i' },
4454 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4455 { { STATE_XTSYNC }, 'o' },
4456 { { STATE_ICOUNT }, 'o' }
4457};
4458
4459static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
56fb3749 4460 { { OPERAND_art }, 'm' }
43cd72b9
BW		 4461};
4462
4463static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
074f5109
BW		 4464 { { STATE_PSEXCM }, 'i' },
4465 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4466 { { STATE_XTSYNC }, 'o' },
4467 { { STATE_ICOUNT }, 'm' }
4468};
4469
4470static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
56fb3749 4471 { { OPERAND_art }, 'o' }
43cd72b9
BW		 4472};
4473
4474static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
074f5109
BW		 4475 { { STATE_PSEXCM }, 'i' },
4476 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4477 { { STATE_ICOUNTLEVEL }, 'i' }
4478};
4479
4480static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
56fb3749 4481 { { OPERAND_art }, 'i' }
43cd72b9
BW		 4482};
4483
4484static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
074f5109
BW		 4485 { { STATE_PSEXCM }, 'i' },
4486 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4487 { { STATE_ICOUNTLEVEL }, 'o' }
4488};
4489
4490static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
56fb3749 4491 { { OPERAND_art }, 'm' }
43cd72b9
BW		 4492};
4493
4494static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
074f5109
BW		 4495 { { STATE_PSEXCM }, 'i' },
4496 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4497 { { STATE_ICOUNTLEVEL }, 'm' }
4498};
4499
4500static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
56fb3749 4501 { { OPERAND_art }, 'o' }
43cd72b9
BW		 4502};
4503
4504static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
074f5109
BW		 4505 { { STATE_PSEXCM }, 'i' },
4506 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4507 { { STATE_DDR }, 'i' }
4508};
4509
4510static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
56fb3749 4511 { { OPERAND_art }, 'i' }
43cd72b9
BW		 4512};
4513
4514static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
074f5109
BW		 4515 { { STATE_PSEXCM }, 'i' },
4516 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4517 { { STATE_XTSYNC }, 'o' },
4518 { { STATE_DDR }, 'o' }
4519};
4520
4521static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
56fb3749 4522 { { OPERAND_art }, 'm' }
43cd72b9
BW		 4523};
4524
4525static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
074f5109
BW		 4526 { { STATE_PSEXCM }, 'i' },
4527 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4528 { { STATE_XTSYNC }, 'o' },
4529 { { STATE_DDR }, 'm' }
4530};
4531
33430bd0 4532static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
56fb3749 4533 { { OPERAND_imms }, 'i' }
33430bd0
BW		 4534};
4535
43cd72b9
BW		 4536static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
4537 { { STATE_InOCDMode }, 'm' },
33430bd0 4538 { { STATE_EPC6 }, 'i' },
43cd72b9
BW		 4539 { { STATE_PSWOE }, 'o' },
4540 { { STATE_PSCALLINC }, 'o' },
4541 { { STATE_PSOWB }, 'o' },
074f5109 4542 { { STATE_PSRING }, 'o' },
43cd72b9
BW		 4543 { { STATE_PSUM }, 'o' },
4544 { { STATE_PSEXCM }, 'o' },
4545 { { STATE_PSINTLEVEL }, 'o' },
33430bd0 4546 { { STATE_EPS6 }, 'i' }
43cd72b9
BW		 4547};
4548
4549static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
4550 { { STATE_InOCDMode }, 'm' }
4551};
4552
33430bd0 4553static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
56fb3749 4554 { { OPERAND_art }, 'i' }
33430bd0
BW		 4555};
4556
4557static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
4558 { { STATE_PSEXCM }, 'i' },
4559 { { STATE_PSRING }, 'i' },
4560 { { STATE_XTSYNC }, 'o' }
4561};
4562
43cd72b9 4563static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
56fb3749 4564 { { OPERAND_art }, 'o' }
43cd72b9
BW		 4565};
4566
4567static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
074f5109
BW		 4568 { { STATE_PSEXCM }, 'i' },
4569 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4570 { { STATE_CCOUNT }, 'i' }
4571};
4572
4573static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
56fb3749 4574 { { OPERAND_art }, 'i' }
43cd72b9
BW		 4575};
4576
4577static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
074f5109
BW		 4578 { { STATE_PSEXCM }, 'i' },
4579 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4580 { { STATE_XTSYNC }, 'o' },
4581 { { STATE_CCOUNT }, 'o' }
4582};
4583
4584static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
56fb3749 4585 { { OPERAND_art }, 'm' }
43cd72b9
BW		 4586};
4587
4588static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
074f5109
BW		 4589 { { STATE_PSEXCM }, 'i' },
4590 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4591 { { STATE_XTSYNC }, 'o' },
4592 { { STATE_CCOUNT }, 'm' }
4593};
4594
4595static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
56fb3749 4596 { { OPERAND_art }, 'o' }
43cd72b9
BW		 4597};
4598
4599static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
074f5109
BW		 4600 { { STATE_PSEXCM }, 'i' },
4601 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4602 { { STATE_CCOMPARE0 }, 'i' }
4603};
4604
4605static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
56fb3749 4606 { { OPERAND_art }, 'i' }
43cd72b9
BW		 4607};
4608
4609static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
074f5109
BW		 4610 { { STATE_PSEXCM }, 'i' },
4611 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4612 { { STATE_CCOMPARE0 }, 'o' },
4613 { { STATE_INTERRUPT }, 'm' }
4614};
4615
4616static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
56fb3749 4617 { { OPERAND_art }, 'm' }
43cd72b9
BW		 4618};
4619
4620static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
074f5109
BW		 4621 { { STATE_PSEXCM }, 'i' },
4622 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4623 { { STATE_CCOMPARE0 }, 'm' },
4624 { { STATE_INTERRUPT }, 'm' }
4625};
4626
4627static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
56fb3749 4628 { { OPERAND_art }, 'o' }
43cd72b9
BW		 4629};
4630
4631static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
074f5109
BW		 4632 { { STATE_PSEXCM }, 'i' },
4633 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4634 { { STATE_CCOMPARE1 }, 'i' }
4635};
4636
4637static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
56fb3749 4638 { { OPERAND_art }, 'i' }
43cd72b9
BW		 4639};
4640
4641static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
074f5109
BW		 4642 { { STATE_PSEXCM }, 'i' },
4643 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4644 { { STATE_CCOMPARE1 }, 'o' },
4645 { { STATE_INTERRUPT }, 'm' }
4646};
4647
4648static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
56fb3749 4649 { { OPERAND_art }, 'm' }
43cd72b9
BW		 4650};
4651
4652static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
074f5109
BW		 4653 { { STATE_PSEXCM }, 'i' },
4654 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4655 { { STATE_CCOMPARE1 }, 'm' },
4656 { { STATE_INTERRUPT }, 'm' }
4657};
4658
4659static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
56fb3749 4660 { { OPERAND_art }, 'o' }
43cd72b9
BW		 4661};
4662
4663static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
074f5109
BW		 4664 { { STATE_PSEXCM }, 'i' },
4665 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4666 { { STATE_CCOMPARE2 }, 'i' }
4667};
4668
4669static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
56fb3749 4670 { { OPERAND_art }, 'i' }
43cd72b9
BW		 4671};
4672
4673static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
074f5109
BW		 4674 { { STATE_PSEXCM }, 'i' },
4675 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4676 { { STATE_CCOMPARE2 }, 'o' },
4677 { { STATE_INTERRUPT }, 'm' }
4678};
4679
4680static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
56fb3749 4681 { { OPERAND_art }, 'm' }
43cd72b9
BW		 4682};
4683
4684static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
074f5109
BW		 4685 { { STATE_PSEXCM }, 'i' },
4686 { { STATE_PSRING }, 'i' },
43cd72b9
BW		 4687 { { STATE_CCOMPARE2 }, 'm' },
4688 { { STATE_INTERRUPT }, 'm' }
4689};
4690
4691static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
56fb3749
SA		 4692 { { OPERAND_ars }, 'i' },
4693 { { OPERAND_uimm8x4 }, 'i' }
43cd72b9
BW		 4694};
4695
33430bd0 4696static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
56fb3749
SA		 4697 { { OPERAND_ars }, 'i' },
4698 { { OPERAND_uimm4x16 }, 'i' }
33430bd0
BW		 4699};
4700
4701static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
4702 { { STATE_PSEXCM }, 'i' },
4703 { { STATE_PSRING }, 'i' }
4704};
4705
43cd72b9 4706static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
56fb3749
SA		 4707 { { OPERAND_ars }, 'i' },
4708 { { OPERAND_uimm8x4 }, 'i' }
43cd72b9
BW		 4709};
4710
074f5109
BW		 4711static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
4712 { { STATE_PSEXCM }, 'i' },
4713 { { STATE_PSRING }, 'i' }
4714};
4715
43cd72b9 4716static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
56fb3749
SA		 4717 { { OPERAND_art }, 'o' },
4718 { { OPERAND_ars }, 'i' }
43cd72b9
BW		 4719};
4720
074f5109
BW		 4721static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
4722 { { STATE_PSEXCM }, 'i' },
4723 { { STATE_PSRING }, 'i' }
4724};
4725
43cd72b9 4726static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
56fb3749
SA		 4727 { { OPERAND_art }, 'i' },
4728 { { OPERAND_ars }, 'i' }
43cd72b9
BW		 4729};
4730
074f5109
BW		 4731static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
4732 { { STATE_PSEXCM }, 'i' },
4733 { { STATE_PSRING }, 'i' }
4734};
4735
43cd72b9 4736static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
56fb3749
SA		 4737 { { OPERAND_ars }, 'i' },
4738 { { OPERAND_uimm8x4 }, 'i' }
43cd72b9
BW		 4739};
4740
4741static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
56fb3749
SA		 4742 { { OPERAND_ars }, 'i' },
4743 { { OPERAND_uimm4x16 }, 'i' }
43cd72b9
BW		 4744};
4745
074f5109
BW		 4746static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
4747 { { STATE_PSEXCM }, 'i' },
4748 { { STATE_PSRING }, 'i' }
4749};
4750
43cd72b9 4751static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
56fb3749
SA		 4752 { { OPERAND_ars }, 'i' },
4753 { { OPERAND_uimm8x4 }, 'i' }
43cd72b9
BW		 4754};
4755
074f5109
BW		 4756static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
4757 { { STATE_PSEXCM }, 'i' },
4758 { { STATE_PSRING }, 'i' }
4759};
4760
43cd72b9 4761static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
56fb3749
SA		 4762 { { OPERAND_ars }, 'i' },
4763 { { OPERAND_uimm8x4 }, 'i' }
43cd72b9
BW		 4764};
4765
33430bd0 4766static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
56fb3749
SA		 4767 { { OPERAND_ars }, 'i' },
4768 { { OPERAND_uimm4x16 }, 'i' }
33430bd0
BW		 4769};
4770
4771static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
4772 { { STATE_PSEXCM }, 'i' },
4773 { { STATE_PSRING }, 'i' }
4774};
4775
43cd72b9 4776static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
56fb3749
SA		 4777 { { OPERAND_art }, 'i' },
4778 { { OPERAND_ars }, 'i' }
43cd72b9
BW		 4779};
4780
074f5109
BW		 4781static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
4782 { { STATE_PSEXCM }, 'i' },
4783 { { STATE_PSRING }, 'i' }
4784};
4785
43cd72b9 4786static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
56fb3749
SA		 4787 { { OPERAND_art }, 'o' },
4788 { { OPERAND_ars }, 'i' }
43cd72b9
BW		 4789};
4790
074f5109
BW		 4791static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
4792 { { STATE_PSEXCM }, 'i' },
4793 { { STATE_PSRING }, 'i' }
4794};
4795
4796static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
56fb3749 4797 { { OPERAND_art }, 'i' }
074f5109
BW		 4798};
4799
4800static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
4801 { { STATE_PSEXCM }, 'i' },
4802 { { STATE_PSRING }, 'i' },
4803 { { STATE_PTBASE }, 'o' },
4804 { { STATE_XTSYNC }, 'o' }
4805};
4806
4807static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
56fb3749 4808 { { OPERAND_art }, 'o' }
074f5109
BW		 4809};
4810
4811static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
4812 { { STATE_PSEXCM }, 'i' },
4813 { { STATE_PSRING }, 'i' },
4814 { { STATE_PTBASE }, 'i' },
4815 { { STATE_EXCVADDR }, 'i' }
4816};
4817
4818static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
56fb3749 4819 { { OPERAND_art }, 'm' }
074f5109
BW		 4820};
4821
4822static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
4823 { { STATE_PSEXCM }, 'i' },
4824 { { STATE_PSRING }, 'i' },
4825 { { STATE_PTBASE }, 'm' },
4826 { { STATE_EXCVADDR }, 'i' },
4827 { { STATE_XTSYNC }, 'o' }
4828};
4829
4830static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
56fb3749 4831 { { OPERAND_art }, 'o' }
074f5109
BW		 4832};
4833
4834static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
4835 { { STATE_PSEXCM }, 'i' },
4836 { { STATE_PSRING }, 'i' },
4837 { { STATE_ASID3 }, 'i' },
4838 { { STATE_ASID2 }, 'i' },
4839 { { STATE_ASID1 }, 'i' }
4840};
4841
4842static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
56fb3749 4843 { { OPERAND_art }, 'i' }
074f5109
BW		 4844};
4845
4846static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
4847 { { STATE_XTSYNC }, 'o' },
4848 { { STATE_PSEXCM }, 'i' },
4849 { { STATE_PSRING }, 'i' },
4850 { { STATE_ASID3 }, 'o' },
4851 { { STATE_ASID2 }, 'o' },
4852 { { STATE_ASID1 }, 'o' }
4853};
4854
4855static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
56fb3749 4856 { { OPERAND_art }, 'm' }
074f5109
BW		 4857};
4858
4859static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
4860 { { STATE_XTSYNC }, 'o' },
4861 { { STATE_PSEXCM }, 'i' },
4862 { { STATE_PSRING }, 'i' },
4863 { { STATE_ASID3 }, 'm' },
4864 { { STATE_ASID2 }, 'm' },
4865 { { STATE_ASID1 }, 'm' }
4866};
4867
4868static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
56fb3749 4869 { { OPERAND_art }, 'o' }
074f5109
BW		 4870};
4871
4872static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
4873 { { STATE_PSEXCM }, 'i' },
4874 { { STATE_PSRING }, 'i' },
4875 { { STATE_INSTPGSZID4 }, 'i' }
4876};
4877
4878static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
56fb3749 4879 { { OPERAND_art }, 'i' }
074f5109
BW		 4880};
4881
4882static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
4883 { { STATE_XTSYNC }, 'o' },
4884 { { STATE_PSEXCM }, 'i' },
4885 { { STATE_PSRING }, 'i' },
4886 { { STATE_INSTPGSZID4 }, 'o' }
4887};
4888
4889static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
56fb3749 4890 { { OPERAND_art }, 'm' }
074f5109
BW		 4891};
4892
4893static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
4894 { { STATE_XTSYNC }, 'o' },
4895 { { STATE_PSEXCM }, 'i' },
4896 { { STATE_PSRING }, 'i' },
4897 { { STATE_INSTPGSZID4 }, 'm' }
4898};
4899
4900static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
56fb3749 4901 { { OPERAND_art }, 'o' }
074f5109
BW		 4902};
4903
4904static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
4905 { { STATE_PSEXCM }, 'i' },
4906 { { STATE_PSRING }, 'i' },
4907 { { STATE_DATAPGSZID4 }, 'i' }
4908};
4909
4910static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
56fb3749 4911 { { OPERAND_art }, 'i' }
074f5109
BW		 4912};
4913
4914static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
4915 { { STATE_XTSYNC }, 'o' },
4916 { { STATE_PSEXCM }, 'i' },
4917 { { STATE_PSRING }, 'i' },
33430bd0
BW		 4918 { { STATE_DATAPGSZID4 }, 'o' }
4919};
4920
4921static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
56fb3749 4922 { { OPERAND_art }, 'm' }
33430bd0
BW		 4923};
4924
4925static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
4926 { { STATE_XTSYNC }, 'o' },
4927 { { STATE_PSEXCM }, 'i' },
4928 { { STATE_PSRING }, 'i' },
4929 { { STATE_DATAPGSZID4 }, 'm' }
4930};
4931
4932static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
56fb3749 4933 { { OPERAND_ars }, 'i' }
33430bd0
BW		 4934};
4935
4936static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
4937 { { STATE_PSEXCM }, 'i' },
4938 { { STATE_PSRING }, 'i' },
4939 { { STATE_XTSYNC }, 'o' }
4940};
4941
4942static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
56fb3749
SA		 4943 { { OPERAND_art }, 'o' },
4944 { { OPERAND_ars }, 'i' }
33430bd0
BW		 4945};
4946
4947static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
4948 { { STATE_PSEXCM }, 'i' },
4949 { { STATE_PSRING }, 'i' }
4950};
4951
4952static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
56fb3749
SA		 4953 { { OPERAND_art }, 'i' },
4954 { { OPERAND_ars }, 'i' }
33430bd0
BW		 4955};
4956
4957static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
4958 { { STATE_PSEXCM }, 'i' },
4959 { { STATE_PSRING }, 'i' },
4960 { { STATE_XTSYNC }, 'o' }
4961};
4962
4963static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
56fb3749 4964 { { OPERAND_ars }, 'i' }
33430bd0
BW		 4965};
4966
4967static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
4968 { { STATE_PSEXCM }, 'i' },
4969 { { STATE_PSRING }, 'i' }
4970};
4971
4972static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
56fb3749
SA		 4973 { { OPERAND_art }, 'o' },
4974 { { OPERAND_ars }, 'i' }
33430bd0
BW		 4975};
4976
4977static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
4978 { { STATE_PSEXCM }, 'i' },
4979 { { STATE_PSRING }, 'i' }
4980};
4981
4982static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
56fb3749
SA		 4983 { { OPERAND_art }, 'i' },
4984 { { OPERAND_ars }, 'i' }
33430bd0
BW		 4985};
4986
4987static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
4988 { { STATE_PSEXCM }, 'i' },
4989 { { STATE_PSRING }, 'i' }
4990};
4991
4992static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
4993 { { STATE_PTBASE }, 'i' },
4994 { { STATE_EXCVADDR }, 'i' }
4995};
4996
4997static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
4998 { { STATE_EXCVADDR }, 'i' }
4999};
5000
5001static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
5002 { { STATE_EXCVADDR }, 'i' }
5003};
5004
5005static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
56fb3749 5006 { { OPERAND_art }, 'o' }
33430bd0
BW		 5007};
5008
5009static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
5010 { { STATE_PSEXCM }, 'i' },
5011 { { STATE_PSRING }, 'i' },
5012 { { STATE_CPENABLE }, 'i' }
5013};
5014
5015static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
56fb3749 5016 { { OPERAND_art }, 'i' }
33430bd0
BW		 5017};
5018
5019static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
5020 { { STATE_PSEXCM }, 'i' },
5021 { { STATE_PSRING }, 'i' },
5022 { { STATE_CPENABLE }, 'o' }
074f5109
BW		 5023};
5024
33430bd0 5025static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
56fb3749 5026 { { OPERAND_art }, 'm' }
074f5109
BW		 5027};
5028
33430bd0 5029static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
074f5109
BW		 5030 { { STATE_PSEXCM }, 'i' },
5031 { { STATE_PSRING }, 'i' },
33430bd0 5032 { { STATE_CPENABLE }, 'm' }
074f5109
BW		 5033};
5034
33430bd0 5035static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
56fb3749
SA		 5036 { { OPERAND_arr }, 'o' },
5037 { { OPERAND_ars }, 'i' },
5038 { { OPERAND_tp7 }, 'i' }
43cd72b9
BW		 5039};
5040
33430bd0 5041static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
56fb3749
SA		 5042 { { OPERAND_arr }, 'o' },
5043 { { OPERAND_ars }, 'i' },
5044 { { OPERAND_art }, 'i' }
43cd72b9
BW		 5045};
5046
33430bd0 5047static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
56fb3749
SA		 5048 { { OPERAND_art }, 'o' },
5049 { { OPERAND_ars }, 'i' }
43cd72b9
BW		 5050};
5051
33430bd0 5052static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
56fb3749
SA		 5053 { { OPERAND_arr }, 'o' },
5054 { { OPERAND_ars }, 'i' },
5055 { { OPERAND_tp7 }, 'i' }
074f5109
BW		 5056};
5057
33430bd0 5058static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
56fb3749
SA		 5059 { { OPERAND_art }, 'o' },
5060 { { OPERAND_ars }, 'i' },
5061 { { OPERAND_uimm8x4 }, 'i' }
43cd72b9
BW		 5062};
5063
33430bd0 5064static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
56fb3749
SA		 5065 { { OPERAND_art }, 'i' },
5066 { { OPERAND_ars }, 'i' },
5067 { { OPERAND_uimm8x4 }, 'i' }
43cd72b9
BW		 5068};
5069
33430bd0 5070static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
56fb3749
SA		 5071 { { OPERAND_art }, 'm' },
5072 { { OPERAND_ars }, 'i' },
5073 { { OPERAND_uimm8x4 }, 'i' }
43cd72b9
BW		 5074};
5075
33430bd0
BW		 5076static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
5077 { { STATE_SCOMPARE1 }, 'i' },
5078 { { STATE_SCOMPARE1 }, 'i' }
074f5109
BW		 5079};
5080
33430bd0 5081static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
56fb3749 5082 { { OPERAND_art }, 'o' }
43cd72b9
BW		 5083};
5084
33430bd0
BW		 5085static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
5086 { { STATE_SCOMPARE1 }, 'i' }
074f5109
BW		 5087};
5088
33430bd0 5089static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
56fb3749 5090 { { OPERAND_art }, 'i' }
43cd72b9
BW		 5091};
5092
33430bd0
BW		 5093static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
5094 { { STATE_SCOMPARE1 }, 'o' }
074f5109
BW		 5095};
5096
33430bd0 5097static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
56fb3749 5098 { { OPERAND_art }, 'm' }
074f5109
BW		 5099};
5100
33430bd0
BW		 5101static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
5102 { { STATE_SCOMPARE1 }, 'm' }
074f5109
BW		 5103};
5104
33430bd0 5105static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
56fb3749
SA		 5106 { { OPERAND_arr }, 'o' },
5107 { { OPERAND_ars }, 'i' },
5108 { { OPERAND_art }, 'i' }
074f5109
BW		 5109};
5110
33430bd0 5111static xtensa_arg_internal Iclass_xt_mul32_args[] = {
56fb3749
SA		 5112 { { OPERAND_arr }, 'o' },
5113 { { OPERAND_ars }, 'i' },
5114 { { OPERAND_art }, 'i' }
43cd72b9
BW		 5115};
5116
5117static xtensa_iclass_internal iclasses[] = {
5118 { 0, 0 /* xt_iclass_excw */,
5119 0, 0, 0, 0 },
5120 { 0, 0 /* xt_iclass_rfe */,
074f5109 5121 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
43cd72b9 5122 { 0, 0 /* xt_iclass_rfde */,
074f5109 5123 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
43cd72b9
BW		 5124 { 0, 0 /* xt_iclass_syscall */,
5125 0, 0, 0, 0 },
5126 { 0, 0 /* xt_iclass_simcall */,
5127 0, 0, 0, 0 },
5128 { 2, Iclass_xt_iclass_call12_args,
5129 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
5130 { 2, Iclass_xt_iclass_call8_args,
5131 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
5132 { 2, Iclass_xt_iclass_call4_args,
5133 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
5134 { 2, Iclass_xt_iclass_callx12_args,
5135 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
5136 { 2, Iclass_xt_iclass_callx8_args,
5137 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
5138 { 2, Iclass_xt_iclass_callx4_args,
5139 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
5140 { 3, Iclass_xt_iclass_entry_args,
5141 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
5142 { 2, Iclass_xt_iclass_movsp_args,
5143 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
5144 { 1, Iclass_xt_iclass_rotw_args,
074f5109 5145 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
43cd72b9
BW		 5146 { 1, Iclass_xt_iclass_retw_args,
5147 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
5148 { 0, 0 /* xt_iclass_rfwou */,
074f5109 5149 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
43cd72b9 5150 { 3, Iclass_xt_iclass_l32e_args,
074f5109 5151 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
43cd72b9 5152 { 3, Iclass_xt_iclass_s32e_args,
074f5109 5153 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
43cd72b9 5154 { 1, Iclass_xt_iclass_rsr_windowbase_args,
074f5109 5155 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
43cd72b9 5156 { 1, Iclass_xt_iclass_wsr_windowbase_args,
074f5109 5157 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
43cd72b9 5158 { 1, Iclass_xt_iclass_xsr_windowbase_args,
074f5109 5159 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
43cd72b9 5160 { 1, Iclass_xt_iclass_rsr_windowstart_args,
074f5109 5161 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
43cd72b9 5162 { 1, Iclass_xt_iclass_wsr_windowstart_args,
074f5109 5163 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
43cd72b9 5164 { 1, Iclass_xt_iclass_xsr_windowstart_args,
074f5109 5165 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
43cd72b9
BW		 5166 { 3, Iclass_xt_iclass_add_n_args,
5167 0, 0, 0, 0 },
5168 { 3, Iclass_xt_iclass_addi_n_args,
5169 0, 0, 0, 0 },
5170 { 2, Iclass_xt_iclass_bz6_args,
5171 0, 0, 0, 0 },
5172 { 0, 0 /* xt_iclass_ill_n */,
5173 0, 0, 0, 0 },
5174 { 3, Iclass_xt_iclass_loadi4_args,
5175 0, 0, 0, 0 },
5176 { 2, Iclass_xt_iclass_mov_n_args,
5177 0, 0, 0, 0 },
5178 { 2, Iclass_xt_iclass_movi_n_args,
5179 0, 0, 0, 0 },
5180 { 0, 0 /* xt_iclass_nopn */,
5181 0, 0, 0, 0 },
5182 { 1, Iclass_xt_iclass_retn_args,
5183 0, 0, 0, 0 },
5184 { 3, Iclass_xt_iclass_storei4_args,
5185 0, 0, 0, 0 },
33430bd0
BW		 5186 { 1, Iclass_rur_threadptr_args,
5187 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
5188 { 1, Iclass_wur_threadptr_args,
5189 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
43cd72b9
BW		 5190 { 3, Iclass_xt_iclass_addi_args,
5191 0, 0, 0, 0 },
5192 { 3, Iclass_xt_iclass_addmi_args,
5193 0, 0, 0, 0 },
5194 { 3, Iclass_xt_iclass_addsub_args,
5195 0, 0, 0, 0 },
5196 { 3, Iclass_xt_iclass_bit_args,
5197 0, 0, 0, 0 },
5198 { 3, Iclass_xt_iclass_bsi8_args,
5199 0, 0, 0, 0 },
5200 { 3, Iclass_xt_iclass_bsi8b_args,
5201 0, 0, 0, 0 },
5202 { 3, Iclass_xt_iclass_bsi8u_args,
5203 0, 0, 0, 0 },
5204 { 3, Iclass_xt_iclass_bst8_args,
5205 0, 0, 0, 0 },
5206 { 2, Iclass_xt_iclass_bsz12_args,
5207 0, 0, 0, 0 },
5208 { 2, Iclass_xt_iclass_call0_args,
5209 0, 0, 0, 0 },
5210 { 2, Iclass_xt_iclass_callx0_args,
5211 0, 0, 0, 0 },
5212 { 4, Iclass_xt_iclass_exti_args,
5213 0, 0, 0, 0 },
5214 { 0, 0 /* xt_iclass_ill */,
5215 0, 0, 0, 0 },
5216 { 1, Iclass_xt_iclass_jump_args,
5217 0, 0, 0, 0 },
5218 { 1, Iclass_xt_iclass_jumpx_args,
5219 0, 0, 0, 0 },
5220 { 3, Iclass_xt_iclass_l16ui_args,
5221 0, 0, 0, 0 },
5222 { 3, Iclass_xt_iclass_l16si_args,
5223 0, 0, 0, 0 },
5224 { 3, Iclass_xt_iclass_l32i_args,
5225 0, 0, 0, 0 },
5226 { 2, Iclass_xt_iclass_l32r_args,
5227 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
5228 { 3, Iclass_xt_iclass_l8i_args,
5229 0, 0, 0, 0 },
5230 { 2, Iclass_xt_iclass_loop_args,
5231 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
5232 { 2, Iclass_xt_iclass_loopz_args,
5233 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
5234 { 2, Iclass_xt_iclass_movi_args,
5235 0, 0, 0, 0 },
5236 { 3, Iclass_xt_iclass_movz_args,
5237 0, 0, 0, 0 },
5238 { 2, Iclass_xt_iclass_neg_args,
5239 0, 0, 0, 0 },
5240 { 0, 0 /* xt_iclass_nop */,
5241 0, 0, 0, 0 },
5242 { 1, Iclass_xt_iclass_return_args,
5243 0, 0, 0, 0 },
5244 { 3, Iclass_xt_iclass_s16i_args,
5245 0, 0, 0, 0 },
5246 { 3, Iclass_xt_iclass_s32i_args,
5247 0, 0, 0, 0 },
5248 { 3, Iclass_xt_iclass_s8i_args,
5249 0, 0, 0, 0 },
5250 { 1, Iclass_xt_iclass_sar_args,
5251 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
5252 { 1, Iclass_xt_iclass_sari_args,
5253 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
5254 { 2, Iclass_xt_iclass_shifts_args,
5255 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
5256 { 3, Iclass_xt_iclass_shiftst_args,
5257 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
5258 { 2, Iclass_xt_iclass_shiftt_args,
5259 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
5260 { 3, Iclass_xt_iclass_slli_args,
5261 0, 0, 0, 0 },
5262 { 3, Iclass_xt_iclass_srai_args,
5263 0, 0, 0, 0 },
5264 { 3, Iclass_xt_iclass_srli_args,
5265 0, 0, 0, 0 },
5266 { 0, 0 /* xt_iclass_memw */,
5267 0, 0, 0, 0 },
5268 { 0, 0 /* xt_iclass_extw */,
5269 0, 0, 0, 0 },
5270 { 0, 0 /* xt_iclass_isync */,
5271 0, 0, 0, 0 },
5272 { 0, 0 /* xt_iclass_sync */,
5273 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
5274 { 2, Iclass_xt_iclass_rsil_args,
074f5109 5275 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
43cd72b9
BW		 5276 { 1, Iclass_xt_iclass_rsr_lend_args,
5277 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
5278 { 1, Iclass_xt_iclass_wsr_lend_args,
5279 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
5280 { 1, Iclass_xt_iclass_xsr_lend_args,
5281 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
5282 { 1, Iclass_xt_iclass_rsr_lcount_args,
5283 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
5284 { 1, Iclass_xt_iclass_wsr_lcount_args,
5285 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
5286 { 1, Iclass_xt_iclass_xsr_lcount_args,
5287 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
5288 { 1, Iclass_xt_iclass_rsr_lbeg_args,
5289 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
5290 { 1, Iclass_xt_iclass_wsr_lbeg_args,
5291 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
5292 { 1, Iclass_xt_iclass_xsr_lbeg_args,
5293 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
5294 { 1, Iclass_xt_iclass_rsr_sar_args,
5295 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
5296 { 1, Iclass_xt_iclass_wsr_sar_args,
5297 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
5298 { 1, Iclass_xt_iclass_xsr_sar_args,
5299 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
5300 { 1, Iclass_xt_iclass_rsr_litbase_args,
5301 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
5302 { 1, Iclass_xt_iclass_wsr_litbase_args,
5303 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
5304 { 1, Iclass_xt_iclass_xsr_litbase_args,
5305 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
5306 { 1, Iclass_xt_iclass_rsr_176_args,
074f5109 5307 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
33430bd0
BW		 5308 { 1, Iclass_xt_iclass_wsr_176_args,
5309 2, Iclass_xt_iclass_wsr_176_stateArgs, 0, 0 },
43cd72b9 5310 { 1, Iclass_xt_iclass_rsr_208_args,
074f5109 5311 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
43cd72b9 5312 { 1, Iclass_xt_iclass_rsr_ps_args,
074f5109 5313 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
43cd72b9 5314 { 1, Iclass_xt_iclass_wsr_ps_args,
074f5109 5315 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
43cd72b9 5316 { 1, Iclass_xt_iclass_xsr_ps_args,
074f5109 5317 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
43cd72b9 5318 { 1, Iclass_xt_iclass_rsr_epc1_args,
074f5109 5319 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
43cd72b9 5320 { 1, Iclass_xt_iclass_wsr_epc1_args,
074f5109 5321 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
43cd72b9 5322 { 1, Iclass_xt_iclass_xsr_epc1_args,
074f5109 5323 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
43cd72b9 5324 { 1, Iclass_xt_iclass_rsr_excsave1_args,
074f5109 5325 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
43cd72b9 5326 { 1, Iclass_xt_iclass_wsr_excsave1_args,
074f5109 5327 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
43cd72b9 5328 { 1, Iclass_xt_iclass_xsr_excsave1_args,
074f5109 5329 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
43cd72b9 5330 { 1, Iclass_xt_iclass_rsr_epc2_args,
074f5109 5331 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
43cd72b9 5332 { 1, Iclass_xt_iclass_wsr_epc2_args,
074f5109 5333 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
43cd72b9 5334 { 1, Iclass_xt_iclass_xsr_epc2_args,
074f5109 5335 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
43cd72b9 5336 { 1, Iclass_xt_iclass_rsr_excsave2_args,
074f5109 5337 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
43cd72b9 5338 { 1, Iclass_xt_iclass_wsr_excsave2_args,
074f5109 5339 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
43cd72b9 5340 { 1, Iclass_xt_iclass_xsr_excsave2_args,
074f5109 5341 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
43cd72b9 5342 { 1, Iclass_xt_iclass_rsr_epc3_args,
074f5109 5343 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
43cd72b9 5344 { 1, Iclass_xt_iclass_wsr_epc3_args,
074f5109 5345 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
43cd72b9 5346 { 1, Iclass_xt_iclass_xsr_epc3_args,
074f5109 5347 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
43cd72b9 5348 { 1, Iclass_xt_iclass_rsr_excsave3_args,
074f5109 5349 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
43cd72b9 5350 { 1, Iclass_xt_iclass_wsr_excsave3_args,
074f5109 5351 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
43cd72b9 5352 { 1, Iclass_xt_iclass_xsr_excsave3_args,
074f5109 5353 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
43cd72b9 5354 { 1, Iclass_xt_iclass_rsr_epc4_args,
074f5109 5355 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
43cd72b9 5356 { 1, Iclass_xt_iclass_wsr_epc4_args,
074f5109 5357 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
43cd72b9 5358 { 1, Iclass_xt_iclass_xsr_epc4_args,
074f5109 5359 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
43cd72b9 5360 { 1, Iclass_xt_iclass_rsr_excsave4_args,
074f5109 5361 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
43cd72b9 5362 { 1, Iclass_xt_iclass_wsr_excsave4_args,
074f5109 5363 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
43cd72b9 5364 { 1, Iclass_xt_iclass_xsr_excsave4_args,
074f5109 5365 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
33430bd0
BW		 5366 { 1, Iclass_xt_iclass_rsr_epc5_args,
5367 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
5368 { 1, Iclass_xt_iclass_wsr_epc5_args,
5369 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
5370 { 1, Iclass_xt_iclass_xsr_epc5_args,
5371 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
5372 { 1, Iclass_xt_iclass_rsr_excsave5_args,
5373 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
5374 { 1, Iclass_xt_iclass_wsr_excsave5_args,
5375 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
5376 { 1, Iclass_xt_iclass_xsr_excsave5_args,
5377 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
5378 { 1, Iclass_xt_iclass_rsr_epc6_args,
5379 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
5380 { 1, Iclass_xt_iclass_wsr_epc6_args,
5381 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
5382 { 1, Iclass_xt_iclass_xsr_epc6_args,
5383 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
5384 { 1, Iclass_xt_iclass_rsr_excsave6_args,
5385 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
5386 { 1, Iclass_xt_iclass_wsr_excsave6_args,
5387 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
5388 { 1, Iclass_xt_iclass_xsr_excsave6_args,
5389 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
5390 { 1, Iclass_xt_iclass_rsr_epc7_args,
5391 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
5392 { 1, Iclass_xt_iclass_wsr_epc7_args,
5393 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
5394 { 1, Iclass_xt_iclass_xsr_epc7_args,
5395 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
5396 { 1, Iclass_xt_iclass_rsr_excsave7_args,
5397 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
5398 { 1, Iclass_xt_iclass_wsr_excsave7_args,
5399 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
5400 { 1, Iclass_xt_iclass_xsr_excsave7_args,
5401 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
43cd72b9 5402 { 1, Iclass_xt_iclass_rsr_eps2_args,
074f5109 5403 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
43cd72b9 5404 { 1, Iclass_xt_iclass_wsr_eps2_args,
074f5109 5405 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
43cd72b9 5406 { 1, Iclass_xt_iclass_xsr_eps2_args,
074f5109 5407 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
43cd72b9 5408 { 1, Iclass_xt_iclass_rsr_eps3_args,
074f5109 5409 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
43cd72b9 5410 { 1, Iclass_xt_iclass_wsr_eps3_args,
074f5109 5411 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
43cd72b9 5412 { 1, Iclass_xt_iclass_xsr_eps3_args,
074f5109 5413 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
43cd72b9 5414 { 1, Iclass_xt_iclass_rsr_eps4_args,
074f5109 5415 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
43cd72b9 5416 { 1, Iclass_xt_iclass_wsr_eps4_args,
074f5109 5417 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
43cd72b9 5418 { 1, Iclass_xt_iclass_xsr_eps4_args,
074f5109 5419 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
33430bd0
BW		 5420 { 1, Iclass_xt_iclass_rsr_eps5_args,
5421 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
5422 { 1, Iclass_xt_iclass_wsr_eps5_args,
5423 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
5424 { 1, Iclass_xt_iclass_xsr_eps5_args,
5425 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
5426 { 1, Iclass_xt_iclass_rsr_eps6_args,
5427 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
5428 { 1, Iclass_xt_iclass_wsr_eps6_args,
5429 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
5430 { 1, Iclass_xt_iclass_xsr_eps6_args,
5431 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
5432 { 1, Iclass_xt_iclass_rsr_eps7_args,
5433 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
5434 { 1, Iclass_xt_iclass_wsr_eps7_args,
5435 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
5436 { 1, Iclass_xt_iclass_xsr_eps7_args,
5437 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
43cd72b9 5438 { 1, Iclass_xt_iclass_rsr_excvaddr_args,
074f5109 5439 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
43cd72b9 5440 { 1, Iclass_xt_iclass_wsr_excvaddr_args,
074f5109 5441 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
43cd72b9 5442 { 1, Iclass_xt_iclass_xsr_excvaddr_args,
074f5109 5443 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
43cd72b9 5444 { 1, Iclass_xt_iclass_rsr_depc_args,
074f5109 5445 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
43cd72b9 5446 { 1, Iclass_xt_iclass_wsr_depc_args,
074f5109 5447 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
43cd72b9 5448 { 1, Iclass_xt_iclass_xsr_depc_args,
074f5109 5449 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
43cd72b9 5450 { 1, Iclass_xt_iclass_rsr_exccause_args,
074f5109 5451 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
43cd72b9 5452 { 1, Iclass_xt_iclass_wsr_exccause_args,
074f5109 5453 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
43cd72b9 5454 { 1, Iclass_xt_iclass_xsr_exccause_args,
074f5109 5455 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
43cd72b9 5456 { 1, Iclass_xt_iclass_rsr_misc0_args,
074f5109 5457 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
43cd72b9 5458 { 1, Iclass_xt_iclass_wsr_misc0_args,
074f5109 5459 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
43cd72b9 5460 { 1, Iclass_xt_iclass_xsr_misc0_args,
074f5109 5461 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
43cd72b9 5462 { 1, Iclass_xt_iclass_rsr_misc1_args,
074f5109 5463 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
43cd72b9 5464 { 1, Iclass_xt_iclass_wsr_misc1_args,
074f5109 5465 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
43cd72b9 5466 { 1, Iclass_xt_iclass_xsr_misc1_args,
074f5109 5467 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
43cd72b9 5468 { 1, Iclass_xt_iclass_rsr_prid_args,
074f5109 5469 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
33430bd0
BW		 5470 { 1, Iclass_xt_iclass_rsr_vecbase_args,
5471 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
5472 { 1, Iclass_xt_iclass_wsr_vecbase_args,
5473 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
5474 { 1, Iclass_xt_iclass_xsr_vecbase_args,
5475 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
5476 { 3, Iclass_xt_iclass_mul16_args,
5477 0, 0, 0, 0 },
43cd72b9 5478 { 1, Iclass_xt_iclass_rfi_args,
33430bd0 5479 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
43cd72b9 5480 { 1, Iclass_xt_iclass_wait_args,
074f5109 5481 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
43cd72b9 5482 { 1, Iclass_xt_iclass_rsr_interrupt_args,
074f5109 5483 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
43cd72b9 5484 { 1, Iclass_xt_iclass_wsr_intset_args,
074f5109 5485 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
43cd72b9 5486 { 1, Iclass_xt_iclass_wsr_intclear_args,
074f5109 5487 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
43cd72b9 5488 { 1, Iclass_xt_iclass_rsr_intenable_args,
074f5109 5489 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
43cd72b9 5490 { 1, Iclass_xt_iclass_wsr_intenable_args,
074f5109 5491 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
43cd72b9 5492 { 1, Iclass_xt_iclass_xsr_intenable_args,
074f5109 5493 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
43cd72b9
BW		 5494 { 2, Iclass_xt_iclass_break_args,
5495 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
5496 { 1, Iclass_xt_iclass_break_n_args,
5497 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
5498 { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
074f5109 5499 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
43cd72b9 5500 { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
074f5109 5501 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
43cd72b9 5502 { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
074f5109 5503 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
43cd72b9 5504 { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
074f5109 5505 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
43cd72b9 5506 { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
074f5109 5507 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
43cd72b9 5508 { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
074f5109 5509 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
43cd72b9 5510 { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
074f5109 5511 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
43cd72b9 5512 { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
074f5109 5513 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
43cd72b9 5514 { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
074f5109 5515 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
43cd72b9 5516 { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
074f5109 5517 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
43cd72b9 5518 { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
074f5109 5519 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
43cd72b9 5520 { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
074f5109 5521 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
43cd72b9 5522 { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
074f5109 5523 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
43cd72b9 5524 { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
074f5109 5525 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
43cd72b9 5526 { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
074f5109 5527 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
43cd72b9 5528 { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
074f5109 5529 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
43cd72b9 5530 { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
074f5109 5531 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
43cd72b9 5532 { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
074f5109 5533 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
43cd72b9 5534 { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
074f5109 5535 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
43cd72b9 5536 { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
074f5109 5537 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
43cd72b9 5538 { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
074f5109 5539 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
43cd72b9 5540 { 1, Iclass_xt_iclass_rsr_debugcause_args,
074f5109 5541 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
43cd72b9 5542 { 1, Iclass_xt_iclass_wsr_debugcause_args,
074f5109 5543 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
43cd72b9 5544 { 1, Iclass_xt_iclass_xsr_debugcause_args,
074f5109 5545 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
43cd72b9 5546 { 1, Iclass_xt_iclass_rsr_icount_args,
074f5109 5547 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
43cd72b9 5548 { 1, Iclass_xt_iclass_wsr_icount_args,
074f5109 5549 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
43cd72b9 5550 { 1, Iclass_xt_iclass_xsr_icount_args,
074f5109 5551 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
43cd72b9 5552 { 1, Iclass_xt_iclass_rsr_icountlevel_args,
074f5109 5553 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
43cd72b9 5554 { 1, Iclass_xt_iclass_wsr_icountlevel_args,
074f5109 5555 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
43cd72b9 5556 { 1, Iclass_xt_iclass_xsr_icountlevel_args,
074f5109 5557 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
43cd72b9 5558 { 1, Iclass_xt_iclass_rsr_ddr_args,
074f5109 5559 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
43cd72b9 5560 { 1, Iclass_xt_iclass_wsr_ddr_args,
074f5109 5561 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
43cd72b9 5562 { 1, Iclass_xt_iclass_xsr_ddr_args,
074f5109 5563 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
33430bd0 5564 { 1, Iclass_xt_iclass_rfdo_args,
074f5109 5565 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
43cd72b9
BW		 5566 { 0, 0 /* xt_iclass_rfdd */,
5567 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
33430bd0
BW		 5568 { 1, Iclass_xt_iclass_wsr_mmid_args,
5569 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
43cd72b9 5570 { 1, Iclass_xt_iclass_rsr_ccount_args,
074f5109 5571 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
43cd72b9 5572 { 1, Iclass_xt_iclass_wsr_ccount_args,
074f5109 5573 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
43cd72b9 5574 { 1, Iclass_xt_iclass_xsr_ccount_args,
074f5109 5575 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
43cd72b9 5576 { 1, Iclass_xt_iclass_rsr_ccompare0_args,
074f5109 5577 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
43cd72b9 5578 { 1, Iclass_xt_iclass_wsr_ccompare0_args,
074f5109 5579 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
43cd72b9 5580 { 1, Iclass_xt_iclass_xsr_ccompare0_args,
074f5109 5581 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
43cd72b9 5582 { 1, Iclass_xt_iclass_rsr_ccompare1_args,
074f5109 5583 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
43cd72b9 5584 { 1, Iclass_xt_iclass_wsr_ccompare1_args,
074f5109 5585 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
43cd72b9 5586 { 1, Iclass_xt_iclass_xsr_ccompare1_args,
074f5109 5587 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
43cd72b9 5588 { 1, Iclass_xt_iclass_rsr_ccompare2_args,
074f5109 5589 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
43cd72b9 5590 { 1, Iclass_xt_iclass_wsr_ccompare2_args,
074f5109 5591 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
43cd72b9 5592 { 1, Iclass_xt_iclass_xsr_ccompare2_args,
074f5109 5593 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
43cd72b9
BW		 5594 { 2, Iclass_xt_iclass_icache_args,
5595 0, 0, 0, 0 },
33430bd0
BW		 5596 { 2, Iclass_xt_iclass_icache_lock_args,
5597 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
43cd72b9 5598 { 2, Iclass_xt_iclass_icache_inv_args,
074f5109 5599 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
43cd72b9 5600 { 2, Iclass_xt_iclass_licx_args,
074f5109 5601 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
43cd72b9 5602 { 2, Iclass_xt_iclass_sicx_args,
074f5109 5603 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
43cd72b9
BW		 5604 { 2, Iclass_xt_iclass_dcache_args,
5605 0, 0, 0, 0 },
5606 { 2, Iclass_xt_iclass_dcache_ind_args,
074f5109 5607 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
43cd72b9 5608 { 2, Iclass_xt_iclass_dcache_inv_args,
074f5109 5609 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
43cd72b9
BW		 5610 { 2, Iclass_xt_iclass_dpf_args,
5611 0, 0, 0, 0 },
33430bd0
BW		 5612 { 2, Iclass_xt_iclass_dcache_lock_args,
5613 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
43cd72b9 5614 { 2, Iclass_xt_iclass_sdct_args,
074f5109 5615 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
43cd72b9 5616 { 2, Iclass_xt_iclass_ldct_args,
074f5109
BW		 5617 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
5618 { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
5619 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
5620 { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
5621 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
5622 { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
5623 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
5624 { 1, Iclass_xt_iclass_rsr_rasid_args,
5625 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
5626 { 1, Iclass_xt_iclass_wsr_rasid_args,
5627 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
5628 { 1, Iclass_xt_iclass_xsr_rasid_args,
5629 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
5630 { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
5631 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
5632 { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
5633 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
5634 { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
5635 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
5636 { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
5637 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
5638 { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
5639 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
5640 { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
5641 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
43cd72b9 5642 { 1, Iclass_xt_iclass_idtlb_args,
074f5109 5643 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
43cd72b9 5644 { 2, Iclass_xt_iclass_rdtlb_args,
074f5109 5645 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
43cd72b9 5646 { 2, Iclass_xt_iclass_wdtlb_args,
074f5109 5647 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
43cd72b9 5648 { 1, Iclass_xt_iclass_iitlb_args,
074f5109 5649 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
43cd72b9 5650 { 2, Iclass_xt_iclass_ritlb_args,
074f5109 5651 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
43cd72b9 5652 { 2, Iclass_xt_iclass_witlb_args,
074f5109
BW		 5653 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
5654 { 0, 0 /* xt_iclass_ldpte */,
5655 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
5656 { 0, 0 /* xt_iclass_hwwitlba */,
5657 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
5658 { 0, 0 /* xt_iclass_hwwdtlba */,
5659 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
33430bd0
BW		 5660 { 1, Iclass_xt_iclass_rsr_cpenable_args,
5661 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
5662 { 1, Iclass_xt_iclass_wsr_cpenable_args,
5663 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
5664 { 1, Iclass_xt_iclass_xsr_cpenable_args,
5665 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
5666 { 3, Iclass_xt_iclass_clamp_args,
5667 0, 0, 0, 0 },
5668 { 3, Iclass_xt_iclass_minmax_args,
5669 0, 0, 0, 0 },
43cd72b9 5670 { 2, Iclass_xt_iclass_nsa_args,
33430bd0
BW		 5671 0, 0, 0, 0 },
5672 { 3, Iclass_xt_iclass_sx_args,
5673 0, 0, 0, 0 },
5674 { 3, Iclass_xt_iclass_l32ai_args,
5675 0, 0, 0, 0 },
5676 { 3, Iclass_xt_iclass_s32ri_args,
5677 0, 0, 0, 0 },
5678 { 3, Iclass_xt_iclass_s32c1i_args,
5679 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
5680 { 1, Iclass_xt_iclass_rsr_scompare1_args,
5681 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
5682 { 1, Iclass_xt_iclass_wsr_scompare1_args,
5683 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
5684 { 1, Iclass_xt_iclass_xsr_scompare1_args,
5685 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
5686 { 3, Iclass_xt_iclass_div_args,
5687 0, 0, 0, 0 },
5688 { 3, Iclass_xt_mul32_args,
43cd72b9
BW		 5689 0, 0, 0, 0 }
5690};
5691
56fb3749
SA		 5692enum xtensa_iclass_id {
5693 ICLASS_xt_iclass_excw,
5694 ICLASS_xt_iclass_rfe,
5695 ICLASS_xt_iclass_rfde,
5696 ICLASS_xt_iclass_syscall,
5697 ICLASS_xt_iclass_simcall,
5698 ICLASS_xt_iclass_call12,
5699 ICLASS_xt_iclass_call8,
5700 ICLASS_xt_iclass_call4,
5701 ICLASS_xt_iclass_callx12,
5702 ICLASS_xt_iclass_callx8,
5703 ICLASS_xt_iclass_callx4,
5704 ICLASS_xt_iclass_entry,
5705 ICLASS_xt_iclass_movsp,
5706 ICLASS_xt_iclass_rotw,
5707 ICLASS_xt_iclass_retw,
5708 ICLASS_xt_iclass_rfwou,
5709 ICLASS_xt_iclass_l32e,
5710 ICLASS_xt_iclass_s32e,
5711 ICLASS_xt_iclass_rsr_windowbase,
5712 ICLASS_xt_iclass_wsr_windowbase,
5713 ICLASS_xt_iclass_xsr_windowbase,
5714 ICLASS_xt_iclass_rsr_windowstart,
5715 ICLASS_xt_iclass_wsr_windowstart,
5716 ICLASS_xt_iclass_xsr_windowstart,
5717 ICLASS_xt_iclass_add_n,
5718 ICLASS_xt_iclass_addi_n,
5719 ICLASS_xt_iclass_bz6,
5720 ICLASS_xt_iclass_ill_n,
5721 ICLASS_xt_iclass_loadi4,
5722 ICLASS_xt_iclass_mov_n,
5723 ICLASS_xt_iclass_movi_n,
5724 ICLASS_xt_iclass_nopn,
5725 ICLASS_xt_iclass_retn,
5726 ICLASS_xt_iclass_storei4,
5727 ICLASS_rur_threadptr,
5728 ICLASS_wur_threadptr,
5729 ICLASS_xt_iclass_addi,
5730 ICLASS_xt_iclass_addmi,
5731 ICLASS_xt_iclass_addsub,
5732 ICLASS_xt_iclass_bit,
5733 ICLASS_xt_iclass_bsi8,
5734 ICLASS_xt_iclass_bsi8b,
5735 ICLASS_xt_iclass_bsi8u,
5736 ICLASS_xt_iclass_bst8,
5737 ICLASS_xt_iclass_bsz12,
5738 ICLASS_xt_iclass_call0,
5739 ICLASS_xt_iclass_callx0,
5740 ICLASS_xt_iclass_exti,
5741 ICLASS_xt_iclass_ill,
5742 ICLASS_xt_iclass_jump,
5743 ICLASS_xt_iclass_jumpx,
5744 ICLASS_xt_iclass_l16ui,
5745 ICLASS_xt_iclass_l16si,
5746 ICLASS_xt_iclass_l32i,
5747 ICLASS_xt_iclass_l32r,
5748 ICLASS_xt_iclass_l8i,
5749 ICLASS_xt_iclass_loop,
5750 ICLASS_xt_iclass_loopz,
5751 ICLASS_xt_iclass_movi,
5752 ICLASS_xt_iclass_movz,
5753 ICLASS_xt_iclass_neg,
5754 ICLASS_xt_iclass_nop,
5755 ICLASS_xt_iclass_return,
5756 ICLASS_xt_iclass_s16i,
5757 ICLASS_xt_iclass_s32i,
5758 ICLASS_xt_iclass_s8i,
5759 ICLASS_xt_iclass_sar,
5760 ICLASS_xt_iclass_sari,
5761 ICLASS_xt_iclass_shifts,
5762 ICLASS_xt_iclass_shiftst,
5763 ICLASS_xt_iclass_shiftt,
5764 ICLASS_xt_iclass_slli,
5765 ICLASS_xt_iclass_srai,
5766 ICLASS_xt_iclass_srli,
5767 ICLASS_xt_iclass_memw,
5768 ICLASS_xt_iclass_extw,
5769 ICLASS_xt_iclass_isync,
5770 ICLASS_xt_iclass_sync,
5771 ICLASS_xt_iclass_rsil,
5772 ICLASS_xt_iclass_rsr_lend,
5773 ICLASS_xt_iclass_wsr_lend,
5774 ICLASS_xt_iclass_xsr_lend,
5775 ICLASS_xt_iclass_rsr_lcount,
5776 ICLASS_xt_iclass_wsr_lcount,
5777 ICLASS_xt_iclass_xsr_lcount,
5778 ICLASS_xt_iclass_rsr_lbeg,
5779 ICLASS_xt_iclass_wsr_lbeg,
5780 ICLASS_xt_iclass_xsr_lbeg,
5781 ICLASS_xt_iclass_rsr_sar,
5782 ICLASS_xt_iclass_wsr_sar,
5783 ICLASS_xt_iclass_xsr_sar,
5784 ICLASS_xt_iclass_rsr_litbase,
5785 ICLASS_xt_iclass_wsr_litbase,
5786 ICLASS_xt_iclass_xsr_litbase,
5787 ICLASS_xt_iclass_rsr_176,
5788 ICLASS_xt_iclass_wsr_176,
5789 ICLASS_xt_iclass_rsr_208,
5790 ICLASS_xt_iclass_rsr_ps,
5791 ICLASS_xt_iclass_wsr_ps,
5792 ICLASS_xt_iclass_xsr_ps,
5793 ICLASS_xt_iclass_rsr_epc1,
5794 ICLASS_xt_iclass_wsr_epc1,
5795 ICLASS_xt_iclass_xsr_epc1,
5796 ICLASS_xt_iclass_rsr_excsave1,
5797 ICLASS_xt_iclass_wsr_excsave1,
5798 ICLASS_xt_iclass_xsr_excsave1,
5799 ICLASS_xt_iclass_rsr_epc2,
5800 ICLASS_xt_iclass_wsr_epc2,
5801 ICLASS_xt_iclass_xsr_epc2,
5802 ICLASS_xt_iclass_rsr_excsave2,
5803 ICLASS_xt_iclass_wsr_excsave2,
5804 ICLASS_xt_iclass_xsr_excsave2,
5805 ICLASS_xt_iclass_rsr_epc3,
5806 ICLASS_xt_iclass_wsr_epc3,
5807 ICLASS_xt_iclass_xsr_epc3,
5808 ICLASS_xt_iclass_rsr_excsave3,
5809 ICLASS_xt_iclass_wsr_excsave3,
5810 ICLASS_xt_iclass_xsr_excsave3,
5811 ICLASS_xt_iclass_rsr_epc4,
5812 ICLASS_xt_iclass_wsr_epc4,
5813 ICLASS_xt_iclass_xsr_epc4,
5814 ICLASS_xt_iclass_rsr_excsave4,
5815 ICLASS_xt_iclass_wsr_excsave4,
5816 ICLASS_xt_iclass_xsr_excsave4,
5817 ICLASS_xt_iclass_rsr_epc5,
5818 ICLASS_xt_iclass_wsr_epc5,
5819 ICLASS_xt_iclass_xsr_epc5,
5820 ICLASS_xt_iclass_rsr_excsave5,
5821 ICLASS_xt_iclass_wsr_excsave5,
5822 ICLASS_xt_iclass_xsr_excsave5,
5823 ICLASS_xt_iclass_rsr_epc6,
5824 ICLASS_xt_iclass_wsr_epc6,
5825 ICLASS_xt_iclass_xsr_epc6,
5826 ICLASS_xt_iclass_rsr_excsave6,
5827 ICLASS_xt_iclass_wsr_excsave6,
5828 ICLASS_xt_iclass_xsr_excsave6,
5829 ICLASS_xt_iclass_rsr_epc7,
5830 ICLASS_xt_iclass_wsr_epc7,
5831 ICLASS_xt_iclass_xsr_epc7,
5832 ICLASS_xt_iclass_rsr_excsave7,
5833 ICLASS_xt_iclass_wsr_excsave7,
5834 ICLASS_xt_iclass_xsr_excsave7,
5835 ICLASS_xt_iclass_rsr_eps2,
5836 ICLASS_xt_iclass_wsr_eps2,
5837 ICLASS_xt_iclass_xsr_eps2,
5838 ICLASS_xt_iclass_rsr_eps3,
5839 ICLASS_xt_iclass_wsr_eps3,
5840 ICLASS_xt_iclass_xsr_eps3,
5841 ICLASS_xt_iclass_rsr_eps4,
5842 ICLASS_xt_iclass_wsr_eps4,
5843 ICLASS_xt_iclass_xsr_eps4,
5844 ICLASS_xt_iclass_rsr_eps5,
5845 ICLASS_xt_iclass_wsr_eps5,
5846 ICLASS_xt_iclass_xsr_eps5,
5847 ICLASS_xt_iclass_rsr_eps6,
5848 ICLASS_xt_iclass_wsr_eps6,
5849 ICLASS_xt_iclass_xsr_eps6,
5850 ICLASS_xt_iclass_rsr_eps7,
5851 ICLASS_xt_iclass_wsr_eps7,
5852 ICLASS_xt_iclass_xsr_eps7,
5853 ICLASS_xt_iclass_rsr_excvaddr,
5854 ICLASS_xt_iclass_wsr_excvaddr,
5855 ICLASS_xt_iclass_xsr_excvaddr,
5856 ICLASS_xt_iclass_rsr_depc,
5857 ICLASS_xt_iclass_wsr_depc,
5858 ICLASS_xt_iclass_xsr_depc,
5859 ICLASS_xt_iclass_rsr_exccause,
5860 ICLASS_xt_iclass_wsr_exccause,
5861 ICLASS_xt_iclass_xsr_exccause,
5862 ICLASS_xt_iclass_rsr_misc0,
5863 ICLASS_xt_iclass_wsr_misc0,
5864 ICLASS_xt_iclass_xsr_misc0,
5865 ICLASS_xt_iclass_rsr_misc1,
5866 ICLASS_xt_iclass_wsr_misc1,
5867 ICLASS_xt_iclass_xsr_misc1,
5868 ICLASS_xt_iclass_rsr_prid,
5869 ICLASS_xt_iclass_rsr_vecbase,
5870 ICLASS_xt_iclass_wsr_vecbase,
5871 ICLASS_xt_iclass_xsr_vecbase,
5872 ICLASS_xt_iclass_mul16,
5873 ICLASS_xt_iclass_rfi,
5874 ICLASS_xt_iclass_wait,
5875 ICLASS_xt_iclass_rsr_interrupt,
5876 ICLASS_xt_iclass_wsr_intset,
5877 ICLASS_xt_iclass_wsr_intclear,
5878 ICLASS_xt_iclass_rsr_intenable,
5879 ICLASS_xt_iclass_wsr_intenable,
5880 ICLASS_xt_iclass_xsr_intenable,
5881 ICLASS_xt_iclass_break,
5882 ICLASS_xt_iclass_break_n,
5883 ICLASS_xt_iclass_rsr_dbreaka0,
5884 ICLASS_xt_iclass_wsr_dbreaka0,
5885 ICLASS_xt_iclass_xsr_dbreaka0,
5886 ICLASS_xt_iclass_rsr_dbreakc0,
5887 ICLASS_xt_iclass_wsr_dbreakc0,
5888 ICLASS_xt_iclass_xsr_dbreakc0,
5889 ICLASS_xt_iclass_rsr_dbreaka1,
5890 ICLASS_xt_iclass_wsr_dbreaka1,
5891 ICLASS_xt_iclass_xsr_dbreaka1,
5892 ICLASS_xt_iclass_rsr_dbreakc1,
5893 ICLASS_xt_iclass_wsr_dbreakc1,
5894 ICLASS_xt_iclass_xsr_dbreakc1,
5895 ICLASS_xt_iclass_rsr_ibreaka0,
5896 ICLASS_xt_iclass_wsr_ibreaka0,
5897 ICLASS_xt_iclass_xsr_ibreaka0,
5898 ICLASS_xt_iclass_rsr_ibreaka1,
5899 ICLASS_xt_iclass_wsr_ibreaka1,
5900 ICLASS_xt_iclass_xsr_ibreaka1,
5901 ICLASS_xt_iclass_rsr_ibreakenable,
5902 ICLASS_xt_iclass_wsr_ibreakenable,
5903 ICLASS_xt_iclass_xsr_ibreakenable,
5904 ICLASS_xt_iclass_rsr_debugcause,
5905 ICLASS_xt_iclass_wsr_debugcause,
5906 ICLASS_xt_iclass_xsr_debugcause,
5907 ICLASS_xt_iclass_rsr_icount,
5908 ICLASS_xt_iclass_wsr_icount,
5909 ICLASS_xt_iclass_xsr_icount,
5910 ICLASS_xt_iclass_rsr_icountlevel,
5911 ICLASS_xt_iclass_wsr_icountlevel,
5912 ICLASS_xt_iclass_xsr_icountlevel,
5913 ICLASS_xt_iclass_rsr_ddr,
5914 ICLASS_xt_iclass_wsr_ddr,
5915 ICLASS_xt_iclass_xsr_ddr,
5916 ICLASS_xt_iclass_rfdo,
5917 ICLASS_xt_iclass_rfdd,
5918 ICLASS_xt_iclass_wsr_mmid,
5919 ICLASS_xt_iclass_rsr_ccount,
5920 ICLASS_xt_iclass_wsr_ccount,
5921 ICLASS_xt_iclass_xsr_ccount,
5922 ICLASS_xt_iclass_rsr_ccompare0,
5923 ICLASS_xt_iclass_wsr_ccompare0,
5924 ICLASS_xt_iclass_xsr_ccompare0,
5925 ICLASS_xt_iclass_rsr_ccompare1,
5926 ICLASS_xt_iclass_wsr_ccompare1,
5927 ICLASS_xt_iclass_xsr_ccompare1,
5928 ICLASS_xt_iclass_rsr_ccompare2,
5929 ICLASS_xt_iclass_wsr_ccompare2,
5930 ICLASS_xt_iclass_xsr_ccompare2,
5931 ICLASS_xt_iclass_icache,
5932 ICLASS_xt_iclass_icache_lock,
5933 ICLASS_xt_iclass_icache_inv,
5934 ICLASS_xt_iclass_licx,
5935 ICLASS_xt_iclass_sicx,
5936 ICLASS_xt_iclass_dcache,
5937 ICLASS_xt_iclass_dcache_ind,
5938 ICLASS_xt_iclass_dcache_inv,
5939 ICLASS_xt_iclass_dpf,
5940 ICLASS_xt_iclass_dcache_lock,
5941 ICLASS_xt_iclass_sdct,
5942 ICLASS_xt_iclass_ldct,
5943 ICLASS_xt_iclass_wsr_ptevaddr,
5944 ICLASS_xt_iclass_rsr_ptevaddr,
5945 ICLASS_xt_iclass_xsr_ptevaddr,
5946 ICLASS_xt_iclass_rsr_rasid,
5947 ICLASS_xt_iclass_wsr_rasid,
5948 ICLASS_xt_iclass_xsr_rasid,
5949 ICLASS_xt_iclass_rsr_itlbcfg,
5950 ICLASS_xt_iclass_wsr_itlbcfg,
5951 ICLASS_xt_iclass_xsr_itlbcfg,
5952 ICLASS_xt_iclass_rsr_dtlbcfg,
5953 ICLASS_xt_iclass_wsr_dtlbcfg,
5954 ICLASS_xt_iclass_xsr_dtlbcfg,
5955 ICLASS_xt_iclass_idtlb,
5956 ICLASS_xt_iclass_rdtlb,
5957 ICLASS_xt_iclass_wdtlb,
5958 ICLASS_xt_iclass_iitlb,
5959 ICLASS_xt_iclass_ritlb,
5960 ICLASS_xt_iclass_witlb,
5961 ICLASS_xt_iclass_ldpte,
5962 ICLASS_xt_iclass_hwwitlba,
5963 ICLASS_xt_iclass_hwwdtlba,
5964 ICLASS_xt_iclass_rsr_cpenable,
5965 ICLASS_xt_iclass_wsr_cpenable,
5966 ICLASS_xt_iclass_xsr_cpenable,
5967 ICLASS_xt_iclass_clamp,
5968 ICLASS_xt_iclass_minmax,
5969 ICLASS_xt_iclass_nsa,
5970 ICLASS_xt_iclass_sx,
5971 ICLASS_xt_iclass_l32ai,
5972 ICLASS_xt_iclass_s32ri,
5973 ICLASS_xt_iclass_s32c1i,
5974 ICLASS_xt_iclass_rsr_scompare1,
5975 ICLASS_xt_iclass_wsr_scompare1,
5976 ICLASS_xt_iclass_xsr_scompare1,
5977 ICLASS_xt_iclass_div,
5978 ICLASS_xt_mul32
5979};
5980
43cd72b9
BW		 5981\f
5982/* Opcode encodings. */
5983
5984static void
5985Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
5986{
5987 slotbuf[0] = 0x80200;
5988}
5989
5990static void
5991Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
5992{
5993 slotbuf[0] = 0x300;
5994}
5995
5996static void
5997Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
5998{
5999 slotbuf[0] = 0x2300;
6000}
6001
6002static void
6003Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
6004{
6005 slotbuf[0] = 0x500;
6006}
6007
6008static void
6009Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
6010{
6011 slotbuf[0] = 0x1500;
6012}
6013
6014static void
6015Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
6016{
6017 slotbuf[0] = 0x5c0000;
6018}
6019
6020static void
6021Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
6022{
6023 slotbuf[0] = 0x580000;
6024}
6025
6026static void
6027Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6028{
6029 slotbuf[0] = 0x540000;
6030}
6031
6032static void
6033Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
6034{
6035 slotbuf[0] = 0xf0000;
6036}
6037
6038static void
6039Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
6040{
6041 slotbuf[0] = 0xb0000;
6042}
6043
6044static void
6045Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6046{
6047 slotbuf[0] = 0x70000;
6048}
6049
6050static void
6051Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
6052{
6053 slotbuf[0] = 0x6c0000;
6054}
6055
6056static void
6057Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
6058{
6059 slotbuf[0] = 0x100;
6060}
6061
6062static void
6063Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6064{
6065 slotbuf[0] = 0x804;
6066}
6067
6068static void
6069Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6070{
6071 slotbuf[0] = 0x60000;
6072}
6073
6074static void
6075Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6076{
6077 slotbuf[0] = 0xd10f;
6078}
6079
6080static void
6081Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
6082{
6083 slotbuf[0] = 0x4300;
6084}
6085
6086static void
6087Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
6088{
6089 slotbuf[0] = 0x5300;
6090}
6091
6092static void
6093Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
6094{
6095 slotbuf[0] = 0x90;
6096}
6097
6098static void
6099Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
6100{
6101 slotbuf[0] = 0x94;
6102}
6103
6104static void
6105Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6106{
6107 slotbuf[0] = 0x4830;
6108}
6109
6110static void
6111Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6112{
6113 slotbuf[0] = 0x4831;
6114}
6115
6116static void
6117Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6118{
6119 slotbuf[0] = 0x4816;
6120}
6121
6122static void
6123Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
6124{
6125 slotbuf[0] = 0x4930;
6126}
6127
6128static void
6129Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
6130{
6131 slotbuf[0] = 0x4931;
6132}
6133
6134static void
6135Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
6136{
6137 slotbuf[0] = 0x4916;
6138}
6139
6140static void
6141Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
6142{
6143 slotbuf[0] = 0xa000;
6144}
6145
6146static void
6147Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
6148{
6149 slotbuf[0] = 0xb000;
6150}
6151
6152static void
6153Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6154{
6155 slotbuf[0] = 0xc800;
6156}
6157
6158static void
6159Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6160{
6161 slotbuf[0] = 0xcc00;
6162}
6163
6164static void
6165Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6166{
6167 slotbuf[0] = 0xd60f;
6168}
6169
6170static void
6171Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
6172{
6173 slotbuf[0] = 0x8000;
6174}
6175
6176static void
6177Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6178{
6179 slotbuf[0] = 0xd000;
6180}
6181
6182static void
6183Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6184{
6185 slotbuf[0] = 0xc000;
6186}
6187
6188static void
6189Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6190{
6191 slotbuf[0] = 0xd30f;
6192}
6193
6194static void
6195Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6196{
6197 slotbuf[0] = 0xd00f;
6198}
6199
6200static void
6201Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
6202{
6203 slotbuf[0] = 0x9000;
6204}
6205
33430bd0
BW		 6206static void
6207Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6208{
6209 slotbuf[0] = 0x7e03e;
6210}
6211
6212static void
6213Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6214{
6215 slotbuf[0] = 0xe73f;
6216}
6217
43cd72b9
BW		 6218static void
6219Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6220{
6221 slotbuf[0] = 0x200c00;
6222}
6223
6224static void
6225Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6226{
6227 slotbuf[0] = 0x200d00;
6228}
6229
6230static void
6231Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
6232{
6233 slotbuf[0] = 0x8;
6234}
6235
6236static void
6237Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
6238{
6239 slotbuf[0] = 0xc;
6240}
6241
6242static void
6243Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6244{
6245 slotbuf[0] = 0x9;
6246}
6247
6248static void
6249Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6250{
6251 slotbuf[0] = 0xa;
6252}
6253
6254static void
6255Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
6256{
6257 slotbuf[0] = 0xb;
6258}
6259
6260static void
6261Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6262{
6263 slotbuf[0] = 0xd;
6264}
6265
6266static void
6267Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6268{
6269 slotbuf[0] = 0xe;
6270}
6271
6272static void
6273Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
6274{
6275 slotbuf[0] = 0xf;
6276}
6277
6278static void
6279Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
6280{
6281 slotbuf[0] = 0x1;
6282}
6283
6284static void
6285Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
6286{
6287 slotbuf[0] = 0x2;
6288}
6289
6290static void
6291Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
6292{
6293 slotbuf[0] = 0x3;
6294}
6295
6296static void
6297Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6298{
6299 slotbuf[0] = 0x680000;
6300}
6301
6302static void
6303Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
6304{
6305 slotbuf[0] = 0x690000;
6306}
6307
6308static void
6309Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
6310{
6311 slotbuf[0] = 0x6b0000;
6312}
6313
6314static void
6315Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
6316{
6317 slotbuf[0] = 0x6a0000;
6318}
6319
6320static void
6321Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
6322{
6323 slotbuf[0] = 0x700600;
6324}
6325
6326static void
6327Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6328{
6329 slotbuf[0] = 0x700e00;
6330}
6331
6332static void
6333Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6334{
6335 slotbuf[0] = 0x6f0000;
6336}
6337
6338static void
6339Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6340{
6341 slotbuf[0] = 0x6e0000;
6342}
6343
6344static void
6345Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
6346{
6347 slotbuf[0] = 0x700100;
6348}
6349
6350static void
6351Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
6352{
6353 slotbuf[0] = 0x700900;
6354}
6355
6356static void
6357Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
6358{
6359 slotbuf[0] = 0x700a00;
6360}
6361
6362static void
6363Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
6364{
6365 slotbuf[0] = 0x700200;
6366}
6367
6368static void
6369Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
6370{
6371 slotbuf[0] = 0x700b00;
6372}
6373
6374static void
6375Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
6376{
6377 slotbuf[0] = 0x700300;
6378}
6379
6380static void
6381Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
6382{
6383 slotbuf[0] = 0x700800;
6384}
6385
6386static void
6387Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
6388{
6389 slotbuf[0] = 0x700000;
6390}
6391
6392static void
6393Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
6394{
6395 slotbuf[0] = 0x700400;
6396}
6397
6398static void
6399Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
6400{
6401 slotbuf[0] = 0x700c00;
6402}
6403
6404static void
6405Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
6406{
6407 slotbuf[0] = 0x700500;
6408}
6409
6410static void
6411Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
6412{
6413 slotbuf[0] = 0x700d00;
6414}
6415
6416static void
6417Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6418{
6419 slotbuf[0] = 0x640000;
6420}
6421
6422static void
6423Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6424{
6425 slotbuf[0] = 0x650000;
6426}
6427
6428static void
6429Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6430{
6431 slotbuf[0] = 0x670000;
6432}
6433
6434static void
6435Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6436{
6437 slotbuf[0] = 0x660000;
6438}
6439
6440static void
6441Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6442{
6443 slotbuf[0] = 0x500000;
6444}
6445
6446static void
6447Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6448{
6449 slotbuf[0] = 0x30000;
6450}
6451
6452static void
6453Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6454{
6455 slotbuf[0] = 0x40;
6456}
6457
6458static void
6459Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
6460{
6461 slotbuf[0] = 0;
6462}
6463
6464static void
6465Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
6466{
6467 slotbuf[0] = 0x600000;
6468}
6469
6470static void
6471Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
6472{
6473 slotbuf[0] = 0xa0000;
6474}
6475
6476static void
6477Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6478{
6479 slotbuf[0] = 0x200100;
6480}
6481
6482static void
6483Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
6484{
6485 slotbuf[0] = 0x200900;
6486}
6487
6488static void
6489Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6490{
6491 slotbuf[0] = 0x200200;
6492}
6493
6494static void
6495Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
6496{
6497 slotbuf[0] = 0x100000;
6498}
6499
6500static void
6501Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6502{
6503 slotbuf[0] = 0x200000;
6504}
6505
6506static void
6507Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
6508{
6509 slotbuf[0] = 0x6d0800;
6510}
6511
6512static void
6513Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6514{
6515 slotbuf[0] = 0x6d0900;
6516}
6517
6518static void
6519Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6520{
6521 slotbuf[0] = 0x6d0a00;
6522}
6523
6524static void
6525Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6526{
6527 slotbuf[0] = 0x200a00;
6528}
6529
6530static void
6531Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6532{
6533 slotbuf[0] = 0x38;
6534}
6535
6536static void
6537Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6538{
6539 slotbuf[0] = 0x39;
6540}
6541
6542static void
6543Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6544{
6545 slotbuf[0] = 0x3a;
6546}
6547
6548static void
6549Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6550{
6551 slotbuf[0] = 0x3b;
6552}
6553
6554static void
6555Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
6556{
6557 slotbuf[0] = 0x6;
6558}
6559
6560static void
6561Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
6562{
6563 slotbuf[0] = 0x1006;
6564}
6565
6566static void
6567Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
6568{
6569 slotbuf[0] = 0xf0200;
6570}
6571
6572static void
6573Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
6574{
6575 slotbuf[0] = 0x20000;
6576}
6577
6578static void
6579Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6580{
6581 slotbuf[0] = 0x200500;
6582}
6583
6584static void
6585Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6586{
6587 slotbuf[0] = 0x200600;
6588}
6589
6590static void
6591Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6592{
6593 slotbuf[0] = 0x200400;
6594}
6595
6596static void
6597Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6598{
6599 slotbuf[0] = 0x4;
6600}
6601
6602static void
6603Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
6604{
6605 slotbuf[0] = 0x104;
6606}
6607
6608static void
6609Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
6610{
6611 slotbuf[0] = 0x204;
6612}
6613
6614static void
6615Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
6616{
6617 slotbuf[0] = 0x304;
6618}
6619
6620static void
6621Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
6622{
6623 slotbuf[0] = 0x404;
6624}
6625
6626static void
6627Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
6628{
6629 slotbuf[0] = 0x1a;
6630}
6631
6632static void
6633Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
6634{
6635 slotbuf[0] = 0x18;
6636}
6637
6638static void
6639Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
6640{
6641 slotbuf[0] = 0x19;
6642}
6643
6644static void
6645Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
6646{
6647 slotbuf[0] = 0x1b;
6648}
6649
6650static void
6651Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
6652{
6653 slotbuf[0] = 0x10;
6654}
6655
6656static void
6657Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
6658{
6659 slotbuf[0] = 0x12;
6660}
6661
6662static void
6663Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
6664{
6665 slotbuf[0] = 0x14;
6666}
6667
6668static void
6669Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6670{
6671 slotbuf[0] = 0xc0200;
6672}
6673
6674static void
6675Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6676{
6677 slotbuf[0] = 0xd0200;
6678}
6679
6680static void
6681Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
6682{
6683 slotbuf[0] = 0x200;
6684}
6685
6686static void
6687Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
6688{
6689 slotbuf[0] = 0x10200;
6690}
6691
6692static void
6693Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
6694{
6695 slotbuf[0] = 0x20200;
6696}
6697
6698static void
6699Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
6700{
6701 slotbuf[0] = 0x30200;
6702}
6703
6704static void
6705Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
6706{
6707 slotbuf[0] = 0x600;
6708}
6709
6710static void
6711Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
6712{
6713 slotbuf[0] = 0x130;
6714}
6715
6716static void
6717Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
6718{
6719 slotbuf[0] = 0x131;
6720}
6721
6722static void
6723Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
6724{
6725 slotbuf[0] = 0x116;
6726}
6727
6728static void
6729Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
6730{
6731 slotbuf[0] = 0x230;
6732}
6733
6734static void
6735Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
6736{
6737 slotbuf[0] = 0x231;
6738}
6739
6740static void
6741Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
6742{
6743 slotbuf[0] = 0x216;
6744}
6745
6746static void
6747Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
6748{
6749 slotbuf[0] = 0x30;
6750}
6751
6752static void
6753Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
6754{
6755 slotbuf[0] = 0x31;
6756}
6757
6758static void
6759Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
6760{
6761 slotbuf[0] = 0x16;
6762}
6763
6764static void
6765Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
6766{
6767 slotbuf[0] = 0x330;
6768}
6769
6770static void
6771Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
6772{
6773 slotbuf[0] = 0x331;
6774}
6775
6776static void
6777Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
6778{
6779 slotbuf[0] = 0x316;
6780}
6781
6782static void
6783Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6784{
6785 slotbuf[0] = 0x530;
6786}
6787
6788static void
33430bd0
BW		 6789Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6790{
6791 slotbuf[0] = 0x531;
6792}
6793
6794static void
6795Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6796{
6797 slotbuf[0] = 0x516;
6798}
6799
6800static void
6801Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
6802{
6803 slotbuf[0] = 0xb030;
6804}
6805
6806static void
6807Opcode_wsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
6808{
6809 slotbuf[0] = 0xb031;
6810}
6811
6812static void
6813Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
6814{
6815 slotbuf[0] = 0xd030;
6816}
6817
6818static void
6819Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
6820{
6821 slotbuf[0] = 0xe630;
6822}
6823
6824static void
6825Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
6826{
6827 slotbuf[0] = 0xe631;
6828}
6829
6830static void
6831Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
6832{
6833 slotbuf[0] = 0xe616;
6834}
6835
6836static void
6837Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6838{
6839 slotbuf[0] = 0xb130;
6840}
6841
6842static void
6843Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6844{
6845 slotbuf[0] = 0xb131;
6846}
6847
6848static void
6849Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6850{
6851 slotbuf[0] = 0xb116;
6852}
6853
6854static void
6855Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6856{
6857 slotbuf[0] = 0xd130;
6858}
6859
6860static void
6861Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6862{
6863 slotbuf[0] = 0xd131;
6864}
6865
6866static void
6867Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
6868{
6869 slotbuf[0] = 0xd116;
6870}
6871
6872static void
6873Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6874{
6875 slotbuf[0] = 0xb230;
6876}
6877
6878static void
6879Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6880{
6881 slotbuf[0] = 0xb231;
6882}
6883
6884static void
6885Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6886{
6887 slotbuf[0] = 0xb216;
6888}
6889
6890static void
6891Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6892{
6893 slotbuf[0] = 0xd230;
6894}
6895
6896static void
6897Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6898{
6899 slotbuf[0] = 0xd231;
6900}
6901
6902static void
6903Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6904{
6905 slotbuf[0] = 0xd216;
6906}
6907
6908static void
6909Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6910{
6911 slotbuf[0] = 0xb330;
6912}
6913
6914static void
6915Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6916{
6917 slotbuf[0] = 0xb331;
6918}
6919
6920static void
6921Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6922{
6923 slotbuf[0] = 0xb316;
6924}
6925
6926static void
6927Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6928{
6929 slotbuf[0] = 0xd330;
6930}
6931
6932static void
6933Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6934{
6935 slotbuf[0] = 0xd331;
6936}
6937
6938static void
6939Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
6940{
6941 slotbuf[0] = 0xd316;
6942}
6943
6944static void
6945Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6946{
6947 slotbuf[0] = 0xb430;
6948}
6949
6950static void
6951Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6952{
6953 slotbuf[0] = 0xb431;
6954}
6955
6956static void
6957Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 6958{
33430bd0 6959 slotbuf[0] = 0xb416;
43cd72b9
BW		 6960}
6961
6962static void
33430bd0 6963Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 6964{
33430bd0 6965 slotbuf[0] = 0xd430;
43cd72b9
BW		 6966}
6967
6968static void
33430bd0 6969Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 6970{
33430bd0 6971 slotbuf[0] = 0xd431;
43cd72b9
BW		 6972}
6973
6974static void
33430bd0 6975Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 6976{
33430bd0 6977 slotbuf[0] = 0xd416;
43cd72b9
BW		 6978}
6979
6980static void
33430bd0 6981Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 6982{
33430bd0 6983 slotbuf[0] = 0xb530;
43cd72b9
BW		 6984}
6985
6986static void
33430bd0 6987Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 6988{
33430bd0 6989 slotbuf[0] = 0xb531;
43cd72b9
BW		 6990}
6991
6992static void
33430bd0 6993Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 6994{
33430bd0 6995 slotbuf[0] = 0xb516;
43cd72b9
BW		 6996}
6997
6998static void
33430bd0 6999Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7000{
33430bd0 7001 slotbuf[0] = 0xd530;
43cd72b9
BW		 7002}
7003
7004static void
33430bd0 7005Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7006{
33430bd0 7007 slotbuf[0] = 0xd531;
43cd72b9
BW		 7008}
7009
7010static void
33430bd0 7011Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7012{
33430bd0 7013 slotbuf[0] = 0xd516;
43cd72b9
BW		 7014}
7015
7016static void
33430bd0 7017Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7018{
33430bd0 7019 slotbuf[0] = 0xb630;
43cd72b9
BW		 7020}
7021
7022static void
33430bd0 7023Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7024{
33430bd0 7025 slotbuf[0] = 0xb631;
43cd72b9
BW		 7026}
7027
7028static void
33430bd0 7029Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7030{
33430bd0 7031 slotbuf[0] = 0xb616;
43cd72b9
BW		 7032}
7033
7034static void
33430bd0 7035Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7036{
33430bd0 7037 slotbuf[0] = 0xd630;
43cd72b9
BW		 7038}
7039
7040static void
33430bd0 7041Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7042{
33430bd0 7043 slotbuf[0] = 0xd631;
43cd72b9
BW		 7044}
7045
7046static void
33430bd0 7047Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7048{
33430bd0 7049 slotbuf[0] = 0xd616;
43cd72b9
BW		 7050}
7051
7052static void
33430bd0 7053Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7054{
33430bd0 7055 slotbuf[0] = 0xb730;
43cd72b9
BW		 7056}
7057
7058static void
33430bd0 7059Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7060{
33430bd0 7061 slotbuf[0] = 0xb731;
43cd72b9
BW		 7062}
7063
7064static void
33430bd0 7065Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7066{
33430bd0 7067 slotbuf[0] = 0xb716;
43cd72b9
BW		 7068}
7069
7070static void
33430bd0 7071Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7072{
33430bd0 7073 slotbuf[0] = 0xd730;
43cd72b9
BW		 7074}
7075
7076static void
33430bd0 7077Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7078{
33430bd0 7079 slotbuf[0] = 0xd731;
43cd72b9
BW		 7080}
7081
7082static void
33430bd0 7083Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7084{
33430bd0 7085 slotbuf[0] = 0xd716;
43cd72b9
BW		 7086}
7087
7088static void
33430bd0 7089Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7090{
33430bd0 7091 slotbuf[0] = 0xc230;
43cd72b9
BW		 7092}
7093
7094static void
33430bd0 7095Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7096{
33430bd0 7097 slotbuf[0] = 0xc231;
43cd72b9
BW		 7098}
7099
7100static void
33430bd0 7101Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7102{
33430bd0 7103 slotbuf[0] = 0xc216;
43cd72b9
BW		 7104}
7105
7106static void
33430bd0 7107Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7108{
33430bd0 7109 slotbuf[0] = 0xc330;
43cd72b9
BW		 7110}
7111
7112static void
33430bd0 7113Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7114{
33430bd0 7115 slotbuf[0] = 0xc331;
43cd72b9
BW		 7116}
7117
7118static void
33430bd0 7119Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7120{
33430bd0 7121 slotbuf[0] = 0xc316;
43cd72b9
BW		 7122}
7123
7124static void
33430bd0 7125Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7126{
33430bd0 7127 slotbuf[0] = 0xc430;
43cd72b9
BW		 7128}
7129
7130static void
33430bd0 7131Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7132{
33430bd0 7133 slotbuf[0] = 0xc431;
43cd72b9
BW		 7134}
7135
7136static void
33430bd0 7137Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7138{
33430bd0 7139 slotbuf[0] = 0xc416;
43cd72b9
BW		 7140}
7141
7142static void
33430bd0 7143Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7144{
33430bd0 7145 slotbuf[0] = 0xc530;
43cd72b9
BW		 7146}
7147
7148static void
33430bd0 7149Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7150{
33430bd0 7151 slotbuf[0] = 0xc531;
43cd72b9
BW		 7152}
7153
7154static void
33430bd0 7155Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7156{
33430bd0 7157 slotbuf[0] = 0xc516;
43cd72b9
BW		 7158}
7159
7160static void
33430bd0 7161Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7162{
33430bd0 7163 slotbuf[0] = 0xc630;
43cd72b9
BW		 7164}
7165
7166static void
33430bd0 7167Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7168{
33430bd0 7169 slotbuf[0] = 0xc631;
43cd72b9
BW		 7170}
7171
7172static void
33430bd0 7173Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7174{
33430bd0 7175 slotbuf[0] = 0xc616;
43cd72b9
BW		 7176}
7177
7178static void
33430bd0 7179Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7180{
33430bd0 7181 slotbuf[0] = 0xc730;
43cd72b9
BW		 7182}
7183
7184static void
33430bd0 7185Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7186{
33430bd0 7187 slotbuf[0] = 0xc731;
43cd72b9
BW		 7188}
7189
7190static void
33430bd0 7191Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 7192{
33430bd0 7193 slotbuf[0] = 0xc716;
43cd72b9
BW		 7194}
7195
7196static void
7197Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7198{
7199 slotbuf[0] = 0xee30;
7200}
7201
7202static void
7203Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7204{
7205 slotbuf[0] = 0xee31;
7206}
7207
7208static void
7209Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7210{
7211 slotbuf[0] = 0xee16;
7212}
7213
7214static void
7215Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
7216{
7217 slotbuf[0] = 0xc030;
7218}
7219
7220static void
7221Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
7222{
7223 slotbuf[0] = 0xc031;
7224}
7225
7226static void
7227Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
7228{
7229 slotbuf[0] = 0xc016;
7230}
7231
7232static void
7233Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
7234{
7235 slotbuf[0] = 0xe830;
7236}
7237
7238static void
7239Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
7240{
7241 slotbuf[0] = 0xe831;
7242}
7243
7244static void
7245Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
7246{
7247 slotbuf[0] = 0xe816;
7248}
7249
7250static void
7251Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7252{
7253 slotbuf[0] = 0xf430;
7254}
7255
7256static void
7257Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7258{
7259 slotbuf[0] = 0xf431;
7260}
7261
7262static void
7263Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7264{
7265 slotbuf[0] = 0xf416;
7266}
7267
7268static void
7269Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7270{
7271 slotbuf[0] = 0xf530;
7272}
7273
7274static void
7275Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7276{
7277 slotbuf[0] = 0xf531;
7278}
7279
7280static void
7281Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7282{
7283 slotbuf[0] = 0xf516;
7284}
7285
7286static void
7287Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
7288{
7289 slotbuf[0] = 0xeb30;
7290}
7291
33430bd0
BW		 7292static void
7293Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7294{
7295 slotbuf[0] = 0xe730;
7296}
7297
7298static void
7299Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7300{
7301 slotbuf[0] = 0xe731;
7302}
7303
7304static void
7305Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7306{
7307 slotbuf[0] = 0xe716;
7308}
7309
7310static void
7311Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
7312{
7313 slotbuf[0] = 0x1c;
7314}
7315
7316static void
7317Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
7318{
7319 slotbuf[0] = 0x1d;
7320}
7321
43cd72b9
BW		 7322static void
7323Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
7324{
7325 slotbuf[0] = 0x10300;
7326}
7327
7328static void
7329Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
7330{
7331 slotbuf[0] = 0x700;
7332}
7333
7334static void
7335Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
7336{
7337 slotbuf[0] = 0xe230;
7338}
7339
7340static void
7341Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
7342{
7343 slotbuf[0] = 0xe231;
7344}
7345
7346static void
7347Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
7348{
7349 slotbuf[0] = 0xe331;
7350}
7351
7352static void
7353Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
7354{
7355 slotbuf[0] = 0xe430;
7356}
7357
7358static void
7359Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
7360{
7361 slotbuf[0] = 0xe431;
7362}
7363
7364static void
7365Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
7366{
7367 slotbuf[0] = 0xe416;
7368}
7369
7370static void
7371Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7372{
43cd72b9 7373 slotbuf[0] = 0x400;
e0001a05
NC		 7374}
7375
43cd72b9
BW		 7376static void
7377Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
e0001a05 7378{
43cd72b9 7379 slotbuf[0] = 0xd20f;
e0001a05
NC		 7380}
7381
43cd72b9
BW		 7382static void
7383Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7384{
43cd72b9 7385 slotbuf[0] = 0x9030;
e0001a05
NC		 7386}
7387
43cd72b9
BW		 7388static void
7389Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7390{
43cd72b9 7391 slotbuf[0] = 0x9031;
e0001a05
NC		 7392}
7393
43cd72b9
BW		 7394static void
7395Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7396{
43cd72b9 7397 slotbuf[0] = 0x9016;
e0001a05
NC		 7398}
7399
43cd72b9
BW		 7400static void
7401Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7402{
43cd72b9 7403 slotbuf[0] = 0xa030;
e0001a05
NC		 7404}
7405
43cd72b9
BW		 7406static void
7407Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7408{
43cd72b9 7409 slotbuf[0] = 0xa031;
e0001a05
NC		 7410}
7411
43cd72b9
BW		 7412static void
7413Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7414{
43cd72b9 7415 slotbuf[0] = 0xa016;
e0001a05
NC		 7416}
7417
43cd72b9
BW		 7418static void
7419Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7420{
43cd72b9 7421 slotbuf[0] = 0x9130;
e0001a05
NC		 7422}
7423
43cd72b9
BW		 7424static void
7425Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7426{
43cd72b9 7427 slotbuf[0] = 0x9131;
e0001a05
NC		 7428}
7429
43cd72b9
BW		 7430static void
7431Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7432{
43cd72b9 7433 slotbuf[0] = 0x9116;
e0001a05
NC		 7434}
7435
43cd72b9
BW		 7436static void
7437Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7438{
43cd72b9 7439 slotbuf[0] = 0xa130;
e0001a05
NC		 7440}
7441
43cd72b9
BW		 7442static void
7443Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7444{
43cd72b9 7445 slotbuf[0] = 0xa131;
e0001a05
NC		 7446}
7447
43cd72b9
BW		 7448static void
7449Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7450{
43cd72b9 7451 slotbuf[0] = 0xa116;
e0001a05
NC		 7452}
7453
43cd72b9
BW		 7454static void
7455Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7456{
43cd72b9 7457 slotbuf[0] = 0x8030;
e0001a05
NC		 7458}
7459
43cd72b9
BW		 7460static void
7461Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7462{
43cd72b9 7463 slotbuf[0] = 0x8031;
e0001a05
NC		 7464}
7465
43cd72b9
BW		 7466static void
7467Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7468{
43cd72b9 7469 slotbuf[0] = 0x8016;
e0001a05
NC		 7470}
7471
43cd72b9
BW		 7472static void
7473Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7474{
43cd72b9 7475 slotbuf[0] = 0x8130;
e0001a05
NC		 7476}
7477
43cd72b9
BW		 7478static void
7479Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7480{
43cd72b9 7481 slotbuf[0] = 0x8131;
e0001a05
NC		 7482}
7483
43cd72b9
BW		 7484static void
7485Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7486{
43cd72b9 7487 slotbuf[0] = 0x8116;
e0001a05
NC		 7488}
7489
43cd72b9
BW		 7490static void
7491Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7492{
43cd72b9 7493 slotbuf[0] = 0x6030;
e0001a05
NC		 7494}
7495
43cd72b9
BW		 7496static void
7497Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7498{
43cd72b9 7499 slotbuf[0] = 0x6031;
e0001a05
NC		 7500}
7501
43cd72b9
BW		 7502static void
7503Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7504{
43cd72b9 7505 slotbuf[0] = 0x6016;
e0001a05
NC		 7506}
7507
43cd72b9
BW		 7508static void
7509Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7510{
43cd72b9 7511 slotbuf[0] = 0xe930;
e0001a05
NC		 7512}
7513
43cd72b9
BW		 7514static void
7515Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7516{
43cd72b9 7517 slotbuf[0] = 0xe931;
e0001a05
NC		 7518}
7519
43cd72b9
BW		 7520static void
7521Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7522{
43cd72b9 7523 slotbuf[0] = 0xe916;
e0001a05
NC		 7524}
7525
43cd72b9
BW		 7526static void
7527Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7528{
43cd72b9 7529 slotbuf[0] = 0xec30;
e0001a05
NC		 7530}
7531
43cd72b9
BW		 7532static void
7533Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7534{
43cd72b9 7535 slotbuf[0] = 0xec31;
e0001a05
NC		 7536}
7537
43cd72b9
BW		 7538static void
7539Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7540{
43cd72b9 7541 slotbuf[0] = 0xec16;
e0001a05
NC		 7542}
7543
43cd72b9
BW		 7544static void
7545Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7546{
43cd72b9 7547 slotbuf[0] = 0xed30;
e0001a05
NC		 7548}
7549
43cd72b9
BW		 7550static void
7551Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7552{
43cd72b9 7553 slotbuf[0] = 0xed31;
e0001a05
NC		 7554}
7555
43cd72b9
BW		 7556static void
7557Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7558{
43cd72b9 7559 slotbuf[0] = 0xed16;
e0001a05
NC		 7560}
7561
43cd72b9
BW		 7562static void
7563Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7564{
43cd72b9 7565 slotbuf[0] = 0x6830;
e0001a05
NC		 7566}
7567
43cd72b9
BW		 7568static void
7569Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7570{
43cd72b9 7571 slotbuf[0] = 0x6831;
e0001a05
NC		 7572}
7573
43cd72b9
BW		 7574static void
7575Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7576{
43cd72b9 7577 slotbuf[0] = 0x6816;
e0001a05
NC		 7578}
7579
43cd72b9
BW		 7580static void
7581Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7582{
43cd72b9 7583 slotbuf[0] = 0xe1f;
e0001a05
NC		 7584}
7585
43cd72b9
BW		 7586static void
7587Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7588{
43cd72b9 7589 slotbuf[0] = 0x10e1f;
e0001a05
NC		 7590}
7591
33430bd0
BW		 7592static void
7593Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
7594{
7595 slotbuf[0] = 0x5931;
7596}
7597
43cd72b9
BW		 7598static void
7599Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7600{
43cd72b9 7601 slotbuf[0] = 0xea30;
e0001a05
NC		 7602}
7603
43cd72b9
BW		 7604static void
7605Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7606{
43cd72b9 7607 slotbuf[0] = 0xea31;
e0001a05
NC		 7608}
7609
43cd72b9
BW		 7610static void
7611Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7612{
43cd72b9 7613 slotbuf[0] = 0xea16;
e0001a05
NC		 7614}
7615
43cd72b9
BW		 7616static void
7617Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7618{
43cd72b9 7619 slotbuf[0] = 0xf030;
e0001a05
NC		 7620}
7621
43cd72b9
BW		 7622static void
7623Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7624{
43cd72b9 7625 slotbuf[0] = 0xf031;
e0001a05
NC		 7626}
7627
43cd72b9
BW		 7628static void
7629Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7630{
43cd72b9 7631 slotbuf[0] = 0xf016;
e0001a05
NC		 7632}
7633
43cd72b9
BW		 7634static void
7635Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7636{
43cd72b9 7637 slotbuf[0] = 0xf130;
e0001a05
NC		 7638}
7639
43cd72b9
BW		 7640static void
7641Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7642{
43cd72b9 7643 slotbuf[0] = 0xf131;
e0001a05
NC		 7644}
7645
43cd72b9
BW		 7646static void
7647Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7648{
43cd72b9 7649 slotbuf[0] = 0xf116;
e0001a05
NC		 7650}
7651
43cd72b9
BW		 7652static void
7653Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7654{
43cd72b9 7655 slotbuf[0] = 0xf230;
e0001a05
NC		 7656}
7657
43cd72b9
BW		 7658static void
7659Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7660{
43cd72b9 7661 slotbuf[0] = 0xf231;
e0001a05
NC		 7662}
7663
43cd72b9
BW		 7664static void
7665Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7666{
43cd72b9 7667 slotbuf[0] = 0xf216;
e0001a05
NC		 7668}
7669
43cd72b9
BW		 7670static void
7671Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7672{
43cd72b9 7673 slotbuf[0] = 0x2c0700;
e0001a05
NC		 7674}
7675
43cd72b9
BW		 7676static void
7677Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7678{
43cd72b9 7679 slotbuf[0] = 0x2e0700;
e0001a05
NC		 7680}
7681
33430bd0
BW		 7682static void
7683Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7684{
7685 slotbuf[0] = 0x2d0700;
7686}
7687
7688static void
7689Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
7690{
7691 slotbuf[0] = 0x2d0720;
7692}
7693
7694static void
7695Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
7696{
7697 slotbuf[0] = 0x2d0730;
7698}
7699
43cd72b9
BW		 7700static void
7701Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7702{
43cd72b9 7703 slotbuf[0] = 0x2f0700;
e0001a05
NC		 7704}
7705
43cd72b9
BW		 7706static void
7707Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7708{
43cd72b9 7709 slotbuf[0] = 0x1f;
e0001a05
NC		 7710}
7711
43cd72b9
BW		 7712static void
7713Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7714{
43cd72b9 7715 slotbuf[0] = 0x21f;
e0001a05
NC		 7716}
7717
43cd72b9
BW		 7718static void
7719Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7720{
43cd72b9 7721 slotbuf[0] = 0x11f;
e0001a05
NC		 7722}
7723
43cd72b9
BW		 7724static void
7725Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7726{
43cd72b9 7727 slotbuf[0] = 0x31f;
e0001a05
NC		 7728}
7729
43cd72b9
BW		 7730static void
7731Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7732{
43cd72b9 7733 slotbuf[0] = 0x240700;
e0001a05
NC		 7734}
7735
43cd72b9
BW		 7736static void
7737Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7738{
43cd72b9 7739 slotbuf[0] = 0x250700;
e0001a05
NC		 7740}
7741
43cd72b9
BW		 7742static void
7743Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7744{
43cd72b9 7745 slotbuf[0] = 0x280740;
e0001a05
NC		 7746}
7747
43cd72b9
BW		 7748static void
7749Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7750{
43cd72b9 7751 slotbuf[0] = 0x280750;
e0001a05
NC		 7752}
7753
43cd72b9
BW		 7754static void
7755Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7756{
43cd72b9 7757 slotbuf[0] = 0x260700;
e0001a05
NC		 7758}
7759
43cd72b9
BW		 7760static void
7761Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7762{
43cd72b9 7763 slotbuf[0] = 0x270700;
e0001a05
NC		 7764}
7765
43cd72b9
BW		 7766static void
7767Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7768{
43cd72b9 7769 slotbuf[0] = 0x200700;
e0001a05
NC		 7770}
7771
43cd72b9
BW		 7772static void
7773Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7774{
43cd72b9 7775 slotbuf[0] = 0x210700;
e0001a05
NC		 7776}
7777
43cd72b9
BW		 7778static void
7779Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7780{
43cd72b9 7781 slotbuf[0] = 0x220700;
e0001a05
NC		 7782}
7783
43cd72b9
BW		 7784static void
7785Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7786{
43cd72b9 7787 slotbuf[0] = 0x230700;
e0001a05
NC		 7788}
7789
33430bd0
BW		 7790static void
7791Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7792{
7793 slotbuf[0] = 0x280700;
7794}
7795
7796static void
7797Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
7798{
7799 slotbuf[0] = 0x280720;
7800}
7801
7802static void
7803Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
7804{
7805 slotbuf[0] = 0x280730;
7806}
7807
43cd72b9
BW		 7808static void
7809Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7810{
43cd72b9 7811 slotbuf[0] = 0x91f;
e0001a05
NC		 7812}
7813
43cd72b9
BW		 7814static void
7815Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7816{
43cd72b9 7817 slotbuf[0] = 0x81f;
e0001a05
NC		 7818}
7819
074f5109
BW		 7820static void
7821Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7822{
7823 slotbuf[0] = 0x5331;
7824}
7825
7826static void
7827Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7828{
7829 slotbuf[0] = 0x5330;
7830}
7831
7832static void
7833Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7834{
7835 slotbuf[0] = 0x5316;
7836}
7837
7838static void
7839Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
7840{
7841 slotbuf[0] = 0x5a30;
7842}
7843
7844static void
7845Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
7846{
7847 slotbuf[0] = 0x5a31;
7848}
7849
7850static void
7851Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
7852{
7853 slotbuf[0] = 0x5a16;
7854}
7855
7856static void
7857Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7858{
7859 slotbuf[0] = 0x5b30;
7860}
7861
7862static void
7863Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7864{
7865 slotbuf[0] = 0x5b31;
7866}
7867
7868static void
7869Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7870{
7871 slotbuf[0] = 0x5b16;
7872}
7873
7874static void
7875Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7876{
7877 slotbuf[0] = 0x5c30;
7878}
7879
7880static void
7881Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7882{
7883 slotbuf[0] = 0x5c31;
7884}
7885
7886static void
7887Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7888{
7889 slotbuf[0] = 0x5c16;
7890}
7891
43cd72b9
BW		 7892static void
7893Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7894{
43cd72b9 7895 slotbuf[0] = 0xc05;
e0001a05
NC		 7896}
7897
43cd72b9
BW		 7898static void
7899Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7900{
43cd72b9 7901 slotbuf[0] = 0xd05;
e0001a05
NC		 7902}
7903
43cd72b9
BW		 7904static void
7905Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7906{
43cd72b9 7907 slotbuf[0] = 0xb05;
e0001a05
NC		 7908}
7909
43cd72b9
BW		 7910static void
7911Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 7912{
43cd72b9 7913 slotbuf[0] = 0xf05;
e0001a05
NC		 7914}
7915
43cd72b9 7916static void
33430bd0
BW		 7917Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
7918{
7919 slotbuf[0] = 0xe05;
7920}
7921
7922static void
7923Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
7924{
7925 slotbuf[0] = 0x405;
7926}
7927
7928static void
7929Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
7930{
7931 slotbuf[0] = 0x505;
7932}
7933
7934static void
7935Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7936{
7937 slotbuf[0] = 0x305;
7938}
7939
7940static void
7941Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7942{
7943 slotbuf[0] = 0x705;
7944}
7945
7946static void
7947Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
7948{
7949 slotbuf[0] = 0x605;
7950}
7951
7952static void
7953Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
7954{
7955 slotbuf[0] = 0xf1f;
7956}
7957
7958static void
7959Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
7960{
7961 slotbuf[0] = 0x105;
7962}
7963
7964static void
7965Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
7966{
7967 slotbuf[0] = 0x905;
7968}
7969
7970static void
7971Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
7972{
7973 slotbuf[0] = 0xe030;
7974}
7975
7976static void
7977Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
7978{
7979 slotbuf[0] = 0xe031;
7980}
7981
7982static void
7983Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
7984{
7985 slotbuf[0] = 0xe016;
7986}
7987
7988static void
7989Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
7990{
7991 slotbuf[0] = 0x33;
7992}
7993
7994static void
7995Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
7996{
7997 slotbuf[0] = 0x34;
7998}
7999
8000static void
8001Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
8002{
8003 slotbuf[0] = 0x35;
8004}
8005
8006static void
8007Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8008{
8009 slotbuf[0] = 0x36;
8010}
8011
8012static void
8013Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8014{
8015 slotbuf[0] = 0x37;
8016}
8017
8018static void
8019Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
8020{
8021 slotbuf[0] = 0xe04;
8022}
8023
8024static void
8025Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
8026{
8027 slotbuf[0] = 0xf04;
8028}
8029
8030static void
8031Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
8032{
8033 slotbuf[0] = 0x32;
8034}
8035
8036static void
8037Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 8038{
33430bd0 8039 slotbuf[0] = 0x200b00;
e0001a05
NC		 8040}
8041
43cd72b9 8042static void
33430bd0 8043Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 8044{
33430bd0 8045 slotbuf[0] = 0x200f00;
e0001a05
NC		 8046}
8047
43cd72b9 8048static void
33430bd0 8049Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 8050{
33430bd0 8051 slotbuf[0] = 0x200e00;
e0001a05
NC		 8052}
8053
43cd72b9 8054static void
33430bd0 8055Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 8056{
33430bd0 8057 slotbuf[0] = 0xc30;
e0001a05
NC		 8058}
8059
43cd72b9 8060static void
33430bd0 8061Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 8062{
33430bd0 8063 slotbuf[0] = 0xc31;
e0001a05
NC		 8064}
8065
43cd72b9 8066static void
33430bd0 8067Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 8068{
33430bd0 8069 slotbuf[0] = 0xc16;
e0001a05
NC		 8070}
8071
074f5109 8072static void
33430bd0 8073Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
074f5109 8074{
33430bd0 8075 slotbuf[0] = 0x2c;
074f5109
BW		 8076}
8077
8078static void
33430bd0 8079Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
074f5109 8080{
33430bd0 8081 slotbuf[0] = 0x2d;
074f5109
BW		 8082}
8083
8084static void
33430bd0 8085Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
074f5109 8086{
33430bd0 8087 slotbuf[0] = 0x2e;
074f5109
BW		 8088}
8089
43cd72b9 8090static void
33430bd0 8091Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 8092{
33430bd0 8093 slotbuf[0] = 0x2f;
43cd72b9
BW		 8094}
8095
8096static void
33430bd0 8097Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 8098{
33430bd0 8099 slotbuf[0] = 0x28;
43cd72b9
BW		 8100}
8101
8102xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
8103 Opcode_excw_Slot_inst_encode, 0, 0
8104};
8105
8106xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
8107 Opcode_rfe_Slot_inst_encode, 0, 0
8108};
8109
8110xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
8111 Opcode_rfde_Slot_inst_encode, 0, 0
8112};
8113
8114xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
8115 Opcode_syscall_Slot_inst_encode, 0, 0
8116};
8117
8118xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
8119 Opcode_simcall_Slot_inst_encode, 0, 0
8120};
8121
8122xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
8123 Opcode_call12_Slot_inst_encode, 0, 0
8124};
8125
8126xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
8127 Opcode_call8_Slot_inst_encode, 0, 0
8128};
8129
8130xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
8131 Opcode_call4_Slot_inst_encode, 0, 0
8132};
8133
8134xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
8135 Opcode_callx12_Slot_inst_encode, 0, 0
8136};
8137
8138xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
8139 Opcode_callx8_Slot_inst_encode, 0, 0
8140};
8141
8142xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
8143 Opcode_callx4_Slot_inst_encode, 0, 0
8144};
8145
8146xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
8147 Opcode_entry_Slot_inst_encode, 0, 0
8148};
8149
8150xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
8151 Opcode_movsp_Slot_inst_encode, 0, 0
8152};
8153
8154xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
8155 Opcode_rotw_Slot_inst_encode, 0, 0
8156};
8157
8158xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
8159 Opcode_retw_Slot_inst_encode, 0, 0
8160};
8161
8162xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
8163 0, 0, Opcode_retw_n_Slot_inst16b_encode
8164};
8165
8166xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
8167 Opcode_rfwo_Slot_inst_encode, 0, 0
8168};
8169
8170xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
8171 Opcode_rfwu_Slot_inst_encode, 0, 0
8172};
8173
8174xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
8175 Opcode_l32e_Slot_inst_encode, 0, 0
8176};
8177
8178xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
8179 Opcode_s32e_Slot_inst_encode, 0, 0
8180};
8181
8182xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
8183 Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
8184};
8185
8186xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
8187 Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
8188};
8189
8190xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
8191 Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
8192};
8193
8194xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
8195 Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
8196};
8197
8198xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
8199 Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
8200};
8201
8202xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
8203 Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
8204};
8205
8206xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
8207 0, Opcode_add_n_Slot_inst16a_encode, 0
8208};
8209
8210xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
8211 0, Opcode_addi_n_Slot_inst16a_encode, 0
8212};
8213
8214xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
8215 0, 0, Opcode_beqz_n_Slot_inst16b_encode
8216};
8217
8218xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
8219 0, 0, Opcode_bnez_n_Slot_inst16b_encode
8220};
8221
8222xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
8223 0, 0, Opcode_ill_n_Slot_inst16b_encode
8224};
8225
8226xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
8227 0, Opcode_l32i_n_Slot_inst16a_encode, 0
8228};
8229
8230xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
8231 0, 0, Opcode_mov_n_Slot_inst16b_encode
8232};
8233
8234xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
8235 0, 0, Opcode_movi_n_Slot_inst16b_encode
8236};
8237
8238xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
8239 0, 0, Opcode_nop_n_Slot_inst16b_encode
8240};
8241
8242xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
8243 0, 0, Opcode_ret_n_Slot_inst16b_encode
8244};
8245
8246xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
8247 0, Opcode_s32i_n_Slot_inst16a_encode, 0
8248};
8249
33430bd0
BW		 8250xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
8251 Opcode_rur_threadptr_Slot_inst_encode, 0, 0
8252};
8253
8254xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
8255 Opcode_wur_threadptr_Slot_inst_encode, 0, 0
8256};
8257
43cd72b9
BW		 8258xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
8259 Opcode_addi_Slot_inst_encode, 0, 0
8260};
8261
8262xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
8263 Opcode_addmi_Slot_inst_encode, 0, 0
8264};
8265
8266xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
8267 Opcode_add_Slot_inst_encode, 0, 0
8268};
8269
8270xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
8271 Opcode_sub_Slot_inst_encode, 0, 0
8272};
8273
8274xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
8275 Opcode_addx2_Slot_inst_encode, 0, 0
8276};
8277
8278xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
8279 Opcode_addx4_Slot_inst_encode, 0, 0
8280};
8281
8282xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
8283 Opcode_addx8_Slot_inst_encode, 0, 0
8284};
8285
8286xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
8287 Opcode_subx2_Slot_inst_encode, 0, 0
8288};
8289
8290xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
8291 Opcode_subx4_Slot_inst_encode, 0, 0
8292};
8293
8294xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
8295 Opcode_subx8_Slot_inst_encode, 0, 0
8296};
8297
8298xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
8299 Opcode_and_Slot_inst_encode, 0, 0
8300};
8301
8302xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
8303 Opcode_or_Slot_inst_encode, 0, 0
8304};
8305
8306xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
8307 Opcode_xor_Slot_inst_encode, 0, 0
8308};
8309
8310xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
8311 Opcode_beqi_Slot_inst_encode, 0, 0
8312};
8313
8314xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
8315 Opcode_bnei_Slot_inst_encode, 0, 0
8316};
8317
8318xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
8319 Opcode_bgei_Slot_inst_encode, 0, 0
8320};
8321
8322xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
8323 Opcode_blti_Slot_inst_encode, 0, 0
8324};
8325
8326xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
8327 Opcode_bbci_Slot_inst_encode, 0, 0
8328};
8329
8330xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
8331 Opcode_bbsi_Slot_inst_encode, 0, 0
8332};
8333
8334xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
8335 Opcode_bgeui_Slot_inst_encode, 0, 0
8336};
8337
8338xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
8339 Opcode_bltui_Slot_inst_encode, 0, 0
8340};
8341
8342xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
8343 Opcode_beq_Slot_inst_encode, 0, 0
8344};
8345
8346xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
8347 Opcode_bne_Slot_inst_encode, 0, 0
8348};
8349
8350xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
8351 Opcode_bge_Slot_inst_encode, 0, 0
8352};
8353
8354xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
8355 Opcode_blt_Slot_inst_encode, 0, 0
8356};
e0001a05 8357
43cd72b9
BW		 8358xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
8359 Opcode_bgeu_Slot_inst_encode, 0, 0
8360};
e0001a05 8361
43cd72b9
BW		 8362xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
8363 Opcode_bltu_Slot_inst_encode, 0, 0
8364};
e0001a05 8365
43cd72b9
BW		 8366xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
8367 Opcode_bany_Slot_inst_encode, 0, 0
8368};
e0001a05 8369
43cd72b9
BW		 8370xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
8371 Opcode_bnone_Slot_inst_encode, 0, 0
8372};
e0001a05 8373
43cd72b9
BW		 8374xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
8375 Opcode_ball_Slot_inst_encode, 0, 0
8376};
e0001a05 8377
43cd72b9
BW		 8378xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
8379 Opcode_bnall_Slot_inst_encode, 0, 0
8380};
e0001a05 8381
43cd72b9
BW		 8382xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
8383 Opcode_bbc_Slot_inst_encode, 0, 0
8384};
e0001a05 8385
43cd72b9
BW		 8386xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
8387 Opcode_bbs_Slot_inst_encode, 0, 0
8388};
e0001a05 8389
43cd72b9
BW		 8390xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
8391 Opcode_beqz_Slot_inst_encode, 0, 0
8392};
e0001a05 8393
43cd72b9
BW		 8394xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
8395 Opcode_bnez_Slot_inst_encode, 0, 0
8396};
e0001a05 8397
43cd72b9
BW		 8398xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
8399 Opcode_bgez_Slot_inst_encode, 0, 0
8400};
e0001a05 8401
43cd72b9
BW		 8402xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
8403 Opcode_bltz_Slot_inst_encode, 0, 0
8404};
e0001a05 8405
43cd72b9
BW		 8406xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
8407 Opcode_call0_Slot_inst_encode, 0, 0
8408};
e0001a05 8409
43cd72b9
BW		 8410xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
8411 Opcode_callx0_Slot_inst_encode, 0, 0
8412};
e0001a05 8413
43cd72b9
BW		 8414xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
8415 Opcode_extui_Slot_inst_encode, 0, 0
8416};
e0001a05 8417
43cd72b9
BW		 8418xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
8419 Opcode_ill_Slot_inst_encode, 0, 0
8420};
e0001a05 8421
43cd72b9
BW		 8422xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
8423 Opcode_j_Slot_inst_encode, 0, 0
8424};
e0001a05 8425
43cd72b9
BW		 8426xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
8427 Opcode_jx_Slot_inst_encode, 0, 0
8428};
e0001a05 8429
43cd72b9
BW		 8430xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
8431 Opcode_l16ui_Slot_inst_encode, 0, 0
8432};
e0001a05 8433
43cd72b9
BW		 8434xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
8435 Opcode_l16si_Slot_inst_encode, 0, 0
8436};
e0001a05 8437
43cd72b9
BW		 8438xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
8439 Opcode_l32i_Slot_inst_encode, 0, 0
8440};
e0001a05 8441
43cd72b9
BW		 8442xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
8443 Opcode_l32r_Slot_inst_encode, 0, 0
8444};
e0001a05 8445
43cd72b9
BW		 8446xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
8447 Opcode_l8ui_Slot_inst_encode, 0, 0
8448};
e0001a05 8449
43cd72b9
BW		 8450xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
8451 Opcode_loop_Slot_inst_encode, 0, 0
8452};
e0001a05 8453
43cd72b9
BW		 8454xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
8455 Opcode_loopnez_Slot_inst_encode, 0, 0
8456};
e0001a05 8457
43cd72b9
BW		 8458xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
8459 Opcode_loopgtz_Slot_inst_encode, 0, 0
8460};
e0001a05 8461
43cd72b9
BW		 8462xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
8463 Opcode_movi_Slot_inst_encode, 0, 0
8464};
e0001a05 8465
43cd72b9
BW		 8466xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
8467 Opcode_moveqz_Slot_inst_encode, 0, 0
8468};
e0001a05 8469
43cd72b9
BW		 8470xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
8471 Opcode_movnez_Slot_inst_encode, 0, 0
8472};
e0001a05 8473
43cd72b9
BW		 8474xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
8475 Opcode_movltz_Slot_inst_encode, 0, 0
8476};
e0001a05 8477
43cd72b9
BW		 8478xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
8479 Opcode_movgez_Slot_inst_encode, 0, 0
8480};
e0001a05 8481
43cd72b9
BW		 8482xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
8483 Opcode_neg_Slot_inst_encode, 0, 0
8484};
e0001a05 8485
43cd72b9
BW		 8486xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
8487 Opcode_abs_Slot_inst_encode, 0, 0
8488};
e0001a05 8489
43cd72b9
BW		 8490xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
8491 Opcode_nop_Slot_inst_encode, 0, 0
8492};
e0001a05 8493
43cd72b9
BW		 8494xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
8495 Opcode_ret_Slot_inst_encode, 0, 0
8496};
e0001a05 8497
43cd72b9
BW		 8498xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
8499 Opcode_s16i_Slot_inst_encode, 0, 0
8500};
e0001a05 8501
43cd72b9
BW		 8502xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
8503 Opcode_s32i_Slot_inst_encode, 0, 0
8504};
e0001a05 8505
43cd72b9
BW		 8506xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
8507 Opcode_s8i_Slot_inst_encode, 0, 0
8508};
e0001a05 8509
43cd72b9
BW		 8510xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
8511 Opcode_ssr_Slot_inst_encode, 0, 0
8512};
e0001a05 8513
43cd72b9
BW		 8514xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
8515 Opcode_ssl_Slot_inst_encode, 0, 0
8516};
e0001a05 8517
43cd72b9
BW		 8518xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
8519 Opcode_ssa8l_Slot_inst_encode, 0, 0
8520};
e0001a05 8521
43cd72b9
BW		 8522xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
8523 Opcode_ssa8b_Slot_inst_encode, 0, 0
8524};
e0001a05 8525
43cd72b9
BW		 8526xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
8527 Opcode_ssai_Slot_inst_encode, 0, 0
8528};
e0001a05 8529
43cd72b9
BW		 8530xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
8531 Opcode_sll_Slot_inst_encode, 0, 0
8532};
e0001a05 8533
43cd72b9
BW		 8534xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
8535 Opcode_src_Slot_inst_encode, 0, 0
8536};
e0001a05 8537
43cd72b9
BW		 8538xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
8539 Opcode_srl_Slot_inst_encode, 0, 0
8540};
e0001a05 8541
43cd72b9
BW		 8542xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
8543 Opcode_sra_Slot_inst_encode, 0, 0
8544};
e0001a05 8545
43cd72b9
BW		 8546xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
8547 Opcode_slli_Slot_inst_encode, 0, 0
8548};
e0001a05 8549
43cd72b9
BW		 8550xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
8551 Opcode_srai_Slot_inst_encode, 0, 0
8552};
e0001a05 8553
43cd72b9
BW		 8554xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
8555 Opcode_srli_Slot_inst_encode, 0, 0
8556};
e0001a05 8557
43cd72b9
BW		 8558xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
8559 Opcode_memw_Slot_inst_encode, 0, 0
8560};
e0001a05 8561
43cd72b9
BW		 8562xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
8563 Opcode_extw_Slot_inst_encode, 0, 0
8564};
e0001a05 8565
43cd72b9
BW		 8566xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
8567 Opcode_isync_Slot_inst_encode, 0, 0
8568};
e0001a05 8569
43cd72b9
BW		 8570xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
8571 Opcode_rsync_Slot_inst_encode, 0, 0
8572};
e0001a05 8573
43cd72b9
BW		 8574xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
8575 Opcode_esync_Slot_inst_encode, 0, 0
8576};
e0001a05 8577
43cd72b9
BW		 8578xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
8579 Opcode_dsync_Slot_inst_encode, 0, 0
8580};
e0001a05 8581
43cd72b9
BW		 8582xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
8583 Opcode_rsil_Slot_inst_encode, 0, 0
8584};
e0001a05 8585
43cd72b9
BW		 8586xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
8587 Opcode_rsr_lend_Slot_inst_encode, 0, 0
8588};
e0001a05 8589
43cd72b9
BW		 8590xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
8591 Opcode_wsr_lend_Slot_inst_encode, 0, 0
8592};
e0001a05 8593
43cd72b9
BW		 8594xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
8595 Opcode_xsr_lend_Slot_inst_encode, 0, 0
8596};
e0001a05 8597
43cd72b9
BW		 8598xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
8599 Opcode_rsr_lcount_Slot_inst_encode, 0, 0
8600};
e0001a05 8601
43cd72b9
BW		 8602xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
8603 Opcode_wsr_lcount_Slot_inst_encode, 0, 0
8604};
e0001a05 8605
43cd72b9
BW		 8606xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
8607 Opcode_xsr_lcount_Slot_inst_encode, 0, 0
8608};
e0001a05 8609
43cd72b9
BW		 8610xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
8611 Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
8612};
e0001a05 8613
43cd72b9
BW		 8614xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
8615 Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
8616};
e0001a05 8617
43cd72b9
BW		 8618xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
8619 Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
e0001a05
NC		 8620};
8621
43cd72b9
BW		 8622xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
8623 Opcode_rsr_sar_Slot_inst_encode, 0, 0
e0001a05
NC		 8624};
8625
43cd72b9
BW		 8626xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
8627 Opcode_wsr_sar_Slot_inst_encode, 0, 0
e0001a05
NC		 8628};
8629
43cd72b9
BW		 8630xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
8631 Opcode_xsr_sar_Slot_inst_encode, 0, 0
e0001a05
NC		 8632};
8633
43cd72b9
BW		 8634xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
8635 Opcode_rsr_litbase_Slot_inst_encode, 0, 0
e0001a05
NC		 8636};
8637
43cd72b9
BW		 8638xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
8639 Opcode_wsr_litbase_Slot_inst_encode, 0, 0
e0001a05
NC		 8640};
8641
43cd72b9
BW		 8642xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
8643 Opcode_xsr_litbase_Slot_inst_encode, 0, 0
e0001a05
NC		 8644};
8645
43cd72b9
BW		 8646xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
8647 Opcode_rsr_176_Slot_inst_encode, 0, 0
e0001a05
NC		 8648};
8649
33430bd0
BW		 8650xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = {
8651 Opcode_wsr_176_Slot_inst_encode, 0, 0
8652};
8653
43cd72b9
BW		 8654xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
8655 Opcode_rsr_208_Slot_inst_encode, 0, 0
e0001a05
NC		 8656};
8657
43cd72b9
BW		 8658xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
8659 Opcode_rsr_ps_Slot_inst_encode, 0, 0
e0001a05
NC		 8660};
8661
43cd72b9
BW		 8662xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
8663 Opcode_wsr_ps_Slot_inst_encode, 0, 0
e0001a05
NC		 8664};
8665
43cd72b9
BW		 8666xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
8667 Opcode_xsr_ps_Slot_inst_encode, 0, 0
e0001a05
NC		 8668};
8669
43cd72b9
BW		 8670xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
8671 Opcode_rsr_epc1_Slot_inst_encode, 0, 0
e0001a05
NC		 8672};
8673
43cd72b9
BW		 8674xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
8675 Opcode_wsr_epc1_Slot_inst_encode, 0, 0
e0001a05
NC		 8676};
8677
43cd72b9
BW		 8678xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
8679 Opcode_xsr_epc1_Slot_inst_encode, 0, 0
e0001a05
NC		 8680};
8681
43cd72b9
BW		 8682xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
8683 Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
e0001a05
NC		 8684};
8685
43cd72b9
BW		 8686xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
8687 Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
e0001a05
NC		 8688};
8689
43cd72b9
BW		 8690xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
8691 Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
e0001a05
NC		 8692};
8693
43cd72b9
BW		 8694xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
8695 Opcode_rsr_epc2_Slot_inst_encode, 0, 0
e0001a05
NC		 8696};
8697
43cd72b9
BW		 8698xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
8699 Opcode_wsr_epc2_Slot_inst_encode, 0, 0
e0001a05
NC		 8700};
8701
43cd72b9
BW		 8702xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
8703 Opcode_xsr_epc2_Slot_inst_encode, 0, 0
e0001a05
NC		 8704};
8705
43cd72b9
BW		 8706xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
8707 Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
e0001a05
NC		 8708};
8709
43cd72b9
BW		 8710xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
8711 Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
e0001a05
NC		 8712};
8713
43cd72b9
BW		 8714xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
8715 Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
e0001a05
NC		 8716};
8717
43cd72b9
BW		 8718xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
8719 Opcode_rsr_epc3_Slot_inst_encode, 0, 0
e0001a05
NC		 8720};
8721
43cd72b9
BW		 8722xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
8723 Opcode_wsr_epc3_Slot_inst_encode, 0, 0
e0001a05
NC		 8724};
8725
43cd72b9
BW		 8726xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
8727 Opcode_xsr_epc3_Slot_inst_encode, 0, 0
e0001a05
NC		 8728};
8729
43cd72b9
BW		 8730xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
8731 Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
e0001a05
NC		 8732};
8733
43cd72b9
BW		 8734xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
8735 Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
e0001a05
NC		 8736};
8737
43cd72b9
BW		 8738xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
8739 Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
e0001a05
NC		 8740};
8741
43cd72b9
BW		 8742xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
8743 Opcode_rsr_epc4_Slot_inst_encode, 0, 0
e0001a05
NC		 8744};
8745
43cd72b9
BW		 8746xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
8747 Opcode_wsr_epc4_Slot_inst_encode, 0, 0
e0001a05
NC		 8748};
8749
43cd72b9
BW		 8750xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
8751 Opcode_xsr_epc4_Slot_inst_encode, 0, 0
e0001a05
NC		 8752};
8753
43cd72b9
BW		 8754xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
8755 Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
e0001a05
NC		 8756};
8757
43cd72b9
BW		 8758xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
8759 Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
e0001a05
NC		 8760};
8761
43cd72b9
BW		 8762xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
8763 Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
e0001a05
NC		 8764};
8765
33430bd0
BW		 8766xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
8767 Opcode_rsr_epc5_Slot_inst_encode, 0, 0
8768};
8769
8770xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
8771 Opcode_wsr_epc5_Slot_inst_encode, 0, 0
8772};
8773
8774xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
8775 Opcode_xsr_epc5_Slot_inst_encode, 0, 0
8776};
8777
8778xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
8779 Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
8780};
8781
8782xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
8783 Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
8784};
8785
8786xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
8787 Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
8788};
8789
8790xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
8791 Opcode_rsr_epc6_Slot_inst_encode, 0, 0
8792};
8793
8794xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
8795 Opcode_wsr_epc6_Slot_inst_encode, 0, 0
8796};
8797
8798xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
8799 Opcode_xsr_epc6_Slot_inst_encode, 0, 0
8800};
8801
8802xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
8803 Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
8804};
8805
8806xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
8807 Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
8808};
8809
8810xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
8811 Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
8812};
8813
8814xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
8815 Opcode_rsr_epc7_Slot_inst_encode, 0, 0
8816};
8817
8818xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
8819 Opcode_wsr_epc7_Slot_inst_encode, 0, 0
8820};
8821
8822xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
8823 Opcode_xsr_epc7_Slot_inst_encode, 0, 0
8824};
8825
8826xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
8827 Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
8828};
8829
8830xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
8831 Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
8832};
8833
8834xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
8835 Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
8836};
8837
43cd72b9
BW		 8838xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
8839 Opcode_rsr_eps2_Slot_inst_encode, 0, 0
e0001a05
NC		 8840};
8841
43cd72b9
BW		 8842xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
8843 Opcode_wsr_eps2_Slot_inst_encode, 0, 0
e0001a05
NC		 8844};
8845
43cd72b9
BW		 8846xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
8847 Opcode_xsr_eps2_Slot_inst_encode, 0, 0
e0001a05
NC		 8848};
8849
43cd72b9
BW		 8850xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
8851 Opcode_rsr_eps3_Slot_inst_encode, 0, 0
e0001a05
NC		 8852};
8853
43cd72b9
BW		 8854xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
8855 Opcode_wsr_eps3_Slot_inst_encode, 0, 0
e0001a05
NC		 8856};
8857
43cd72b9
BW		 8858xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
8859 Opcode_xsr_eps3_Slot_inst_encode, 0, 0
e0001a05
NC		 8860};
8861
43cd72b9
BW		 8862xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
8863 Opcode_rsr_eps4_Slot_inst_encode, 0, 0
e0001a05
NC		 8864};
8865
43cd72b9
BW		 8866xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
8867 Opcode_wsr_eps4_Slot_inst_encode, 0, 0
e0001a05
NC		 8868};
8869
43cd72b9
BW		 8870xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
8871 Opcode_xsr_eps4_Slot_inst_encode, 0, 0
e0001a05
NC		 8872};
8873
33430bd0
BW		 8874xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
8875 Opcode_rsr_eps5_Slot_inst_encode, 0, 0
8876};
8877
8878xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
8879 Opcode_wsr_eps5_Slot_inst_encode, 0, 0
8880};
8881
8882xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
8883 Opcode_xsr_eps5_Slot_inst_encode, 0, 0
8884};
8885
8886xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
8887 Opcode_rsr_eps6_Slot_inst_encode, 0, 0
8888};
8889
8890xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
8891 Opcode_wsr_eps6_Slot_inst_encode, 0, 0
8892};
8893
8894xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
8895 Opcode_xsr_eps6_Slot_inst_encode, 0, 0
8896};
8897
8898xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
8899 Opcode_rsr_eps7_Slot_inst_encode, 0, 0
8900};
8901
8902xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
8903 Opcode_wsr_eps7_Slot_inst_encode, 0, 0
8904};
8905
8906xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
8907 Opcode_xsr_eps7_Slot_inst_encode, 0, 0
8908};
8909
43cd72b9
BW		 8910xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
8911 Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
e0001a05
NC		 8912};
8913
43cd72b9
BW		 8914xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
8915 Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
e0001a05
NC		 8916};
8917
43cd72b9
BW		 8918xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
8919 Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
e0001a05
NC		 8920};
8921
43cd72b9
BW		 8922xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
8923 Opcode_rsr_depc_Slot_inst_encode, 0, 0
e0001a05
NC		 8924};
8925
43cd72b9
BW		 8926xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
8927 Opcode_wsr_depc_Slot_inst_encode, 0, 0
e0001a05
NC		 8928};
8929
43cd72b9
BW		 8930xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
8931 Opcode_xsr_depc_Slot_inst_encode, 0, 0
e0001a05
NC		 8932};
8933
43cd72b9
BW		 8934xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
8935 Opcode_rsr_exccause_Slot_inst_encode, 0, 0
e0001a05
NC		 8936};
8937
43cd72b9
BW		 8938xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
8939 Opcode_wsr_exccause_Slot_inst_encode, 0, 0
e0001a05
NC		 8940};
8941
43cd72b9
BW		 8942xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
8943 Opcode_xsr_exccause_Slot_inst_encode, 0, 0
e0001a05
NC		 8944};
8945
43cd72b9
BW		 8946xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
8947 Opcode_rsr_misc0_Slot_inst_encode, 0, 0
e0001a05
NC		 8948};
8949
43cd72b9
BW		 8950xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
8951 Opcode_wsr_misc0_Slot_inst_encode, 0, 0
8952};
8953
8954xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
8955 Opcode_xsr_misc0_Slot_inst_encode, 0, 0
e0001a05
NC		 8956};
8957
43cd72b9
BW		 8958xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
8959 Opcode_rsr_misc1_Slot_inst_encode, 0, 0
e0001a05
NC		 8960};
8961
43cd72b9
BW		 8962xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
8963 Opcode_wsr_misc1_Slot_inst_encode, 0, 0
e0001a05
NC		 8964};
8965
43cd72b9
BW		 8966xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
8967 Opcode_xsr_misc1_Slot_inst_encode, 0, 0
e0001a05
NC		 8968};
8969
43cd72b9
BW		 8970xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
8971 Opcode_rsr_prid_Slot_inst_encode, 0, 0
e0001a05
NC		 8972};
8973
33430bd0
BW		 8974xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
8975 Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
8976};
8977
8978xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
8979 Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
8980};
8981
8982xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
8983 Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
8984};
8985
8986xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
8987 Opcode_mul16u_Slot_inst_encode, 0, 0
8988};
8989
8990xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
8991 Opcode_mul16s_Slot_inst_encode, 0, 0
8992};
8993
43cd72b9
BW		 8994xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
8995 Opcode_rfi_Slot_inst_encode, 0, 0
e0001a05
NC		 8996};
8997
43cd72b9
BW		 8998xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
8999 Opcode_waiti_Slot_inst_encode, 0, 0
e0001a05
NC		 9000};
9001
43cd72b9
BW		 9002xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
9003 Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
e0001a05
NC		 9004};
9005
43cd72b9
BW		 9006xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
9007 Opcode_wsr_intset_Slot_inst_encode, 0, 0
e0001a05
NC		 9008};
9009
43cd72b9
BW		 9010xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
9011 Opcode_wsr_intclear_Slot_inst_encode, 0, 0
e0001a05
NC		 9012};
9013
43cd72b9
BW		 9014xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
9015 Opcode_rsr_intenable_Slot_inst_encode, 0, 0
e0001a05
NC		 9016};
9017
43cd72b9
BW		 9018xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
9019 Opcode_wsr_intenable_Slot_inst_encode, 0, 0
e0001a05
NC		 9020};
9021
43cd72b9
BW		 9022xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
9023 Opcode_xsr_intenable_Slot_inst_encode, 0, 0
e0001a05
NC		 9024};
9025
43cd72b9
BW		 9026xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
9027 Opcode_break_Slot_inst_encode, 0, 0
e0001a05
NC		 9028};
9029
43cd72b9
BW		 9030xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
9031 0, 0, Opcode_break_n_Slot_inst16b_encode
e0001a05
NC		 9032};
9033
43cd72b9
BW		 9034xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
9035 Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
e0001a05
NC		 9036};
9037
43cd72b9
BW		 9038xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
9039 Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
e0001a05
NC		 9040};
9041
43cd72b9
BW		 9042xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
9043 Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
e0001a05
NC		 9044};
9045
43cd72b9
BW		 9046xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
9047 Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
e0001a05
NC		 9048};
9049
43cd72b9
BW		 9050xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
9051 Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
e0001a05
NC		 9052};
9053
43cd72b9
BW		 9054xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
9055 Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
e0001a05
NC		 9056};
9057
43cd72b9
BW		 9058xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
9059 Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
e0001a05
NC		 9060};
9061
43cd72b9
BW		 9062xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
9063 Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
e0001a05
NC		 9064};
9065
43cd72b9
BW		 9066xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
9067 Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
e0001a05
NC		 9068};
9069
43cd72b9
BW		 9070xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
9071 Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
e0001a05
NC		 9072};
9073
43cd72b9
BW		 9074xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
9075 Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
e0001a05
NC		 9076};
9077
43cd72b9
BW		 9078xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
9079 Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
e0001a05
NC		 9080};
9081
43cd72b9
BW		 9082xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
9083 Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
e0001a05
NC		 9084};
9085
43cd72b9
BW		 9086xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
9087 Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
e0001a05
NC		 9088};
9089
43cd72b9
BW		 9090xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
9091 Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
e0001a05
NC		 9092};
9093
43cd72b9
BW		 9094xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
9095 Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
e0001a05
NC		 9096};
9097
43cd72b9
BW		 9098xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
9099 Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
e0001a05
NC		 9100};
9101
43cd72b9
BW		 9102xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
9103 Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
e0001a05
NC		 9104};
9105
43cd72b9
BW		 9106xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
9107 Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
e0001a05
NC		 9108};
9109
43cd72b9
BW		 9110xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
9111 Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
e0001a05
NC		 9112};
9113
43cd72b9
BW		 9114xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
9115 Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
e0001a05
NC		 9116};
9117
43cd72b9
BW		 9118xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
9119 Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
e0001a05
NC		 9120};
9121
43cd72b9
BW		 9122xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
9123 Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
e0001a05
NC		 9124};
9125
43cd72b9
BW		 9126xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
9127 Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
e0001a05
NC		 9128};
9129
43cd72b9
BW		 9130xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
9131 Opcode_rsr_icount_Slot_inst_encode, 0, 0
e0001a05
NC		 9132};
9133
43cd72b9
BW		 9134xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
9135 Opcode_wsr_icount_Slot_inst_encode, 0, 0
e0001a05
NC		 9136};
9137
43cd72b9
BW		 9138xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
9139 Opcode_xsr_icount_Slot_inst_encode, 0, 0
e0001a05
NC		 9140};
9141
43cd72b9
BW		 9142xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
9143 Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
e0001a05
NC		 9144};
9145
43cd72b9
BW		 9146xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
9147 Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
e0001a05
NC		 9148};
9149
43cd72b9
BW		 9150xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
9151 Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
e0001a05
NC		 9152};
9153
43cd72b9
BW		 9154xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
9155 Opcode_rsr_ddr_Slot_inst_encode, 0, 0
e0001a05
NC		 9156};
9157
43cd72b9
BW		 9158xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
9159 Opcode_wsr_ddr_Slot_inst_encode, 0, 0
e0001a05
NC		 9160};
9161
43cd72b9
BW		 9162xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
9163 Opcode_xsr_ddr_Slot_inst_encode, 0, 0
e0001a05
NC		 9164};
9165
43cd72b9
BW		 9166xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
9167 Opcode_rfdo_Slot_inst_encode, 0, 0
e0001a05
NC		 9168};
9169
43cd72b9
BW		 9170xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
9171 Opcode_rfdd_Slot_inst_encode, 0, 0
e0001a05
NC		 9172};
9173
33430bd0
BW		 9174xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
9175 Opcode_wsr_mmid_Slot_inst_encode, 0, 0
9176};
9177
43cd72b9
BW		 9178xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
9179 Opcode_rsr_ccount_Slot_inst_encode, 0, 0
e0001a05
NC		 9180};
9181
43cd72b9
BW		 9182xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
9183 Opcode_wsr_ccount_Slot_inst_encode, 0, 0
e0001a05
NC		 9184};
9185
43cd72b9
BW		 9186xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
9187 Opcode_xsr_ccount_Slot_inst_encode, 0, 0
e0001a05
NC		 9188};
9189
43cd72b9
BW		 9190xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
9191 Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
e0001a05
NC		 9192};
9193
43cd72b9
BW		 9194xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
9195 Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
e0001a05
NC		 9196};
9197
43cd72b9
BW		 9198xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
9199 Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
e0001a05
NC		 9200};
9201
43cd72b9
BW		 9202xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
9203 Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
e0001a05
NC		 9204};
9205
43cd72b9
BW		 9206xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
9207 Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
e0001a05
NC		 9208};
9209
43cd72b9
BW		 9210xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
9211 Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
e0001a05
NC		 9212};
9213
43cd72b9
BW		 9214xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
9215 Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
e0001a05
NC		 9216};
9217
43cd72b9
BW		 9218xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
9219 Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
e0001a05
NC		 9220};
9221
43cd72b9
BW		 9222xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
9223 Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
e0001a05
NC		 9224};
9225
43cd72b9
BW		 9226xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
9227 Opcode_ipf_Slot_inst_encode, 0, 0
e0001a05
NC		 9228};
9229
43cd72b9
BW		 9230xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
9231 Opcode_ihi_Slot_inst_encode, 0, 0
e0001a05
NC		 9232};
9233
33430bd0
BW		 9234xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
9235 Opcode_ipfl_Slot_inst_encode, 0, 0
9236};
9237
9238xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
9239 Opcode_ihu_Slot_inst_encode, 0, 0
9240};
9241
9242xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
9243 Opcode_iiu_Slot_inst_encode, 0, 0
9244};
9245
43cd72b9
BW		 9246xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
9247 Opcode_iii_Slot_inst_encode, 0, 0
e0001a05
NC		 9248};
9249
43cd72b9
BW		 9250xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
9251 Opcode_lict_Slot_inst_encode, 0, 0
e0001a05
NC		 9252};
9253
43cd72b9
BW		 9254xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
9255 Opcode_licw_Slot_inst_encode, 0, 0
e0001a05
NC		 9256};
9257
43cd72b9
BW		 9258xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
9259 Opcode_sict_Slot_inst_encode, 0, 0
e0001a05
NC		 9260};
9261
43cd72b9
BW		 9262xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
9263 Opcode_sicw_Slot_inst_encode, 0, 0
e0001a05
NC		 9264};
9265
43cd72b9
BW		 9266xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
9267 Opcode_dhwb_Slot_inst_encode, 0, 0
e0001a05
NC		 9268};
9269
43cd72b9
BW		 9270xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
9271 Opcode_dhwbi_Slot_inst_encode, 0, 0
e0001a05
NC		 9272};
9273
43cd72b9
BW		 9274xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
9275 Opcode_diwb_Slot_inst_encode, 0, 0
e0001a05
NC		 9276};
9277
43cd72b9
BW		 9278xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
9279 Opcode_diwbi_Slot_inst_encode, 0, 0
e0001a05
NC		 9280};
9281
43cd72b9
BW		 9282xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
9283 Opcode_dhi_Slot_inst_encode, 0, 0
e0001a05
NC		 9284};
9285
43cd72b9
BW		 9286xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
9287 Opcode_dii_Slot_inst_encode, 0, 0
e0001a05
NC		 9288};
9289
43cd72b9
BW		 9290xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
9291 Opcode_dpfr_Slot_inst_encode, 0, 0
e0001a05
NC		 9292};
9293
43cd72b9
BW		 9294xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
9295 Opcode_dpfw_Slot_inst_encode, 0, 0
e0001a05
NC		 9296};
9297
43cd72b9
BW		 9298xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
9299 Opcode_dpfro_Slot_inst_encode, 0, 0
e0001a05
NC		 9300};
9301
43cd72b9
BW		 9302xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
9303 Opcode_dpfwo_Slot_inst_encode, 0, 0
e0001a05
NC		 9304};
9305
33430bd0
BW		 9306xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
9307 Opcode_dpfl_Slot_inst_encode, 0, 0
9308};
9309
9310xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
9311 Opcode_dhu_Slot_inst_encode, 0, 0
9312};
9313
9314xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
9315 Opcode_diu_Slot_inst_encode, 0, 0
9316};
9317
43cd72b9
BW		 9318xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
9319 Opcode_sdct_Slot_inst_encode, 0, 0
e0001a05
NC		 9320};
9321
43cd72b9
BW		 9322xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
9323 Opcode_ldct_Slot_inst_encode, 0, 0
e0001a05
NC		 9324};
9325
074f5109
BW		 9326xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
9327 Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0
9328};
9329
9330xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
9331 Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0
9332};
9333
9334xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
9335 Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0
9336};
9337
9338xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
9339 Opcode_rsr_rasid_Slot_inst_encode, 0, 0
9340};
9341
9342xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
9343 Opcode_wsr_rasid_Slot_inst_encode, 0, 0
9344};
9345
9346xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
9347 Opcode_xsr_rasid_Slot_inst_encode, 0, 0
9348};
9349
9350xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
9351 Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0
9352};
9353
9354xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
9355 Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0
9356};
9357
9358xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
9359 Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0
9360};
9361
9362xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
9363 Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0
9364};
9365
9366xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
9367 Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0
9368};
9369
9370xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
9371 Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0
9372};
9373
43cd72b9
BW		 9374xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
9375 Opcode_idtlb_Slot_inst_encode, 0, 0
e0001a05
NC		 9376};
9377
43cd72b9
BW		 9378xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
9379 Opcode_pdtlb_Slot_inst_encode, 0, 0
e0001a05
NC		 9380};
9381
43cd72b9
BW		 9382xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
9383 Opcode_rdtlb0_Slot_inst_encode, 0, 0
e0001a05
NC		 9384};
9385
43cd72b9
BW		 9386xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
9387 Opcode_rdtlb1_Slot_inst_encode, 0, 0
e0001a05
NC		 9388};
9389
43cd72b9
BW		 9390xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
9391 Opcode_wdtlb_Slot_inst_encode, 0, 0
e0001a05
NC		 9392};
9393
43cd72b9
BW		 9394xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
9395 Opcode_iitlb_Slot_inst_encode, 0, 0
e0001a05
NC		 9396};
9397
43cd72b9
BW		 9398xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
9399 Opcode_pitlb_Slot_inst_encode, 0, 0
e0001a05
NC		 9400};
9401
43cd72b9
BW		 9402xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
9403 Opcode_ritlb0_Slot_inst_encode, 0, 0
e0001a05
NC		 9404};
9405
43cd72b9
BW		 9406xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
9407 Opcode_ritlb1_Slot_inst_encode, 0, 0
e0001a05
NC		 9408};
9409
43cd72b9
BW		 9410xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
9411 Opcode_witlb_Slot_inst_encode, 0, 0
e0001a05
NC		 9412};
9413
074f5109
BW		 9414xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
9415 Opcode_ldpte_Slot_inst_encode, 0, 0
9416};
9417
9418xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
9419 Opcode_hwwitlba_Slot_inst_encode, 0, 0
9420};
9421
9422xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
9423 Opcode_hwwdtlba_Slot_inst_encode, 0, 0
9424};
9425
33430bd0
BW		 9426xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
9427 Opcode_rsr_cpenable_Slot_inst_encode, 0, 0
9428};
9429
9430xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
9431 Opcode_wsr_cpenable_Slot_inst_encode, 0, 0
9432};
9433
9434xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
9435 Opcode_xsr_cpenable_Slot_inst_encode, 0, 0
9436};
9437
9438xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
9439 Opcode_clamps_Slot_inst_encode, 0, 0
9440};
9441
9442xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
9443 Opcode_min_Slot_inst_encode, 0, 0
9444};
9445
9446xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
9447 Opcode_max_Slot_inst_encode, 0, 0
9448};
9449
9450xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
9451 Opcode_minu_Slot_inst_encode, 0, 0
9452};
9453
9454xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
9455 Opcode_maxu_Slot_inst_encode, 0, 0
9456};
9457
43cd72b9
BW		 9458xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
9459 Opcode_nsa_Slot_inst_encode, 0, 0
e0001a05
NC		 9460};
9461
43cd72b9
BW		 9462xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
9463 Opcode_nsau_Slot_inst_encode, 0, 0
e0001a05
NC		 9464};
9465
33430bd0
BW		 9466xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
9467 Opcode_sext_Slot_inst_encode, 0, 0
9468};
9469
9470xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
9471 Opcode_l32ai_Slot_inst_encode, 0, 0
9472};
9473
9474xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
9475 Opcode_s32ri_Slot_inst_encode, 0, 0
9476};
9477
9478xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
9479 Opcode_s32c1i_Slot_inst_encode, 0, 0
9480};
9481
9482xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
9483 Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
9484};
9485
9486xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
9487 Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
9488};
9489
9490xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
9491 Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
9492};
9493
9494xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
9495 Opcode_quou_Slot_inst_encode, 0, 0
9496};
9497
9498xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
9499 Opcode_quos_Slot_inst_encode, 0, 0
9500};
9501
9502xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
9503 Opcode_remu_Slot_inst_encode, 0, 0
9504};
9505
9506xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
9507 Opcode_rems_Slot_inst_encode, 0, 0
9508};
9509
9510xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
9511 Opcode_mull_Slot_inst_encode, 0, 0
9512};
9513
43cd72b9
BW		 9514\f
9515/* Opcode table. */
9516
9517static xtensa_opcode_internal opcodes[] = {
56fb3749 9518 { "excw", ICLASS_xt_iclass_excw,
43cd72b9
BW		 9519 0,
9520 Opcode_excw_encode_fns, 0, 0 },
56fb3749 9521 { "rfe", ICLASS_xt_iclass_rfe,
43cd72b9
BW		 9522 XTENSA_OPCODE_IS_JUMP,
9523 Opcode_rfe_encode_fns, 0, 0 },
56fb3749 9524 { "rfde", ICLASS_xt_iclass_rfde,
43cd72b9
BW		 9525 XTENSA_OPCODE_IS_JUMP,
9526 Opcode_rfde_encode_fns, 0, 0 },
56fb3749 9527 { "syscall", ICLASS_xt_iclass_syscall,
43cd72b9
BW		 9528 0,
9529 Opcode_syscall_encode_fns, 0, 0 },
56fb3749 9530 { "simcall", ICLASS_xt_iclass_simcall,
43cd72b9
BW		 9531 0,
9532 Opcode_simcall_encode_fns, 0, 0 },
56fb3749 9533 { "call12", ICLASS_xt_iclass_call12,
43cd72b9
BW		 9534 XTENSA_OPCODE_IS_CALL,
9535 Opcode_call12_encode_fns, 0, 0 },
56fb3749 9536 { "call8", ICLASS_xt_iclass_call8,
43cd72b9
BW		 9537 XTENSA_OPCODE_IS_CALL,
9538 Opcode_call8_encode_fns, 0, 0 },
56fb3749 9539 { "call4", ICLASS_xt_iclass_call4,
43cd72b9
BW		 9540 XTENSA_OPCODE_IS_CALL,
9541 Opcode_call4_encode_fns, 0, 0 },
56fb3749 9542 { "callx12", ICLASS_xt_iclass_callx12,
43cd72b9
BW		 9543 XTENSA_OPCODE_IS_CALL,
9544 Opcode_callx12_encode_fns, 0, 0 },
56fb3749 9545 { "callx8", ICLASS_xt_iclass_callx8,
43cd72b9
BW		 9546 XTENSA_OPCODE_IS_CALL,
9547 Opcode_callx8_encode_fns, 0, 0 },
56fb3749 9548 { "callx4", ICLASS_xt_iclass_callx4,
43cd72b9
BW		 9549 XTENSA_OPCODE_IS_CALL,
9550 Opcode_callx4_encode_fns, 0, 0 },
56fb3749 9551 { "entry", ICLASS_xt_iclass_entry,
43cd72b9
BW		 9552 0,
9553 Opcode_entry_encode_fns, 0, 0 },
56fb3749 9554 { "movsp", ICLASS_xt_iclass_movsp,
43cd72b9
BW		 9555 0,
9556 Opcode_movsp_encode_fns, 0, 0 },
56fb3749 9557 { "rotw", ICLASS_xt_iclass_rotw,
43cd72b9
BW		 9558 0,
9559 Opcode_rotw_encode_fns, 0, 0 },
56fb3749 9560 { "retw", ICLASS_xt_iclass_retw,
43cd72b9
BW		 9561 XTENSA_OPCODE_IS_JUMP,
9562 Opcode_retw_encode_fns, 0, 0 },
56fb3749 9563 { "retw.n", ICLASS_xt_iclass_retw,
43cd72b9
BW		 9564 XTENSA_OPCODE_IS_JUMP,
9565 Opcode_retw_n_encode_fns, 0, 0 },
56fb3749 9566 { "rfwo", ICLASS_xt_iclass_rfwou,
43cd72b9
BW		 9567 XTENSA_OPCODE_IS_JUMP,
9568 Opcode_rfwo_encode_fns, 0, 0 },
56fb3749 9569 { "rfwu", ICLASS_xt_iclass_rfwou,
43cd72b9
BW		 9570 XTENSA_OPCODE_IS_JUMP,
9571 Opcode_rfwu_encode_fns, 0, 0 },
56fb3749 9572 { "l32e", ICLASS_xt_iclass_l32e,
43cd72b9
BW		 9573 0,
9574 Opcode_l32e_encode_fns, 0, 0 },
56fb3749 9575 { "s32e", ICLASS_xt_iclass_s32e,
43cd72b9
BW		 9576 0,
9577 Opcode_s32e_encode_fns, 0, 0 },
56fb3749 9578 { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
43cd72b9
BW		 9579 0,
9580 Opcode_rsr_windowbase_encode_fns, 0, 0 },
56fb3749 9581 { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
43cd72b9
BW		 9582 0,
9583 Opcode_wsr_windowbase_encode_fns, 0, 0 },
56fb3749 9584 { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
43cd72b9
BW		 9585 0,
9586 Opcode_xsr_windowbase_encode_fns, 0, 0 },
56fb3749 9587 { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
43cd72b9
BW		 9588 0,
9589 Opcode_rsr_windowstart_encode_fns, 0, 0 },
56fb3749 9590 { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
43cd72b9
BW		 9591 0,
9592 Opcode_wsr_windowstart_encode_fns, 0, 0 },
56fb3749 9593 { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
43cd72b9
BW		 9594 0,
9595 Opcode_xsr_windowstart_encode_fns, 0, 0 },
56fb3749 9596 { "add.n", ICLASS_xt_iclass_add_n,
43cd72b9
BW		 9597 0,
9598 Opcode_add_n_encode_fns, 0, 0 },
56fb3749 9599 { "addi.n", ICLASS_xt_iclass_addi_n,
43cd72b9
BW		 9600 0,
9601 Opcode_addi_n_encode_fns, 0, 0 },
56fb3749 9602 { "beqz.n", ICLASS_xt_iclass_bz6,
43cd72b9
BW		 9603 XTENSA_OPCODE_IS_BRANCH,
9604 Opcode_beqz_n_encode_fns, 0, 0 },
56fb3749 9605 { "bnez.n", ICLASS_xt_iclass_bz6,
43cd72b9
BW		 9606 XTENSA_OPCODE_IS_BRANCH,
9607 Opcode_bnez_n_encode_fns, 0, 0 },
56fb3749 9608 { "ill.n", ICLASS_xt_iclass_ill_n,
43cd72b9
BW		 9609 0,
9610 Opcode_ill_n_encode_fns, 0, 0 },
56fb3749 9611 { "l32i.n", ICLASS_xt_iclass_loadi4,
43cd72b9
BW		 9612 0,
9613 Opcode_l32i_n_encode_fns, 0, 0 },
56fb3749 9614 { "mov.n", ICLASS_xt_iclass_mov_n,
43cd72b9
BW		 9615 0,
9616 Opcode_mov_n_encode_fns, 0, 0 },
56fb3749 9617 { "movi.n", ICLASS_xt_iclass_movi_n,
43cd72b9
BW		 9618 0,
9619 Opcode_movi_n_encode_fns, 0, 0 },
56fb3749 9620 { "nop.n", ICLASS_xt_iclass_nopn,
43cd72b9
BW		 9621 0,
9622 Opcode_nop_n_encode_fns, 0, 0 },
56fb3749 9623 { "ret.n", ICLASS_xt_iclass_retn,
43cd72b9
BW		 9624 XTENSA_OPCODE_IS_JUMP,
9625 Opcode_ret_n_encode_fns, 0, 0 },
56fb3749 9626 { "s32i.n", ICLASS_xt_iclass_storei4,
43cd72b9
BW		 9627 0,
9628 Opcode_s32i_n_encode_fns, 0, 0 },
56fb3749 9629 { "rur.threadptr", ICLASS_rur_threadptr,
33430bd0
BW		 9630 0,
9631 Opcode_rur_threadptr_encode_fns, 0, 0 },
56fb3749 9632 { "wur.threadptr", ICLASS_wur_threadptr,
33430bd0
BW		 9633 0,
9634 Opcode_wur_threadptr_encode_fns, 0, 0 },
56fb3749 9635 { "addi", ICLASS_xt_iclass_addi,
43cd72b9
BW		 9636 0,
9637 Opcode_addi_encode_fns, 0, 0 },
56fb3749 9638 { "addmi", ICLASS_xt_iclass_addmi,
43cd72b9
BW		 9639 0,
9640 Opcode_addmi_encode_fns, 0, 0 },
56fb3749 9641 { "add", ICLASS_xt_iclass_addsub,
43cd72b9
BW		 9642 0,
9643 Opcode_add_encode_fns, 0, 0 },
56fb3749 9644 { "sub", ICLASS_xt_iclass_addsub,
43cd72b9
BW		 9645 0,
9646 Opcode_sub_encode_fns, 0, 0 },
56fb3749 9647 { "addx2", ICLASS_xt_iclass_addsub,
43cd72b9
BW		 9648 0,
9649 Opcode_addx2_encode_fns, 0, 0 },
56fb3749 9650 { "addx4", ICLASS_xt_iclass_addsub,
43cd72b9
BW		 9651 0,
9652 Opcode_addx4_encode_fns, 0, 0 },
56fb3749 9653 { "addx8", ICLASS_xt_iclass_addsub,
43cd72b9
BW		 9654 0,
9655 Opcode_addx8_encode_fns, 0, 0 },
56fb3749 9656 { "subx2", ICLASS_xt_iclass_addsub,
43cd72b9
BW		 9657 0,
9658 Opcode_subx2_encode_fns, 0, 0 },
56fb3749 9659 { "subx4", ICLASS_xt_iclass_addsub,
43cd72b9
BW		 9660 0,
9661 Opcode_subx4_encode_fns, 0, 0 },
56fb3749 9662 { "subx8", ICLASS_xt_iclass_addsub,
43cd72b9
BW		 9663 0,
9664 Opcode_subx8_encode_fns, 0, 0 },
56fb3749 9665 { "and", ICLASS_xt_iclass_bit,
43cd72b9
BW		 9666 0,
9667 Opcode_and_encode_fns, 0, 0 },
56fb3749 9668 { "or", ICLASS_xt_iclass_bit,
43cd72b9
BW		 9669 0,
9670 Opcode_or_encode_fns, 0, 0 },
56fb3749 9671 { "xor", ICLASS_xt_iclass_bit,
43cd72b9
BW		 9672 0,
9673 Opcode_xor_encode_fns, 0, 0 },
56fb3749 9674 { "beqi", ICLASS_xt_iclass_bsi8,
43cd72b9
BW		 9675 XTENSA_OPCODE_IS_BRANCH,
9676 Opcode_beqi_encode_fns, 0, 0 },
56fb3749 9677 { "bnei", ICLASS_xt_iclass_bsi8,
43cd72b9
BW		 9678 XTENSA_OPCODE_IS_BRANCH,
9679 Opcode_bnei_encode_fns, 0, 0 },
56fb3749 9680 { "bgei", ICLASS_xt_iclass_bsi8,
43cd72b9
BW		 9681 XTENSA_OPCODE_IS_BRANCH,
9682 Opcode_bgei_encode_fns, 0, 0 },
56fb3749 9683 { "blti", ICLASS_xt_iclass_bsi8,
43cd72b9
BW		 9684 XTENSA_OPCODE_IS_BRANCH,
9685 Opcode_blti_encode_fns, 0, 0 },
56fb3749 9686 { "bbci", ICLASS_xt_iclass_bsi8b,
43cd72b9
BW		 9687 XTENSA_OPCODE_IS_BRANCH,
9688 Opcode_bbci_encode_fns, 0, 0 },
56fb3749 9689 { "bbsi", ICLASS_xt_iclass_bsi8b,
43cd72b9
BW		 9690 XTENSA_OPCODE_IS_BRANCH,
9691 Opcode_bbsi_encode_fns, 0, 0 },
56fb3749 9692 { "bgeui", ICLASS_xt_iclass_bsi8u,
43cd72b9
BW		 9693 XTENSA_OPCODE_IS_BRANCH,
9694 Opcode_bgeui_encode_fns, 0, 0 },
56fb3749 9695 { "bltui", ICLASS_xt_iclass_bsi8u,
43cd72b9
BW		 9696 XTENSA_OPCODE_IS_BRANCH,
9697 Opcode_bltui_encode_fns, 0, 0 },
56fb3749 9698 { "beq", ICLASS_xt_iclass_bst8,
43cd72b9
BW		 9699 XTENSA_OPCODE_IS_BRANCH,
9700 Opcode_beq_encode_fns, 0, 0 },
56fb3749 9701 { "bne", ICLASS_xt_iclass_bst8,
43cd72b9
BW		 9702 XTENSA_OPCODE_IS_BRANCH,
9703 Opcode_bne_encode_fns, 0, 0 },
56fb3749 9704 { "bge", ICLASS_xt_iclass_bst8,
43cd72b9
BW		 9705 XTENSA_OPCODE_IS_BRANCH,
9706 Opcode_bge_encode_fns, 0, 0 },
56fb3749 9707 { "blt", ICLASS_xt_iclass_bst8,
43cd72b9
BW		 9708 XTENSA_OPCODE_IS_BRANCH,
9709 Opcode_blt_encode_fns, 0, 0 },
56fb3749 9710 { "bgeu", ICLASS_xt_iclass_bst8,
43cd72b9
BW		 9711 XTENSA_OPCODE_IS_BRANCH,
9712 Opcode_bgeu_encode_fns, 0, 0 },
56fb3749 9713 { "bltu", ICLASS_xt_iclass_bst8,
43cd72b9
BW		 9714 XTENSA_OPCODE_IS_BRANCH,
9715 Opcode_bltu_encode_fns, 0, 0 },
56fb3749 9716 { "bany", ICLASS_xt_iclass_bst8,
43cd72b9
BW		 9717 XTENSA_OPCODE_IS_BRANCH,
9718 Opcode_bany_encode_fns, 0, 0 },
56fb3749 9719 { "bnone", ICLASS_xt_iclass_bst8,
43cd72b9
BW		 9720 XTENSA_OPCODE_IS_BRANCH,
9721 Opcode_bnone_encode_fns, 0, 0 },
56fb3749 9722 { "ball", ICLASS_xt_iclass_bst8,
43cd72b9
BW		 9723 XTENSA_OPCODE_IS_BRANCH,
9724 Opcode_ball_encode_fns, 0, 0 },
56fb3749 9725 { "bnall", ICLASS_xt_iclass_bst8,
43cd72b9
BW		 9726 XTENSA_OPCODE_IS_BRANCH,
9727 Opcode_bnall_encode_fns, 0, 0 },
56fb3749 9728 { "bbc", ICLASS_xt_iclass_bst8,
43cd72b9
BW		 9729 XTENSA_OPCODE_IS_BRANCH,
9730 Opcode_bbc_encode_fns, 0, 0 },
56fb3749 9731 { "bbs", ICLASS_xt_iclass_bst8,
43cd72b9
BW		 9732 XTENSA_OPCODE_IS_BRANCH,
9733 Opcode_bbs_encode_fns, 0, 0 },
56fb3749 9734 { "beqz", ICLASS_xt_iclass_bsz12,
43cd72b9
BW		 9735 XTENSA_OPCODE_IS_BRANCH,
9736 Opcode_beqz_encode_fns, 0, 0 },
56fb3749 9737 { "bnez", ICLASS_xt_iclass_bsz12,
43cd72b9
BW		 9738 XTENSA_OPCODE_IS_BRANCH,
9739 Opcode_bnez_encode_fns, 0, 0 },
56fb3749 9740 { "bgez", ICLASS_xt_iclass_bsz12,
43cd72b9
BW		 9741 XTENSA_OPCODE_IS_BRANCH,
9742 Opcode_bgez_encode_fns, 0, 0 },
56fb3749 9743 { "bltz", ICLASS_xt_iclass_bsz12,
43cd72b9
BW		 9744 XTENSA_OPCODE_IS_BRANCH,
9745 Opcode_bltz_encode_fns, 0, 0 },
56fb3749 9746 { "call0", ICLASS_xt_iclass_call0,
43cd72b9
BW		 9747 XTENSA_OPCODE_IS_CALL,
9748 Opcode_call0_encode_fns, 0, 0 },
56fb3749 9749 { "callx0", ICLASS_xt_iclass_callx0,
43cd72b9
BW		 9750 XTENSA_OPCODE_IS_CALL,
9751 Opcode_callx0_encode_fns, 0, 0 },
56fb3749 9752 { "extui", ICLASS_xt_iclass_exti,
43cd72b9
BW		 9753 0,
9754 Opcode_extui_encode_fns, 0, 0 },
56fb3749 9755 { "ill", ICLASS_xt_iclass_ill,
43cd72b9
BW		 9756 0,
9757 Opcode_ill_encode_fns, 0, 0 },
56fb3749 9758 { "j", ICLASS_xt_iclass_jump,
43cd72b9
BW		 9759 XTENSA_OPCODE_IS_JUMP,
9760 Opcode_j_encode_fns, 0, 0 },
56fb3749 9761 { "jx", ICLASS_xt_iclass_jumpx,
43cd72b9
BW		 9762 XTENSA_OPCODE_IS_JUMP,
9763 Opcode_jx_encode_fns, 0, 0 },
56fb3749 9764 { "l16ui", ICLASS_xt_iclass_l16ui,
43cd72b9
BW		 9765 0,
9766 Opcode_l16ui_encode_fns, 0, 0 },
56fb3749 9767 { "l16si", ICLASS_xt_iclass_l16si,
43cd72b9
BW		 9768 0,
9769 Opcode_l16si_encode_fns, 0, 0 },
56fb3749 9770 { "l32i", ICLASS_xt_iclass_l32i,
43cd72b9
BW		 9771 0,
9772 Opcode_l32i_encode_fns, 0, 0 },
56fb3749 9773 { "l32r", ICLASS_xt_iclass_l32r,
43cd72b9
BW		 9774 0,
9775 Opcode_l32r_encode_fns, 0, 0 },
56fb3749 9776 { "l8ui", ICLASS_xt_iclass_l8i,
43cd72b9
BW		 9777 0,
9778 Opcode_l8ui_encode_fns, 0, 0 },
56fb3749 9779 { "loop", ICLASS_xt_iclass_loop,
43cd72b9
BW		 9780 XTENSA_OPCODE_IS_LOOP,
9781 Opcode_loop_encode_fns, 0, 0 },
56fb3749 9782 { "loopnez", ICLASS_xt_iclass_loopz,
43cd72b9
BW		 9783 XTENSA_OPCODE_IS_LOOP,
9784 Opcode_loopnez_encode_fns, 0, 0 },
56fb3749 9785 { "loopgtz", ICLASS_xt_iclass_loopz,
43cd72b9
BW		 9786 XTENSA_OPCODE_IS_LOOP,
9787 Opcode_loopgtz_encode_fns, 0, 0 },
56fb3749 9788 { "movi", ICLASS_xt_iclass_movi,
43cd72b9
BW		 9789 0,
9790 Opcode_movi_encode_fns, 0, 0 },
56fb3749 9791 { "moveqz", ICLASS_xt_iclass_movz,
43cd72b9
BW		 9792 0,
9793 Opcode_moveqz_encode_fns, 0, 0 },
56fb3749 9794 { "movnez", ICLASS_xt_iclass_movz,
43cd72b9
BW		 9795 0,
9796 Opcode_movnez_encode_fns, 0, 0 },
56fb3749 9797 { "movltz", ICLASS_xt_iclass_movz,
43cd72b9
BW		 9798 0,
9799 Opcode_movltz_encode_fns, 0, 0 },
56fb3749 9800 { "movgez", ICLASS_xt_iclass_movz,
43cd72b9
BW		 9801 0,
9802 Opcode_movgez_encode_fns, 0, 0 },
56fb3749 9803 { "neg", ICLASS_xt_iclass_neg,
43cd72b9
BW		 9804 0,
9805 Opcode_neg_encode_fns, 0, 0 },
56fb3749 9806 { "abs", ICLASS_xt_iclass_neg,
43cd72b9
BW		 9807 0,
9808 Opcode_abs_encode_fns, 0, 0 },
56fb3749 9809 { "nop", ICLASS_xt_iclass_nop,
43cd72b9
BW		 9810 0,
9811 Opcode_nop_encode_fns, 0, 0 },
56fb3749 9812 { "ret", ICLASS_xt_iclass_return,
43cd72b9
BW		 9813 XTENSA_OPCODE_IS_JUMP,
9814 Opcode_ret_encode_fns, 0, 0 },
56fb3749 9815 { "s16i", ICLASS_xt_iclass_s16i,
43cd72b9
BW		 9816 0,
9817 Opcode_s16i_encode_fns, 0, 0 },
56fb3749 9818 { "s32i", ICLASS_xt_iclass_s32i,
43cd72b9
BW		 9819 0,
9820 Opcode_s32i_encode_fns, 0, 0 },
56fb3749 9821 { "s8i", ICLASS_xt_iclass_s8i,
43cd72b9
BW		 9822 0,
9823 Opcode_s8i_encode_fns, 0, 0 },
56fb3749 9824 { "ssr", ICLASS_xt_iclass_sar,
43cd72b9
BW		 9825 0,
9826 Opcode_ssr_encode_fns, 0, 0 },
56fb3749 9827 { "ssl", ICLASS_xt_iclass_sar,
43cd72b9
BW		 9828 0,
9829 Opcode_ssl_encode_fns, 0, 0 },
56fb3749 9830 { "ssa8l", ICLASS_xt_iclass_sar,
43cd72b9
BW		 9831 0,
9832 Opcode_ssa8l_encode_fns, 0, 0 },
56fb3749 9833 { "ssa8b", ICLASS_xt_iclass_sar,
43cd72b9
BW		 9834 0,
9835 Opcode_ssa8b_encode_fns, 0, 0 },
56fb3749 9836 { "ssai", ICLASS_xt_iclass_sari,
43cd72b9
BW		 9837 0,
9838 Opcode_ssai_encode_fns, 0, 0 },
56fb3749 9839 { "sll", ICLASS_xt_iclass_shifts,
43cd72b9
BW		 9840 0,
9841 Opcode_sll_encode_fns, 0, 0 },
56fb3749 9842 { "src", ICLASS_xt_iclass_shiftst,
43cd72b9
BW		 9843 0,
9844 Opcode_src_encode_fns, 0, 0 },
56fb3749 9845 { "srl", ICLASS_xt_iclass_shiftt,
43cd72b9
BW		 9846 0,
9847 Opcode_srl_encode_fns, 0, 0 },
56fb3749 9848 { "sra", ICLASS_xt_iclass_shiftt,
43cd72b9
BW		 9849 0,
9850 Opcode_sra_encode_fns, 0, 0 },
56fb3749 9851 { "slli", ICLASS_xt_iclass_slli,
43cd72b9
BW		 9852 0,
9853 Opcode_slli_encode_fns, 0, 0 },
56fb3749 9854 { "srai", ICLASS_xt_iclass_srai,
43cd72b9
BW		 9855 0,
9856 Opcode_srai_encode_fns, 0, 0 },
56fb3749 9857 { "srli", ICLASS_xt_iclass_srli,
43cd72b9
BW		 9858 0,
9859 Opcode_srli_encode_fns, 0, 0 },
56fb3749 9860 { "memw", ICLASS_xt_iclass_memw,
43cd72b9
BW		 9861 0,
9862 Opcode_memw_encode_fns, 0, 0 },
56fb3749 9863 { "extw", ICLASS_xt_iclass_extw,
43cd72b9
BW		 9864 0,
9865 Opcode_extw_encode_fns, 0, 0 },
56fb3749 9866 { "isync", ICLASS_xt_iclass_isync,
43cd72b9
BW		 9867 0,
9868 Opcode_isync_encode_fns, 0, 0 },
56fb3749 9869 { "rsync", ICLASS_xt_iclass_sync,
43cd72b9
BW		 9870 0,
9871 Opcode_rsync_encode_fns, 0, 0 },
56fb3749 9872 { "esync", ICLASS_xt_iclass_sync,
43cd72b9
BW		 9873 0,
9874 Opcode_esync_encode_fns, 0, 0 },
56fb3749 9875 { "dsync", ICLASS_xt_iclass_sync,
43cd72b9
BW		 9876 0,
9877 Opcode_dsync_encode_fns, 0, 0 },
56fb3749 9878 { "rsil", ICLASS_xt_iclass_rsil,
43cd72b9
BW		 9879 0,
9880 Opcode_rsil_encode_fns, 0, 0 },
56fb3749 9881 { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
43cd72b9
BW		 9882 0,
9883 Opcode_rsr_lend_encode_fns, 0, 0 },
56fb3749 9884 { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
43cd72b9
BW		 9885 0,
9886 Opcode_wsr_lend_encode_fns, 0, 0 },
56fb3749 9887 { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
43cd72b9
BW		 9888 0,
9889 Opcode_xsr_lend_encode_fns, 0, 0 },
56fb3749 9890 { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
43cd72b9
BW		 9891 0,
9892 Opcode_rsr_lcount_encode_fns, 0, 0 },
56fb3749 9893 { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
43cd72b9
BW		 9894 0,
9895 Opcode_wsr_lcount_encode_fns, 0, 0 },
56fb3749 9896 { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
43cd72b9
BW		 9897 0,
9898 Opcode_xsr_lcount_encode_fns, 0, 0 },
56fb3749 9899 { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
43cd72b9
BW		 9900 0,
9901 Opcode_rsr_lbeg_encode_fns, 0, 0 },
56fb3749 9902 { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
43cd72b9
BW		 9903 0,
9904 Opcode_wsr_lbeg_encode_fns, 0, 0 },
56fb3749 9905 { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
43cd72b9
BW		 9906 0,
9907 Opcode_xsr_lbeg_encode_fns, 0, 0 },
56fb3749 9908 { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
43cd72b9
BW		 9909 0,
9910 Opcode_rsr_sar_encode_fns, 0, 0 },
56fb3749 9911 { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
43cd72b9
BW		 9912 0,
9913 Opcode_wsr_sar_encode_fns, 0, 0 },
56fb3749 9914 { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
43cd72b9
BW		 9915 0,
9916 Opcode_xsr_sar_encode_fns, 0, 0 },
56fb3749 9917 { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
43cd72b9
BW		 9918 0,
9919 Opcode_rsr_litbase_encode_fns, 0, 0 },
56fb3749 9920 { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
43cd72b9
BW		 9921 0,
9922 Opcode_wsr_litbase_encode_fns, 0, 0 },
56fb3749 9923 { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
43cd72b9
BW		 9924 0,
9925 Opcode_xsr_litbase_encode_fns, 0, 0 },
56fb3749 9926 { "rsr.176", ICLASS_xt_iclass_rsr_176,
43cd72b9
BW		 9927 0,
9928 Opcode_rsr_176_encode_fns, 0, 0 },
56fb3749 9929 { "wsr.176", ICLASS_xt_iclass_wsr_176,
33430bd0
BW		 9930 0,
9931 Opcode_wsr_176_encode_fns, 0, 0 },
56fb3749 9932 { "rsr.208", ICLASS_xt_iclass_rsr_208,
43cd72b9
BW		 9933 0,
9934 Opcode_rsr_208_encode_fns, 0, 0 },
56fb3749 9935 { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
43cd72b9
BW		 9936 0,
9937 Opcode_rsr_ps_encode_fns, 0, 0 },
56fb3749 9938 { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
43cd72b9
BW		 9939 0,
9940 Opcode_wsr_ps_encode_fns, 0, 0 },
56fb3749 9941 { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
43cd72b9
BW		 9942 0,
9943 Opcode_xsr_ps_encode_fns, 0, 0 },
56fb3749 9944 { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
43cd72b9
BW		 9945 0,
9946 Opcode_rsr_epc1_encode_fns, 0, 0 },
56fb3749 9947 { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
43cd72b9
BW		 9948 0,
9949 Opcode_wsr_epc1_encode_fns, 0, 0 },
56fb3749 9950 { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
43cd72b9
BW		 9951 0,
9952 Opcode_xsr_epc1_encode_fns, 0, 0 },
56fb3749 9953 { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
43cd72b9
BW		 9954 0,
9955 Opcode_rsr_excsave1_encode_fns, 0, 0 },
56fb3749 9956 { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
43cd72b9
BW		 9957 0,
9958 Opcode_wsr_excsave1_encode_fns, 0, 0 },
56fb3749 9959 { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
43cd72b9
BW		 9960 0,
9961 Opcode_xsr_excsave1_encode_fns, 0, 0 },
56fb3749 9962 { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
43cd72b9
BW		 9963 0,
9964 Opcode_rsr_epc2_encode_fns, 0, 0 },
56fb3749 9965 { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
43cd72b9
BW		 9966 0,
9967 Opcode_wsr_epc2_encode_fns, 0, 0 },
56fb3749 9968 { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
43cd72b9
BW		 9969 0,
9970 Opcode_xsr_epc2_encode_fns, 0, 0 },
56fb3749 9971 { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
43cd72b9
BW		 9972 0,
9973 Opcode_rsr_excsave2_encode_fns, 0, 0 },
56fb3749 9974 { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
43cd72b9
BW		 9975 0,
9976 Opcode_wsr_excsave2_encode_fns, 0, 0 },
56fb3749 9977 { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
43cd72b9
BW		 9978 0,
9979 Opcode_xsr_excsave2_encode_fns, 0, 0 },
56fb3749 9980 { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
43cd72b9
BW		 9981 0,
9982 Opcode_rsr_epc3_encode_fns, 0, 0 },
56fb3749 9983 { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
43cd72b9
BW		 9984 0,
9985 Opcode_wsr_epc3_encode_fns, 0, 0 },
56fb3749 9986 { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
43cd72b9
BW		 9987 0,
9988 Opcode_xsr_epc3_encode_fns, 0, 0 },
56fb3749 9989 { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
43cd72b9
BW		 9990 0,
9991 Opcode_rsr_excsave3_encode_fns, 0, 0 },
56fb3749 9992 { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
43cd72b9
BW		 9993 0,
9994 Opcode_wsr_excsave3_encode_fns, 0, 0 },
56fb3749 9995 { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
43cd72b9
BW		 9996 0,
9997 Opcode_xsr_excsave3_encode_fns, 0, 0 },
56fb3749 9998 { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
43cd72b9
BW		 9999 0,
10000 Opcode_rsr_epc4_encode_fns, 0, 0 },
56fb3749 10001 { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
43cd72b9
BW		 10002 0,
10003 Opcode_wsr_epc4_encode_fns, 0, 0 },
56fb3749 10004 { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
43cd72b9
BW		 10005 0,
10006 Opcode_xsr_epc4_encode_fns, 0, 0 },
56fb3749 10007 { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
43cd72b9
BW		 10008 0,
10009 Opcode_rsr_excsave4_encode_fns, 0, 0 },
56fb3749 10010 { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
43cd72b9
BW		 10011 0,
10012 Opcode_wsr_excsave4_encode_fns, 0, 0 },
56fb3749 10013 { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
43cd72b9
BW		 10014 0,
10015 Opcode_xsr_excsave4_encode_fns, 0, 0 },
56fb3749 10016 { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
33430bd0
BW		 10017 0,
10018 Opcode_rsr_epc5_encode_fns, 0, 0 },
56fb3749 10019 { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
33430bd0
BW		 10020 0,
10021 Opcode_wsr_epc5_encode_fns, 0, 0 },
56fb3749 10022 { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
33430bd0
BW		 10023 0,
10024 Opcode_xsr_epc5_encode_fns, 0, 0 },
56fb3749 10025 { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
33430bd0
BW		 10026 0,
10027 Opcode_rsr_excsave5_encode_fns, 0, 0 },
56fb3749 10028 { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
33430bd0
BW		 10029 0,
10030 Opcode_wsr_excsave5_encode_fns, 0, 0 },
56fb3749 10031 { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
33430bd0
BW		 10032 0,
10033 Opcode_xsr_excsave5_encode_fns, 0, 0 },
56fb3749 10034 { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
33430bd0
BW		 10035 0,
10036 Opcode_rsr_epc6_encode_fns, 0, 0 },
56fb3749 10037 { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
33430bd0
BW		 10038 0,
10039 Opcode_wsr_epc6_encode_fns, 0, 0 },
56fb3749 10040 { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
33430bd0
BW		 10041 0,
10042 Opcode_xsr_epc6_encode_fns, 0, 0 },
56fb3749 10043 { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
33430bd0
BW		 10044 0,
10045 Opcode_rsr_excsave6_encode_fns, 0, 0 },
56fb3749 10046 { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
33430bd0
BW		 10047 0,
10048 Opcode_wsr_excsave6_encode_fns, 0, 0 },
56fb3749 10049 { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
33430bd0
BW		 10050 0,
10051 Opcode_xsr_excsave6_encode_fns, 0, 0 },
56fb3749 10052 { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
33430bd0
BW		 10053 0,
10054 Opcode_rsr_epc7_encode_fns, 0, 0 },
56fb3749 10055 { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
33430bd0
BW		 10056 0,
10057 Opcode_wsr_epc7_encode_fns, 0, 0 },
56fb3749 10058 { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
33430bd0
BW		 10059 0,
10060 Opcode_xsr_epc7_encode_fns, 0, 0 },
56fb3749 10061 { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
33430bd0
BW		 10062 0,
10063 Opcode_rsr_excsave7_encode_fns, 0, 0 },
56fb3749 10064 { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
33430bd0
BW		 10065 0,
10066 Opcode_wsr_excsave7_encode_fns, 0, 0 },
56fb3749 10067 { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
33430bd0
BW		 10068 0,
10069 Opcode_xsr_excsave7_encode_fns, 0, 0 },
56fb3749 10070 { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
43cd72b9
BW		 10071 0,
10072 Opcode_rsr_eps2_encode_fns, 0, 0 },
56fb3749 10073 { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
43cd72b9
BW		 10074 0,
10075 Opcode_wsr_eps2_encode_fns, 0, 0 },
56fb3749 10076 { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
43cd72b9
BW		 10077 0,
10078 Opcode_xsr_eps2_encode_fns, 0, 0 },
56fb3749 10079 { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
43cd72b9
BW		 10080 0,
10081 Opcode_rsr_eps3_encode_fns, 0, 0 },
56fb3749 10082 { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
43cd72b9
BW		 10083 0,
10084 Opcode_wsr_eps3_encode_fns, 0, 0 },
56fb3749 10085 { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
43cd72b9
BW		 10086 0,
10087 Opcode_xsr_eps3_encode_fns, 0, 0 },
56fb3749 10088 { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
43cd72b9
BW		 10089 0,
10090 Opcode_rsr_eps4_encode_fns, 0, 0 },
56fb3749 10091 { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
43cd72b9
BW		 10092 0,
10093 Opcode_wsr_eps4_encode_fns, 0, 0 },
56fb3749 10094 { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
43cd72b9
BW		 10095 0,
10096 Opcode_xsr_eps4_encode_fns, 0, 0 },
56fb3749 10097 { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
33430bd0
BW		 10098 0,
10099 Opcode_rsr_eps5_encode_fns, 0, 0 },
56fb3749 10100 { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
33430bd0
BW		 10101 0,
10102 Opcode_wsr_eps5_encode_fns, 0, 0 },
56fb3749 10103 { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
33430bd0
BW		 10104 0,
10105 Opcode_xsr_eps5_encode_fns, 0, 0 },
56fb3749 10106 { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
33430bd0
BW		 10107 0,
10108 Opcode_rsr_eps6_encode_fns, 0, 0 },
56fb3749 10109 { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
33430bd0
BW		 10110 0,
10111 Opcode_wsr_eps6_encode_fns, 0, 0 },
56fb3749 10112 { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
33430bd0
BW		 10113 0,
10114 Opcode_xsr_eps6_encode_fns, 0, 0 },
56fb3749 10115 { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
33430bd0
BW		 10116 0,
10117 Opcode_rsr_eps7_encode_fns, 0, 0 },
56fb3749 10118 { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
33430bd0
BW		 10119 0,
10120 Opcode_wsr_eps7_encode_fns, 0, 0 },
56fb3749 10121 { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
33430bd0
BW		 10122 0,
10123 Opcode_xsr_eps7_encode_fns, 0, 0 },
56fb3749 10124 { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
43cd72b9
BW		 10125 0,
10126 Opcode_rsr_excvaddr_encode_fns, 0, 0 },
56fb3749 10127 { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
43cd72b9
BW		 10128 0,
10129 Opcode_wsr_excvaddr_encode_fns, 0, 0 },
56fb3749 10130 { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
43cd72b9
BW		 10131 0,
10132 Opcode_xsr_excvaddr_encode_fns, 0, 0 },
56fb3749 10133 { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
43cd72b9
BW		 10134 0,
10135 Opcode_rsr_depc_encode_fns, 0, 0 },
56fb3749 10136 { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
43cd72b9
BW		 10137 0,
10138 Opcode_wsr_depc_encode_fns, 0, 0 },
56fb3749 10139 { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
43cd72b9
BW		 10140 0,
10141 Opcode_xsr_depc_encode_fns, 0, 0 },
56fb3749 10142 { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
43cd72b9
BW		 10143 0,
10144 Opcode_rsr_exccause_encode_fns, 0, 0 },
56fb3749 10145 { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
43cd72b9
BW		 10146 0,
10147 Opcode_wsr_exccause_encode_fns, 0, 0 },
56fb3749 10148 { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
43cd72b9
BW		 10149 0,
10150 Opcode_xsr_exccause_encode_fns, 0, 0 },
56fb3749 10151 { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
43cd72b9
BW		 10152 0,
10153 Opcode_rsr_misc0_encode_fns, 0, 0 },
56fb3749 10154 { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
43cd72b9
BW		 10155 0,
10156 Opcode_wsr_misc0_encode_fns, 0, 0 },
56fb3749 10157 { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
43cd72b9
BW		 10158 0,
10159 Opcode_xsr_misc0_encode_fns, 0, 0 },
56fb3749 10160 { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
43cd72b9
BW		 10161 0,
10162 Opcode_rsr_misc1_encode_fns, 0, 0 },
56fb3749 10163 { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
43cd72b9
BW		 10164 0,
10165 Opcode_wsr_misc1_encode_fns, 0, 0 },
56fb3749 10166 { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
43cd72b9
BW		 10167 0,
10168 Opcode_xsr_misc1_encode_fns, 0, 0 },
56fb3749 10169 { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
43cd72b9
BW		 10170 0,
10171 Opcode_rsr_prid_encode_fns, 0, 0 },
56fb3749 10172 { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
33430bd0
BW		 10173 0,
10174 Opcode_rsr_vecbase_encode_fns, 0, 0 },
56fb3749 10175 { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
33430bd0
BW		 10176 0,
10177 Opcode_wsr_vecbase_encode_fns, 0, 0 },
56fb3749 10178 { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
33430bd0
BW		 10179 0,
10180 Opcode_xsr_vecbase_encode_fns, 0, 0 },
56fb3749 10181 { "mul16u", ICLASS_xt_iclass_mul16,
33430bd0
BW		 10182 0,
10183 Opcode_mul16u_encode_fns, 0, 0 },
56fb3749 10184 { "mul16s", ICLASS_xt_iclass_mul16,
33430bd0
BW		 10185 0,
10186 Opcode_mul16s_encode_fns, 0, 0 },
56fb3749 10187 { "rfi", ICLASS_xt_iclass_rfi,
43cd72b9
BW		 10188 XTENSA_OPCODE_IS_JUMP,
10189 Opcode_rfi_encode_fns, 0, 0 },
56fb3749 10190 { "waiti", ICLASS_xt_iclass_wait,
43cd72b9
BW		 10191 0,
10192 Opcode_waiti_encode_fns, 0, 0 },
56fb3749 10193 { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
43cd72b9
BW		 10194 0,
10195 Opcode_rsr_interrupt_encode_fns, 0, 0 },
56fb3749 10196 { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
43cd72b9
BW		 10197 0,
10198 Opcode_wsr_intset_encode_fns, 0, 0 },
56fb3749 10199 { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
43cd72b9
BW		 10200 0,
10201 Opcode_wsr_intclear_encode_fns, 0, 0 },
56fb3749 10202 { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
43cd72b9
BW		 10203 0,
10204 Opcode_rsr_intenable_encode_fns, 0, 0 },
56fb3749 10205 { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
43cd72b9
BW		 10206 0,
10207 Opcode_wsr_intenable_encode_fns, 0, 0 },
56fb3749 10208 { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
43cd72b9
BW		 10209 0,
10210 Opcode_xsr_intenable_encode_fns, 0, 0 },
56fb3749 10211 { "break", ICLASS_xt_iclass_break,
43cd72b9
BW		 10212 0,
10213 Opcode_break_encode_fns, 0, 0 },
56fb3749 10214 { "break.n", ICLASS_xt_iclass_break_n,
43cd72b9
BW		 10215 0,
10216 Opcode_break_n_encode_fns, 0, 0 },
56fb3749 10217 { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
43cd72b9
BW		 10218 0,
10219 Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
56fb3749 10220 { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
43cd72b9
BW		 10221 0,
10222 Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
56fb3749 10223 { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
43cd72b9
BW		 10224 0,
10225 Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
56fb3749 10226 { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
43cd72b9
BW		 10227 0,
10228 Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
56fb3749 10229 { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
43cd72b9
BW		 10230 0,
10231 Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
56fb3749 10232 { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
43cd72b9
BW		 10233 0,
10234 Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
56fb3749 10235 { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
43cd72b9
BW		 10236 0,
10237 Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
56fb3749 10238 { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
43cd72b9
BW		 10239 0,
10240 Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
56fb3749 10241 { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
43cd72b9
BW		 10242 0,
10243 Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
56fb3749 10244 { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
43cd72b9
BW		 10245 0,
10246 Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
56fb3749 10247 { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
43cd72b9
BW		 10248 0,
10249 Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
56fb3749 10250 { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
43cd72b9
BW		 10251 0,
10252 Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
56fb3749 10253 { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
43cd72b9
BW		 10254 0,
10255 Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
56fb3749 10256 { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
43cd72b9
BW		 10257 0,
10258 Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
56fb3749 10259 { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
43cd72b9
BW		 10260 0,
10261 Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
56fb3749 10262 { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
43cd72b9
BW		 10263 0,
10264 Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
56fb3749 10265 { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
43cd72b9
BW		 10266 0,
10267 Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
56fb3749 10268 { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
43cd72b9
BW		 10269 0,
10270 Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
56fb3749 10271 { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
43cd72b9
BW		 10272 0,
10273 Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
56fb3749 10274 { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
43cd72b9
BW		 10275 0,
10276 Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
56fb3749 10277 { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
43cd72b9
BW		 10278 0,
10279 Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
56fb3749 10280 { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
43cd72b9
BW		 10281 0,
10282 Opcode_rsr_debugcause_encode_fns, 0, 0 },
56fb3749 10283 { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
43cd72b9
BW		 10284 0,
10285 Opcode_wsr_debugcause_encode_fns, 0, 0 },
56fb3749 10286 { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
43cd72b9
BW		 10287 0,
10288 Opcode_xsr_debugcause_encode_fns, 0, 0 },
56fb3749 10289 { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
43cd72b9
BW		 10290 0,
10291 Opcode_rsr_icount_encode_fns, 0, 0 },
56fb3749 10292 { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
43cd72b9
BW		 10293 0,
10294 Opcode_wsr_icount_encode_fns, 0, 0 },
56fb3749 10295 { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
43cd72b9
BW		 10296 0,
10297 Opcode_xsr_icount_encode_fns, 0, 0 },
56fb3749 10298 { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
43cd72b9
BW		 10299 0,
10300 Opcode_rsr_icountlevel_encode_fns, 0, 0 },
56fb3749 10301 { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
43cd72b9
BW		 10302 0,
10303 Opcode_wsr_icountlevel_encode_fns, 0, 0 },
56fb3749 10304 { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
43cd72b9
BW		 10305 0,
10306 Opcode_xsr_icountlevel_encode_fns, 0, 0 },
56fb3749 10307 { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
43cd72b9
BW		 10308 0,
10309 Opcode_rsr_ddr_encode_fns, 0, 0 },
56fb3749 10310 { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
43cd72b9
BW		 10311 0,
10312 Opcode_wsr_ddr_encode_fns, 0, 0 },
56fb3749 10313 { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
43cd72b9
BW		 10314 0,
10315 Opcode_xsr_ddr_encode_fns, 0, 0 },
56fb3749 10316 { "rfdo", ICLASS_xt_iclass_rfdo,
43cd72b9
BW		 10317 XTENSA_OPCODE_IS_JUMP,
10318 Opcode_rfdo_encode_fns, 0, 0 },
56fb3749 10319 { "rfdd", ICLASS_xt_iclass_rfdd,
43cd72b9
BW		 10320 XTENSA_OPCODE_IS_JUMP,
10321 Opcode_rfdd_encode_fns, 0, 0 },
56fb3749 10322 { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
33430bd0
BW		 10323 0,
10324 Opcode_wsr_mmid_encode_fns, 0, 0 },
56fb3749 10325 { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
43cd72b9
BW		 10326 0,
10327 Opcode_rsr_ccount_encode_fns, 0, 0 },
56fb3749 10328 { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
43cd72b9
BW		 10329 0,
10330 Opcode_wsr_ccount_encode_fns, 0, 0 },
56fb3749 10331 { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
43cd72b9
BW		 10332 0,
10333 Opcode_xsr_ccount_encode_fns, 0, 0 },
56fb3749 10334 { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
43cd72b9
BW		 10335 0,
10336 Opcode_rsr_ccompare0_encode_fns, 0, 0 },
56fb3749 10337 { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
43cd72b9
BW		 10338 0,
10339 Opcode_wsr_ccompare0_encode_fns, 0, 0 },
56fb3749 10340 { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
43cd72b9
BW		 10341 0,
10342 Opcode_xsr_ccompare0_encode_fns, 0, 0 },
56fb3749 10343 { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
43cd72b9
BW		 10344 0,
10345 Opcode_rsr_ccompare1_encode_fns, 0, 0 },
56fb3749 10346 { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
43cd72b9
BW		 10347 0,
10348 Opcode_wsr_ccompare1_encode_fns, 0, 0 },
56fb3749 10349 { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
43cd72b9
BW		 10350 0,
10351 Opcode_xsr_ccompare1_encode_fns, 0, 0 },
56fb3749 10352 { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
43cd72b9
BW		 10353 0,
10354 Opcode_rsr_ccompare2_encode_fns, 0, 0 },
56fb3749 10355 { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
43cd72b9
BW		 10356 0,
10357 Opcode_wsr_ccompare2_encode_fns, 0, 0 },
56fb3749 10358 { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
43cd72b9
BW		 10359 0,
10360 Opcode_xsr_ccompare2_encode_fns, 0, 0 },
56fb3749 10361 { "ipf", ICLASS_xt_iclass_icache,
43cd72b9
BW		 10362 0,
10363 Opcode_ipf_encode_fns, 0, 0 },
56fb3749 10364 { "ihi", ICLASS_xt_iclass_icache,
43cd72b9
BW		 10365 0,
10366 Opcode_ihi_encode_fns, 0, 0 },
56fb3749 10367 { "ipfl", ICLASS_xt_iclass_icache_lock,
33430bd0
BW		 10368 0,
10369 Opcode_ipfl_encode_fns, 0, 0 },
56fb3749 10370 { "ihu", ICLASS_xt_iclass_icache_lock,
33430bd0
BW		 10371 0,
10372 Opcode_ihu_encode_fns, 0, 0 },
56fb3749 10373 { "iiu", ICLASS_xt_iclass_icache_lock,
33430bd0
BW		 10374 0,
10375 Opcode_iiu_encode_fns, 0, 0 },
56fb3749 10376 { "iii", ICLASS_xt_iclass_icache_inv,
43cd72b9
BW		 10377 0,
10378 Opcode_iii_encode_fns, 0, 0 },
56fb3749 10379 { "lict", ICLASS_xt_iclass_licx,
43cd72b9
BW		 10380 0,
10381 Opcode_lict_encode_fns, 0, 0 },
56fb3749 10382 { "licw", ICLASS_xt_iclass_licx,
43cd72b9
BW		 10383 0,
10384 Opcode_licw_encode_fns, 0, 0 },
56fb3749 10385 { "sict", ICLASS_xt_iclass_sicx,
43cd72b9
BW		 10386 0,
10387 Opcode_sict_encode_fns, 0, 0 },
56fb3749 10388 { "sicw", ICLASS_xt_iclass_sicx,
43cd72b9
BW		 10389 0,
10390 Opcode_sicw_encode_fns, 0, 0 },
56fb3749 10391 { "dhwb", ICLASS_xt_iclass_dcache,
43cd72b9
BW		 10392 0,
10393 Opcode_dhwb_encode_fns, 0, 0 },
56fb3749 10394 { "dhwbi", ICLASS_xt_iclass_dcache,
43cd72b9
BW		 10395 0,
10396 Opcode_dhwbi_encode_fns, 0, 0 },
56fb3749 10397 { "diwb", ICLASS_xt_iclass_dcache_ind,
43cd72b9
BW		 10398 0,
10399 Opcode_diwb_encode_fns, 0, 0 },
56fb3749 10400 { "diwbi", ICLASS_xt_iclass_dcache_ind,
43cd72b9
BW		 10401 0,
10402 Opcode_diwbi_encode_fns, 0, 0 },
56fb3749 10403 { "dhi", ICLASS_xt_iclass_dcache_inv,
43cd72b9
BW		 10404 0,
10405 Opcode_dhi_encode_fns, 0, 0 },
56fb3749 10406 { "dii", ICLASS_xt_iclass_dcache_inv,
43cd72b9
BW		 10407 0,
10408 Opcode_dii_encode_fns, 0, 0 },
56fb3749 10409 { "dpfr", ICLASS_xt_iclass_dpf,
43cd72b9
BW		 10410 0,
10411 Opcode_dpfr_encode_fns, 0, 0 },
56fb3749 10412 { "dpfw", ICLASS_xt_iclass_dpf,
43cd72b9
BW		 10413 0,
10414 Opcode_dpfw_encode_fns, 0, 0 },
56fb3749 10415 { "dpfro", ICLASS_xt_iclass_dpf,
43cd72b9
BW		 10416 0,
10417 Opcode_dpfro_encode_fns, 0, 0 },
56fb3749 10418 { "dpfwo", ICLASS_xt_iclass_dpf,
43cd72b9
BW		 10419 0,
10420 Opcode_dpfwo_encode_fns, 0, 0 },
56fb3749 10421 { "dpfl", ICLASS_xt_iclass_dcache_lock,
33430bd0
BW		 10422 0,
10423 Opcode_dpfl_encode_fns, 0, 0 },
56fb3749 10424 { "dhu", ICLASS_xt_iclass_dcache_lock,
33430bd0
BW		 10425 0,
10426 Opcode_dhu_encode_fns, 0, 0 },
56fb3749 10427 { "diu", ICLASS_xt_iclass_dcache_lock,
33430bd0
BW		 10428 0,
10429 Opcode_diu_encode_fns, 0, 0 },
56fb3749 10430 { "sdct", ICLASS_xt_iclass_sdct,
43cd72b9
BW		 10431 0,
10432 Opcode_sdct_encode_fns, 0, 0 },
56fb3749 10433 { "ldct", ICLASS_xt_iclass_ldct,
43cd72b9
BW		 10434 0,
10435 Opcode_ldct_encode_fns, 0, 0 },
56fb3749 10436 { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr,
074f5109
BW		 10437 0,
10438 Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
56fb3749 10439 { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr,
074f5109
BW		 10440 0,
10441 Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
56fb3749 10442 { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr,
074f5109
BW		 10443 0,
10444 Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
56fb3749 10445 { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid,
074f5109
BW		 10446 0,
10447 Opcode_rsr_rasid_encode_fns, 0, 0 },
56fb3749 10448 { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid,
074f5109
BW		 10449 0,
10450 Opcode_wsr_rasid_encode_fns, 0, 0 },
56fb3749 10451 { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid,
074f5109
BW		 10452 0,
10453 Opcode_xsr_rasid_encode_fns, 0, 0 },
56fb3749 10454 { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg,
074f5109
BW		 10455 0,
10456 Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
56fb3749 10457 { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg,
074f5109
BW		 10458 0,
10459 Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
56fb3749 10460 { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg,
074f5109
BW		 10461 0,
10462 Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
56fb3749 10463 { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg,
074f5109
BW		 10464 0,
10465 Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
56fb3749 10466 { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg,
074f5109
BW		 10467 0,
10468 Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
56fb3749 10469 { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg,
074f5109
BW		 10470 0,
10471 Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
56fb3749 10472 { "idtlb", ICLASS_xt_iclass_idtlb,
43cd72b9
BW		 10473 0,
10474 Opcode_idtlb_encode_fns, 0, 0 },
56fb3749 10475 { "pdtlb", ICLASS_xt_iclass_rdtlb,
43cd72b9
BW		 10476 0,
10477 Opcode_pdtlb_encode_fns, 0, 0 },
56fb3749 10478 { "rdtlb0", ICLASS_xt_iclass_rdtlb,
43cd72b9
BW		 10479 0,
10480 Opcode_rdtlb0_encode_fns, 0, 0 },
56fb3749 10481 { "rdtlb1", ICLASS_xt_iclass_rdtlb,
43cd72b9
BW		 10482 0,
10483 Opcode_rdtlb1_encode_fns, 0, 0 },
56fb3749 10484 { "wdtlb", ICLASS_xt_iclass_wdtlb,
43cd72b9
BW		 10485 0,
10486 Opcode_wdtlb_encode_fns, 0, 0 },
56fb3749 10487 { "iitlb", ICLASS_xt_iclass_iitlb,
43cd72b9
BW		 10488 0,
10489 Opcode_iitlb_encode_fns, 0, 0 },
56fb3749 10490 { "pitlb", ICLASS_xt_iclass_ritlb,
43cd72b9
BW		 10491 0,
10492 Opcode_pitlb_encode_fns, 0, 0 },
56fb3749 10493 { "ritlb0", ICLASS_xt_iclass_ritlb,
43cd72b9
BW		 10494 0,
10495 Opcode_ritlb0_encode_fns, 0, 0 },
56fb3749 10496 { "ritlb1", ICLASS_xt_iclass_ritlb,
43cd72b9
BW		 10497 0,
10498 Opcode_ritlb1_encode_fns, 0, 0 },
56fb3749 10499 { "witlb", ICLASS_xt_iclass_witlb,
43cd72b9
BW		 10500 0,
10501 Opcode_witlb_encode_fns, 0, 0 },
56fb3749 10502 { "ldpte", ICLASS_xt_iclass_ldpte,
074f5109
BW		 10503 0,
10504 Opcode_ldpte_encode_fns, 0, 0 },
56fb3749 10505 { "hwwitlba", ICLASS_xt_iclass_hwwitlba,
074f5109
BW		 10506 XTENSA_OPCODE_IS_BRANCH,
10507 Opcode_hwwitlba_encode_fns, 0, 0 },
56fb3749 10508 { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba,
074f5109
BW		 10509 0,
10510 Opcode_hwwdtlba_encode_fns, 0, 0 },
56fb3749 10511 { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable,
33430bd0
BW		 10512 0,
10513 Opcode_rsr_cpenable_encode_fns, 0, 0 },
56fb3749 10514 { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable,
33430bd0
BW		 10515 0,
10516 Opcode_wsr_cpenable_encode_fns, 0, 0 },
56fb3749 10517 { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable,
33430bd0
BW		 10518 0,
10519 Opcode_xsr_cpenable_encode_fns, 0, 0 },
56fb3749 10520 { "clamps", ICLASS_xt_iclass_clamp,
33430bd0
BW		 10521 0,
10522 Opcode_clamps_encode_fns, 0, 0 },
56fb3749 10523 { "min", ICLASS_xt_iclass_minmax,
33430bd0
BW		 10524 0,
10525 Opcode_min_encode_fns, 0, 0 },
56fb3749 10526 { "max", ICLASS_xt_iclass_minmax,
33430bd0
BW		 10527 0,
10528 Opcode_max_encode_fns, 0, 0 },
56fb3749 10529 { "minu", ICLASS_xt_iclass_minmax,
33430bd0
BW		 10530 0,
10531 Opcode_minu_encode_fns, 0, 0 },
56fb3749 10532 { "maxu", ICLASS_xt_iclass_minmax,
33430bd0
BW		 10533 0,
10534 Opcode_maxu_encode_fns, 0, 0 },
56fb3749 10535 { "nsa", ICLASS_xt_iclass_nsa,
43cd72b9
BW		 10536 0,
10537 Opcode_nsa_encode_fns, 0, 0 },
56fb3749 10538 { "nsau", ICLASS_xt_iclass_nsa,
43cd72b9 10539 0,
33430bd0 10540 Opcode_nsau_encode_fns, 0, 0 },
56fb3749 10541 { "sext", ICLASS_xt_iclass_sx,
33430bd0
BW		 10542 0,
10543 Opcode_sext_encode_fns, 0, 0 },
56fb3749 10544 { "l32ai", ICLASS_xt_iclass_l32ai,
33430bd0
BW		 10545 0,
10546 Opcode_l32ai_encode_fns, 0, 0 },
56fb3749 10547 { "s32ri", ICLASS_xt_iclass_s32ri,
33430bd0
BW		 10548 0,
10549 Opcode_s32ri_encode_fns, 0, 0 },
56fb3749 10550 { "s32c1i", ICLASS_xt_iclass_s32c1i,
33430bd0
BW		 10551 0,
10552 Opcode_s32c1i_encode_fns, 0, 0 },
56fb3749 10553 { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
33430bd0
BW		 10554 0,
10555 Opcode_rsr_scompare1_encode_fns, 0, 0 },
56fb3749 10556 { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
33430bd0
BW		 10557 0,
10558 Opcode_wsr_scompare1_encode_fns, 0, 0 },
56fb3749 10559 { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
33430bd0
BW		 10560 0,
10561 Opcode_xsr_scompare1_encode_fns, 0, 0 },
56fb3749 10562 { "quou", ICLASS_xt_iclass_div,
33430bd0
BW		 10563 0,
10564 Opcode_quou_encode_fns, 0, 0 },
56fb3749 10565 { "quos", ICLASS_xt_iclass_div,
33430bd0
BW		 10566 0,
10567 Opcode_quos_encode_fns, 0, 0 },
56fb3749 10568 { "remu", ICLASS_xt_iclass_div,
33430bd0
BW		 10569 0,
10570 Opcode_remu_encode_fns, 0, 0 },
56fb3749 10571 { "rems", ICLASS_xt_iclass_div,
33430bd0
BW		 10572 0,
10573 Opcode_rems_encode_fns, 0, 0 },
56fb3749 10574 { "mull", ICLASS_xt_mul32,
33430bd0
BW		 10575 0,
10576 Opcode_mull_encode_fns, 0, 0 }
43cd72b9
BW		 10577};
10578
56fb3749
SA		 10579enum xtensa_opcode_id {
10580 OPCODE_EXCW,
10581 OPCODE_RFE,
10582 OPCODE_RFDE,
10583 OPCODE_SYSCALL,
10584 OPCODE_SIMCALL,
10585 OPCODE_CALL12,
10586 OPCODE_CALL8,
10587 OPCODE_CALL4,
10588 OPCODE_CALLX12,
10589 OPCODE_CALLX8,
10590 OPCODE_CALLX4,
10591 OPCODE_ENTRY,
10592 OPCODE_MOVSP,
10593 OPCODE_ROTW,
10594 OPCODE_RETW,
10595 OPCODE_RETW_N,
10596 OPCODE_RFWO,
10597 OPCODE_RFWU,
10598 OPCODE_L32E,
10599 OPCODE_S32E,
10600 OPCODE_RSR_WINDOWBASE,
10601 OPCODE_WSR_WINDOWBASE,
10602 OPCODE_XSR_WINDOWBASE,
10603 OPCODE_RSR_WINDOWSTART,
10604 OPCODE_WSR_WINDOWSTART,
10605 OPCODE_XSR_WINDOWSTART,
10606 OPCODE_ADD_N,
10607 OPCODE_ADDI_N,
10608 OPCODE_BEQZ_N,
10609 OPCODE_BNEZ_N,
10610 OPCODE_ILL_N,
10611 OPCODE_L32I_N,
10612 OPCODE_MOV_N,
10613 OPCODE_MOVI_N,
10614 OPCODE_NOP_N,
10615 OPCODE_RET_N,
10616 OPCODE_S32I_N,
10617 OPCODE_RUR_THREADPTR,
10618 OPCODE_WUR_THREADPTR,
10619 OPCODE_ADDI,
10620 OPCODE_ADDMI,
10621 OPCODE_ADD,
10622 OPCODE_SUB,
10623 OPCODE_ADDX2,
10624 OPCODE_ADDX4,
10625 OPCODE_ADDX8,
10626 OPCODE_SUBX2,
10627 OPCODE_SUBX4,
10628 OPCODE_SUBX8,
10629 OPCODE_AND,
10630 OPCODE_OR,
10631 OPCODE_XOR,
10632 OPCODE_BEQI,
10633 OPCODE_BNEI,
10634 OPCODE_BGEI,
10635 OPCODE_BLTI,
10636 OPCODE_BBCI,
10637 OPCODE_BBSI,
10638 OPCODE_BGEUI,
10639 OPCODE_BLTUI,
10640 OPCODE_BEQ,
10641 OPCODE_BNE,
10642 OPCODE_BGE,
10643 OPCODE_BLT,
10644 OPCODE_BGEU,
10645 OPCODE_BLTU,
10646 OPCODE_BANY,
10647 OPCODE_BNONE,
10648 OPCODE_BALL,
10649 OPCODE_BNALL,
10650 OPCODE_BBC,
10651 OPCODE_BBS,
10652 OPCODE_BEQZ,
10653 OPCODE_BNEZ,
10654 OPCODE_BGEZ,
10655 OPCODE_BLTZ,
10656 OPCODE_CALL0,
10657 OPCODE_CALLX0,
10658 OPCODE_EXTUI,
10659 OPCODE_ILL,
10660 OPCODE_J,
10661 OPCODE_JX,
10662 OPCODE_L16UI,
10663 OPCODE_L16SI,
10664 OPCODE_L32I,
10665 OPCODE_L32R,
10666 OPCODE_L8UI,
10667 OPCODE_LOOP,
10668 OPCODE_LOOPNEZ,
10669 OPCODE_LOOPGTZ,
10670 OPCODE_MOVI,
10671 OPCODE_MOVEQZ,
10672 OPCODE_MOVNEZ,
10673 OPCODE_MOVLTZ,
10674 OPCODE_MOVGEZ,
10675 OPCODE_NEG,
10676 OPCODE_ABS,
10677 OPCODE_NOP,
10678 OPCODE_RET,
10679 OPCODE_S16I,
10680 OPCODE_S32I,
10681 OPCODE_S8I,
10682 OPCODE_SSR,
10683 OPCODE_SSL,
10684 OPCODE_SSA8L,
10685 OPCODE_SSA8B,
10686 OPCODE_SSAI,
10687 OPCODE_SLL,
10688 OPCODE_SRC,
10689 OPCODE_SRL,
10690 OPCODE_SRA,
10691 OPCODE_SLLI,
10692 OPCODE_SRAI,
10693 OPCODE_SRLI,
10694 OPCODE_MEMW,
10695 OPCODE_EXTW,
10696 OPCODE_ISYNC,
10697 OPCODE_RSYNC,
10698 OPCODE_ESYNC,
10699 OPCODE_DSYNC,
10700 OPCODE_RSIL,
10701 OPCODE_RSR_LEND,
10702 OPCODE_WSR_LEND,
10703 OPCODE_XSR_LEND,
10704 OPCODE_RSR_LCOUNT,
10705 OPCODE_WSR_LCOUNT,
10706 OPCODE_XSR_LCOUNT,
10707 OPCODE_RSR_LBEG,
10708 OPCODE_WSR_LBEG,
10709 OPCODE_XSR_LBEG,
10710 OPCODE_RSR_SAR,
10711 OPCODE_WSR_SAR,
10712 OPCODE_XSR_SAR,
10713 OPCODE_RSR_LITBASE,
10714 OPCODE_WSR_LITBASE,
10715 OPCODE_XSR_LITBASE,
10716 OPCODE_RSR_176,
10717 OPCODE_WSR_176,
10718 OPCODE_RSR_208,
10719 OPCODE_RSR_PS,
10720 OPCODE_WSR_PS,
10721 OPCODE_XSR_PS,
10722 OPCODE_RSR_EPC1,
10723 OPCODE_WSR_EPC1,
10724 OPCODE_XSR_EPC1,
10725 OPCODE_RSR_EXCSAVE1,
10726 OPCODE_WSR_EXCSAVE1,
10727 OPCODE_XSR_EXCSAVE1,
10728 OPCODE_RSR_EPC2,
10729 OPCODE_WSR_EPC2,
10730 OPCODE_XSR_EPC2,
10731 OPCODE_RSR_EXCSAVE2,
10732 OPCODE_WSR_EXCSAVE2,
10733 OPCODE_XSR_EXCSAVE2,
10734 OPCODE_RSR_EPC3,
10735 OPCODE_WSR_EPC3,
10736 OPCODE_XSR_EPC3,
10737 OPCODE_RSR_EXCSAVE3,
10738 OPCODE_WSR_EXCSAVE3,
10739 OPCODE_XSR_EXCSAVE3,
10740 OPCODE_RSR_EPC4,
10741 OPCODE_WSR_EPC4,
10742 OPCODE_XSR_EPC4,
10743 OPCODE_RSR_EXCSAVE4,
10744 OPCODE_WSR_EXCSAVE4,
10745 OPCODE_XSR_EXCSAVE4,
10746 OPCODE_RSR_EPC5,
10747 OPCODE_WSR_EPC5,
10748 OPCODE_XSR_EPC5,
10749 OPCODE_RSR_EXCSAVE5,
10750 OPCODE_WSR_EXCSAVE5,
10751 OPCODE_XSR_EXCSAVE5,
10752 OPCODE_RSR_EPC6,
10753 OPCODE_WSR_EPC6,
10754 OPCODE_XSR_EPC6,
10755 OPCODE_RSR_EXCSAVE6,
10756 OPCODE_WSR_EXCSAVE6,
10757 OPCODE_XSR_EXCSAVE6,
10758 OPCODE_RSR_EPC7,
10759 OPCODE_WSR_EPC7,
10760 OPCODE_XSR_EPC7,
10761 OPCODE_RSR_EXCSAVE7,
10762 OPCODE_WSR_EXCSAVE7,
10763 OPCODE_XSR_EXCSAVE7,
10764 OPCODE_RSR_EPS2,
10765 OPCODE_WSR_EPS2,
10766 OPCODE_XSR_EPS2,
10767 OPCODE_RSR_EPS3,
10768 OPCODE_WSR_EPS3,
10769 OPCODE_XSR_EPS3,
10770 OPCODE_RSR_EPS4,
10771 OPCODE_WSR_EPS4,
10772 OPCODE_XSR_EPS4,
10773 OPCODE_RSR_EPS5,
10774 OPCODE_WSR_EPS5,
10775 OPCODE_XSR_EPS5,
10776 OPCODE_RSR_EPS6,
10777 OPCODE_WSR_EPS6,
10778 OPCODE_XSR_EPS6,
10779 OPCODE_RSR_EPS7,
10780 OPCODE_WSR_EPS7,
10781 OPCODE_XSR_EPS7,
10782 OPCODE_RSR_EXCVADDR,
10783 OPCODE_WSR_EXCVADDR,
10784 OPCODE_XSR_EXCVADDR,
10785 OPCODE_RSR_DEPC,
10786 OPCODE_WSR_DEPC,
10787 OPCODE_XSR_DEPC,
10788 OPCODE_RSR_EXCCAUSE,
10789 OPCODE_WSR_EXCCAUSE,
10790 OPCODE_XSR_EXCCAUSE,
10791 OPCODE_RSR_MISC0,
10792 OPCODE_WSR_MISC0,
10793 OPCODE_XSR_MISC0,
10794 OPCODE_RSR_MISC1,
10795 OPCODE_WSR_MISC1,
10796 OPCODE_XSR_MISC1,
10797 OPCODE_RSR_PRID,
10798 OPCODE_RSR_VECBASE,
10799 OPCODE_WSR_VECBASE,
10800 OPCODE_XSR_VECBASE,
10801 OPCODE_MUL16U,
10802 OPCODE_MUL16S,
10803 OPCODE_RFI,
10804 OPCODE_WAITI,
10805 OPCODE_RSR_INTERRUPT,
10806 OPCODE_WSR_INTSET,
10807 OPCODE_WSR_INTCLEAR,
10808 OPCODE_RSR_INTENABLE,
10809 OPCODE_WSR_INTENABLE,
10810 OPCODE_XSR_INTENABLE,
10811 OPCODE_BREAK,
10812 OPCODE_BREAK_N,
10813 OPCODE_RSR_DBREAKA0,
10814 OPCODE_WSR_DBREAKA0,
10815 OPCODE_XSR_DBREAKA0,
10816 OPCODE_RSR_DBREAKC0,
10817 OPCODE_WSR_DBREAKC0,
10818 OPCODE_XSR_DBREAKC0,
10819 OPCODE_RSR_DBREAKA1,
10820 OPCODE_WSR_DBREAKA1,
10821 OPCODE_XSR_DBREAKA1,
10822 OPCODE_RSR_DBREAKC1,
10823 OPCODE_WSR_DBREAKC1,
10824 OPCODE_XSR_DBREAKC1,
10825 OPCODE_RSR_IBREAKA0,
10826 OPCODE_WSR_IBREAKA0,
10827 OPCODE_XSR_IBREAKA0,
10828 OPCODE_RSR_IBREAKA1,
10829 OPCODE_WSR_IBREAKA1,
10830 OPCODE_XSR_IBREAKA1,
10831 OPCODE_RSR_IBREAKENABLE,
10832 OPCODE_WSR_IBREAKENABLE,
10833 OPCODE_XSR_IBREAKENABLE,
10834 OPCODE_RSR_DEBUGCAUSE,
10835 OPCODE_WSR_DEBUGCAUSE,
10836 OPCODE_XSR_DEBUGCAUSE,
10837 OPCODE_RSR_ICOUNT,
10838 OPCODE_WSR_ICOUNT,
10839 OPCODE_XSR_ICOUNT,
10840 OPCODE_RSR_ICOUNTLEVEL,
10841 OPCODE_WSR_ICOUNTLEVEL,
10842 OPCODE_XSR_ICOUNTLEVEL,
10843 OPCODE_RSR_DDR,
10844 OPCODE_WSR_DDR,
10845 OPCODE_XSR_DDR,
10846 OPCODE_RFDO,
10847 OPCODE_RFDD,
10848 OPCODE_WSR_MMID,
10849 OPCODE_RSR_CCOUNT,
10850 OPCODE_WSR_CCOUNT,
10851 OPCODE_XSR_CCOUNT,
10852 OPCODE_RSR_CCOMPARE0,
10853 OPCODE_WSR_CCOMPARE0,
10854 OPCODE_XSR_CCOMPARE0,
10855 OPCODE_RSR_CCOMPARE1,
10856 OPCODE_WSR_CCOMPARE1,
10857 OPCODE_XSR_CCOMPARE1,
10858 OPCODE_RSR_CCOMPARE2,
10859 OPCODE_WSR_CCOMPARE2,
10860 OPCODE_XSR_CCOMPARE2,
10861 OPCODE_IPF,
10862 OPCODE_IHI,
10863 OPCODE_IPFL,
10864 OPCODE_IHU,
10865 OPCODE_IIU,
10866 OPCODE_III,
10867 OPCODE_LICT,
10868 OPCODE_LICW,
10869 OPCODE_SICT,
10870 OPCODE_SICW,
10871 OPCODE_DHWB,
10872 OPCODE_DHWBI,
10873 OPCODE_DIWB,
10874 OPCODE_DIWBI,
10875 OPCODE_DHI,
10876 OPCODE_DII,
10877 OPCODE_DPFR,
10878 OPCODE_DPFW,
10879 OPCODE_DPFRO,
10880 OPCODE_DPFWO,
10881 OPCODE_DPFL,
10882 OPCODE_DHU,
10883 OPCODE_DIU,
10884 OPCODE_SDCT,
10885 OPCODE_LDCT,
10886 OPCODE_WSR_PTEVADDR,
10887 OPCODE_RSR_PTEVADDR,
10888 OPCODE_XSR_PTEVADDR,
10889 OPCODE_RSR_RASID,
10890 OPCODE_WSR_RASID,
10891 OPCODE_XSR_RASID,
10892 OPCODE_RSR_ITLBCFG,
10893 OPCODE_WSR_ITLBCFG,
10894 OPCODE_XSR_ITLBCFG,
10895 OPCODE_RSR_DTLBCFG,
10896 OPCODE_WSR_DTLBCFG,
10897 OPCODE_XSR_DTLBCFG,
10898 OPCODE_IDTLB,
10899 OPCODE_PDTLB,
10900 OPCODE_RDTLB0,
10901 OPCODE_RDTLB1,
10902 OPCODE_WDTLB,
10903 OPCODE_IITLB,
10904 OPCODE_PITLB,
10905 OPCODE_RITLB0,
10906 OPCODE_RITLB1,
10907 OPCODE_WITLB,
10908 OPCODE_LDPTE,
10909 OPCODE_HWWITLBA,
10910 OPCODE_HWWDTLBA,
10911 OPCODE_RSR_CPENABLE,
10912 OPCODE_WSR_CPENABLE,
10913 OPCODE_XSR_CPENABLE,
10914 OPCODE_CLAMPS,
10915 OPCODE_MIN,
10916 OPCODE_MAX,
10917 OPCODE_MINU,
10918 OPCODE_MAXU,
10919 OPCODE_NSA,
10920 OPCODE_NSAU,
10921 OPCODE_SEXT,
10922 OPCODE_L32AI,
10923 OPCODE_S32RI,
10924 OPCODE_S32C1I,
10925 OPCODE_RSR_SCOMPARE1,
10926 OPCODE_WSR_SCOMPARE1,
10927 OPCODE_XSR_SCOMPARE1,
10928 OPCODE_QUOU,
10929 OPCODE_QUOS,
10930 OPCODE_REMU,
10931 OPCODE_REMS,
10932 OPCODE_MULL
10933};
10934
43cd72b9
BW		 10935\f
10936/* Slot-specific opcode decode functions. */
10937
10938static int
10939Slot_inst_decode (const xtensa_insnbuf insn)
10940{
10941 switch (Field_op0_Slot_inst_get (insn))
10942 {
10943 case 0:
10944 switch (Field_op1_Slot_inst_get (insn))
10945 {
10946 case 0:
10947 switch (Field_op2_Slot_inst_get (insn))
10948 {
10949 case 0:
10950 switch (Field_r_Slot_inst_get (insn))
10951 {
10952 case 0:
10953 switch (Field_m_Slot_inst_get (insn))
10954 {
10955 case 0:
074f5109
BW		 10956 if (Field_s_Slot_inst_get (insn) == 0 &&
10957 Field_n_Slot_inst_get (insn) == 0)
56fb3749 10958 return OPCODE_ILL;
074f5109 10959 break;
43cd72b9
BW		 10960 case 2:
10961 switch (Field_n_Slot_inst_get (insn))
10962 {
10963 case 0:
56fb3749 10964 return OPCODE_RET;
43cd72b9 10965 case 1:
56fb3749 10966 return OPCODE_RETW;
43cd72b9 10967 case 2:
56fb3749 10968 return OPCODE_JX;
43cd72b9
BW		 10969 }
10970 break;
10971 case 3:
10972 switch (Field_n_Slot_inst_get (insn))
10973 {
10974 case 0:
56fb3749 10975 return OPCODE_CALLX0;
43cd72b9 10976 case 1:
56fb3749 10977 return OPCODE_CALLX4;
43cd72b9 10978 case 2:
56fb3749 10979 return OPCODE_CALLX8;
43cd72b9 10980 case 3:
56fb3749 10981 return OPCODE_CALLX12;
43cd72b9
BW		 10982 }
10983 break;
10984 }
10985 break;
10986 case 1:
56fb3749 10987 return OPCODE_MOVSP;
43cd72b9
BW		 10988 case 2:
10989 if (Field_s_Slot_inst_get (insn) == 0)
10990 {
10991 switch (Field_t_Slot_inst_get (insn))
10992 {
10993 case 0:
56fb3749 10994 return OPCODE_ISYNC;
43cd72b9 10995 case 1:
56fb3749 10996 return OPCODE_RSYNC;
43cd72b9 10997 case 2:
56fb3749 10998 return OPCODE_ESYNC;
43cd72b9 10999 case 3:
56fb3749 11000 return OPCODE_DSYNC;
43cd72b9 11001 case 8:
56fb3749 11002 return OPCODE_EXCW;
43cd72b9 11003 case 12:
56fb3749 11004 return OPCODE_MEMW;
43cd72b9 11005 case 13:
56fb3749 11006 return OPCODE_EXTW;
43cd72b9 11007 case 15:
56fb3749 11008 return OPCODE_NOP;
43cd72b9
BW		 11009 }
11010 }
11011 break;
11012 case 3:
11013 switch (Field_t_Slot_inst_get (insn))
11014 {
11015 case 0:
11016 switch (Field_s_Slot_inst_get (insn))
11017 {
11018 case 0:
56fb3749 11019 return OPCODE_RFE;
43cd72b9 11020 case 2:
56fb3749 11021 return OPCODE_RFDE;
43cd72b9 11022 case 4:
56fb3749 11023 return OPCODE_RFWO;
43cd72b9 11024 case 5:
56fb3749 11025 return OPCODE_RFWU;
43cd72b9
BW		 11026 }
11027 break;
11028 case 1:
56fb3749 11029 return OPCODE_RFI;
43cd72b9
BW		 11030 }
11031 break;
11032 case 4:
56fb3749 11033 return OPCODE_BREAK;
43cd72b9
BW		 11034 case 5:
11035 switch (Field_s_Slot_inst_get (insn))
11036 {
11037 case 0:
11038 if (Field_t_Slot_inst_get (insn) == 0)
56fb3749 11039 return OPCODE_SYSCALL;
43cd72b9
BW		 11040 break;
11041 case 1:
11042 if (Field_t_Slot_inst_get (insn) == 0)
56fb3749 11043 return OPCODE_SIMCALL;
43cd72b9
BW		 11044 break;
11045 }
11046 break;
11047 case 6:
56fb3749 11048 return OPCODE_RSIL;
43cd72b9
BW		 11049 case 7:
11050 if (Field_t_Slot_inst_get (insn) == 0)
56fb3749 11051 return OPCODE_WAITI;
43cd72b9
BW		 11052 break;
11053 }
11054 break;
11055 case 1:
56fb3749 11056 return OPCODE_AND;
43cd72b9 11057 case 2:
56fb3749 11058 return OPCODE_OR;
43cd72b9 11059 case 3:
56fb3749 11060 return OPCODE_XOR;
43cd72b9
BW		 11061 case 4:
11062 switch (Field_r_Slot_inst_get (insn))
11063 {
11064 case 0:
11065 if (Field_t_Slot_inst_get (insn) == 0)
56fb3749 11066 return OPCODE_SSR;
43cd72b9
BW		 11067 break;
11068 case 1:
11069 if (Field_t_Slot_inst_get (insn) == 0)
56fb3749 11070 return OPCODE_SSL;
43cd72b9
BW		 11071 break;
11072 case 2:
11073 if (Field_t_Slot_inst_get (insn) == 0)
56fb3749 11074 return OPCODE_SSA8L;
43cd72b9
BW		 11075 break;
11076 case 3:
11077 if (Field_t_Slot_inst_get (insn) == 0)
56fb3749 11078 return OPCODE_SSA8B;
43cd72b9
BW		 11079 break;
11080 case 4:
11081 if (Field_thi3_Slot_inst_get (insn) == 0)
56fb3749 11082 return OPCODE_SSAI;
43cd72b9
BW		 11083 break;
11084 case 8:
11085 if (Field_s_Slot_inst_get (insn) == 0)
56fb3749 11086 return OPCODE_ROTW;
43cd72b9
BW		 11087 break;
11088 case 14:
56fb3749 11089 return OPCODE_NSA;
43cd72b9 11090 case 15:
56fb3749 11091 return OPCODE_NSAU;
43cd72b9
BW		 11092 }
11093 break;
11094 case 5:
11095 switch (Field_r_Slot_inst_get (insn))
11096 {
074f5109 11097 case 1:
56fb3749 11098 return OPCODE_HWWITLBA;
43cd72b9 11099 case 3:
56fb3749 11100 return OPCODE_RITLB0;
43cd72b9 11101 case 4:
074f5109 11102 if (Field_t_Slot_inst_get (insn) == 0)
56fb3749 11103 return OPCODE_IITLB;
074f5109 11104 break;
43cd72b9 11105 case 5:
56fb3749 11106 return OPCODE_PITLB;
43cd72b9 11107 case 6:
56fb3749 11108 return OPCODE_WITLB;
43cd72b9 11109 case 7:
56fb3749 11110 return OPCODE_RITLB1;
074f5109 11111 case 9:
56fb3749 11112 return OPCODE_HWWDTLBA;
43cd72b9 11113 case 11:
56fb3749 11114 return OPCODE_RDTLB0;
43cd72b9 11115 case 12:
074f5109 11116 if (Field_t_Slot_inst_get (insn) == 0)
56fb3749 11117 return OPCODE_IDTLB;
074f5109 11118 break;
43cd72b9 11119 case 13:
56fb3749 11120 return OPCODE_PDTLB;
43cd72b9 11121 case 14:
56fb3749 11122 return OPCODE_WDTLB;
43cd72b9 11123 case 15:
56fb3749 11124 return OPCODE_RDTLB1;
43cd72b9
BW		 11125 }
11126 break;
11127 case 6:
11128 switch (Field_s_Slot_inst_get (insn))
11129 {
11130 case 0:
56fb3749 11131 return OPCODE_NEG;
43cd72b9 11132 case 1:
56fb3749 11133 return OPCODE_ABS;
43cd72b9
BW		 11134 }
11135 break;
11136 case 8:
56fb3749 11137 return OPCODE_ADD;
43cd72b9 11138 case 9:
56fb3749 11139 return OPCODE_ADDX2;
43cd72b9 11140 case 10:
56fb3749 11141 return OPCODE_ADDX4;
43cd72b9 11142 case 11:
56fb3749 11143 return OPCODE_ADDX8;
43cd72b9 11144 case 12:
56fb3749 11145 return OPCODE_SUB;
43cd72b9 11146 case 13:
56fb3749 11147 return OPCODE_SUBX2;
43cd72b9 11148 case 14:
56fb3749 11149 return OPCODE_SUBX4;
43cd72b9 11150 case 15:
56fb3749 11151 return OPCODE_SUBX8;
43cd72b9
BW		 11152 }
11153 break;
11154 case 1:
11155 switch (Field_op2_Slot_inst_get (insn))
11156 {
11157 case 0:
11158 case 1:
56fb3749 11159 return OPCODE_SLLI;
43cd72b9
BW		 11160 case 2:
11161 case 3:
56fb3749 11162 return OPCODE_SRAI;
43cd72b9 11163 case 4:
56fb3749 11164 return OPCODE_SRLI;
43cd72b9
BW		 11165 case 6:
11166 switch (Field_sr_Slot_inst_get (insn))
11167 {
11168 case 0:
56fb3749 11169 return OPCODE_XSR_LBEG;
43cd72b9 11170 case 1:
56fb3749 11171 return OPCODE_XSR_LEND;
43cd72b9 11172 case 2:
56fb3749 11173 return OPCODE_XSR_LCOUNT;
43cd72b9 11174 case 3:
56fb3749 11175 return OPCODE_XSR_SAR;
43cd72b9 11176 case 5:
56fb3749 11177 return OPCODE_XSR_LITBASE;
33430bd0 11178 case 12:
56fb3749 11179 return OPCODE_XSR_SCOMPARE1;
43cd72b9 11180 case 72:
56fb3749 11181 return OPCODE_XSR_WINDOWBASE;
43cd72b9 11182 case 73:
56fb3749 11183 return OPCODE_XSR_WINDOWSTART;
074f5109 11184 case 83:
56fb3749 11185 return OPCODE_XSR_PTEVADDR;
074f5109 11186 case 90:
56fb3749 11187 return OPCODE_XSR_RASID;
074f5109 11188 case 91:
56fb3749 11189 return OPCODE_XSR_ITLBCFG;
074f5109 11190 case 92:
56fb3749 11191 return OPCODE_XSR_DTLBCFG;
43cd72b9 11192 case 96:
56fb3749 11193 return OPCODE_XSR_IBREAKENABLE;
43cd72b9 11194 case 104:
56fb3749 11195 return OPCODE_XSR_DDR;
43cd72b9 11196 case 128:
56fb3749 11197 return OPCODE_XSR_IBREAKA0;
43cd72b9 11198 case 129:
56fb3749 11199 return OPCODE_XSR_IBREAKA1;
43cd72b9 11200 case 144:
56fb3749 11201 return OPCODE_XSR_DBREAKA0;
43cd72b9 11202 case 145:
56fb3749 11203 return OPCODE_XSR_DBREAKA1;
43cd72b9 11204 case 160:
56fb3749 11205 return OPCODE_XSR_DBREAKC0;
43cd72b9 11206 case 161:
56fb3749 11207 return OPCODE_XSR_DBREAKC1;
43cd72b9 11208 case 177:
56fb3749 11209 return OPCODE_XSR_EPC1;
43cd72b9 11210 case 178:
56fb3749 11211 return OPCODE_XSR_EPC2;
43cd72b9 11212 case 179:
56fb3749 11213 return OPCODE_XSR_EPC3;
43cd72b9 11214 case 180:
56fb3749 11215 return OPCODE_XSR_EPC4;
33430bd0 11216 case 181:
56fb3749 11217 return OPCODE_XSR_EPC5;
33430bd0 11218 case 182:
56fb3749 11219 return OPCODE_XSR_EPC6;
33430bd0 11220 case 183:
56fb3749 11221 return OPCODE_XSR_EPC7;
43cd72b9 11222 case 192:
56fb3749 11223 return OPCODE_XSR_DEPC;
43cd72b9 11224 case 194:
56fb3749 11225 return OPCODE_XSR_EPS2;
43cd72b9 11226 case 195:
56fb3749 11227 return OPCODE_XSR_EPS3;
43cd72b9 11228 case 196:
56fb3749 11229 return OPCODE_XSR_EPS4;
33430bd0 11230 case 197:
56fb3749 11231 return OPCODE_XSR_EPS5;
33430bd0 11232 case 198:
56fb3749 11233 return OPCODE_XSR_EPS6;
33430bd0 11234 case 199:
56fb3749 11235 return OPCODE_XSR_EPS7;
43cd72b9 11236 case 209:
56fb3749 11237 return OPCODE_XSR_EXCSAVE1;
43cd72b9 11238 case 210:
56fb3749 11239 return OPCODE_XSR_EXCSAVE2;
43cd72b9 11240 case 211:
56fb3749 11241 return OPCODE_XSR_EXCSAVE3;
43cd72b9 11242 case 212:
56fb3749 11243 return OPCODE_XSR_EXCSAVE4;
33430bd0 11244 case 213:
56fb3749 11245 return OPCODE_XSR_EXCSAVE5;
33430bd0 11246 case 214:
56fb3749 11247 return OPCODE_XSR_EXCSAVE6;
33430bd0 11248 case 215:
56fb3749 11249 return OPCODE_XSR_EXCSAVE7;
33430bd0 11250 case 224:
56fb3749 11251 return OPCODE_XSR_CPENABLE;
43cd72b9 11252 case 228:
56fb3749 11253 return OPCODE_XSR_INTENABLE;
43cd72b9 11254 case 230:
56fb3749 11255 return OPCODE_XSR_PS;
33430bd0 11256 case 231:
56fb3749 11257 return OPCODE_XSR_VECBASE;
43cd72b9 11258 case 232:
56fb3749 11259 return OPCODE_XSR_EXCCAUSE;
43cd72b9 11260 case 233:
56fb3749 11261 return OPCODE_XSR_DEBUGCAUSE;
43cd72b9 11262 case 234:
56fb3749 11263 return OPCODE_XSR_CCOUNT;
43cd72b9 11264 case 236:
56fb3749 11265 return OPCODE_XSR_ICOUNT;
43cd72b9 11266 case 237:
56fb3749 11267 return OPCODE_XSR_ICOUNTLEVEL;
43cd72b9 11268 case 238:
56fb3749 11269 return OPCODE_XSR_EXCVADDR;
43cd72b9 11270 case 240:
56fb3749 11271 return OPCODE_XSR_CCOMPARE0;
43cd72b9 11272 case 241:
56fb3749 11273 return OPCODE_XSR_CCOMPARE1;
43cd72b9 11274 case 242:
56fb3749 11275 return OPCODE_XSR_CCOMPARE2;
43cd72b9 11276 case 244:
56fb3749 11277 return OPCODE_XSR_MISC0;
43cd72b9 11278 case 245:
56fb3749 11279 return OPCODE_XSR_MISC1;
43cd72b9
BW		 11280 }
11281 break;
11282 case 8:
56fb3749 11283 return OPCODE_SRC;
43cd72b9
BW		 11284 case 9:
11285 if (Field_s_Slot_inst_get (insn) == 0)
56fb3749 11286 return OPCODE_SRL;
43cd72b9
BW		 11287 break;
11288 case 10:
11289 if (Field_t_Slot_inst_get (insn) == 0)
56fb3749 11290 return OPCODE_SLL;
43cd72b9
BW		 11291 break;
11292 case 11:
11293 if (Field_s_Slot_inst_get (insn) == 0)
56fb3749 11294 return OPCODE_SRA;
43cd72b9 11295 break;
33430bd0 11296 case 12:
56fb3749 11297 return OPCODE_MUL16U;
33430bd0 11298 case 13:
56fb3749 11299 return OPCODE_MUL16S;
43cd72b9
BW		 11300 case 15:
11301 switch (Field_r_Slot_inst_get (insn))
11302 {
11303 case 0:
56fb3749 11304 return OPCODE_LICT;
43cd72b9 11305 case 1:
56fb3749 11306 return OPCODE_SICT;
43cd72b9 11307 case 2:
56fb3749 11308 return OPCODE_LICW;
43cd72b9 11309 case 3:
56fb3749 11310 return OPCODE_SICW;
43cd72b9 11311 case 8:
56fb3749 11312 return OPCODE_LDCT;
43cd72b9 11313 case 9:
56fb3749 11314 return OPCODE_SDCT;
43cd72b9 11315 case 14:
af4bed4b 11316 if (Field_t_Slot_inst_get (insn) == 0)
56fb3749 11317 return OPCODE_RFDO;
af4bed4b 11318 if (Field_t_Slot_inst_get (insn) == 1)
56fb3749 11319 return OPCODE_RFDD;
43cd72b9 11320 break;
074f5109 11321 case 15:
56fb3749 11322 return OPCODE_LDPTE;
43cd72b9
BW		 11323 }
11324 break;
11325 }
11326 break;
33430bd0
BW		 11327 case 2:
11328 switch (Field_op2_Slot_inst_get (insn))
11329 {
11330 case 8:
56fb3749 11331 return OPCODE_MULL;
33430bd0 11332 case 12:
56fb3749 11333 return OPCODE_QUOU;
33430bd0 11334 case 13:
56fb3749 11335 return OPCODE_QUOS;
33430bd0 11336 case 14:
56fb3749 11337 return OPCODE_REMU;
33430bd0 11338 case 15:
56fb3749 11339 return OPCODE_REMS;
33430bd0
BW		 11340 }
11341 break;
43cd72b9
BW		 11342 case 3:
11343 switch (Field_op2_Slot_inst_get (insn))
11344 {
11345 case 0:
11346 switch (Field_sr_Slot_inst_get (insn))
11347 {
11348 case 0:
56fb3749 11349 return OPCODE_RSR_LBEG;
43cd72b9 11350 case 1:
56fb3749 11351 return OPCODE_RSR_LEND;
43cd72b9 11352 case 2:
56fb3749 11353 return OPCODE_RSR_LCOUNT;
43cd72b9 11354 case 3:
56fb3749 11355 return OPCODE_RSR_SAR;
43cd72b9 11356 case 5:
56fb3749 11357 return OPCODE_RSR_LITBASE;
33430bd0 11358 case 12:
56fb3749 11359 return OPCODE_RSR_SCOMPARE1;
43cd72b9 11360 case 72:
56fb3749 11361 return OPCODE_RSR_WINDOWBASE;
43cd72b9 11362 case 73:
56fb3749 11363 return OPCODE_RSR_WINDOWSTART;
074f5109 11364 case 83:
56fb3749 11365 return OPCODE_RSR_PTEVADDR;
074f5109 11366 case 90:
56fb3749 11367 return OPCODE_RSR_RASID;
074f5109 11368 case 91:
56fb3749 11369 return OPCODE_RSR_ITLBCFG;
074f5109 11370 case 92:
56fb3749 11371 return OPCODE_RSR_DTLBCFG;
43cd72b9 11372 case 96:
56fb3749 11373 return OPCODE_RSR_IBREAKENABLE;
43cd72b9 11374 case 104:
56fb3749 11375 return OPCODE_RSR_DDR;
43cd72b9 11376 case 128:
56fb3749 11377 return OPCODE_RSR_IBREAKA0;
43cd72b9 11378 case 129:
56fb3749 11379 return OPCODE_RSR_IBREAKA1;
43cd72b9 11380 case 144:
56fb3749 11381 return OPCODE_RSR_DBREAKA0;
43cd72b9 11382 case 145:
56fb3749 11383 return OPCODE_RSR_DBREAKA1;
43cd72b9 11384 case 160:
56fb3749 11385 return OPCODE_RSR_DBREAKC0;
43cd72b9 11386 case 161:
56fb3749 11387 return OPCODE_RSR_DBREAKC1;
43cd72b9 11388 case 176:
56fb3749 11389 return OPCODE_RSR_176;
43cd72b9 11390 case 177:
56fb3749 11391 return OPCODE_RSR_EPC1;
43cd72b9 11392 case 178:
56fb3749 11393 return OPCODE_RSR_EPC2;
43cd72b9 11394 case 179:
56fb3749 11395 return OPCODE_RSR_EPC3;
43cd72b9 11396 case 180:
56fb3749 11397 return OPCODE_RSR_EPC4;
33430bd0 11398 case 181:
56fb3749 11399 return OPCODE_RSR_EPC5;
33430bd0 11400 case 182:
56fb3749 11401 return OPCODE_RSR_EPC6;
33430bd0 11402 case 183:
56fb3749 11403 return OPCODE_RSR_EPC7;
43cd72b9 11404 case 192:
56fb3749 11405 return OPCODE_RSR_DEPC;
43cd72b9 11406 case 194:
56fb3749 11407 return OPCODE_RSR_EPS2;
43cd72b9 11408 case 195:
56fb3749 11409 return OPCODE_RSR_EPS3;
43cd72b9 11410 case 196:
56fb3749 11411 return OPCODE_RSR_EPS4;
33430bd0 11412 case 197:
56fb3749 11413 return OPCODE_RSR_EPS5;
33430bd0 11414 case 198:
56fb3749 11415 return OPCODE_RSR_EPS6;
33430bd0 11416 case 199:
56fb3749 11417 return OPCODE_RSR_EPS7;
43cd72b9 11418 case 208:
56fb3749 11419 return OPCODE_RSR_208;
43cd72b9 11420 case 209:
56fb3749 11421 return OPCODE_RSR_EXCSAVE1;
43cd72b9 11422 case 210:
56fb3749 11423 return OPCODE_RSR_EXCSAVE2;
43cd72b9 11424 case 211:
56fb3749 11425 return OPCODE_RSR_EXCSAVE3;
43cd72b9 11426 case 212:
56fb3749 11427 return OPCODE_RSR_EXCSAVE4;
33430bd0 11428 case 213:
56fb3749 11429 return OPCODE_RSR_EXCSAVE5;
33430bd0 11430 case 214:
56fb3749 11431 return OPCODE_RSR_EXCSAVE6;
33430bd0 11432 case 215:
56fb3749 11433 return OPCODE_RSR_EXCSAVE7;
33430bd0 11434 case 224:
56fb3749 11435 return OPCODE_RSR_CPENABLE;
43cd72b9 11436 case 226:
56fb3749 11437 return OPCODE_RSR_INTERRUPT;
43cd72b9 11438 case 228:
56fb3749 11439 return OPCODE_RSR_INTENABLE;
43cd72b9 11440 case 230:
56fb3749 11441 return OPCODE_RSR_PS;
33430bd0 11442 case 231:
56fb3749 11443 return OPCODE_RSR_VECBASE;
43cd72b9 11444 case 232:
56fb3749 11445 return OPCODE_RSR_EXCCAUSE;
43cd72b9 11446 case 233:
56fb3749 11447 return OPCODE_RSR_DEBUGCAUSE;
43cd72b9 11448 case 234:
56fb3749 11449 return OPCODE_RSR_CCOUNT;
43cd72b9 11450 case 235:
56fb3749 11451 return OPCODE_RSR_PRID;
43cd72b9 11452 case 236:
56fb3749 11453 return OPCODE_RSR_ICOUNT;
43cd72b9 11454 case 237:
56fb3749 11455 return OPCODE_RSR_ICOUNTLEVEL;
43cd72b9 11456 case 238:
56fb3749 11457 return OPCODE_RSR_EXCVADDR;
43cd72b9 11458 case 240:
56fb3749 11459 return OPCODE_RSR_CCOMPARE0;
43cd72b9 11460 case 241:
56fb3749 11461 return OPCODE_RSR_CCOMPARE1;
43cd72b9 11462 case 242:
56fb3749 11463 return OPCODE_RSR_CCOMPARE2;
43cd72b9 11464 case 244:
56fb3749 11465 return OPCODE_RSR_MISC0;
43cd72b9 11466 case 245:
56fb3749 11467 return OPCODE_RSR_MISC1;
43cd72b9
BW		 11468 }
11469 break;
11470 case 1:
11471 switch (Field_sr_Slot_inst_get (insn))
11472 {
11473 case 0:
56fb3749 11474 return OPCODE_WSR_LBEG;
43cd72b9 11475 case 1:
56fb3749 11476 return OPCODE_WSR_LEND;
43cd72b9 11477 case 2:
56fb3749 11478 return OPCODE_WSR_LCOUNT;
43cd72b9 11479 case 3:
56fb3749 11480 return OPCODE_WSR_SAR;
43cd72b9 11481 case 5:
56fb3749 11482 return OPCODE_WSR_LITBASE;
33430bd0 11483 case 12:
56fb3749 11484 return OPCODE_WSR_SCOMPARE1;
43cd72b9 11485 case 72:
56fb3749 11486 return OPCODE_WSR_WINDOWBASE;
43cd72b9 11487 case 73:
56fb3749 11488 return OPCODE_WSR_WINDOWSTART;
074f5109 11489 case 83:
56fb3749 11490 return OPCODE_WSR_PTEVADDR;
33430bd0 11491 case 89:
56fb3749 11492 return OPCODE_WSR_MMID;
074f5109 11493 case 90:
56fb3749 11494 return OPCODE_WSR_RASID;
074f5109 11495 case 91:
56fb3749 11496 return OPCODE_WSR_ITLBCFG;
074f5109 11497 case 92:
56fb3749 11498 return OPCODE_WSR_DTLBCFG;
43cd72b9 11499 case 96:
56fb3749 11500 return OPCODE_WSR_IBREAKENABLE;
43cd72b9 11501 case 104:
56fb3749 11502 return OPCODE_WSR_DDR;
43cd72b9 11503 case 128:
56fb3749 11504 return OPCODE_WSR_IBREAKA0;
43cd72b9 11505 case 129:
56fb3749 11506 return OPCODE_WSR_IBREAKA1;
43cd72b9 11507 case 144:
56fb3749 11508 return OPCODE_WSR_DBREAKA0;
43cd72b9 11509 case 145:
56fb3749 11510 return OPCODE_WSR_DBREAKA1;
43cd72b9 11511 case 160:
56fb3749 11512 return OPCODE_WSR_DBREAKC0;
43cd72b9 11513 case 161:
56fb3749 11514 return OPCODE_WSR_DBREAKC1;
33430bd0 11515 case 176:
56fb3749 11516 return OPCODE_WSR_176;
43cd72b9 11517 case 177:
56fb3749 11518 return OPCODE_WSR_EPC1;
43cd72b9 11519 case 178:
56fb3749 11520 return OPCODE_WSR_EPC2;
43cd72b9 11521 case 179:
56fb3749 11522 return OPCODE_WSR_EPC3;
43cd72b9 11523 case 180:
56fb3749 11524 return OPCODE_WSR_EPC4;
33430bd0 11525 case 181:
56fb3749 11526 return OPCODE_WSR_EPC5;
33430bd0 11527 case 182:
56fb3749 11528 return OPCODE_WSR_EPC6;
33430bd0 11529 case 183:
56fb3749 11530 return OPCODE_WSR_EPC7;
43cd72b9 11531 case 192:
56fb3749 11532 return OPCODE_WSR_DEPC;
43cd72b9 11533 case 194:
56fb3749 11534 return OPCODE_WSR_EPS2;
43cd72b9 11535 case 195:
56fb3749 11536 return OPCODE_WSR_EPS3;
43cd72b9 11537 case 196:
56fb3749 11538 return OPCODE_WSR_EPS4;
33430bd0 11539 case 197:
56fb3749 11540 return OPCODE_WSR_EPS5;
33430bd0 11541 case 198:
56fb3749 11542 return OPCODE_WSR_EPS6;
33430bd0 11543 case 199:
56fb3749 11544 return OPCODE_WSR_EPS7;
43cd72b9 11545 case 209:
56fb3749 11546 return OPCODE_WSR_EXCSAVE1;
43cd72b9 11547 case 210:
56fb3749 11548 return OPCODE_WSR_EXCSAVE2;
43cd72b9 11549 case 211:
56fb3749 11550 return OPCODE_WSR_EXCSAVE3;
43cd72b9 11551 case 212:
56fb3749 11552 return OPCODE_WSR_EXCSAVE4;
33430bd0 11553 case 213:
56fb3749 11554 return OPCODE_WSR_EXCSAVE5;
33430bd0 11555 case 214:
56fb3749 11556 return OPCODE_WSR_EXCSAVE6;
33430bd0 11557 case 215:
56fb3749 11558 return OPCODE_WSR_EXCSAVE7;
33430bd0 11559 case 224:
56fb3749 11560 return OPCODE_WSR_CPENABLE;
43cd72b9 11561 case 226:
56fb3749 11562 return OPCODE_WSR_INTSET;
43cd72b9 11563 case 227:
56fb3749 11564 return OPCODE_WSR_INTCLEAR;
43cd72b9 11565 case 228:
56fb3749 11566 return OPCODE_WSR_INTENABLE;
43cd72b9 11567 case 230:
56fb3749 11568 return OPCODE_WSR_PS;
33430bd0 11569 case 231:
56fb3749 11570 return OPCODE_WSR_VECBASE;
43cd72b9 11571 case 232:
56fb3749 11572 return OPCODE_WSR_EXCCAUSE;
43cd72b9 11573 case 233:
56fb3749 11574 return OPCODE_WSR_DEBUGCAUSE;
43cd72b9 11575 case 234:
56fb3749 11576 return OPCODE_WSR_CCOUNT;
43cd72b9 11577 case 236:
56fb3749 11578 return OPCODE_WSR_ICOUNT;
43cd72b9 11579 case 237:
56fb3749 11580 return OPCODE_WSR_ICOUNTLEVEL;
43cd72b9 11581 case 238:
56fb3749 11582 return OPCODE_WSR_EXCVADDR;
43cd72b9 11583 case 240:
56fb3749 11584 return OPCODE_WSR_CCOMPARE0;
43cd72b9 11585 case 241:
56fb3749 11586 return OPCODE_WSR_CCOMPARE1;
43cd72b9 11587 case 242:
56fb3749 11588 return OPCODE_WSR_CCOMPARE2;
43cd72b9 11589 case 244:
56fb3749 11590 return OPCODE_WSR_MISC0;
43cd72b9 11591 case 245:
56fb3749 11592 return OPCODE_WSR_MISC1;
43cd72b9
BW		 11593 }
11594 break;
33430bd0 11595 case 2:
56fb3749 11596 return OPCODE_SEXT;
33430bd0 11597 case 3:
56fb3749 11598 return OPCODE_CLAMPS;
33430bd0 11599 case 4:
56fb3749 11600 return OPCODE_MIN;
33430bd0 11601 case 5:
56fb3749 11602 return OPCODE_MAX;
33430bd0 11603 case 6:
56fb3749 11604 return OPCODE_MINU;
33430bd0 11605 case 7:
56fb3749 11606 return OPCODE_MAXU;
43cd72b9 11607 case 8:
56fb3749 11608 return OPCODE_MOVEQZ;
43cd72b9 11609 case 9:
56fb3749 11610 return OPCODE_MOVNEZ;
43cd72b9 11611 case 10:
56fb3749 11612 return OPCODE_MOVLTZ;
43cd72b9 11613 case 11:
56fb3749 11614 return OPCODE_MOVGEZ;
33430bd0
BW		 11615 case 14:
11616 if (Field_st_Slot_inst_get (insn) == 231)
56fb3749 11617 return OPCODE_RUR_THREADPTR;
33430bd0
BW		 11618 break;
11619 case 15:
11620 if (Field_sr_Slot_inst_get (insn) == 231)
56fb3749 11621 return OPCODE_WUR_THREADPTR;
33430bd0 11622 break;
43cd72b9
BW		 11623 }
11624 break;
11625 case 4:
11626 case 5:
56fb3749 11627 return OPCODE_EXTUI;
43cd72b9
BW		 11628 case 9:
11629 switch (Field_op2_Slot_inst_get (insn))
11630 {
11631 case 0:
56fb3749 11632 return OPCODE_L32E;
43cd72b9 11633 case 4:
56fb3749 11634 return OPCODE_S32E;
43cd72b9
BW		 11635 }
11636 break;
11637 }
e0001a05 11638 break;
43cd72b9 11639 case 1:
56fb3749 11640 return OPCODE_L32R;
43cd72b9
BW		 11641 case 2:
11642 switch (Field_r_Slot_inst_get (insn))
11643 {
11644 case 0:
56fb3749 11645 return OPCODE_L8UI;
43cd72b9 11646 case 1:
56fb3749 11647 return OPCODE_L16UI;
43cd72b9 11648 case 2:
56fb3749 11649 return OPCODE_L32I;
43cd72b9 11650 case 4:
56fb3749 11651 return OPCODE_S8I;
43cd72b9 11652 case 5:
56fb3749 11653 return OPCODE_S16I;
43cd72b9 11654 case 6:
56fb3749 11655 return OPCODE_S32I;
43cd72b9
BW		 11656 case 7:
11657 switch (Field_t_Slot_inst_get (insn))
11658 {
11659 case 0:
56fb3749 11660 return OPCODE_DPFR;
43cd72b9 11661 case 1:
56fb3749 11662 return OPCODE_DPFW;
43cd72b9 11663 case 2:
56fb3749 11664 return OPCODE_DPFRO;
43cd72b9 11665 case 3:
56fb3749 11666 return OPCODE_DPFWO;
43cd72b9 11667 case 4:
56fb3749 11668 return OPCODE_DHWB;
43cd72b9 11669 case 5:
56fb3749 11670 return OPCODE_DHWBI;
43cd72b9 11671 case 6:
56fb3749 11672 return OPCODE_DHI;
43cd72b9 11673 case 7:
56fb3749 11674 return OPCODE_DII;
43cd72b9
BW		 11675 case 8:
11676 switch (Field_op1_Slot_inst_get (insn))
11677 {
33430bd0 11678 case 0:
56fb3749 11679 return OPCODE_DPFL;
33430bd0 11680 case 2:
56fb3749 11681 return OPCODE_DHU;
33430bd0 11682 case 3:
56fb3749 11683 return OPCODE_DIU;
43cd72b9 11684 case 4:
56fb3749 11685 return OPCODE_DIWB;
43cd72b9 11686 case 5:
56fb3749 11687 return OPCODE_DIWBI;
43cd72b9
BW		 11688 }
11689 break;
11690 case 12:
56fb3749 11691 return OPCODE_IPF;
33430bd0
BW		 11692 case 13:
11693 switch (Field_op1_Slot_inst_get (insn))
11694 {
11695 case 0:
56fb3749 11696 return OPCODE_IPFL;
33430bd0 11697 case 2:
56fb3749 11698 return OPCODE_IHU;
33430bd0 11699 case 3:
56fb3749 11700 return OPCODE_IIU;
33430bd0
BW		 11701 }
11702 break;
43cd72b9 11703 case 14:
56fb3749 11704 return OPCODE_IHI;
43cd72b9 11705 case 15:
56fb3749 11706 return OPCODE_III;
43cd72b9
BW		 11707 }
11708 break;
11709 case 9:
56fb3749 11710 return OPCODE_L16SI;
43cd72b9 11711 case 10:
56fb3749 11712 return OPCODE_MOVI;
33430bd0 11713 case 11:
56fb3749 11714 return OPCODE_L32AI;
43cd72b9 11715 case 12:
56fb3749 11716 return OPCODE_ADDI;
43cd72b9 11717 case 13:
56fb3749 11718 return OPCODE_ADDMI;
33430bd0 11719 case 14:
56fb3749 11720 return OPCODE_S32C1I;
33430bd0 11721 case 15:
56fb3749 11722 return OPCODE_S32RI;
43cd72b9 11723 }
e0001a05 11724 break;
43cd72b9
BW		 11725 case 5:
11726 switch (Field_n_Slot_inst_get (insn))
11727 {
11728 case 0:
56fb3749 11729 return OPCODE_CALL0;
43cd72b9 11730 case 1:
56fb3749 11731 return OPCODE_CALL4;
43cd72b9 11732 case 2:
56fb3749 11733 return OPCODE_CALL8;
43cd72b9 11734 case 3:
56fb3749 11735 return OPCODE_CALL12;
43cd72b9 11736 }
e0001a05 11737 break;
43cd72b9
BW		 11738 case 6:
11739 switch (Field_n_Slot_inst_get (insn))
11740 {
11741 case 0:
56fb3749 11742 return OPCODE_J;
43cd72b9
BW		 11743 case 1:
11744 switch (Field_m_Slot_inst_get (insn))
11745 {
11746 case 0:
56fb3749 11747 return OPCODE_BEQZ;
43cd72b9 11748 case 1:
56fb3749 11749 return OPCODE_BNEZ;
43cd72b9 11750 case 2:
56fb3749 11751 return OPCODE_BLTZ;
43cd72b9 11752 case 3:
56fb3749 11753 return OPCODE_BGEZ;
43cd72b9
BW		 11754 }
11755 break;
11756 case 2:
11757 switch (Field_m_Slot_inst_get (insn))
11758 {
11759 case 0:
56fb3749 11760 return OPCODE_BEQI;
43cd72b9 11761 case 1:
56fb3749 11762 return OPCODE_BNEI;
43cd72b9 11763 case 2:
56fb3749 11764 return OPCODE_BLTI;
43cd72b9 11765 case 3:
56fb3749 11766 return OPCODE_BGEI;
43cd72b9
BW		 11767 }
11768 break;
11769 case 3:
11770 switch (Field_m_Slot_inst_get (insn))
11771 {
11772 case 0:
56fb3749 11773 return OPCODE_ENTRY;
43cd72b9
BW		 11774 case 1:
11775 switch (Field_r_Slot_inst_get (insn))
11776 {
11777 case 8:
56fb3749 11778 return OPCODE_LOOP;
43cd72b9 11779 case 9:
56fb3749 11780 return OPCODE_LOOPNEZ;
43cd72b9 11781 case 10:
56fb3749 11782 return OPCODE_LOOPGTZ;
43cd72b9
BW		 11783 }
11784 break;
11785 case 2:
56fb3749 11786 return OPCODE_BLTUI;
43cd72b9 11787 case 3:
56fb3749 11788 return OPCODE_BGEUI;
43cd72b9
BW		 11789 }
11790 break;
11791 }
e0001a05 11792 break;
43cd72b9
BW		 11793 case 7:
11794 switch (Field_r_Slot_inst_get (insn))
11795 {
11796 case 0:
56fb3749 11797 return OPCODE_BNONE;
43cd72b9 11798 case 1:
56fb3749 11799 return OPCODE_BEQ;
43cd72b9 11800 case 2:
56fb3749 11801 return OPCODE_BLT;
43cd72b9 11802 case 3:
56fb3749 11803 return OPCODE_BLTU;
43cd72b9 11804 case 4:
56fb3749 11805 return OPCODE_BALL;
43cd72b9 11806 case 5:
56fb3749 11807 return OPCODE_BBC;
43cd72b9
BW		 11808 case 6:
11809 case 7:
56fb3749 11810 return OPCODE_BBCI;
43cd72b9 11811 case 8:
56fb3749 11812 return OPCODE_BANY;
43cd72b9 11813 case 9:
56fb3749 11814 return OPCODE_BNE;
43cd72b9 11815 case 10:
56fb3749 11816 return OPCODE_BGE;
43cd72b9 11817 case 11:
56fb3749 11818 return OPCODE_BGEU;
43cd72b9 11819 case 12:
56fb3749 11820 return OPCODE_BNALL;
43cd72b9 11821 case 13:
56fb3749 11822 return OPCODE_BBS;
43cd72b9
BW		 11823 case 14:
11824 case 15:
56fb3749 11825 return OPCODE_BBSI;
43cd72b9 11826 }
e0001a05 11827 break;
e0001a05 11828 }
43cd72b9
BW		 11829 return 0;
11830}
11831
11832static int
11833Slot_inst16b_decode (const xtensa_insnbuf insn)
11834{
11835 switch (Field_op0_Slot_inst16b_get (insn))
11836 {
11837 case 12:
11838 switch (Field_i_Slot_inst16b_get (insn))
11839 {
11840 case 0:
56fb3749 11841 return OPCODE_MOVI_N;
43cd72b9
BW		 11842 case 1:
11843 switch (Field_z_Slot_inst16b_get (insn))
11844 {
11845 case 0:
56fb3749 11846 return OPCODE_BEQZ_N;
43cd72b9 11847 case 1:
56fb3749 11848 return OPCODE_BNEZ_N;
43cd72b9
BW		 11849 }
11850 break;
11851 }
e0001a05 11852 break;
43cd72b9
BW		 11853 case 13:
11854 switch (Field_r_Slot_inst16b_get (insn))
11855 {
11856 case 0:
56fb3749 11857 return OPCODE_MOV_N;
43cd72b9
BW		 11858 case 15:
11859 switch (Field_t_Slot_inst16b_get (insn))
11860 {
11861 case 0:
56fb3749 11862 return OPCODE_RET_N;
43cd72b9 11863 case 1:
56fb3749 11864 return OPCODE_RETW_N;
43cd72b9 11865 case 2:
56fb3749 11866 return OPCODE_BREAK_N;
43cd72b9
BW		 11867 case 3:
11868 if (Field_s_Slot_inst16b_get (insn) == 0)
56fb3749 11869 return OPCODE_NOP_N;
43cd72b9
BW		 11870 break;
11871 case 6:
074f5109 11872 if (Field_s_Slot_inst16b_get (insn) == 0)
56fb3749 11873 return OPCODE_ILL_N;
074f5109 11874 break;
43cd72b9
BW		 11875 }
11876 break;
11877 }
e0001a05
NC		 11878 break;
11879 }
43cd72b9
BW		 11880 return 0;
11881}
11882
11883static int
11884Slot_inst16a_decode (const xtensa_insnbuf insn)
11885{
11886 switch (Field_op0_Slot_inst16a_get (insn))
11887 {
11888 case 8:
56fb3749 11889 return OPCODE_L32I_N;
43cd72b9 11890 case 9:
56fb3749 11891 return OPCODE_S32I_N;
43cd72b9 11892 case 10:
56fb3749 11893 return OPCODE_ADD_N;
43cd72b9 11894 case 11:
56fb3749 11895 return OPCODE_ADDI_N;
e0001a05 11896 }
43cd72b9
BW		 11897 return 0;
11898}
11899
11900\f
11901/* Instruction slots. */
11902
11903static void
11904Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
11905 xtensa_insnbuf slotbuf)
11906{
11907 slotbuf[0] = (insn[0] & 0xffffff);
11908}
11909
11910static void
11911Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
11912 const xtensa_insnbuf slotbuf)
11913{
11914 insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
11915}
11916
11917static void
11918Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
11919 xtensa_insnbuf slotbuf)
11920{
11921 slotbuf[0] = ((insn[0] & 0xffff00) >> 8);
11922}
11923
11924static void
11925Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
11926 const xtensa_insnbuf slotbuf)
11927{
11928 insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8);
11929}
11930
11931static void
11932Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
11933 xtensa_insnbuf slotbuf)
11934{
11935 slotbuf[0] = ((insn[0] & 0xffff00) >> 8);
11936}
11937
11938static void
11939Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
11940 const xtensa_insnbuf slotbuf)
11941{
11942 insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8);
11943}
11944
11945static xtensa_get_field_fn
11946Slot_inst_get_field_fns[] = {
11947 Field_t_Slot_inst_get,
11948 Field_bbi4_Slot_inst_get,
11949 Field_bbi_Slot_inst_get,
11950 Field_imm12_Slot_inst_get,
11951 Field_imm8_Slot_inst_get,
11952 Field_s_Slot_inst_get,
11953 Field_imm12b_Slot_inst_get,
11954 Field_imm16_Slot_inst_get,
11955 Field_m_Slot_inst_get,
11956 Field_n_Slot_inst_get,
11957 Field_offset_Slot_inst_get,
11958 Field_op0_Slot_inst_get,
11959 Field_op1_Slot_inst_get,
11960 Field_op2_Slot_inst_get,
11961 Field_r_Slot_inst_get,
11962 Field_sa4_Slot_inst_get,
11963 Field_sae4_Slot_inst_get,
11964 Field_sae_Slot_inst_get,
11965 Field_sal_Slot_inst_get,
11966 Field_sargt_Slot_inst_get,
11967 Field_sas4_Slot_inst_get,
11968 Field_sas_Slot_inst_get,
11969 Field_sr_Slot_inst_get,
11970 Field_st_Slot_inst_get,
11971 Field_thi3_Slot_inst_get,
11972 Field_imm4_Slot_inst_get,
11973 Field_mn_Slot_inst_get,
11974 0,
11975 0,
11976 0,
11977 0,
11978 0,
11979 0,
11980 0,
11981 0,
33430bd0
BW		 11982 Field_xt_wbr15_imm_Slot_inst_get,
11983 Field_xt_wbr18_imm_Slot_inst_get,
43cd72b9
BW		 11984 Implicit_Field_ar0_get,
11985 Implicit_Field_ar4_get,
11986 Implicit_Field_ar8_get,
11987 Implicit_Field_ar12_get
11988};
11989
11990static xtensa_set_field_fn
11991Slot_inst_set_field_fns[] = {
11992 Field_t_Slot_inst_set,
11993 Field_bbi4_Slot_inst_set,
11994 Field_bbi_Slot_inst_set,
11995 Field_imm12_Slot_inst_set,
11996 Field_imm8_Slot_inst_set,
11997 Field_s_Slot_inst_set,
11998 Field_imm12b_Slot_inst_set,
11999 Field_imm16_Slot_inst_set,
12000 Field_m_Slot_inst_set,
12001 Field_n_Slot_inst_set,
12002 Field_offset_Slot_inst_set,
12003 Field_op0_Slot_inst_set,
12004 Field_op1_Slot_inst_set,
12005 Field_op2_Slot_inst_set,
12006 Field_r_Slot_inst_set,
12007 Field_sa4_Slot_inst_set,
12008 Field_sae4_Slot_inst_set,
12009 Field_sae_Slot_inst_set,
12010 Field_sal_Slot_inst_set,
12011 Field_sargt_Slot_inst_set,
12012 Field_sas4_Slot_inst_set,
12013 Field_sas_Slot_inst_set,
12014 Field_sr_Slot_inst_set,
12015 Field_st_Slot_inst_set,
12016 Field_thi3_Slot_inst_set,
12017 Field_imm4_Slot_inst_set,
12018 Field_mn_Slot_inst_set,
12019 0,
12020 0,
12021 0,
12022 0,
12023 0,
12024 0,
12025 0,
12026 0,
33430bd0
BW		 12027 Field_xt_wbr15_imm_Slot_inst_set,
12028 Field_xt_wbr18_imm_Slot_inst_set,
43cd72b9
BW		 12029 Implicit_Field_set,
12030 Implicit_Field_set,
12031 Implicit_Field_set,
12032 Implicit_Field_set
12033};
12034
12035static xtensa_get_field_fn
12036Slot_inst16a_get_field_fns[] = {
12037 Field_t_Slot_inst16a_get,
12038 0,
12039 0,
12040 0,
12041 0,
12042 Field_s_Slot_inst16a_get,
12043 0,
12044 0,
12045 0,
12046 0,
12047 0,
12048 Field_op0_Slot_inst16a_get,
12049 0,
12050 0,
12051 Field_r_Slot_inst16a_get,
12052 0,
12053 0,
12054 0,
12055 0,
12056 0,
12057 0,
12058 0,
12059 Field_sr_Slot_inst16a_get,
12060 Field_st_Slot_inst16a_get,
12061 0,
12062 Field_imm4_Slot_inst16a_get,
12063 0,
12064 Field_i_Slot_inst16a_get,
12065 Field_imm6lo_Slot_inst16a_get,
12066 Field_imm6hi_Slot_inst16a_get,
12067 Field_imm7lo_Slot_inst16a_get,
12068 Field_imm7hi_Slot_inst16a_get,
12069 Field_z_Slot_inst16a_get,
12070 Field_imm6_Slot_inst16a_get,
12071 Field_imm7_Slot_inst16a_get,
33430bd0
BW		 12072 0,
12073 0,
43cd72b9
BW		 12074 Implicit_Field_ar0_get,
12075 Implicit_Field_ar4_get,
12076 Implicit_Field_ar8_get,
12077 Implicit_Field_ar12_get
12078};
12079
12080static xtensa_set_field_fn
12081Slot_inst16a_set_field_fns[] = {
12082 Field_t_Slot_inst16a_set,
12083 0,
12084 0,
12085 0,
12086 0,
12087 Field_s_Slot_inst16a_set,
12088 0,
12089 0,
12090 0,
12091 0,
12092 0,
12093 Field_op0_Slot_inst16a_set,
12094 0,
12095 0,
12096 Field_r_Slot_inst16a_set,
12097 0,
12098 0,
12099 0,
12100 0,
12101 0,
12102 0,
12103 0,
12104 Field_sr_Slot_inst16a_set,
12105 Field_st_Slot_inst16a_set,
12106 0,
12107 Field_imm4_Slot_inst16a_set,
12108 0,
12109 Field_i_Slot_inst16a_set,
12110 Field_imm6lo_Slot_inst16a_set,
12111 Field_imm6hi_Slot_inst16a_set,
12112 Field_imm7lo_Slot_inst16a_set,
12113 Field_imm7hi_Slot_inst16a_set,
12114 Field_z_Slot_inst16a_set,
12115 Field_imm6_Slot_inst16a_set,
12116 Field_imm7_Slot_inst16a_set,
33430bd0
BW		 12117 0,
12118 0,
43cd72b9
BW		 12119 Implicit_Field_set,
12120 Implicit_Field_set,
12121 Implicit_Field_set,
12122 Implicit_Field_set
12123};
12124
12125static xtensa_get_field_fn
12126Slot_inst16b_get_field_fns[] = {
12127 Field_t_Slot_inst16b_get,
12128 0,
12129 0,
12130 0,
12131 0,
12132 Field_s_Slot_inst16b_get,
12133 0,
12134 0,
12135 0,
12136 0,
12137 0,
12138 Field_op0_Slot_inst16b_get,
12139 0,
12140 0,
12141 Field_r_Slot_inst16b_get,
12142 0,
12143 0,
12144 0,
12145 0,
12146 0,
12147 0,
12148 0,
12149 Field_sr_Slot_inst16b_get,
12150 Field_st_Slot_inst16b_get,
12151 0,
12152 Field_imm4_Slot_inst16b_get,
12153 0,
12154 Field_i_Slot_inst16b_get,
12155 Field_imm6lo_Slot_inst16b_get,
12156 Field_imm6hi_Slot_inst16b_get,
12157 Field_imm7lo_Slot_inst16b_get,
12158 Field_imm7hi_Slot_inst16b_get,
12159 Field_z_Slot_inst16b_get,
12160 Field_imm6_Slot_inst16b_get,
12161 Field_imm7_Slot_inst16b_get,
33430bd0
BW		 12162 0,
12163 0,
43cd72b9
BW		 12164 Implicit_Field_ar0_get,
12165 Implicit_Field_ar4_get,
12166 Implicit_Field_ar8_get,
12167 Implicit_Field_ar12_get
12168};
12169
12170static xtensa_set_field_fn
12171Slot_inst16b_set_field_fns[] = {
12172 Field_t_Slot_inst16b_set,
12173 0,
12174 0,
12175 0,
12176 0,
12177 Field_s_Slot_inst16b_set,
12178 0,
12179 0,
12180 0,
12181 0,
12182 0,
12183 Field_op0_Slot_inst16b_set,
12184 0,
12185 0,
12186 Field_r_Slot_inst16b_set,
12187 0,
12188 0,
12189 0,
12190 0,
12191 0,
12192 0,
12193 0,
12194 Field_sr_Slot_inst16b_set,
12195 Field_st_Slot_inst16b_set,
12196 0,
12197 Field_imm4_Slot_inst16b_set,
12198 0,
12199 Field_i_Slot_inst16b_set,
12200 Field_imm6lo_Slot_inst16b_set,
12201 Field_imm6hi_Slot_inst16b_set,
12202 Field_imm7lo_Slot_inst16b_set,
12203 Field_imm7hi_Slot_inst16b_set,
12204 Field_z_Slot_inst16b_set,
12205 Field_imm6_Slot_inst16b_set,
12206 Field_imm7_Slot_inst16b_set,
33430bd0
BW		 12207 0,
12208 0,
43cd72b9
BW		 12209 Implicit_Field_set,
12210 Implicit_Field_set,
12211 Implicit_Field_set,
12212 Implicit_Field_set
12213};
12214
12215static xtensa_slot_internal slots[] = {
12216 { "Inst", "x24", 0,
12217 Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
12218 Slot_inst_get_field_fns, Slot_inst_set_field_fns,
12219 Slot_inst_decode, "nop" },
12220 { "Inst16a", "x16a", 0,
12221 Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
12222 Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
12223 Slot_inst16a_decode, "" },
12224 { "Inst16b", "x16b", 0,
12225 Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
12226 Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
12227 Slot_inst16b_decode, "nop.n" }
12228};
12229
12230\f
12231/* Instruction formats. */
12232
12233static void
12234Format_x24_encode (xtensa_insnbuf insn)
12235{
12236 insn[0] = 0;
12237}
12238
12239static void
12240Format_x16a_encode (xtensa_insnbuf insn)
12241{
12242 insn[0] = 0x800000;
e0001a05
NC		 12243}
12244
43cd72b9
BW		 12245static void
12246Format_x16b_encode (xtensa_insnbuf insn)
e0001a05 12247{
43cd72b9 12248 insn[0] = 0xc00000;
e0001a05
NC		 12249}
12250
43cd72b9
BW		 12251static int Format_x24_slots[] = { 0 };
12252
12253static int Format_x16a_slots[] = { 1 };
12254
12255static int Format_x16b_slots[] = { 2 };
12256
12257static xtensa_format_internal formats[] = {
12258 { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
12259 { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
12260 { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
e0001a05
NC		 12261};
12262
e0001a05 12263
43cd72b9
BW		 12264static int
12265format_decoder (const xtensa_insnbuf insn)
e0001a05 12266{
43cd72b9
BW		 12267 if ((insn[0] & 0x800000) == 0)
12268 return 0; /* x24 */
12269 if ((insn[0] & 0xc00000) == 0x800000)
12270 return 1; /* x16a */
12271 if ((insn[0] & 0xe00000) == 0xc00000)
12272 return 2; /* x16b */
12273 return -1;
e0001a05
NC		 12274}
12275
43cd72b9
BW		 12276static int length_table[16] = {
12277 3,
12278 3,
12279 3,
12280 3,
12281 3,
12282 3,
12283 3,
12284 3,
12285 2,
12286 2,
12287 2,
12288 2,
12289 2,
12290 2,
12291 -1,
12292 -1
12293};
12294
12295static int
f075ee0c 12296length_decoder (const unsigned char *insn)
43cd72b9
BW		 12297{
12298 int op0 = (insn[0] >> 4) & 0xf;
12299 return length_table[op0];
12300}
12301
12302\f
12303/* Top-level ISA structure. */
12304
12305xtensa_isa_internal xtensa_modules = {
12306 1 /* big-endian */,
12307 3 /* insn_size */, 0,
12308 3, formats, format_decoder, length_decoder,
12309 3, slots,
33430bd0
BW		 12310 41 /* num_fields */,
12311 75, operands,
12312 286, iclasses,
12313 353, opcodes, 0,
43cd72b9
BW		 12314 1, regfiles,
12315 NUM_STATES, states, 0,
12316 NUM_SYSREGS, sysregs, 0,
12317 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
12318 0, interfaces, 0,
12319 0, funcUnits, 0
e0001a05 12320};
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