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c906108c 1/* Target-dependent code for Hitachi Super-H, for GDB.
1e698235 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3116c80a 3 Free Software Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b
JM		 17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
c906108c
SS		 21
22/*
c5aa993b
JM		 23 Contributed by Steve Chamberlain
24 [email protected]
c906108c
SS		 25 */
26
27#include "defs.h"
28#include "frame.h"
c906108c
SS		 29#include "symtab.h"
30#include "symfile.h"
31#include "gdbtypes.h"
32#include "gdbcmd.h"
33#include "gdbcore.h"
34#include "value.h"
35#include "dis-asm.h"
36#include "inferior.h" /* for BEFORE_TEXT_END etc. */
37#include "gdb_string.h"
b4a20239 38#include "arch-utils.h"
fb409745 39#include "floatformat.h"
4e052eda 40#include "regcache.h"
d16aafd8 41#include "doublest.h"
c906108c 42
ab3b8126
JT		 43#include "sh-tdep.h"
44
d658f924 45#include "elf-bfd.h"
1a8629c7
MS		 46#include "solib-svr4.h"
47
283150cd
EZ		 48/* sh64 flags */
49#include "elf/sh.h"
50/* registers numbers shared with the simulator */
1c922164 51#include "gdb/sim-sh.h"
283150cd 52
53116e27 53void (*sh_show_regs) (void);
3bbfbb92
EZ		 54CORE_ADDR (*skip_prologue_hard_way) (CORE_ADDR);
55void (*do_pseudo_register) (int);
cc17453a 56
88e04cc1
EZ		 57#define SH_DEFAULT_NUM_REGS 59
58
cc17453a
EZ		 59/* Define other aspects of the stack frame.
60 we keep a copy of the worked out return pc lying around, since it
61 is a useful bit of info */
62
63struct frame_extra_info
64{
65 CORE_ADDR return_pc;
66 int leaf_function;
67 int f_offset;
63978407 68};
c906108c 69
fa88f677 70static const char *
cc17453a 71sh_generic_register_name (int reg_nr)
c5aa993b 72{
cc17453a 73 static char *register_names[] =
c5aa993b 74 {
cc17453a
EZ		 75 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
76 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
77 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
78 "fpul", "fpscr",
79 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
80 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
81 "ssr", "spc",
82 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
83 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
84 };
85 if (reg_nr < 0)
86 return NULL;
87 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
88 return NULL;
89 return register_names[reg_nr];
90}
91
fa88f677 92static const char *
cc17453a
EZ		 93sh_sh_register_name (int reg_nr)
94{
95 static char *register_names[] =
63978407 96 {
cc17453a
EZ		 97 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
98 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
99 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
100 "", "",
101 "", "", "", "", "", "", "", "",
102 "", "", "", "", "", "", "", "",
103 "", "",
104 "", "", "", "", "", "", "", "",
105 "", "", "", "", "", "", "", "",
106 };
107 if (reg_nr < 0)
108 return NULL;
109 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
110 return NULL;
111 return register_names[reg_nr];
112}
113
fa88f677 114static const char *
cc17453a
EZ		 115sh_sh3_register_name (int reg_nr)
116{
117 static char *register_names[] =
c5aa993b 118 {
cc17453a
EZ		 119 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
120 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
121 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
122 "", "",
123 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "",
125 "ssr", "spc",
126 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
127 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
128 };
129 if (reg_nr < 0)
130 return NULL;
131 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
132 return NULL;
133 return register_names[reg_nr];
134}
135
fa88f677 136static const char *
cc17453a
EZ		 137sh_sh3e_register_name (int reg_nr)
138{
139 static char *register_names[] =
63978407 140 {
cc17453a
EZ		 141 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
142 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
143 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
144 "fpul", "fpscr",
145 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
146 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
147 "ssr", "spc",
148 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
149 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
150 };
151 if (reg_nr < 0)
152 return NULL;
153 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
154 return NULL;
155 return register_names[reg_nr];
156}
157
fa88f677 158static const char *
cc17453a
EZ		 159sh_sh_dsp_register_name (int reg_nr)
160{
161 static char *register_names[] =
c5aa993b 162 {
cc17453a
EZ		 163 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
164 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
165 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
166 "", "dsr",
167 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
168 "y0", "y1", "", "", "", "", "", "mod",
169 "", "",
170 "rs", "re", "", "", "", "", "", "",
171 "", "", "", "", "", "", "", "",
172 };
173 if (reg_nr < 0)
174 return NULL;
175 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
176 return NULL;
177 return register_names[reg_nr];
178}
179
fa88f677 180static const char *
cc17453a
EZ		 181sh_sh3_dsp_register_name (int reg_nr)
182{
183 static char *register_names[] =
c5aa993b 184 {
cc17453a
EZ		 185 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
186 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
187 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
188 "", "dsr",
189 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
190 "y0", "y1", "", "", "", "", "", "mod",
191 "ssr", "spc",
192 "rs", "re", "", "", "", "", "", "",
193 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
194 "", "", "", "", "", "", "", "",
195 };
196 if (reg_nr < 0)
197 return NULL;
198 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
199 return NULL;
200 return register_names[reg_nr];
201}
202
fa88f677 203static const char *
53116e27
EZ		 204sh_sh4_register_name (int reg_nr)
205{
206 static char *register_names[] =
207 {
a38d2a54 208 /* general registers 0-15 */
53116e27
EZ		 209 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
210 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 211 /* 16 - 22 */
53116e27 212 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 213 /* 23, 24 */
53116e27 214 "fpul", "fpscr",
a38d2a54 215 /* floating point registers 25 - 40 */
53116e27
EZ		 216 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
217 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 218 /* 41, 42 */
53116e27 219 "ssr", "spc",
a38d2a54 220 /* bank 0 43 - 50 */
53116e27 221 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 222 /* bank 1 51 - 58 */
53116e27 223 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
a38d2a54 224 /* double precision (pseudo) 59 - 66 */
fe9f384f 225 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 226 /* vectors (pseudo) 67 - 70 */
fe9f384f 227 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ		 228 /* FIXME: missing XF 71 - 86 */
229 /* FIXME: missing XD 87 - 94 */
53116e27
EZ		 230 };
231 if (reg_nr < 0)
232 return NULL;
233 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
234 return NULL;
235 return register_names[reg_nr];
236}
237
fa88f677 238static const char *
283150cd
EZ		 239sh_sh64_register_name (int reg_nr)
240{
241 static char *register_names[] =
242 {
243 /* SH MEDIA MODE (ISA 32) */
244 /* general registers (64-bit) 0-63 */
245 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
246 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
247 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
248 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
249 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
250 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
251 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
252 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
253
254 /* pc (64-bit) 64 */
255 "pc",
256
257 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
258 "sr", "ssr", "spc",
259
260 /* target registers (64-bit) 68-75*/
261 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
262
263 /* floating point state control register (32-bit) 76 */
264 "fpscr",
265
266 /* single precision floating point registers (32-bit) 77-140*/
267 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
268 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
269 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
270 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
271 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
272 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
273 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
274 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
275
276 /* double precision registers (pseudo) 141-172 */
277 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
278 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
279 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
280 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
281
282 /* floating point pairs (pseudo) 173-204*/
283 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
284 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
285 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
286 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
287
288 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
289 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
290 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
291
292 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
293 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
294 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
295 "pc_c",
296 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
297 "fpscr_c", "fpul_c",
298 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
299 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
300 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
301 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
302 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
303 };
304
305 if (reg_nr < 0)
306 return NULL;
307 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
308 return NULL;
309 return register_names[reg_nr];
310}
311
312#define NUM_PSEUDO_REGS_SH_MEDIA 80
313#define NUM_PSEUDO_REGS_SH_COMPACT 51
314
3117ed25 315static const unsigned char *
fba45db2 316sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
cc17453a
EZ		 317{
318 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
319 static unsigned char breakpoint[] = {0xc3, 0xc3};
320
321 *lenptr = sizeof (breakpoint);
322 return breakpoint;
323}
c906108c 324
283150cd
EZ		 325/* Macros and functions for setting and testing a bit in a minimal
326 symbol that marks it as 32-bit function. The MSB of the minimal
327 symbol's "info" field is used for this purpose. This field is
328 already being used to store the symbol size, so the assumption is
329 that the symbol size cannot exceed 2^31.
330
331 ELF_MAKE_MSYMBOL_SPECIAL
332 tests whether an ELF symbol is "special", i.e. refers
333 to a 32-bit function, and sets a "special" bit in a
334 minimal symbol to mark it as a 32-bit function
335 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
336 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
337 the "info" field with the "special" bit masked out */
338
339#define MSYMBOL_IS_SPECIAL(msym) \
340 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
341
342void
343sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
344{
345 if (msym == NULL)
346 return;
347
348 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
349 {
350 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000);
351 SYMBOL_VALUE_ADDRESS (msym) |= 1;
352 }
353}
354
355/* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
356 are some macros to test, set, or clear bit 0 of addresses. */
357#define IS_ISA32_ADDR(addr) ((addr) & 1)
358#define MAKE_ISA32_ADDR(addr) ((addr) | 1)
359#define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
360
361static int
362pc_is_isa32 (bfd_vma memaddr)
363{
364 struct minimal_symbol *sym;
365
366 /* If bit 0 of the address is set, assume this is a
367 ISA32 (shmedia) address. */
368 if (IS_ISA32_ADDR (memaddr))
369 return 1;
370
371 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
372 the high bit of the info field. Use this to decide if the function is
373 ISA16 or ISA32. */
374 sym = lookup_minimal_symbol_by_pc (memaddr);
375 if (sym)
376 return MSYMBOL_IS_SPECIAL (sym);
377 else
378 return 0;
379}
380
381static const unsigned char *
382sh_sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
383{
384 /* The BRK instruction for shmedia is
385 01101111 11110101 11111111 11110000
386 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
387 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
388
389 /* The BRK instruction for shcompact is
390 00000000 00111011
391 which translates in big endian mode to 0x0, 0x3b
392 and in little endian mode to 0x3b, 0x0*/
393
394 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
395 {
396 if (pc_is_isa32 (*pcptr))
397 {
398 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
399 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
400 *lenptr = sizeof (big_breakpoint_media);
401 return big_breakpoint_media;
402 }
403 else
404 {
405 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
406 *lenptr = sizeof (big_breakpoint_compact);
407 return big_breakpoint_compact;
408 }
409 }
410 else
411 {
412 if (pc_is_isa32 (*pcptr))
413 {
414 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
415 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
416 *lenptr = sizeof (little_breakpoint_media);
417 return little_breakpoint_media;
418 }
419 else
420 {
421 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
422 *lenptr = sizeof (little_breakpoint_compact);
423 return little_breakpoint_compact;
424 }
425 }
426}
427
c906108c 428/* Prologue looks like
c5aa993b
JM		 429 [mov.l <regs>,@-r15]...
430 [sts.l pr,@-r15]
431 [mov.l r14,@-r15]
432 [mov r15,r14]
8db62801
EZ		 433
434 Actually it can be more complicated than this. For instance, with
435 newer gcc's:
436
437 mov.l r14,@-r15
438 add #-12,r15
439 mov r15,r14
440 mov r4,r1
441 mov r5,r2
442 mov.l r6,@(4,r14)
443 mov.l r7,@(8,r14)
444 mov.b r1,@r14
445 mov r14,r1
446 mov r14,r1
447 add #2,r1
448 mov.w r2,@r1
449
c5aa993b 450 */
c906108c 451
283150cd
EZ		 452/* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
453 with l=1 and n = 18 0110101111110001010010100aaa0000 */
454#define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
455
456/* STS.L PR,@-r0 0100000000100010
457 r0-4-->r0, PR-->(r0) */
458#define IS_STS_R0(x) ((x) == 0x4022)
459
460/* STS PR, Rm 0000mmmm00101010
461 PR-->Rm */
462#define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
463
464/* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
465 Rm-->(dispx4+r15) */
466#define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
467
468/* MOV.L R14,@(disp,r15) 000111111110dddd
469 R14-->(dispx4+r15) */
470#define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
471
472/* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
473 R18-->(dispx8+R14) */
474#define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
475
476/* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
477 R18-->(dispx8+R15) */
478#define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
479
480/* ST.L R15, disp, R18 101010001111dddddddddd0100100000
481 R18-->(dispx4+R15) */
482#define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
483
484/* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
485 R14-->(dispx8+R15) */
486#define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
487
488/* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
489 R14-->(dispx4+R15) */
490#define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
491
492/* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
493 R15 + imm --> R15 */
494#define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
495
496/* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
497 R15 + imm --> R15 */
498#define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
499
500/* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
501 R15 + R63 --> R14 */
502#define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
503
504/* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
505 R15 + R63 --> R14 */
506#define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
507
508#define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
509
510/* MOV #imm, R0 1110 0000 ssss ssss
511 #imm-->R0 */
512#define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
513
514/* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
515#define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
516
517/* ADD r15,r0 0011 0000 1111 1100
518 r15+r0-->r0 */
519#define IS_ADD_SP_R0(x) ((x) == 0x30fc)
520
521/* MOV.L R14 @-R0 0010 0000 1110 0110
522 R14-->(R0-4), R0-4-->R0 */
523#define IS_MOV_R14_R0(x) ((x) == 0x20e6)
524
525/* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
526 where Rm is one of r2-r9 which are the argument registers. */
527/* FIXME: Recognize the float and double register moves too! */
528#define IS_MEDIA_IND_ARG_MOV(x) \
529((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
530
531/* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
532 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
533 where Rm is one of r2-r9 which are the argument registers. */
534#define IS_MEDIA_ARG_MOV(x) \
535(((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
536 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
537
538/* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
539/* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
540/* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
541/* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
542/* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
543#define IS_MEDIA_MOV_TO_R14(x) \
544((((x) & 0xfffffc0f) == 0xa0e00000) \
545|| (((x) & 0xfffffc0f) == 0xa4e00000) \
546|| (((x) & 0xfffffc0f) == 0xa8e00000) \
547|| (((x) & 0xfffffc0f) == 0xb4e00000) \
548|| (((x) & 0xfffffc0f) == 0xbce00000))
549
550/* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
551 where Rm is r2-r9 */
552#define IS_COMPACT_IND_ARG_MOV(x) \
553((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
554
555/* compact direct arg move!
556 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
557#define IS_COMPACT_ARG_MOV(x) \
558(((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
559
560/* MOV.B Rm, @R14 0010 1110 mmmm 0000
561 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
562#define IS_COMPACT_MOV_TO_R14(x) \
563((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
564
565#define IS_JSR_R0(x) ((x) == 0x400b)
566#define IS_NOP(x) ((x) == 0x0009)
567
568
8db62801
EZ		 569/* STS.L PR,@-r15 0100111100100010
570 r15-4-->r15, PR-->(r15) */
c906108c 571#define IS_STS(x) ((x) == 0x4f22)
8db62801
EZ		 572
573/* MOV.L Rm,@-r15 00101111mmmm0110
574 r15-4-->r15, Rm-->(R15) */
c906108c 575#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 576
c906108c 577#define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
8db62801
EZ		 578
579/* MOV r15,r14 0110111011110011
580 r15-->r14 */
c906108c 581#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 582
583/* ADD #imm,r15 01111111iiiiiiii
584 r15+imm-->r15 */
c906108c 585#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 586
c906108c
SS		 587#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
588#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 589
590/* ADD r3,r15 0011111100111100
591 r15+r3-->r15 */
c906108c 592#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 593
594/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 595 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 596 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
c906108c 597#define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
c906108c 598
8db62801 599/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
8db62801 600 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
8db62801
EZ		 601 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
602 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
603#define IS_ARG_MOV(x) \
604(((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
cc17453a
EZ		 605 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
606 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
8db62801
EZ		 607
608/* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
609 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
3bbfbb92 610#define IS_MOV_TO_R14(x) \
cc17453a 611 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
8db62801
EZ		 612
613#define FPSCR_SZ (1 << 20)
c906108c 614
c906108c
SS		 615/* Skip any prologue before the guts of a function */
616
8db62801
EZ		 617/* Skip the prologue using the debug information. If this fails we'll
618 fall back on the 'guess' method below. */
619static CORE_ADDR
fba45db2 620after_prologue (CORE_ADDR pc)
8db62801
EZ		 621{
622 struct symtab_and_line sal;
623 CORE_ADDR func_addr, func_end;
624
625 /* If we can not find the symbol in the partial symbol table, then
626 there is no hope we can determine the function's start address
627 with this code. */
628 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
629 return 0;
630
631 /* Get the line associated with FUNC_ADDR. */
632 sal = find_pc_line (func_addr, 0);
633
634 /* There are only two cases to consider. First, the end of the source line
635 is within the function bounds. In that case we return the end of the
636 source line. Second is the end of the source line extends beyond the
637 bounds of the current function. We need to use the slow code to
638 examine instructions in that case. */
639 if (sal.end < func_end)
640 return sal.end;
641 else
642 return 0;
643}
644
645/* Here we look at each instruction in the function, and try to guess
646 where the prologue ends. Unfortunately this is not always
647 accurate. */
648static CORE_ADDR
3bbfbb92 649sh_skip_prologue_hard_way (CORE_ADDR start_pc)
c906108c 650{
2bfa91ee 651 CORE_ADDR here, end;
8db62801 652 int updated_fp = 0;
2bfa91ee
EZ		 653
654 if (!start_pc)
655 return 0;
656
657 for (here = start_pc, end = start_pc + (2 * 28); here < end;)
c906108c 658 {
2bfa91ee
EZ		 659 int w = read_memory_integer (here, 2);
660 here += 2;
661 if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w)
8db62801 662 || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w)
3bbfbb92 663 || IS_ARG_MOV (w) || IS_MOV_TO_R14 (w))
2bfa91ee
EZ		 664 {
665 start_pc = here;
2bfa91ee 666 }
8db62801
EZ		 667 else if (IS_MOV_SP_FP (w))
668 {
669 start_pc = here;
670 updated_fp = 1;
671 }
672 else
673 /* Don't bail out yet, if we are before the copy of sp. */
674 if (updated_fp)
675 break;
c906108c
SS		 676 }
677
678 return start_pc;
679}
680
283150cd
EZ		 681static CORE_ADDR
682look_for_args_moves (CORE_ADDR start_pc, int media_mode)
683{
684 CORE_ADDR here, end;
685 int w;
686 int insn_size = (media_mode ? 4 : 2);
687
688 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
689 {
690 if (media_mode)
691 {
692 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
693 here += insn_size;
694 if (IS_MEDIA_IND_ARG_MOV (w))
695 {
696 /* This must be followed by a store to r14, so the argument
697 is where the debug info says it is. This can happen after
698 the SP has been saved, unfortunately. */
699
700 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
701 insn_size);
702 here += insn_size;
703 if (IS_MEDIA_MOV_TO_R14 (next_insn))
704 start_pc = here;
705 }
706 else if (IS_MEDIA_ARG_MOV (w))
707 {
708 /* These instructions store directly the argument in r14. */
709 start_pc = here;
710 }
711 else
712 break;
713 }
714 else
715 {
716 w = read_memory_integer (here, insn_size);
717 w = w & 0xffff;
718 here += insn_size;
719 if (IS_COMPACT_IND_ARG_MOV (w))
720 {
721 /* This must be followed by a store to r14, so the argument
722 is where the debug info says it is. This can happen after
723 the SP has been saved, unfortunately. */
724
725 int next_insn = 0xffff & read_memory_integer (here, insn_size);
726 here += insn_size;
727 if (IS_COMPACT_MOV_TO_R14 (next_insn))
728 start_pc = here;
729 }
730 else if (IS_COMPACT_ARG_MOV (w))
731 {
732 /* These instructions store directly the argument in r14. */
733 start_pc = here;
734 }
735 else if (IS_MOVL_R0 (w))
736 {
737 /* There is a function that gcc calls to get the arguments
738 passed correctly to the function. Only after this
739 function call the arguments will be found at the place
740 where they are supposed to be. This happens in case the
741 argument has to be stored into a 64-bit register (for
742 instance doubles, long longs). SHcompact doesn't have
743 access to the full 64-bits, so we store the register in
744 stack slot and store the address of the stack slot in
745 the register, then do a call through a wrapper that
746 loads the memory value into the register. A SHcompact
747 callee calls an argument decoder
748 (GCC_shcompact_incoming_args) that stores the 64-bit
749 value in a stack slot and stores the address of the
750 stack slot in the register. GCC thinks the argument is
751 just passed by transparent reference, but this is only
752 true after the argument decoder is called. Such a call
753 needs to be considered part of the prologue. */
754
755 /* This must be followed by a JSR @r0 instruction and by
756 a NOP instruction. After these, the prologue is over! */
757
758 int next_insn = 0xffff & read_memory_integer (here, insn_size);
759 here += insn_size;
760 if (IS_JSR_R0 (next_insn))
761 {
762 next_insn = 0xffff & read_memory_integer (here, insn_size);
763 here += insn_size;
764
765 if (IS_NOP (next_insn))
766 start_pc = here;
767 }
768 }
769 else
770 break;
771 }
772 }
773
774 return start_pc;
775}
776
777static CORE_ADDR
778sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
779{
780 CORE_ADDR here, end;
781 int updated_fp = 0;
782 int insn_size = 4;
783 int media_mode = 1;
784
785 if (!start_pc)
786 return 0;
787
788 if (pc_is_isa32 (start_pc) == 0)
789 {
790 insn_size = 2;
791 media_mode = 0;
792 }
793
794 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
795 {
796
797 if (media_mode)
798 {
799 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
800 here += insn_size;
801 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
802 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
803 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
804 {
805 start_pc = here;
806 }
807 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
808 {
809 start_pc = here;
810 updated_fp = 1;
811 }
812 else
813 if (updated_fp)
814 {
815 /* Don't bail out yet, we may have arguments stored in
816 registers here, according to the debug info, so that
817 gdb can print the frames correctly. */
818 start_pc = look_for_args_moves (here - insn_size, media_mode);
819 break;
820 }
821 }
822 else
823 {
824 int w = 0xffff & read_memory_integer (here, insn_size);
825 here += insn_size;
826
827 if (IS_STS_R0 (w) || IS_STS_PR (w)
828 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
829 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
830 {
831 start_pc = here;
832 }
833 else if (IS_MOV_SP_FP (w))
834 {
835 start_pc = here;
836 updated_fp = 1;
837 }
838 else
839 if (updated_fp)
840 {
841 /* Don't bail out yet, we may have arguments stored in
842 registers here, according to the debug info, so that
843 gdb can print the frames correctly. */
844 start_pc = look_for_args_moves (here - insn_size, media_mode);
845 break;
846 }
847 }
848 }
849
850 return start_pc;
851}
852
cc17453a 853static CORE_ADDR
fba45db2 854sh_skip_prologue (CORE_ADDR pc)
8db62801
EZ		 855{
856 CORE_ADDR post_prologue_pc;
857
858 /* See if we can determine the end of the prologue via the symbol table.
859 If so, then return either PC, or the PC after the prologue, whichever
860 is greater. */
8db62801
EZ		 861 post_prologue_pc = after_prologue (pc);
862
863 /* If after_prologue returned a useful address, then use it. Else
864 fall back on the instruction skipping code. */
865 if (post_prologue_pc != 0)
866 return max (pc, post_prologue_pc);
867 else
868 return (skip_prologue_hard_way (pc));
869}
870
cc17453a
EZ		 871/* Immediately after a function call, return the saved pc.
872 Can't always go through the frames for this because on some machines
873 the new frame is not set up until the new function executes
874 some instructions.
875
876 The return address is the value saved in the PR register + 4 */
877static CORE_ADDR
fba45db2 878sh_saved_pc_after_call (struct frame_info *frame)
cc17453a 879{
3bbfbb92 880 return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM)));
cc17453a
EZ		 881}
882
883/* Should call_function allocate stack space for a struct return? */
884static int
fba45db2 885sh_use_struct_convention (int gcc_p, struct type *type)
cc17453a 886{
7079c36c 887#if 0
cc17453a 888 return (TYPE_LENGTH (type) > 1);
7079c36c
CV		 889#else
890 int len = TYPE_LENGTH (type);
891 int nelem = TYPE_NFIELDS (type);
892 return ((len != 1 && len != 2 && len != 4 && len != 8) || nelem != 1) &&
893 (len != 8 || TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) != 4);
894#endif
cc17453a
EZ		 895}
896
283150cd
EZ		 897static int
898sh64_use_struct_convention (int gcc_p, struct type *type)
899{
900 return (TYPE_LENGTH (type) > 8);
901}
902
cc17453a
EZ		 903/* Store the address of the place in which to copy the structure the
904 subroutine will return. This is called from call_function.
905
3bbfbb92 906 We store structs through a pointer passed in R2 */
cc17453a 907static void
fba45db2 908sh_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
cc17453a
EZ		 909{
910 write_register (STRUCT_RETURN_REGNUM, (addr));
911}
c906108c 912
cc17453a
EZ		 913/* Disassemble an instruction. */
914static int
fba45db2 915gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
c906108c 916{
1c509ca8
JR		 917 info->endian = TARGET_BYTE_ORDER;
918 return print_insn_sh (memaddr, info);
283150cd
EZ		 919}
920
a5afb99f
AC		 921/* Given a GDB frame, determine the address of the calling function's
922 frame. This will be used to create a new GDB frame struct, and
923 then INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC will be
924 called for the new frame.
c906108c
SS		 925
926 For us, the frame address is its stack pointer value, so we look up
927 the function prologue to determine the caller's sp value, and return it. */
cc17453a 928static CORE_ADDR
fba45db2 929sh_frame_chain (struct frame_info *frame)
c906108c 930{
50abf9e5 931 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), frame->frame, frame->frame))
c906108c 932 return frame->frame; /* dummy frame same as caller's frame */
50abf9e5 933 if (get_frame_pc (frame) && !inside_entry_file (get_frame_pc (frame)))
c193f6ac 934 return read_memory_integer (get_frame_base (frame) + frame->extra_info->f_offset, 4);
c906108c
SS		 935 else
936 return 0;
937}
938
283150cd
EZ		 939/* Given a register number RN as it appears in an assembly
940 instruction, find the corresponding register number in the GDB
941 scheme. */
942static int
943translate_insn_rn (int rn, int media_mode)
944{
945 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
946
947 /* FIXME: this assumes that the number rn is for a not pseudo
948 register only. */
949 if (media_mode)
950 return rn;
951 else
952 {
953 /* These registers don't have a corresponding compact one. */
954 /* FIXME: This is probably not enough. */
955#if 0
956 if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140))
957 return rn;
958#endif
959 if (rn >= 0 && rn <= tdep->R0_C_REGNUM)
960 return tdep->R0_C_REGNUM + rn;
961 else
962 return rn;
963 }
964}
965
966static CORE_ADDR
967sh64_frame_chain (struct frame_info *frame)
968{
50abf9e5 969 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), frame->frame, frame->frame))
283150cd 970 return frame->frame; /* dummy frame same as caller's frame */
50abf9e5 971 if (get_frame_pc (frame) && !inside_entry_file (get_frame_pc (frame)))
283150cd 972 {
50abf9e5 973 int media_mode = pc_is_isa32 (get_frame_pc (frame));
283150cd
EZ		 974 int size;
975 if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
976 size = 4;
977 else
978 size = REGISTER_RAW_SIZE (translate_insn_rn (FP_REGNUM, media_mode));
c193f6ac 979 return read_memory_integer (get_frame_base (frame) + frame->extra_info->f_offset, size);
283150cd
EZ		 980 }
981 else
982 return 0;
983}
984
c906108c
SS		 985/* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
986 we might want to do here is to check REGNUM against the clobber mask, and
987 somehow flag it as invalid if it isn't saved on the stack somewhere. This
988 would provide a graceful failure mode when trying to get the value of
989 caller-saves registers for an inner frame. */
cc17453a 990static CORE_ADDR
fba45db2 991sh_find_callers_reg (struct frame_info *fi, int regnum)
c906108c 992{
c906108c 993 for (; fi; fi = fi->next)
50abf9e5 994 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), fi->frame, fi->frame))
c906108c 995 /* When the caller requests PR from the dummy frame, we return PC because
c5aa993b 996 that's where the previous routine appears to have done a call from. */
50abf9e5 997 return deprecated_read_register_dummy (get_frame_pc (fi), fi->frame, regnum);
c5aa993b 998 else
c906108c 999 {
cc17453a 1000 FRAME_INIT_SAVED_REGS (fi);
50abf9e5 1001 if (!get_frame_pc (fi))
2bfa91ee 1002 return 0;
b2fb4676
AC		 1003 if (get_frame_saved_regs (fi)[regnum] != 0)
1004 return read_memory_integer (get_frame_saved_regs (fi)[regnum],
c5aa993b 1005 REGISTER_RAW_SIZE (regnum));
c906108c
SS		 1006 }
1007 return read_register (regnum);
1008}
1009
283150cd
EZ		 1010static CORE_ADDR
1011sh64_get_saved_pr (struct frame_info *fi, int pr_regnum)
1012{
1013 int media_mode = 0;
1014
1015 for (; fi; fi = fi->next)
50abf9e5 1016 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), fi->frame, fi->frame))
283150cd
EZ		 1017 /* When the caller requests PR from the dummy frame, we return PC because
1018 that's where the previous routine appears to have done a call from. */
50abf9e5 1019 return deprecated_read_register_dummy (get_frame_pc (fi), fi->frame, pr_regnum);
283150cd
EZ		 1020 else
1021 {
1022 FRAME_INIT_SAVED_REGS (fi);
50abf9e5 1023 if (!get_frame_pc (fi))
283150cd
EZ		 1024 return 0;
1025
50abf9e5 1026 media_mode = pc_is_isa32 (get_frame_pc (fi));
283150cd 1027
b2fb4676 1028 if (get_frame_saved_regs (fi)[pr_regnum] != 0)
283150cd
EZ		 1029 {
1030 int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode);
1031 int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
1032 ? 4
1033 : REGISTER_RAW_SIZE (gdb_reg_num));
b2fb4676 1034 return read_memory_integer (get_frame_saved_regs (fi)[pr_regnum], size);
283150cd
EZ		 1035 }
1036 }
1037 return read_register (pr_regnum);
1038}
1039
c906108c
SS		 1040/* Put here the code to store, into a struct frame_saved_regs, the
1041 addresses of the saved registers of frame described by FRAME_INFO.
1042 This includes special registers such as pc and fp saved in special
1043 ways in the stack frame. sp is even more special: the address we
1044 return for it IS the sp for the next frame. */
cc17453a 1045static void
fba45db2 1046sh_nofp_frame_init_saved_regs (struct frame_info *fi)
c906108c 1047{
e7d717c0 1048 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof(int));
c906108c
SS		 1049 int rn;
1050 int have_fp = 0;
1051 int depth;
1052 int pc;
1053 int opc;
1054 int insn;
1055 int r3_val = 0;
50abf9e5 1056 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), fi->frame);
cc17453a 1057
b2fb4676 1058 if (get_frame_saved_regs (fi) == NULL)
cc17453a
EZ		 1059 frame_saved_regs_zalloc (fi);
1060 else
b2fb4676 1061 memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
cc17453a
EZ		 1062
1063 if (dummy_regs)
1064 {
1065 /* DANGER! This is ONLY going to work if the char buffer format of
1066 the saved registers is byte-for-byte identical to the
1067 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1068 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
1069 return;
1070 }
1071
1072 fi->extra_info->leaf_function = 1;
1073 fi->extra_info->f_offset = 0;
1074
cd4bffcf 1075 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
cc17453a
EZ		 1076 where[rn] = -1;
1077
1078 depth = 0;
1079
1080 /* Loop around examining the prologue insns until we find something
1081 that does not appear to be part of the prologue. But give up
1082 after 20 of them, since we're getting silly then. */
1083
50abf9e5 1084 pc = get_pc_function_start (get_frame_pc (fi));
cc17453a
EZ		 1085 if (!pc)
1086 {
50abf9e5 1087 deprecated_update_frame_pc_hack (fi, 0);
cc17453a
EZ		 1088 return;
1089 }
1090
1091 for (opc = pc + (2 * 28); pc < opc; pc += 2)
1092 {
1093 insn = read_memory_integer (pc, 2);
1094 /* See where the registers will be saved to */
1095 if (IS_PUSH (insn))
1096 {
1097 rn = GET_PUSHED_REG (insn);
1098 where[rn] = depth;
1099 depth += 4;
1100 }
1101 else if (IS_STS (insn))
1102 {
3bbfbb92 1103 where[gdbarch_tdep (current_gdbarch)->PR_REGNUM] = depth;
cc17453a
EZ		 1104 /* If we're storing the pr then this isn't a leaf */
1105 fi->extra_info->leaf_function = 0;
1106 depth += 4;
1107 }
1108 else if (IS_MOV_R3 (insn))
1109 {
1110 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
1111 }
1112 else if (IS_SHLL_R3 (insn))
1113 {
1114 r3_val <<= 1;
1115 }
1116 else if (IS_ADD_R3SP (insn))
1117 {
1118 depth += -r3_val;
1119 }
1120 else if (IS_ADD_SP (insn))
1121 {
1122 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1123 }
1124 else if (IS_MOV_SP_FP (insn))
1125 break;
1126#if 0 /* This used to just stop when it found an instruction that
1127 was not considered part of the prologue. Now, we just
1128 keep going looking for likely instructions. */
1129 else
1130 break;
1131#endif
1132 }
1133
1134 /* Now we know how deep things are, we can work out their addresses */
1135
cd4bffcf 1136 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
cc17453a
EZ		 1137 {
1138 if (where[rn] >= 0)
1139 {
1140 if (rn == FP_REGNUM)
1141 have_fp = 1;
c906108c 1142
b2fb4676 1143 get_frame_saved_regs (fi)[rn] = fi->frame - where[rn] + depth - 4;
cc17453a
EZ		 1144 }
1145 else
1146 {
b2fb4676 1147 get_frame_saved_regs (fi)[rn] = 0;
cc17453a
EZ		 1148 }
1149 }
1150
1151 if (have_fp)
1152 {
b2fb4676 1153 get_frame_saved_regs (fi)[SP_REGNUM] = read_memory_integer (get_frame_saved_regs (fi)[FP_REGNUM], 4);
cc17453a
EZ		 1154 }
1155 else
1156 {
b2fb4676 1157 get_frame_saved_regs (fi)[SP_REGNUM] = fi->frame - 4;
cc17453a
EZ		 1158 }
1159
1160 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
1161 /* Work out the return pc - either from the saved pr or the pr
1162 value */
1163}
1164
3bbfbb92
EZ		 1165/* For vectors of 4 floating point registers. */
1166static int
1167fv_reg_base_num (int fv_regnum)
1168{
1169 int fp_regnum;
1170
1171 fp_regnum = FP0_REGNUM +
1172 (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4;
1173 return fp_regnum;
1174}
1175
1176/* For double precision floating point registers, i.e 2 fp regs.*/
1177static int
1178dr_reg_base_num (int dr_regnum)
1179{
1180 int fp_regnum;
1181
1182 fp_regnum = FP0_REGNUM +
1183 (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2;
1184 return fp_regnum;
1185}
1186
283150cd
EZ		 1187/* For pairs of floating point registers */
1188static int
1189fpp_reg_base_num (int fpp_regnum)
1190{
1191 int fp_regnum;
1192
1193 fp_regnum = FP0_REGNUM +
1194 (fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM) * 2;
1195 return fp_regnum;
1196}
1197
1198static int
1199is_media_pseudo (int rn)
1200{
1201 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1202
1203 return (rn >= tdep->DR0_REGNUM
1204 && rn <= tdep->FV_LAST_REGNUM);
1205}
1206
1207int
1208sh64_get_gdb_regnum (int gcc_regnum, CORE_ADDR pc)
1209{
1210 return translate_insn_rn (gcc_regnum, pc_is_isa32 (pc));
1211}
1212
1213static int
1214sh64_media_reg_base_num (int reg_nr)
1215{
1216 int base_regnum = -1;
1217 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1218
1219 if (reg_nr >= tdep->DR0_REGNUM
1220 && reg_nr <= tdep->DR_LAST_REGNUM)
1221 base_regnum = dr_reg_base_num (reg_nr);
1222
1223 else if (reg_nr >= tdep->FPP0_REGNUM
1224 && reg_nr <= tdep->FPP_LAST_REGNUM)
1225 base_regnum = fpp_reg_base_num (reg_nr);
1226
1227 else if (reg_nr >= tdep->FV0_REGNUM
1228 && reg_nr <= tdep->FV_LAST_REGNUM)
1229 base_regnum = fv_reg_base_num (reg_nr);
1230
1231 return base_regnum;
1232}
1233
1234/* *INDENT-OFF* */
1235/*
1236 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1237 GDB_REGNUM BASE_REGNUM
1238 r0_c 221 0
1239 r1_c 222 1
1240 r2_c 223 2
1241 r3_c 224 3
1242 r4_c 225 4
1243 r5_c 226 5
1244 r6_c 227 6
1245 r7_c 228 7
1246 r8_c 229 8
1247 r9_c 230 9
1248 r10_c 231 10
1249 r11_c 232 11
1250 r12_c 233 12
1251 r13_c 234 13
1252 r14_c 235 14
1253 r15_c 236 15
1254
1255 pc_c 237 64
1256 gbr_c 238 16
1257 mach_c 239 17
1258 macl_c 240 17
1259 pr_c 241 18
1260 t_c 242 19
1261 fpscr_c 243 76
1262 fpul_c 244 109
1263
1264 fr0_c 245 77
1265 fr1_c 246 78
1266 fr2_c 247 79
1267 fr3_c 248 80
1268 fr4_c 249 81
1269 fr5_c 250 82
1270 fr6_c 251 83
1271 fr7_c 252 84
1272 fr8_c 253 85
1273 fr9_c 254 86
1274 fr10_c 255 87
1275 fr11_c 256 88
1276 fr12_c 257 89
1277 fr13_c 258 90
1278 fr14_c 259 91
1279 fr15_c 260 92
1280
1281 dr0_c 261 77
1282 dr2_c 262 79
1283 dr4_c 263 81
1284 dr6_c 264 83
1285 dr8_c 265 85
1286 dr10_c 266 87
1287 dr12_c 267 89
1288 dr14_c 268 91
1289
1290 fv0_c 269 77
1291 fv4_c 270 81
1292 fv8_c 271 85
1293 fv12_c 272 91
1294*/
1295/* *INDENT-ON* */
1296static int
1297sh64_compact_reg_base_num (int reg_nr)
1298{
1299 int base_regnum = -1;
1300 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1301
1302 /* general register N maps to general register N */
1303 if (reg_nr >= tdep->R0_C_REGNUM
1304 && reg_nr <= tdep->R_LAST_C_REGNUM)
1305 base_regnum = reg_nr - tdep->R0_C_REGNUM;
1306
1307 /* floating point register N maps to floating point register N */
1308 else if (reg_nr >= tdep->FP0_C_REGNUM
1309 && reg_nr <= tdep->FP_LAST_C_REGNUM)
1310 base_regnum = reg_nr - tdep->FP0_C_REGNUM + FP0_REGNUM;
1311
1312 /* double prec register N maps to base regnum for double prec register N */
1313 else if (reg_nr >= tdep->DR0_C_REGNUM
1314 && reg_nr <= tdep->DR_LAST_C_REGNUM)
1315 base_regnum = dr_reg_base_num (tdep->DR0_REGNUM
1316 + reg_nr - tdep->DR0_C_REGNUM);
1317
1318 /* vector N maps to base regnum for vector register N */
1319 else if (reg_nr >= tdep->FV0_C_REGNUM
1320 && reg_nr <= tdep->FV_LAST_C_REGNUM)
1321 base_regnum = fv_reg_base_num (tdep->FV0_REGNUM
1322 + reg_nr - tdep->FV0_C_REGNUM);
1323
1324 else if (reg_nr == tdep->PC_C_REGNUM)
1325 base_regnum = PC_REGNUM;
1326
1327 else if (reg_nr == tdep->GBR_C_REGNUM)
1328 base_regnum = 16;
1329
1330 else if (reg_nr == tdep->MACH_C_REGNUM
1331 || reg_nr == tdep->MACL_C_REGNUM)
1332 base_regnum = 17;
1333
1334 else if (reg_nr == tdep->PR_C_REGNUM)
1335 base_regnum = 18;
1336
1337 else if (reg_nr == tdep->T_C_REGNUM)
1338 base_regnum = 19;
1339
1340 else if (reg_nr == tdep->FPSCR_C_REGNUM)
1341 base_regnum = tdep->FPSCR_REGNUM; /*???? this register is a mess. */
1342
1343 else if (reg_nr == tdep->FPUL_C_REGNUM)
1344 base_regnum = FP0_REGNUM + 32;
1345
1346 return base_regnum;
1347}
1348
1349/* Given a register number RN (according to the gdb scheme) , return
1350 its corresponding architectural register. In media mode, only a
1351 subset of the registers is pseudo registers. For compact mode, all
1352 the registers are pseudo. */
1353static int
1354translate_rn_to_arch_reg_num (int rn, int media_mode)
1355{
1356
1357 if (media_mode)
1358 {
1359 if (!is_media_pseudo (rn))
1360 return rn;
1361 else
1362 return sh64_media_reg_base_num (rn);
1363 }
1364 else
1365 /* All compact registers are pseudo. */
1366 return sh64_compact_reg_base_num (rn);
1367}
1368
1369static int
1370sign_extend (int value, int bits)
1371{
1372 value = value & ((1 << bits) - 1);
1373 return (value & (1 << (bits - 1))
1374 ? value | (~((1 << bits) - 1))
1375 : value);
1376}
1377
cc17453a 1378static void
283150cd 1379sh64_nofp_frame_init_saved_regs (struct frame_info *fi)
cc17453a 1380{
ddde02bd 1381 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
cc17453a
EZ		 1382 int rn;
1383 int have_fp = 0;
283150cd
EZ		 1384 int fp_regnum;
1385 int sp_regnum;
1386 int depth;
1387 int pc;
1388 int opc;
1389 int insn;
1390 int r0_val = 0;
1391 int media_mode = 0;
1392 int insn_size;
1393 int gdb_register_number;
1394 int register_number;
50abf9e5 1395 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), fi->frame);
283150cd
EZ		 1396 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1397
b2fb4676 1398 if (get_frame_saved_regs (fi) == NULL)
283150cd
EZ		 1399 frame_saved_regs_zalloc (fi);
1400 else
b2fb4676 1401 memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
283150cd
EZ		 1402
1403 if (dummy_regs)
1404 {
1405 /* DANGER! This is ONLY going to work if the char buffer format of
1406 the saved registers is byte-for-byte identical to the
1407 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1408 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
1409 return;
1410 }
1411
1412 fi->extra_info->leaf_function = 1;
1413 fi->extra_info->f_offset = 0;
1414
1415 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1416 where[rn] = -1;
1417
1418 depth = 0;
1419
1420 /* Loop around examining the prologue insns until we find something
1421 that does not appear to be part of the prologue. But give up
1422 after 20 of them, since we're getting silly then. */
1423
50abf9e5 1424 pc = get_pc_function_start (get_frame_pc (fi));
283150cd
EZ		 1425 if (!pc)
1426 {
50abf9e5 1427 deprecated_update_frame_pc_hack (fi, 0);
283150cd
EZ		 1428 return;
1429 }
1430
1431 if (pc_is_isa32 (pc))
1432 {
1433 media_mode = 1;
1434 insn_size = 4;
1435 }
1436 else
1437 {
1438 media_mode = 0;
1439 insn_size = 2;
1440 }
1441
1442 /* The frame pointer register is general register 14 in shmedia and
1443 shcompact modes. In sh compact it is a pseudo register. Same goes
1444 for the stack pointer register, which is register 15. */
1445 fp_regnum = translate_insn_rn (FP_REGNUM, media_mode);
1446 sp_regnum = translate_insn_rn (SP_REGNUM, media_mode);
1447
1448 for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size)
1449 {
1450 insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc,
1451 insn_size);
1452
1453 if (media_mode == 0)
1454 {
1455 if (IS_STS_PR (insn))
1456 {
1457 int next_insn = read_memory_integer (pc + insn_size, insn_size);
1458 if (IS_MOV_TO_R15 (next_insn))
1459 {
1460 int reg_nr = tdep->PR_C_REGNUM;
1461
1462 where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
1463 fi->extra_info->leaf_function = 0;
1464 pc += insn_size;
1465 }
1466 }
1467 else if (IS_MOV_R14 (insn))
1468 {
1469 where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
1470 }
1471
1472 else if (IS_MOV_R0 (insn))
1473 {
1474 /* Put in R0 the offset from SP at which to store some
1475 registers. We are interested in this value, because it
1476 will tell us where the given registers are stored within
1477 the frame. */
1478 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
1479 }
1480 else if (IS_ADD_SP_R0 (insn))
1481 {
1482 /* This instruction still prepares r0, but we don't care.
1483 We already have the offset in r0_val. */
1484 }
1485 else if (IS_STS_R0 (insn))
1486 {
1487 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1488 int reg_nr = tdep->PR_C_REGNUM;
1489 where[reg_nr] = depth - (r0_val - 4);
1490 r0_val -= 4;
1491 fi->extra_info->leaf_function = 0;
1492 }
1493 else if (IS_MOV_R14_R0 (insn))
1494 {
1495 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1496 where[fp_regnum] = depth - (r0_val - 4);
1497 r0_val -= 4;
1498 }
1499
1500 else if (IS_ADD_SP (insn))
1501 {
1502 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1503 }
1504 else if (IS_MOV_SP_FP (insn))
1505 break;
1506 }
1507 else
1508 {
1509 if (IS_ADDIL_SP_MEDIA (insn)
1510 || IS_ADDI_SP_MEDIA (insn))
1511 {
1512 depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1513 }
1514
1515 else if (IS_STQ_R18_R15 (insn))
1516 {
1517 where[tdep->PR_REGNUM] =
1518 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1519 fi->extra_info->leaf_function = 0;
1520 }
1521
1522 else if (IS_STL_R18_R15 (insn))
1523 {
1524 where[tdep->PR_REGNUM] =
1525 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1526 fi->extra_info->leaf_function = 0;
1527 }
1528
1529 else if (IS_STQ_R14_R15 (insn))
1530 {
1531 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1532 }
1533
1534 else if (IS_STL_R14_R15 (insn))
1535 {
1536 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1537 }
1538
1539 else if (IS_MOV_SP_FP_MEDIA (insn))
1540 break;
1541 }
1542 }
1543
1544 /* Now we know how deep things are, we can work out their addresses. */
1545 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1546 {
1547 register_number = translate_rn_to_arch_reg_num (rn, media_mode);
1548
1549 if (where[rn] >= 0)
1550 {
1551 if (rn == fp_regnum)
1552 have_fp = 1;
1553
1554 /* Watch out! saved_regs is only for the real registers, and
1555 doesn't include space for the pseudo registers. */
b2fb4676 1556 get_frame_saved_regs (fi)[register_number]= fi->frame - where[rn] + depth;
283150cd
EZ		 1557
1558 }
1559 else
b2fb4676 1560 get_frame_saved_regs (fi)[register_number] = 0;
283150cd
EZ		 1561 }
1562
1563 if (have_fp)
1564 {
1565 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1566 shcompact 15 is the arch register corresponding to the pseudo
1567 register r15 which still is the SP register. */
1568 /* The place on the stack where fp is stored contains the sp of
1569 the caller. */
1570 /* Again, saved_registers contains only space for the real registers,
1571 so we store in FP_REGNUM position. */
1572 int size;
1573 if (tdep->sh_abi == SH_ABI_32)
1574 size = 4;
1575 else
1576 size = REGISTER_RAW_SIZE (fp_regnum);
b2fb4676 1577 get_frame_saved_regs (fi)[sp_regnum] = read_memory_integer (get_frame_saved_regs (fi)[fp_regnum], size);
283150cd
EZ		 1578 }
1579 else
b2fb4676 1580 get_frame_saved_regs (fi)[sp_regnum] = fi->frame;
283150cd
EZ		 1581
1582 fi->extra_info->f_offset = depth - where[fp_regnum];
1583}
1584
1585static void
1586sh_fp_frame_init_saved_regs (struct frame_info *fi)
1587{
ddde02bd 1588 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
283150cd
EZ		 1589 int rn;
1590 int have_fp = 0;
cc17453a
EZ		 1591 int depth;
1592 int pc;
1593 int opc;
1594 int insn;
1595 int r3_val = 0;
50abf9e5 1596 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), fi->frame);
f81353e4 1597 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
cc17453a 1598
b2fb4676 1599 if (get_frame_saved_regs (fi) == NULL)
cc17453a
EZ		 1600 frame_saved_regs_zalloc (fi);
1601 else
b2fb4676 1602 memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
cc17453a 1603
c906108c
SS		 1604 if (dummy_regs)
1605 {
1606 /* DANGER! This is ONLY going to work if the char buffer format of
c5aa993b
JM		 1607 the saved registers is byte-for-byte identical to the
1608 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
cc17453a 1609 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
c906108c
SS		 1610 return;
1611 }
1612
cc17453a
EZ		 1613 fi->extra_info->leaf_function = 1;
1614 fi->extra_info->f_offset = 0;
c906108c 1615
cd4bffcf 1616 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
c906108c
SS		 1617 where[rn] = -1;
1618
1619 depth = 0;
1620
1621 /* Loop around examining the prologue insns until we find something
1622 that does not appear to be part of the prologue. But give up
1623 after 20 of them, since we're getting silly then. */
1624
50abf9e5 1625 pc = get_pc_function_start (get_frame_pc (fi));
2bfa91ee 1626 if (!pc)
c906108c 1627 {
50abf9e5 1628 deprecated_update_frame_pc_hack (fi, 0);
2bfa91ee
EZ		 1629 return;
1630 }
1631
1632 for (opc = pc + (2 * 28); pc < opc; pc += 2)
1633 {
1634 insn = read_memory_integer (pc, 2);
c906108c
SS		 1635 /* See where the registers will be saved to */
1636 if (IS_PUSH (insn))
1637 {
c906108c
SS		 1638 rn = GET_PUSHED_REG (insn);
1639 where[rn] = depth;
c906108c
SS		 1640 depth += 4;
1641 }
1642 else if (IS_STS (insn))
1643 {
f81353e4 1644 where[tdep->PR_REGNUM] = depth;
c906108c 1645 /* If we're storing the pr then this isn't a leaf */
cc17453a 1646 fi->extra_info->leaf_function = 0;
c906108c
SS		 1647 depth += 4;
1648 }
1649 else if (IS_MOV_R3 (insn))
1650 {
1651 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 1652 }
1653 else if (IS_SHLL_R3 (insn))
1654 {
1655 r3_val <<= 1;
c906108c
SS		 1656 }
1657 else if (IS_ADD_R3SP (insn))
1658 {
1659 depth += -r3_val;
c906108c
SS		 1660 }
1661 else if (IS_ADD_SP (insn))
1662 {
c906108c 1663 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 1664 }
1665 else if (IS_FMOV (insn))
1666 {
f81353e4 1667 if (read_register (tdep->FPSCR_REGNUM) & FPSCR_SZ)
c906108c
SS		 1668 {
1669 depth += 8;
1670 }
1671 else
1672 {
1673 depth += 4;
1674 }
1675 }
2bfa91ee
EZ		 1676 else if (IS_MOV_SP_FP (insn))
1677 break;
1678#if 0 /* This used to just stop when it found an instruction that
1679 was not considered part of the prologue. Now, we just
1680 keep going looking for likely instructions. */
c906108c
SS		 1681 else
1682 break;
2bfa91ee 1683#endif
c906108c
SS		 1684 }
1685
1686 /* Now we know how deep things are, we can work out their addresses */
1687
cd4bffcf 1688 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
c906108c
SS		 1689 {
1690 if (where[rn] >= 0)
1691 {
1692 if (rn == FP_REGNUM)
1693 have_fp = 1;
1694
b2fb4676 1695 get_frame_saved_regs (fi)[rn] = fi->frame - where[rn] + depth - 4;
c906108c
SS		 1696 }
1697 else
1698 {
b2fb4676 1699 get_frame_saved_regs (fi)[rn] = 0;
c906108c
SS		 1700 }
1701 }
1702
1703 if (have_fp)
1704 {
b2fb4676
AC		 1705 get_frame_saved_regs (fi)[SP_REGNUM] =
1706 read_memory_integer (get_frame_saved_regs (fi)[FP_REGNUM], 4);
c906108c
SS		 1707 }
1708 else
1709 {
b2fb4676 1710 get_frame_saved_regs (fi)[SP_REGNUM] = fi->frame - 4;
c906108c
SS		 1711 }
1712
cc17453a 1713 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
c906108c
SS		 1714 /* Work out the return pc - either from the saved pr or the pr
1715 value */
1716}
1717
cc17453a
EZ		 1718/* Initialize the extra info saved in a FRAME */
1719static void
fba45db2 1720sh_init_extra_frame_info (int fromleaf, struct frame_info *fi)
c906108c 1721{
cc17453a
EZ		 1722
1723 fi->extra_info = (struct frame_extra_info *)
1724 frame_obstack_alloc (sizeof (struct frame_extra_info));
c906108c
SS		 1725
1726 if (fi->next)
50abf9e5 1727 deprecated_update_frame_pc_hack (fi, FRAME_SAVED_PC (fi->next));
c906108c 1728
50abf9e5 1729 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), fi->frame, fi->frame))
c906108c
SS		 1730 {
1731 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
c5aa993b 1732 by assuming it's always FP. */
8ccd593b
AC		 1733 deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), fi->frame,
1734 SP_REGNUM));
50abf9e5 1735 fi->extra_info->return_pc = deprecated_read_register_dummy (get_frame_pc (fi),
135c175f
AC		 1736 fi->frame,
1737 PC_REGNUM);
cc17453a
EZ		 1738 fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
1739 fi->extra_info->leaf_function = 0;
c906108c
SS		 1740 return;
1741 }
1742 else
1743 {
cc17453a 1744 FRAME_INIT_SAVED_REGS (fi);
cd4bffcf
EZ		 1745 fi->extra_info->return_pc =
1746 sh_find_callers_reg (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
c906108c
SS		 1747 }
1748}
1749
283150cd
EZ		 1750static void
1751sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1752{
50abf9e5 1753 int media_mode = pc_is_isa32 (get_frame_pc (fi));
283150cd
EZ		 1754
1755 fi->extra_info = (struct frame_extra_info *)
1756 frame_obstack_alloc (sizeof (struct frame_extra_info));
1757
50abf9e5
AC		 1758 if (fi->next)
1759 deprecated_update_frame_pc_hack (fi, FRAME_SAVED_PC (fi->next));
283150cd 1760
50abf9e5 1761 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), fi->frame, fi->frame))
283150cd
EZ		 1762 {
1763 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1764 by assuming it's always FP. */
8ccd593b
AC		 1765 deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), fi->frame,
1766 SP_REGNUM));
283150cd 1767 fi->extra_info->return_pc =
50abf9e5 1768 deprecated_read_register_dummy (get_frame_pc (fi), fi->frame, PC_REGNUM);
283150cd
EZ		 1769 fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
1770 fi->extra_info->leaf_function = 0;
1771 return;
1772 }
1773 else
1774 {
1775 FRAME_INIT_SAVED_REGS (fi);
1776 fi->extra_info->return_pc =
1777 sh64_get_saved_pr (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
1778 }
1779}
1780
1781void
1782sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp,
1783 struct frame_info *frame, int regnum,
1784 enum lval_type *lval)
1785{
1786 int media_mode;
1787 int live_regnum = regnum;
1788 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1789
1790 if (!target_has_registers)
1791 error ("No registers.");
1792
1793 /* Normal systems don't optimize out things with register numbers. */
1794 if (optimized != NULL)
1795 *optimized = 0;
1796
1797 if (addrp) /* default assumption: not found in memory */
1798 *addrp = 0;
1799
1800 if (raw_buffer)
1801 memset (raw_buffer, 0, sizeof (raw_buffer));
1802
1803 /* We must do this here, before the following while loop changes
1804 frame, and makes it NULL. If this is a media register number,
1805 but we are in compact mode, it will become the corresponding
1806 compact pseudo register. If there is no corresponding compact
1807 pseudo-register what do we do?*/
50abf9e5 1808 media_mode = pc_is_isa32 (get_frame_pc (frame));
283150cd
EZ		 1809 live_regnum = translate_insn_rn (regnum, media_mode);
1810
1811 /* Note: since the current frame's registers could only have been
1812 saved by frames INTERIOR TO the current frame, we skip examining
1813 the current frame itself: otherwise, we would be getting the
1814 previous frame's registers which were saved by the current frame. */
1815
1816 while (frame && ((frame = frame->next) != NULL))
1817 {
50abf9e5 1818 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), frame->frame, frame->frame))
283150cd
EZ		 1819 {
1820 if (lval) /* found it in a CALL_DUMMY frame */
1821 *lval = not_lval;
1822 if (raw_buffer)
1823 memcpy (raw_buffer,
50abf9e5 1824 (deprecated_generic_find_dummy_frame (get_frame_pc (frame), frame->frame)
da130f98 1825 + REGISTER_BYTE (regnum)),
283150cd
EZ		 1826 REGISTER_RAW_SIZE (regnum));
1827 return;
1828 }
1829
1830 FRAME_INIT_SAVED_REGS (frame);
b2fb4676
AC		 1831 if (get_frame_saved_regs (frame) != NULL
1832 && get_frame_saved_regs (frame)[regnum] != 0)
283150cd
EZ		 1833 {
1834 if (lval) /* found it saved on the stack */
1835 *lval = lval_memory;
1836 if (regnum == SP_REGNUM)
1837 {
1838 if (raw_buffer) /* SP register treated specially */
1839 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum),
b2fb4676 1840 get_frame_saved_regs (frame)[regnum]);
283150cd
EZ		 1841 }
1842 else
1843 { /* any other register */
1844
1845 if (addrp)
b2fb4676 1846 *addrp = get_frame_saved_regs (frame)[regnum];
283150cd
EZ		 1847 if (raw_buffer)
1848 {
1849 int size;
1850 if (tdep->sh_abi == SH_ABI_32
1851 && (live_regnum == FP_REGNUM
1852 || live_regnum == tdep->PR_REGNUM))
1853 size = 4;
1854 else
1855 size = REGISTER_RAW_SIZE (live_regnum);
1856 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
b2fb4676 1857 read_memory (get_frame_saved_regs (frame)[regnum], raw_buffer, size);
283150cd 1858 else
b2fb4676 1859 read_memory (get_frame_saved_regs (frame)[regnum],
283150cd
EZ		 1860 raw_buffer
1861 + REGISTER_RAW_SIZE (live_regnum)
1862 - size,
1863 size);
1864 }
1865 }
1866 return;
1867 }
1868 }
1869
1870 /* If we get thru the loop to this point, it means the register was
1871 not saved in any frame. Return the actual live-register value. */
1872
1873 if (lval) /* found it in a live register */
1874 *lval = lval_register;
1875 if (addrp)
1876 *addrp = REGISTER_BYTE (live_regnum);
1877 if (raw_buffer)
4caf0990 1878 deprecated_read_register_gen (live_regnum, raw_buffer);
283150cd
EZ		 1879}
1880
cc17453a
EZ		 1881/* Extract from an array REGBUF containing the (raw) register state
1882 the address in which a function should return its structure value,
1883 as a CORE_ADDR (or an expression that can be used as one). */
b3df3fff 1884static CORE_ADDR
0c8053b6 1885sh_extract_struct_value_address (char *regbuf)
cc17453a
EZ		 1886{
1887 return (extract_address ((regbuf), REGISTER_RAW_SIZE (0)));
1888}
1889
283150cd
EZ		 1890static CORE_ADDR
1891sh64_extract_struct_value_address (char *regbuf)
1892{
1893 return (extract_address ((regbuf + REGISTER_BYTE (STRUCT_RETURN_REGNUM)),
1894 REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM)));
1895}
1896
cc17453a 1897static CORE_ADDR
fba45db2 1898sh_frame_saved_pc (struct frame_info *frame)
cc17453a
EZ		 1899{
1900 return ((frame)->extra_info->return_pc);
1901}
1902
c906108c
SS		 1903/* Discard from the stack the innermost frame,
1904 restoring all saved registers. */
cc17453a 1905static void
fba45db2 1906sh_pop_frame (void)
c906108c
SS		 1907{
1908 register struct frame_info *frame = get_current_frame ();
1909 register CORE_ADDR fp;
1910 register int regnum;
c906108c 1911
50abf9e5 1912 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), frame->frame, frame->frame))
c906108c
SS		 1913 generic_pop_dummy_frame ();
1914 else
c5aa993b 1915 {
c193f6ac 1916 fp = get_frame_base (frame);
cc17453a 1917 FRAME_INIT_SAVED_REGS (frame);
c906108c 1918
c5aa993b 1919 /* Copy regs from where they were saved in the frame */
cd4bffcf 1920 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
b2fb4676 1921 if (get_frame_saved_regs (frame)[regnum])
cd4bffcf 1922 write_register (regnum,
b2fb4676 1923 read_memory_integer (get_frame_saved_regs (frame)[regnum], 4));
c906108c 1924
cc17453a 1925 write_register (PC_REGNUM, frame->extra_info->return_pc);
c5aa993b
JM		 1926 write_register (SP_REGNUM, fp + 4);
1927 }
c906108c
SS		 1928 flush_cached_frames ();
1929}
1930
283150cd
EZ		 1931/* Used in the 'return' command. */
1932static void
1933sh64_pop_frame (void)
1934{
1935 register struct frame_info *frame = get_current_frame ();
1936 register CORE_ADDR fp;
1937 register int regnum;
1938 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1939
50abf9e5 1940 int media_mode = pc_is_isa32 (get_frame_pc (frame));
283150cd 1941
50abf9e5 1942 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), frame->frame, frame->frame))
283150cd
EZ		 1943 generic_pop_dummy_frame ();
1944 else
1945 {
c193f6ac 1946 fp = get_frame_base (frame);
283150cd
EZ		 1947 FRAME_INIT_SAVED_REGS (frame);
1948
1949 /* Copy regs from where they were saved in the frame */
1950 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
b2fb4676 1951 if (get_frame_saved_regs (frame)[regnum])
283150cd
EZ		 1952 {
1953 int size;
1954 if (tdep->sh_abi == SH_ABI_32
1955 && (regnum == FP_REGNUM
1956 || regnum == tdep->PR_REGNUM))
1957 size = 4;
1958 else
1959 size = REGISTER_RAW_SIZE (translate_insn_rn (regnum,
1960 media_mode));
1961 write_register (regnum,
b2fb4676 1962 read_memory_integer (get_frame_saved_regs (frame)[regnum],
283150cd
EZ		 1963 size));
1964 }
1965
1966 write_register (PC_REGNUM, frame->extra_info->return_pc);
1967 write_register (SP_REGNUM, fp + 8);
1968 }
1969 flush_cached_frames ();
1970}
1971
c906108c
SS		 1972/* Function: push_arguments
1973 Setup the function arguments for calling a function in the inferior.
1974
1975 On the Hitachi SH architecture, there are four registers (R4 to R7)
1976 which are dedicated for passing function arguments. Up to the first
1977 four arguments (depending on size) may go into these registers.
1978 The rest go on the stack.
1979
1980 Arguments that are smaller than 4 bytes will still take up a whole
1981 register or a whole 32-bit word on the stack, and will be
1982 right-justified in the register or the stack word. This includes
1983 chars, shorts, and small aggregate types.
1984
1985 Arguments that are larger than 4 bytes may be split between two or
1986 more registers. If there are not enough registers free, an argument
1987 may be passed partly in a register (or registers), and partly on the
1988 stack. This includes doubles, long longs, and larger aggregates.
1989 As far as I know, there is no upper limit to the size of aggregates
1990 that will be passed in this way; in other words, the convention of
1991 passing a pointer to a large aggregate instead of a copy is not used.
1992
1993 An exceptional case exists for struct arguments (and possibly other
1994 aggregates such as arrays) if the size is larger than 4 bytes but
1995 not a multiple of 4 bytes. In this case the argument is never split
1996 between the registers and the stack, but instead is copied in its
1997 entirety onto the stack, AND also copied into as many registers as
1998 there is room for. In other words, space in registers permitting,
1999 two copies of the same argument are passed in. As far as I can tell,
2000 only the one on the stack is used, although that may be a function
2001 of the level of compiler optimization. I suspect this is a compiler
2002 bug. Arguments of these odd sizes are left-justified within the
2003 word (as opposed to arguments smaller than 4 bytes, which are
2004 right-justified).
c5aa993b 2005
c906108c
SS		 2006 If the function is to return an aggregate type such as a struct, it
2007 is either returned in the normal return value register R0 (if its
2008 size is no greater than one byte), or else the caller must allocate
2009 space into which the callee will copy the return value (if the size
2010 is greater than one byte). In this case, a pointer to the return
2011 value location is passed into the callee in register R2, which does
2012 not displace any of the other arguments passed in via registers R4
2013 to R7. */
2014
cc17453a 2015static CORE_ADDR
34e9d9bb 2016sh_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
3bbfbb92 2017 int struct_return, CORE_ADDR struct_addr)
c906108c
SS		 2018{
2019 int stack_offset, stack_alloc;
2020 int argreg;
2021 int argnum;
2022 struct type *type;
2023 CORE_ADDR regval;
2024 char *val;
2025 char valbuf[4];
2026 int len;
2027 int odd_sized_struct;
f81353e4 2028 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
c906108c
SS		 2029
2030 /* first force sp to a 4-byte alignment */
2031 sp = sp & ~3;
2032
2033 /* The "struct return pointer" pseudo-argument has its own dedicated
2034 register */
2035 if (struct_return)
c5aa993b 2036 write_register (STRUCT_RETURN_REGNUM, struct_addr);
c906108c
SS		 2037
2038 /* Now make sure there's space on the stack */
cc17453a 2039 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
c5aa993b
JM		 2040 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
2041 sp -= stack_alloc; /* make room on stack for args */
c906108c 2042
c906108c
SS		 2043 /* Now load as many as possible of the first arguments into
2044 registers, and push the rest onto the stack. There are 16 bytes
2045 in four registers available. Loop thru args from first to last. */
2046
f81353e4 2047 argreg = tdep->ARG0_REGNUM;
c906108c
SS		 2048 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
2049 {
2050 type = VALUE_TYPE (args[argnum]);
c5aa993b
JM		 2051 len = TYPE_LENGTH (type);
2052 memset (valbuf, 0, sizeof (valbuf));
c906108c 2053 if (len < 4)
cc17453a
EZ		 2054 {
2055 /* value gets right-justified in the register or stack word */
7079c36c
CV		 2056 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2057 memcpy (valbuf + (4 - len),
2058 (char *) VALUE_CONTENTS (args[argnum]), len);
2059 else
2060 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
c5aa993b
JM		 2061 val = valbuf;
2062 }
c906108c 2063 else
c5aa993b 2064 val = (char *) VALUE_CONTENTS (args[argnum]);
c906108c
SS		 2065
2066 if (len > 4 && (len & 3) != 0)
c5aa993b
JM		 2067 odd_sized_struct = 1; /* such structs go entirely on stack */
2068 else
c906108c
SS		 2069 odd_sized_struct = 0;
2070 while (len > 0)
2071 {
f81353e4 2072 if (argreg > tdep->ARGLAST_REGNUM
3bbfbb92
EZ		 2073 || odd_sized_struct)
2074 {
2075 /* must go on the stack */
c906108c
SS		 2076 write_memory (sp + stack_offset, val, 4);
2077 stack_offset += 4;
2078 }
2079 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2080 That's because some *&^%$ things get passed on the stack
2081 AND in the registers! */
f81353e4 2082 if (argreg <= tdep->ARGLAST_REGNUM)
3bbfbb92
EZ		 2083 {
2084 /* there's room in a register */
c5aa993b 2085 regval = extract_address (val, REGISTER_RAW_SIZE (argreg));
c906108c
SS		 2086 write_register (argreg++, regval);
2087 }
2088 /* Store the value 4 bytes at a time. This means that things
2089 larger than 4 bytes may go partly in registers and partly
2090 on the stack. */
c5aa993b
JM		 2091 len -= REGISTER_RAW_SIZE (argreg);
2092 val += REGISTER_RAW_SIZE (argreg);
c906108c
SS		 2093 }
2094 }
2095 return sp;
2096}
2097
283150cd
EZ		 2098/* R2-R9 for integer types and integer equivalent (char, pointers) and
2099 non-scalar (struct, union) elements (even if the elements are
2100 floats).
2101 FR0-FR11 for single precision floating point (float)
2102 DR0-DR10 for double precision floating point (double)
2103
2104 If a float is argument number 3 (for instance) and arguments number
2105 1,2, and 4 are integer, the mapping will be:
2106 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
2107
2108 If a float is argument number 10 (for instance) and arguments number
2109 1 through 10 are integer, the mapping will be:
2110 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
2111 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
2112 I.e. there is hole in the stack.
2113
2114 Different rules apply for variable arguments functions, and for functions
2115 for which the prototype is not known. */
2116
2117static CORE_ADDR
2118sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
2119 int struct_return, CORE_ADDR struct_addr)
2120{
2121 int stack_offset, stack_alloc;
2122 int int_argreg;
2123 int float_argreg;
2124 int double_argreg;
2125 int float_arg_index = 0;
2126 int double_arg_index = 0;
2127 int argnum;
2128 struct type *type;
2129 CORE_ADDR regval;
2130 char *val;
2131 char valbuf[8];
2132 char valbuf_tmp[8];
2133 int len;
2134 int argreg_size;
2135 int fp_args[12];
2136 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2137
2138 memset (fp_args, 0, sizeof (fp_args));
2139
2140 /* first force sp to a 8-byte alignment */
2141 sp = sp & ~7;
2142
2143 /* The "struct return pointer" pseudo-argument has its own dedicated
2144 register */
2145
2146 if (struct_return)
2147 write_register (STRUCT_RETURN_REGNUM, struct_addr);
2148
2149 /* Now make sure there's space on the stack */
2150 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
2151 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7);
2152 sp -= stack_alloc; /* make room on stack for args */
2153
2154 /* Now load as many as possible of the first arguments into
2155 registers, and push the rest onto the stack. There are 64 bytes
2156 in eight registers available. Loop thru args from first to last. */
2157
2158 int_argreg = tdep->ARG0_REGNUM;
2159 float_argreg = FP0_REGNUM;
2160 double_argreg = tdep->DR0_REGNUM;
2161
2162 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
2163 {
2164 type = VALUE_TYPE (args[argnum]);
2165 len = TYPE_LENGTH (type);
2166 memset (valbuf, 0, sizeof (valbuf));
2167
2168 if (TYPE_CODE (type) != TYPE_CODE_FLT)
2169 {
2170 argreg_size = REGISTER_RAW_SIZE (int_argreg);
2171
2172 if (len < argreg_size)
2173 {
2174 /* value gets right-justified in the register or stack word */
2175 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2176 memcpy (valbuf + argreg_size - len,
2177 (char *) VALUE_CONTENTS (args[argnum]), len);
2178 else
2179 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
2180
2181 val = valbuf;
2182 }
2183 else
2184 val = (char *) VALUE_CONTENTS (args[argnum]);
2185
2186 while (len > 0)
2187 {
2188 if (int_argreg > tdep->ARGLAST_REGNUM)
2189 {
2190 /* must go on the stack */
2191 write_memory (sp + stack_offset, val, argreg_size);
2192 stack_offset += 8;/*argreg_size;*/
2193 }
2194 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2195 That's because some *&^%$ things get passed on the stack
2196 AND in the registers! */
2197 if (int_argreg <= tdep->ARGLAST_REGNUM)
2198 {
2199 /* there's room in a register */
2200 regval = extract_address (val, argreg_size);
2201 write_register (int_argreg, regval);
2202 }
2203 /* Store the value 8 bytes at a time. This means that
2204 things larger than 8 bytes may go partly in registers
2205 and partly on the stack. FIXME: argreg is incremented
2206 before we use its size. */
2207 len -= argreg_size;
2208 val += argreg_size;
2209 int_argreg++;
2210 }
2211 }
2212 else
2213 {
2214 val = (char *) VALUE_CONTENTS (args[argnum]);
2215 if (len == 4)
2216 {
2217 /* Where is it going to be stored? */
2218 while (fp_args[float_arg_index])
2219 float_arg_index ++;
2220
2221 /* Now float_argreg points to the register where it
2222 should be stored. Are we still within the allowed
2223 register set? */
2224 if (float_arg_index <= tdep->FLOAT_ARGLAST_REGNUM)
2225 {
2226 /* Goes in FR0...FR11 */
4caf0990
AC		 2227 deprecated_write_register_gen (FP0_REGNUM + float_arg_index,
2228 val);
283150cd
EZ		 2229 fp_args[float_arg_index] = 1;
2230 /* Skip the corresponding general argument register. */
2231 int_argreg ++;
2232 }
2233 else
2234 ;
2235 /* Store it as the integers, 8 bytes at the time, if
2236 necessary spilling on the stack. */
2237
2238 }
2239 else if (len == 8)
2240 {
2241 /* Where is it going to be stored? */
2242 while (fp_args[double_arg_index])
2243 double_arg_index += 2;
2244 /* Now double_argreg points to the register
2245 where it should be stored.
2246 Are we still within the allowed register set? */
2247 if (double_arg_index < tdep->FLOAT_ARGLAST_REGNUM)
2248 {
2249 /* Goes in DR0...DR10 */
2250 /* The numbering of the DRi registers is consecutive,
2251 i.e. includes odd numbers. */
2252 int double_register_offset = double_arg_index / 2;
2253 int regnum = tdep->DR0_REGNUM +
2254 double_register_offset;
2255#if 0
2256 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2257 {
2258 memset (valbuf_tmp, 0, sizeof (valbuf_tmp));
2259 REGISTER_CONVERT_TO_VIRTUAL (regnum,
2260 type, val, valbuf_tmp);
2261 val = valbuf_tmp;
2262 }
2263#endif
2264 /* Note: must use write_register_gen here instead
0818c12a
AC		 2265 of regcache_raw_write, because
2266 regcache_raw_write works only for real
2267 registers, not pseudo. write_register_gen will
2268 call the gdbarch function to do register
2269 writes, and that will properly know how to deal
2270 with pseudoregs. */
4caf0990 2271 deprecated_write_register_gen (regnum, val);
283150cd
EZ		 2272 fp_args[double_arg_index] = 1;
2273 fp_args[double_arg_index + 1] = 1;
2274 /* Skip the corresponding general argument register. */
2275 int_argreg ++;
2276 }
2277 else
2278 ;
2279 /* Store it as the integers, 8 bytes at the time, if
2280 necessary spilling on the stack. */
2281 }
2282 }
2283 }
2284 return sp;
2285}
2286
c906108c
SS		 2287/* Function: push_return_address (pc)
2288 Set up the return address for the inferior function call.
2289 Needed for targets where we don't actually execute a JSR/BSR instruction */
2290
cc17453a 2291static CORE_ADDR
fba45db2 2292sh_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
c906108c 2293{
283150cd
EZ		 2294 write_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM,
2295 CALL_DUMMY_ADDRESS ());
c906108c
SS		 2296 return sp;
2297}
2298
2299/* Function: fix_call_dummy
2300 Poke the callee function's address into the destination part of
2301 the CALL_DUMMY. The address is actually stored in a data word
2302 following the actualy CALL_DUMMY instructions, which will load
2303 it into a register using PC-relative addressing. This function
2304 expects the CALL_DUMMY to look like this:
2305
c5aa993b
JM		 2306 mov.w @(2,PC), R8
2307 jsr @R8
2308 nop
2309 trap
2310 <destination>
2311 */
c906108c
SS		 2312
2313#if 0
2314void
fba45db2 2315sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
ea7c478f 2316 struct value **args, struct type *type, int gcc_p)
c906108c
SS		 2317{
2318 *(unsigned long *) (dummy + 8) = fun;
2319}
2320#endif
2321
cc17453a
EZ		 2322/* Find a function's return value in the appropriate registers (in
2323 regbuf), and copy it into valbuf. Extract from an array REGBUF
2324 containing the (raw) register state a function return value of type
2325 TYPE, and copy that, in virtual format, into VALBUF. */
2326static void
fba45db2 2327sh_extract_return_value (struct type *type, char *regbuf, char *valbuf)
c906108c 2328{
cc17453a 2329 int len = TYPE_LENGTH (type);
3116c80a
EZ		 2330 int return_register = R0_REGNUM;
2331 int offset;
2332
cc17453a 2333 if (len <= 4)
3116c80a 2334 {
d7449b42 2335 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 2336 offset = REGISTER_BYTE (return_register) + 4 - len;
2337 else
2338 offset = REGISTER_BYTE (return_register);
2339 memcpy (valbuf, regbuf + offset, len);
2340 }
cc17453a 2341 else if (len <= 8)
3116c80a 2342 {
d7449b42 2343 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 2344 offset = REGISTER_BYTE (return_register) + 8 - len;
2345 else
2346 offset = REGISTER_BYTE (return_register);
2347 memcpy (valbuf, regbuf + offset, len);
2348 }
2349 else
2350 error ("bad size for return value");
2351}
2352
2353static void
2354sh3e_sh4_extract_return_value (struct type *type, char *regbuf, char *valbuf)
2355{
2356 int return_register;
2357 int offset;
2358 int len = TYPE_LENGTH (type);
2359
2360 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2361 return_register = FP0_REGNUM;
2362 else
2363 return_register = R0_REGNUM;
2364
2365 if (len == 8 && TYPE_CODE (type) == TYPE_CODE_FLT)
2366 {
2367 DOUBLEST val;
778eb05e 2368 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
3116c80a
EZ		 2369 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2370 (char *) regbuf + REGISTER_BYTE (return_register),
2371 &val);
2372 else
2373 floatformat_to_doublest (&floatformat_ieee_double_big,
2374 (char *) regbuf + REGISTER_BYTE (return_register),
2375 &val);
2376 store_floating (valbuf, len, val);
2377 }
2378 else if (len <= 4)
2379 {
d7449b42 2380 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 2381 offset = REGISTER_BYTE (return_register) + 4 - len;
2382 else
2383 offset = REGISTER_BYTE (return_register);
2384 memcpy (valbuf, regbuf + offset, len);
2385 }
2386 else if (len <= 8)
2387 {
d7449b42 2388 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 2389 offset = REGISTER_BYTE (return_register) + 8 - len;
2390 else
2391 offset = REGISTER_BYTE (return_register);
2392 memcpy (valbuf, regbuf + offset, len);
2393 }
cc17453a
EZ		 2394 else
2395 error ("bad size for return value");
2396}
c906108c 2397
283150cd
EZ		 2398static void
2399sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf)
2400{
2401 int offset;
2402 int return_register;
2403 int len = TYPE_LENGTH (type);
2404 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2405
2406 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2407 {
2408 if (len == 4)
2409 {
2410 /* Return value stored in FP0_REGNUM */
2411 return_register = FP0_REGNUM;
2412 offset = REGISTER_BYTE (return_register);
2413 memcpy (valbuf, (char *) regbuf + offset, len);
2414 }
2415 else if (len == 8)
2416 {
2417 /* return value stored in DR0_REGNUM */
2418 DOUBLEST val;
2419
2420 return_register = tdep->DR0_REGNUM;
2421 offset = REGISTER_BYTE (return_register);
2422
2423 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2424 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2425 (char *) regbuf + offset, &val);
2426 else
2427 floatformat_to_doublest (&floatformat_ieee_double_big,
2428 (char *) regbuf + offset, &val);
2429 store_floating (valbuf, len, val);
2430 }
2431 }
2432 else
2433 {
2434 if (len <= 8)
2435 {
2436 /* Result is in register 2. If smaller than 8 bytes, it is padded
2437 at the most significant end. */
2438 return_register = tdep->RETURN_REGNUM;
2439 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2440 offset = REGISTER_BYTE (return_register) +
2441 REGISTER_RAW_SIZE (return_register) - len;
2442 else
2443 offset = REGISTER_BYTE (return_register);
2444 memcpy (valbuf, (char *) regbuf + offset, len);
2445 }
2446 else
2447 error ("bad size for return value");
2448 }
2449}
2450
cc17453a
EZ		 2451/* Write into appropriate registers a function return value
2452 of type TYPE, given in virtual format.
2453 If the architecture is sh4 or sh3e, store a function's return value
2454 in the R0 general register or in the FP0 floating point register,
2455 depending on the type of the return value. In all the other cases
3bbfbb92 2456 the result is stored in r0, left-justified. */
cc17453a
EZ		 2457static void
2458sh_default_store_return_value (struct type *type, char *valbuf)
2459{
d19b71be
MS		 2460 char buf[32]; /* more than enough... */
2461
2462 if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (R0_REGNUM))
2463 {
2464 /* Add leading zeros to the value. */
2465 memset (buf, 0, REGISTER_RAW_SIZE (R0_REGNUM));
7079c36c
CV		 2466 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2467 memcpy (buf + REGISTER_RAW_SIZE (R0_REGNUM) - TYPE_LENGTH (type),
2468 valbuf, TYPE_LENGTH (type));
2469 else
2470 memcpy (buf, valbuf, TYPE_LENGTH (type));
73937e03
AC		 2471 deprecated_write_register_bytes (REGISTER_BYTE (R0_REGNUM), buf,
2472 REGISTER_RAW_SIZE (R0_REGNUM));
d19b71be
MS		 2473 }
2474 else
73937e03
AC		 2475 deprecated_write_register_bytes (REGISTER_BYTE (R0_REGNUM), valbuf,
2476 TYPE_LENGTH (type));
cc17453a 2477}
c906108c 2478
cc17453a
EZ		 2479static void
2480sh3e_sh4_store_return_value (struct type *type, char *valbuf)
2481{
2482 if (TYPE_CODE (type) == TYPE_CODE_FLT)
73937e03
AC		 2483 deprecated_write_register_bytes (REGISTER_BYTE (FP0_REGNUM),
2484 valbuf, TYPE_LENGTH (type));
cc17453a 2485 else
d19b71be 2486 sh_default_store_return_value (type, valbuf);
c906108c
SS		 2487}
2488
283150cd
EZ		 2489static void
2490sh64_store_return_value (struct type *type, char *valbuf)
2491{
2492 char buf[64]; /* more than enough... */
2493 int len = TYPE_LENGTH (type);
2494
2495 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2496 {
2497 if (len == 4)
2498 {
2499 /* Return value stored in FP0_REGNUM */
4caf0990 2500 deprecated_write_register_gen (FP0_REGNUM, valbuf);
283150cd
EZ		 2501 }
2502 if (len == 8)
2503 {
2504 /* return value stored in DR0_REGNUM */
2505 /* FIXME: Implement */
2506 }
2507 }
2508 else
2509 {
2510 int return_register = gdbarch_tdep (current_gdbarch)->RETURN_REGNUM;
2511 int offset = 0;
2512
2513 if (len <= REGISTER_RAW_SIZE (return_register))
2514 {
2515 /* Pad with zeros. */
2516 memset (buf, 0, REGISTER_RAW_SIZE (return_register));
2517 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2518 offset = 0; /*REGISTER_RAW_SIZE (return_register) - len;*/
2519 else
2520 offset = REGISTER_RAW_SIZE (return_register) - len;
2521
2522 memcpy (buf + offset, valbuf, len);
4caf0990 2523 deprecated_write_register_gen (return_register, buf);
283150cd
EZ		 2524 }
2525 else
4caf0990 2526 deprecated_write_register_gen (return_register, valbuf);
283150cd
EZ		 2527 }
2528}
2529
c906108c
SS		 2530/* Print the registers in a form similar to the E7000 */
2531
2532static void
fba45db2 2533sh_generic_show_regs (void)
c906108c 2534{
f81353e4
EZ		 2535 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2536
cc17453a
EZ		 2537 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2538 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 2539 (long) read_register (tdep->SR_REGNUM),
2540 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 2541 (long) read_register (MACH_REGNUM),
2542 (long) read_register (MACL_REGNUM));
2543
2544 printf_filtered ("GBR=%08lx VBR=%08lx",
2545 (long) read_register (GBR_REGNUM),
2546 (long) read_register (VBR_REGNUM));
2547
2548 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2549 (long) read_register (0),
2550 (long) read_register (1),
2551 (long) read_register (2),
2552 (long) read_register (3),
2553 (long) read_register (4),
2554 (long) read_register (5),
2555 (long) read_register (6),
2556 (long) read_register (7));
2557 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2558 (long) read_register (8),
2559 (long) read_register (9),
2560 (long) read_register (10),
2561 (long) read_register (11),
2562 (long) read_register (12),
2563 (long) read_register (13),
2564 (long) read_register (14),
2565 (long) read_register (15));
2566}
c906108c 2567
cc17453a 2568static void
fba45db2 2569sh3_show_regs (void)
cc17453a 2570{
f81353e4
EZ		 2571 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2572
d4f3574e
SS		 2573 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2574 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 2575 (long) read_register (tdep->SR_REGNUM),
2576 (long) read_register (tdep->PR_REGNUM),
d4f3574e
SS		 2577 (long) read_register (MACH_REGNUM),
2578 (long) read_register (MACL_REGNUM));
2579
2580 printf_filtered ("GBR=%08lx VBR=%08lx",
2581 (long) read_register (GBR_REGNUM),
2582 (long) read_register (VBR_REGNUM));
cc17453a 2583 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 2584 (long) read_register (tdep->SSR_REGNUM),
2585 (long) read_register (tdep->SPC_REGNUM));
c906108c 2586
d4f3574e
SS		 2587 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2588 (long) read_register (0),
2589 (long) read_register (1),
2590 (long) read_register (2),
2591 (long) read_register (3),
2592 (long) read_register (4),
2593 (long) read_register (5),
2594 (long) read_register (6),
2595 (long) read_register (7));
2596 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2597 (long) read_register (8),
2598 (long) read_register (9),
2599 (long) read_register (10),
2600 (long) read_register (11),
2601 (long) read_register (12),
2602 (long) read_register (13),
2603 (long) read_register (14),
2604 (long) read_register (15));
c906108c
SS		 2605}
2606
53116e27 2607
cc17453a 2608static void
fba45db2 2609sh3e_show_regs (void)
cc17453a 2610{
f81353e4
EZ		 2611 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2612
cc17453a
EZ		 2613 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2614 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 2615 (long) read_register (tdep->SR_REGNUM),
2616 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 2617 (long) read_register (MACH_REGNUM),
2618 (long) read_register (MACL_REGNUM));
2619
2620 printf_filtered ("GBR=%08lx VBR=%08lx",
2621 (long) read_register (GBR_REGNUM),
2622 (long) read_register (VBR_REGNUM));
2623 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 2624 (long) read_register (tdep->SSR_REGNUM),
2625 (long) read_register (tdep->SPC_REGNUM));
cc17453a 2626 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
f81353e4
EZ		 2627 (long) read_register (tdep->FPUL_REGNUM),
2628 (long) read_register (tdep->FPSCR_REGNUM));
c906108c 2629
cc17453a
EZ		 2630 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2631 (long) read_register (0),
2632 (long) read_register (1),
2633 (long) read_register (2),
2634 (long) read_register (3),
2635 (long) read_register (4),
2636 (long) read_register (5),
2637 (long) read_register (6),
2638 (long) read_register (7));
2639 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2640 (long) read_register (8),
2641 (long) read_register (9),
2642 (long) read_register (10),
2643 (long) read_register (11),
2644 (long) read_register (12),
2645 (long) read_register (13),
2646 (long) read_register (14),
2647 (long) read_register (15));
2648
2649 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2650 (long) read_register (FP0_REGNUM + 0),
2651 (long) read_register (FP0_REGNUM + 1),
2652 (long) read_register (FP0_REGNUM + 2),
2653 (long) read_register (FP0_REGNUM + 3),
2654 (long) read_register (FP0_REGNUM + 4),
2655 (long) read_register (FP0_REGNUM + 5),
2656 (long) read_register (FP0_REGNUM + 6),
2657 (long) read_register (FP0_REGNUM + 7));
2658 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2659 (long) read_register (FP0_REGNUM + 8),
2660 (long) read_register (FP0_REGNUM + 9),
2661 (long) read_register (FP0_REGNUM + 10),
2662 (long) read_register (FP0_REGNUM + 11),
2663 (long) read_register (FP0_REGNUM + 12),
2664 (long) read_register (FP0_REGNUM + 13),
2665 (long) read_register (FP0_REGNUM + 14),
2666 (long) read_register (FP0_REGNUM + 15));
2667}
2668
2669static void
fba45db2 2670sh3_dsp_show_regs (void)
c906108c 2671{
f81353e4
EZ		 2672 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2673
cc17453a
EZ		 2674 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2675 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 2676 (long) read_register (tdep->SR_REGNUM),
2677 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 2678 (long) read_register (MACH_REGNUM),
2679 (long) read_register (MACL_REGNUM));
c906108c 2680
cc17453a
EZ		 2681 printf_filtered ("GBR=%08lx VBR=%08lx",
2682 (long) read_register (GBR_REGNUM),
2683 (long) read_register (VBR_REGNUM));
2684
2685 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 2686 (long) read_register (tdep->SSR_REGNUM),
2687 (long) read_register (tdep->SPC_REGNUM));
cc17453a
EZ		 2688
2689 printf_filtered (" DSR=%08lx",
f81353e4 2690 (long) read_register (tdep->DSR_REGNUM));
cc17453a
EZ		 2691
2692 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2693 (long) read_register (0),
2694 (long) read_register (1),
2695 (long) read_register (2),
2696 (long) read_register (3),
2697 (long) read_register (4),
2698 (long) read_register (5),
2699 (long) read_register (6),
2700 (long) read_register (7));
2701 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2702 (long) read_register (8),
2703 (long) read_register (9),
2704 (long) read_register (10),
2705 (long) read_register (11),
2706 (long) read_register (12),
2707 (long) read_register (13),
2708 (long) read_register (14),
2709 (long) read_register (15));
2710
2711 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
f81353e4
EZ		 2712 (long) read_register (tdep->A0G_REGNUM) & 0xff,
2713 (long) read_register (tdep->A0_REGNUM),
2714 (long) read_register (tdep->M0_REGNUM),
2715 (long) read_register (tdep->X0_REGNUM),
2716 (long) read_register (tdep->Y0_REGNUM),
2717 (long) read_register (tdep->RS_REGNUM),
2718 (long) read_register (tdep->MOD_REGNUM));
cc17453a 2719 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
f81353e4
EZ		 2720 (long) read_register (tdep->A1G_REGNUM) & 0xff,
2721 (long) read_register (tdep->A1_REGNUM),
2722 (long) read_register (tdep->M1_REGNUM),
2723 (long) read_register (tdep->X1_REGNUM),
2724 (long) read_register (tdep->Y1_REGNUM),
2725 (long) read_register (tdep->RE_REGNUM));
c906108c
SS		 2726}
2727
cc17453a 2728static void
fba45db2 2729sh4_show_regs (void)
cc17453a 2730{
f81353e4
EZ		 2731 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2732
2733 int pr = read_register (tdep->FPSCR_REGNUM) & 0x80000;
cc17453a
EZ		 2734 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2735 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 2736 (long) read_register (tdep->SR_REGNUM),
2737 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 2738 (long) read_register (MACH_REGNUM),
2739 (long) read_register (MACL_REGNUM));
2740
2741 printf_filtered ("GBR=%08lx VBR=%08lx",
2742 (long) read_register (GBR_REGNUM),
2743 (long) read_register (VBR_REGNUM));
2744 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 2745 (long) read_register (tdep->SSR_REGNUM),
2746 (long) read_register (tdep->SPC_REGNUM));
cc17453a 2747 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
f81353e4
EZ		 2748 (long) read_register (tdep->FPUL_REGNUM),
2749 (long) read_register (tdep->FPSCR_REGNUM));
cc17453a
EZ		 2750
2751 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2752 (long) read_register (0),
2753 (long) read_register (1),
2754 (long) read_register (2),
2755 (long) read_register (3),
2756 (long) read_register (4),
2757 (long) read_register (5),
2758 (long) read_register (6),
2759 (long) read_register (7));
2760 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2761 (long) read_register (8),
2762 (long) read_register (9),
2763 (long) read_register (10),
2764 (long) read_register (11),
2765 (long) read_register (12),
2766 (long) read_register (13),
2767 (long) read_register (14),
2768 (long) read_register (15));
2769
2770 printf_filtered ((pr
2771 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2772 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2773 (long) read_register (FP0_REGNUM + 0),
2774 (long) read_register (FP0_REGNUM + 1),
2775 (long) read_register (FP0_REGNUM + 2),
2776 (long) read_register (FP0_REGNUM + 3),
2777 (long) read_register (FP0_REGNUM + 4),
2778 (long) read_register (FP0_REGNUM + 5),
2779 (long) read_register (FP0_REGNUM + 6),
2780 (long) read_register (FP0_REGNUM + 7));
2781 printf_filtered ((pr
2782 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2783 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2784 (long) read_register (FP0_REGNUM + 8),
2785 (long) read_register (FP0_REGNUM + 9),
2786 (long) read_register (FP0_REGNUM + 10),
2787 (long) read_register (FP0_REGNUM + 11),
2788 (long) read_register (FP0_REGNUM + 12),
2789 (long) read_register (FP0_REGNUM + 13),
2790 (long) read_register (FP0_REGNUM + 14),
2791 (long) read_register (FP0_REGNUM + 15));
2792}
2793
2794static void
fba45db2 2795sh_dsp_show_regs (void)
cc17453a 2796{
f81353e4
EZ		 2797 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2798
cc17453a
EZ		 2799 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2800 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 2801 (long) read_register (tdep->SR_REGNUM),
2802 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 2803 (long) read_register (MACH_REGNUM),
2804 (long) read_register (MACL_REGNUM));
2805
2806 printf_filtered ("GBR=%08lx VBR=%08lx",
2807 (long) read_register (GBR_REGNUM),
2808 (long) read_register (VBR_REGNUM));
2809
2810 printf_filtered (" DSR=%08lx",
f81353e4 2811 (long) read_register (tdep->DSR_REGNUM));
cc17453a
EZ		 2812
2813 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2814 (long) read_register (0),
2815 (long) read_register (1),
2816 (long) read_register (2),
2817 (long) read_register (3),
2818 (long) read_register (4),
2819 (long) read_register (5),
2820 (long) read_register (6),
2821 (long) read_register (7));
2822 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2823 (long) read_register (8),
2824 (long) read_register (9),
2825 (long) read_register (10),
2826 (long) read_register (11),
2827 (long) read_register (12),
2828 (long) read_register (13),
2829 (long) read_register (14),
2830 (long) read_register (15));
2831
2832 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
f81353e4
EZ		 2833 (long) read_register (tdep->A0G_REGNUM) & 0xff,
2834 (long) read_register (tdep->A0_REGNUM),
2835 (long) read_register (tdep->M0_REGNUM),
2836 (long) read_register (tdep->X0_REGNUM),
2837 (long) read_register (tdep->Y0_REGNUM),
2838 (long) read_register (tdep->RS_REGNUM),
2839 (long) read_register (tdep->MOD_REGNUM));
cc17453a 2840 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
f81353e4
EZ		 2841 (long) read_register (tdep->A1G_REGNUM) & 0xff,
2842 (long) read_register (tdep->A1_REGNUM),
2843 (long) read_register (tdep->M1_REGNUM),
2844 (long) read_register (tdep->X1_REGNUM),
2845 (long) read_register (tdep->Y1_REGNUM),
2846 (long) read_register (tdep->RE_REGNUM));
cc17453a
EZ		 2847}
2848
283150cd
EZ		 2849static void
2850sh64_show_media_regs (void)
2851{
2852 int i;
2853 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2854
2855 printf_filtered ("PC=%s SR=%016llx \n",
2856 paddr (read_register (PC_REGNUM)),
2857 (long long) read_register (tdep->SR_REGNUM));
2858
2859 printf_filtered ("SSR=%016llx SPC=%016llx \n",
2860 (long long) read_register (tdep->SSR_REGNUM),
2861 (long long) read_register (tdep->SPC_REGNUM));
2862 printf_filtered ("FPSCR=%016lx\n ",
2863 (long) read_register (tdep->FPSCR_REGNUM));
2864
2865 for (i = 0; i < 64; i = i + 4)
2866 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
2867 i, i + 3,
2868 (long long) read_register (i + 0),
2869 (long long) read_register (i + 1),
2870 (long long) read_register (i + 2),
2871 (long long) read_register (i + 3));
2872
2873 printf_filtered ("\n");
2874
2875 for (i = 0; i < 64; i = i + 8)
2876 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2877 i, i + 7,
2878 (long) read_register (FP0_REGNUM + i + 0),
2879 (long) read_register (FP0_REGNUM + i + 1),
2880 (long) read_register (FP0_REGNUM + i + 2),
2881 (long) read_register (FP0_REGNUM + i + 3),
2882 (long) read_register (FP0_REGNUM + i + 4),
2883 (long) read_register (FP0_REGNUM + i + 5),
2884 (long) read_register (FP0_REGNUM + i + 6),
2885 (long) read_register (FP0_REGNUM + i + 7));
2886}
2887
2888static void
2889sh64_show_compact_regs (void)
2890{
2891 int i;
2892 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2893
2894 printf_filtered ("PC=%s \n",
2895 paddr (read_register (tdep->PC_C_REGNUM)));
2896
2897 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
2898 (long) read_register (tdep->GBR_C_REGNUM),
2899 (long) read_register (tdep->MACH_C_REGNUM),
2900 (long) read_register (tdep->MACL_C_REGNUM),
2901 (long) read_register (tdep->PR_C_REGNUM),
2902 (long) read_register (tdep->T_C_REGNUM));
2903 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
2904 (long) read_register (tdep->FPSCR_REGNUM),
2905 (long) read_register (tdep->FPUL_REGNUM));
2906
2907 for (i = 0; i < 16; i = i + 4)
2908 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
2909 i, i + 3,
2910 (long) read_register (i + 0),
2911 (long) read_register (i + 1),
2912 (long) read_register (i + 2),
2913 (long) read_register (i + 3));
2914
2915 printf_filtered ("\n");
2916
2917 for (i = 0; i < 16; i = i + 8)
2918 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2919 i, i + 7,
2920 (long) read_register (FP0_REGNUM + i + 0),
2921 (long) read_register (FP0_REGNUM + i + 1),
2922 (long) read_register (FP0_REGNUM + i + 2),
2923 (long) read_register (FP0_REGNUM + i + 3),
2924 (long) read_register (FP0_REGNUM + i + 4),
2925 (long) read_register (FP0_REGNUM + i + 5),
2926 (long) read_register (FP0_REGNUM + i + 6),
2927 (long) read_register (FP0_REGNUM + i + 7));
2928}
2929
2930/*FIXME!!! This only shows the registers for shmedia, excluding the
2931 pseudo registers. */
2932static void
2933sh64_show_regs (void)
2934{
50abf9e5 2935 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
283150cd
EZ		 2936 sh64_show_media_regs ();
2937 else
2938 sh64_show_compact_regs ();
2939}
2940
53116e27
EZ		 2941void sh_show_regs_command (char *args, int from_tty)
2942{
2943 if (sh_show_regs)
2944 (*sh_show_regs)();
2945}
2946
cc17453a
EZ		 2947/* Index within `registers' of the first byte of the space for
2948 register N. */
2949static int
fba45db2 2950sh_default_register_byte (int reg_nr)
8db62801 2951{
cc17453a
EZ		 2952 return (reg_nr * 4);
2953}
2954
53116e27 2955static int
fba45db2 2956sh_sh4_register_byte (int reg_nr)
53116e27 2957{
f81353e4
EZ		 2958 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2959
2960 if (reg_nr >= tdep->DR0_REGNUM
2961 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27 2962 return (dr_reg_base_num (reg_nr) * 4);
f81353e4
EZ		 2963 else if (reg_nr >= tdep->FV0_REGNUM
2964 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 2965 return (fv_reg_base_num (reg_nr) * 4);
2966 else
2967 return (reg_nr * 4);
2968}
2969
283150cd
EZ		 2970/* *INDENT-OFF* */
2971/*
2972 SH MEDIA MODE (ISA 32)
2973 general registers (64-bit) 0-63
29740 r0, r1, r2, r3, r4, r5, r6, r7,
297564 r8, r9, r10, r11, r12, r13, r14, r15,
2976128 r16, r17, r18, r19, r20, r21, r22, r23,
2977192 r24, r25, r26, r27, r28, r29, r30, r31,
2978256 r32, r33, r34, r35, r36, r37, r38, r39,
2979320 r40, r41, r42, r43, r44, r45, r46, r47,
2980384 r48, r49, r50, r51, r52, r53, r54, r55,
2981448 r56, r57, r58, r59, r60, r61, r62, r63,
2982
2983 pc (64-bit) 64
2984512 pc,
2985
2986 status reg., saved status reg., saved pc reg. (64-bit) 65-67
2987520 sr, ssr, spc,
2988
2989 target registers (64-bit) 68-75
2990544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
2991
2992 floating point state control register (32-bit) 76
2993608 fpscr,
2994
2995 single precision floating point registers (32-bit) 77-140
2996612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
2997644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
2998676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
2999708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
3000740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
3001772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
3002804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
3003836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
3004
3005TOTAL SPACE FOR REGISTERS: 868 bytes
3006
3007From here on they are all pseudo registers: no memory allocated.
3008REGISTER_BYTE returns the register byte for the base register.
3009
3010 double precision registers (pseudo) 141-172
3011 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
3012 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
3013 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
3014 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
3015
3016 floating point pairs (pseudo) 173-204
3017 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
3018 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
3019 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
3020 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
3021
3022 floating point vectors (4 floating point regs) (pseudo) 205-220
3023 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
3024 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
3025
3026 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
3027 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
3028 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
3029 pc_c,
3030 gbr_c, mach_c, macl_c, pr_c, t_c,
3031 fpscr_c, fpul_c,
3032 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
3033 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
3034 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
3035 fv0_c, fv4_c, fv8_c, fv12_c
3036*/
3037/* *INDENT-ON* */
3038static int
3039sh_sh64_register_byte (int reg_nr)
3040{
3041 int base_regnum = -1;
3042 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3043
3044 /* If it is a pseudo register, get the number of the first floating
3045 point register that is part of it. */
3046 if (reg_nr >= tdep->DR0_REGNUM
3047 && reg_nr <= tdep->DR_LAST_REGNUM)
3048 base_regnum = dr_reg_base_num (reg_nr);
3049
3050 else if (reg_nr >= tdep->FPP0_REGNUM
3051 && reg_nr <= tdep->FPP_LAST_REGNUM)
3052 base_regnum = fpp_reg_base_num (reg_nr);
3053
3054 else if (reg_nr >= tdep->FV0_REGNUM
3055 && reg_nr <= tdep->FV_LAST_REGNUM)
3056 base_regnum = fv_reg_base_num (reg_nr);
3057
3058 /* sh compact pseudo register. FPSCR is a pathological case, need to
3059 treat it as special. */
3060 else if ((reg_nr >= tdep->R0_C_REGNUM
3061 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3062 && reg_nr != tdep->FPSCR_C_REGNUM)
3063 base_regnum = sh64_compact_reg_base_num (reg_nr);
3064
3065 /* Now return the offset in bytes within the register cache. */
3066 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
3067 if (reg_nr >= tdep->DR0_REGNUM
3068 && reg_nr <= tdep->FV_LAST_REGNUM)
3069 return (base_regnum - FP0_REGNUM + 1) * 4
3070 + (tdep->TR7_REGNUM + 1) * 8;
3071
3072 /* sh compact pseudo register: general register */
3073 if ((reg_nr >= tdep->R0_C_REGNUM
3074 && reg_nr <= tdep->R_LAST_C_REGNUM))
3075 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3076 ? base_regnum * 8 + 4
3077 : base_regnum * 8);
3078
3079 /* sh compact pseudo register: */
3080 if (reg_nr == tdep->PC_C_REGNUM
3081 || reg_nr == tdep->GBR_C_REGNUM
3082 || reg_nr == tdep->MACL_C_REGNUM
3083 || reg_nr == tdep->PR_C_REGNUM)
3084 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3085 ? base_regnum * 8 + 4
3086 : base_regnum * 8);
3087
3088 if (reg_nr == tdep->MACH_C_REGNUM)
3089 return base_regnum * 8;
3090
3091 if (reg_nr == tdep->T_C_REGNUM)
3092 return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */
3093
3094 /* sh compact pseudo register: floating point register */
3095 else if (reg_nr >=tdep->FP0_C_REGNUM
3096 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3097 return (base_regnum - FP0_REGNUM) * 4
3098 + (tdep->TR7_REGNUM + 1) * 8 + 4;
3099
3100 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3101 /* This is complicated, for now return the beginning of the
3102 architectural FPSCR register. */
3103 return (tdep->TR7_REGNUM + 1) * 8;
3104
3105 else if (reg_nr == tdep->FPUL_C_REGNUM)
3106 return ((base_regnum - FP0_REGNUM) * 4 +
3107 (tdep->TR7_REGNUM + 1) * 8 + 4);
3108
3109 /* It is not a pseudo register. */
3110 /* It is a 64 bit register. */
3111 else if (reg_nr <= tdep->TR7_REGNUM)
3112 return reg_nr * 8;
3113
3114 /* It is a 32 bit register. */
3115 else
3116 if (reg_nr == tdep->FPSCR_REGNUM)
3117 return (tdep->FPSCR_REGNUM * 8);
3118
3119 /* It is floating point 32-bit register */
3120 else
3121 return ((tdep->TR7_REGNUM + 1) * 8
3122 + (reg_nr - FP0_REGNUM + 1) * 4);
3123}
3124
cc17453a
EZ		 3125/* Number of bytes of storage in the actual machine representation for
3126 register REG_NR. */
3127static int
fba45db2 3128sh_default_register_raw_size (int reg_nr)
cc17453a
EZ		 3129{
3130 return 4;
3131}
3132
53116e27 3133static int
fba45db2 3134sh_sh4_register_raw_size (int reg_nr)
53116e27 3135{
f81353e4
EZ		 3136 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3137
3138 if (reg_nr >= tdep->DR0_REGNUM
3139 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27 3140 return 8;
f81353e4
EZ		 3141 else if (reg_nr >= tdep->FV0_REGNUM
3142 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 3143 return 16;
3144 else
3145 return 4;
3146}
3147
283150cd
EZ		 3148static int
3149sh_sh64_register_raw_size (int reg_nr)
3150{
3151 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3152
3153 if ((reg_nr >= tdep->DR0_REGNUM
3154 && reg_nr <= tdep->DR_LAST_REGNUM)
3155 || (reg_nr >= tdep->FPP0_REGNUM
3156 && reg_nr <= tdep->FPP_LAST_REGNUM)
3157 || (reg_nr >= tdep->DR0_C_REGNUM
3158 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3159 || (reg_nr <= tdep->TR7_REGNUM))
3160 return 8;
3161
3162 else if ((reg_nr >= tdep->FV0_REGNUM
3163 && reg_nr <= tdep->FV_LAST_REGNUM)
3164 || (reg_nr >= tdep->FV0_C_REGNUM
3165 && reg_nr <= tdep->FV_LAST_C_REGNUM))
3166 return 16;
3167
3168 else /* this covers also the 32-bit SH compact registers. */
3169 return 4;
3170}
3171
cc17453a
EZ		 3172/* Number of bytes of storage in the program's representation
3173 for register N. */
3174static int
fba45db2 3175sh_register_virtual_size (int reg_nr)
cc17453a
EZ		 3176{
3177 return 4;
3178}
3179
283150cd
EZ		 3180/* ??????? FIXME */
3181static int
3182sh_sh64_register_virtual_size (int reg_nr)
3183{
3184 if (reg_nr >= FP0_REGNUM
3185 && reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM)
3186 return 4;
3187 else
3188 return 8;
3189}
3190
cc17453a
EZ		 3191/* Return the GDB type object for the "standard" data type
3192 of data in register N. */
cc17453a 3193static struct type *
fba45db2 3194sh_sh3e_register_virtual_type (int reg_nr)
cc17453a 3195{
f81353e4
EZ		 3196 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3197
cc17453a 3198 if ((reg_nr >= FP0_REGNUM
f81353e4
EZ		 3199 && (reg_nr <= tdep->FP_LAST_REGNUM))
3200 || (reg_nr == tdep->FPUL_REGNUM))
cc17453a 3201 return builtin_type_float;
8db62801 3202 else
cc17453a
EZ		 3203 return builtin_type_int;
3204}
3205
7f4dbe94
EZ		 3206static struct type *
3207sh_sh4_build_float_register_type (int high)
3208{
3209 struct type *temp;
3210
3211 temp = create_range_type (NULL, builtin_type_int, 0, high);
3212 return create_array_type (NULL, builtin_type_float, temp);
3213}
3214
53116e27 3215static struct type *
fba45db2 3216sh_sh4_register_virtual_type (int reg_nr)
53116e27 3217{
f81353e4
EZ		 3218 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3219
53116e27 3220 if ((reg_nr >= FP0_REGNUM
f81353e4
EZ		 3221 && (reg_nr <= tdep->FP_LAST_REGNUM))
3222 || (reg_nr == tdep->FPUL_REGNUM))
53116e27 3223 return builtin_type_float;
f81353e4
EZ		 3224 else if (reg_nr >= tdep->DR0_REGNUM
3225 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27 3226 return builtin_type_double;
f81353e4
EZ		 3227 else if (reg_nr >= tdep->FV0_REGNUM
3228 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 3229 return sh_sh4_build_float_register_type (3);
3230 else
3231 return builtin_type_int;
3232}
3233
283150cd
EZ		 3234static struct type *
3235sh_sh64_register_virtual_type (int reg_nr)
3236{
3237 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3238
3239 if ((reg_nr >= FP0_REGNUM
3240 && reg_nr <= tdep->FP_LAST_REGNUM)
3241 || (reg_nr >= tdep->FP0_C_REGNUM
3242 && reg_nr <= tdep->FP_LAST_C_REGNUM))
3243 return builtin_type_float;
3244 else if ((reg_nr >= tdep->DR0_REGNUM
3245 && reg_nr <= tdep->DR_LAST_REGNUM)
3246 || (reg_nr >= tdep->DR0_C_REGNUM
3247 && reg_nr <= tdep->DR_LAST_C_REGNUM))
3248 return builtin_type_double;
3249 else if (reg_nr >= tdep->FPP0_REGNUM
3250 && reg_nr <= tdep->FPP_LAST_REGNUM)
3251 return sh_sh4_build_float_register_type (1);
3252 else if ((reg_nr >= tdep->FV0_REGNUM
3253 && reg_nr <= tdep->FV_LAST_REGNUM)
3254 ||(reg_nr >= tdep->FV0_C_REGNUM
3255 && reg_nr <= tdep->FV_LAST_C_REGNUM))
3256 return sh_sh4_build_float_register_type (3);
3257 else if (reg_nr == tdep->FPSCR_REGNUM)
3258 return builtin_type_int;
3259 else if (reg_nr >= tdep->R0_C_REGNUM
3260 && reg_nr < tdep->FP0_C_REGNUM)
3261 return builtin_type_int;
3262 else
3263 return builtin_type_long_long;
3264}
3265
cc17453a 3266static struct type *
fba45db2 3267sh_default_register_virtual_type (int reg_nr)
cc17453a
EZ		 3268{
3269 return builtin_type_int;
3270}
3271
fb409745
EZ		 3272/* On the sh4, the DRi pseudo registers are problematic if the target
3273 is little endian. When the user writes one of those registers, for
3274 instance with 'ser var $dr0=1', we want the double to be stored
3275 like this:
3276 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3277 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3278
3279 This corresponds to little endian byte order & big endian word
3280 order. However if we let gdb write the register w/o conversion, it
3281 will write fr0 and fr1 this way:
3282 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3283 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3284 because it will consider fr0 and fr1 as a single LE stretch of memory.
3285
3286 To achieve what we want we must force gdb to store things in
3287 floatformat_ieee_double_littlebyte_bigword (which is defined in
3288 include/floatformat.h and libiberty/floatformat.c.
3289
3290 In case the target is big endian, there is no problem, the
3291 raw bytes will look like:
3292 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
3293 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3294
3295 The other pseudo registers (the FVs) also don't pose a problem
3296 because they are stored as 4 individual FP elements. */
3297
7bd872fe 3298static void
fb409745
EZ		 3299sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
3300 char *from, char *to)
3301{
f81353e4
EZ		 3302 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3303
3304 if (regnum >= tdep->DR0_REGNUM
3305 && regnum <= tdep->DR_LAST_REGNUM)
fb409745
EZ		 3306 {
3307 DOUBLEST val;
3308 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
3bbfbb92 3309 store_floating (to, TYPE_LENGTH (type), val);
fb409745
EZ		 3310 }
3311 else
3bbfbb92 3312 error ("sh_register_convert_to_virtual called with non DR register number");
fb409745
EZ		 3313}
3314
283150cd
EZ		 3315void
3316sh_sh64_register_convert_to_virtual (int regnum, struct type *type,
3317 char *from, char *to)
3318{
3319 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3320
3321 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
3322 {
3323 /* It is a no-op. */
3324 memcpy (to, from, REGISTER_RAW_SIZE (regnum));
3325 return;
3326 }
3327
3328 if ((regnum >= tdep->DR0_REGNUM
3329 && regnum <= tdep->DR_LAST_REGNUM)
3330 || (regnum >= tdep->DR0_C_REGNUM
3331 && regnum <= tdep->DR_LAST_C_REGNUM))
3332 {
3333 DOUBLEST val;
3334 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
3335 store_floating(to, TYPE_LENGTH(type), val);
3336 }
3337 else
3338 error("sh_register_convert_to_virtual called with non DR register number");
3339}
3340
3341static void
3342sh_sh4_register_convert_to_raw (struct type *type, int regnum,
d8124050 3343 const void *from, void *to)
283150cd
EZ		 3344{
3345 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3346
3347 if (regnum >= tdep->DR0_REGNUM
3348 && regnum <= tdep->DR_LAST_REGNUM)
3349 {
3350 DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
3351 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
3352 }
3353 else
3354 error("sh_register_convert_to_raw called with non DR register number");
3355}
3356
3357void
3358sh_sh64_register_convert_to_raw (struct type *type, int regnum,
d8124050 3359 const void *from, void *to)
fb409745 3360{
f81353e4
EZ		 3361 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3362
283150cd
EZ		 3363 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
3364 {
3365 /* It is a no-op. */
3366 memcpy (to, from, REGISTER_RAW_SIZE (regnum));
3367 return;
3368 }
3369
3370 if ((regnum >= tdep->DR0_REGNUM
3371 && regnum <= tdep->DR_LAST_REGNUM)
3372 || (regnum >= tdep->DR0_C_REGNUM
3373 && regnum <= tdep->DR_LAST_C_REGNUM))
fb409745
EZ		 3374 {
3375 DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
3376 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
3377 }
3378 else
3379 error("sh_register_convert_to_raw called with non DR register number");
3380}
3381
53116e27 3382void
d8124050
AC		 3383sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
3384 int reg_nr, void *buffer)
53116e27
EZ		 3385{
3386 int base_regnum, portion;
7bd872fe 3387 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
d8124050 3388 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
53116e27 3389
7bd872fe
EZ		 3390 if (reg_nr >= tdep->DR0_REGNUM
3391 && reg_nr <= tdep->DR_LAST_REGNUM)
3392 {
3393 base_regnum = dr_reg_base_num (reg_nr);
3394
3395 /* Build the value in the provided buffer. */
3396 /* Read the real regs for which this one is an alias. */
3397 for (portion = 0; portion < 2; portion++)
d8124050 3398 regcache_raw_read (regcache, base_regnum + portion,
0818c12a
AC		 3399 (temp_buffer
3400 + REGISTER_RAW_SIZE (base_regnum) * portion));
7bd872fe
EZ		 3401 /* We must pay attention to the endiannes. */
3402 sh_sh4_register_convert_to_virtual (reg_nr,
3403 REGISTER_VIRTUAL_TYPE (reg_nr),
3404 temp_buffer, buffer);
3405 }
3406 else if (reg_nr >= tdep->FV0_REGNUM
3407 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27 3408 {
7bd872fe
EZ		 3409 base_regnum = fv_reg_base_num (reg_nr);
3410
3411 /* Read the real regs for which this one is an alias. */
3412 for (portion = 0; portion < 4; portion++)
d8124050
AC		 3413 regcache_raw_read (regcache, base_regnum + portion,
3414 ((char *) buffer
3415 + REGISTER_RAW_SIZE (base_regnum) * portion));
53116e27
EZ		 3416 }
3417}
3418
7bd872fe 3419static void
d8124050
AC		 3420sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
3421 int reg_nr, void *buffer)
283150cd
EZ		 3422{
3423 int base_regnum;
3424 int portion;
3425 int offset = 0;
3426 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
d8124050 3427 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
283150cd
EZ		 3428
3429 if (reg_nr >= tdep->DR0_REGNUM
3430 && reg_nr <= tdep->DR_LAST_REGNUM)
3431 {
3432 base_regnum = dr_reg_base_num (reg_nr);
3433
3434 /* Build the value in the provided buffer. */
3435 /* DR regs are double precision registers obtained by
3436 concatenating 2 single precision floating point registers. */
3437 for (portion = 0; portion < 2; portion++)
d8124050 3438 regcache_raw_read (regcache, base_regnum + portion,
0818c12a
AC		 3439 (temp_buffer
3440 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3441
3442 /* We must pay attention to the endiannes. */
3443 sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr),
3444 temp_buffer, buffer);
3445
3446 }
3447
3448 else if (reg_nr >= tdep->FPP0_REGNUM
3449 && reg_nr <= tdep->FPP_LAST_REGNUM)
3450 {
3451 base_regnum = fpp_reg_base_num (reg_nr);
3452
3453 /* Build the value in the provided buffer. */
3454 /* FPP regs are pairs of single precision registers obtained by
3455 concatenating 2 single precision floating point registers. */
3456 for (portion = 0; portion < 2; portion++)
d8124050
AC		 3457 regcache_raw_read (regcache, base_regnum + portion,
3458 ((char *) buffer
0818c12a 3459 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3460 }
3461
3462 else if (reg_nr >= tdep->FV0_REGNUM
3463 && reg_nr <= tdep->FV_LAST_REGNUM)
3464 {
3465 base_regnum = fv_reg_base_num (reg_nr);
3466
3467 /* Build the value in the provided buffer. */
3468 /* FV regs are vectors of single precision registers obtained by
3469 concatenating 4 single precision floating point registers. */
3470 for (portion = 0; portion < 4; portion++)
d8124050
AC		 3471 regcache_raw_read (regcache, base_regnum + portion,
3472 ((char *) buffer
0818c12a 3473 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3474 }
3475
3476 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
3477 else if (reg_nr >= tdep->R0_C_REGNUM
3478 && reg_nr <= tdep->T_C_REGNUM)
3479 {
3480 base_regnum = sh64_compact_reg_base_num (reg_nr);
3481
3482 /* Build the value in the provided buffer. */
d8124050 3483 regcache_raw_read (regcache, base_regnum, temp_buffer);
283150cd
EZ		 3484 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3485 offset = 4;
3486 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
3487 }
3488
3489 else if (reg_nr >= tdep->FP0_C_REGNUM
3490 && reg_nr <= tdep->FP_LAST_C_REGNUM)
3491 {
3492 base_regnum = sh64_compact_reg_base_num (reg_nr);
3493
3494 /* Build the value in the provided buffer. */
3495 /* Floating point registers map 1-1 to the media fp regs,
3496 they have the same size and endienness. */
d8124050 3497 regcache_raw_read (regcache, base_regnum, buffer);
283150cd
EZ		 3498 }
3499
3500 else if (reg_nr >= tdep->DR0_C_REGNUM
3501 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3502 {
3503 base_regnum = sh64_compact_reg_base_num (reg_nr);
3504
3505 /* DR_C regs are double precision registers obtained by
3506 concatenating 2 single precision floating point registers. */
3507 for (portion = 0; portion < 2; portion++)
d8124050 3508 regcache_raw_read (regcache, base_regnum + portion,
0818c12a
AC		 3509 (temp_buffer
3510 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3511
3512 /* We must pay attention to the endiannes. */
3513 sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr),
3514 temp_buffer, buffer);
3515 }
3516
3517 else if (reg_nr >= tdep->FV0_C_REGNUM
3518 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3519 {
3520 base_regnum = sh64_compact_reg_base_num (reg_nr);
3521
3522 /* Build the value in the provided buffer. */
3523 /* FV_C regs are vectors of single precision registers obtained by
3524 concatenating 4 single precision floating point registers. */
3525 for (portion = 0; portion < 4; portion++)
d8124050
AC		 3526 regcache_raw_read (regcache, base_regnum + portion,
3527 ((char *) buffer
0818c12a 3528 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3529 }
3530
3531 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3532 {
3533 int fpscr_base_regnum;
3534 int sr_base_regnum;
3535 unsigned int fpscr_value;
3536 unsigned int sr_value;
3537 unsigned int fpscr_c_value;
3538 unsigned int fpscr_c_part1_value;
3539 unsigned int fpscr_c_part2_value;
3540
3541 fpscr_base_regnum = tdep->FPSCR_REGNUM;
3542 sr_base_regnum = tdep->SR_REGNUM;
3543
3544 /* Build the value in the provided buffer. */
3545 /* FPSCR_C is a very weird register that contains sparse bits
3546 from the FPSCR and the SR architectural registers.
3547 Specifically: */
3548 /* *INDENT-OFF* */
3549 /*
3550 FPSRC_C bit
3551 0 Bit 0 of FPSCR
3552 1 reserved
3553 2-17 Bit 2-18 of FPSCR
3554 18-20 Bits 12,13,14 of SR
3555 21-31 reserved
3556 */
3557 /* *INDENT-ON* */
3558 /* Get FPSCR into a local buffer */
d8124050 3559 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
283150cd
EZ		 3560 /* Get value as an int. */
3561 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
3562 /* Get SR into a local buffer */
d8124050 3563 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
283150cd
EZ		 3564 /* Get value as an int. */
3565 sr_value = extract_unsigned_integer (temp_buffer, 4);
3566 /* Build the new value. */
3567 fpscr_c_part1_value = fpscr_value & 0x3fffd;
3568 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
3569 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
3570 /* Store that in out buffer!!! */
3571 store_unsigned_integer (buffer, 4, fpscr_c_value);
3572 /* FIXME There is surely an endianness gotcha here. */
3573 }
3574
3575 else if (reg_nr == tdep->FPUL_C_REGNUM)
3576 {
3577 base_regnum = sh64_compact_reg_base_num (reg_nr);
3578
3579 /* FPUL_C register is floating point register 32,
3580 same size, same endianness. */
d8124050 3581 regcache_raw_read (regcache, base_regnum, buffer);
283150cd
EZ		 3582 }
3583}
3584
53116e27 3585void
d8124050
AC		 3586sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3587 int reg_nr, const void *buffer)
53116e27
EZ		 3588{
3589 int base_regnum, portion;
7bd872fe 3590 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
d8124050 3591 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
53116e27 3592
f81353e4
EZ		 3593 if (reg_nr >= tdep->DR0_REGNUM
3594 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27
EZ		 3595 {
3596 base_regnum = dr_reg_base_num (reg_nr);
3597
7bd872fe
EZ		 3598 /* We must pay attention to the endiannes. */
3599 sh_sh4_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3600 buffer, temp_buffer);
3601
53116e27
EZ		 3602 /* Write the real regs for which this one is an alias. */
3603 for (portion = 0; portion < 2; portion++)
d8124050 3604 regcache_raw_write (regcache, base_regnum + portion,
0818c12a
AC		 3605 (temp_buffer
3606 + REGISTER_RAW_SIZE (base_regnum) * portion));
53116e27 3607 }
f81353e4
EZ		 3608 else if (reg_nr >= tdep->FV0_REGNUM
3609 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 3610 {
3611 base_regnum = fv_reg_base_num (reg_nr);
3612
3613 /* Write the real regs for which this one is an alias. */
3614 for (portion = 0; portion < 4; portion++)
d8124050
AC		 3615 regcache_raw_write (regcache, base_regnum + portion,
3616 ((char *) buffer
0818c12a 3617 + REGISTER_RAW_SIZE (base_regnum) * portion));
53116e27
EZ		 3618 }
3619}
3620
283150cd 3621void
d8124050
AC		 3622sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3623 int reg_nr, const void *buffer)
283150cd
EZ		 3624{
3625 int base_regnum, portion;
3626 int offset;
3627 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
d8124050 3628 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
283150cd
EZ		 3629
3630 if (reg_nr >= tdep->DR0_REGNUM
3631 && reg_nr <= tdep->DR_LAST_REGNUM)
3632 {
3633 base_regnum = dr_reg_base_num (reg_nr);
3634 /* We must pay attention to the endiannes. */
3635 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3636 buffer, temp_buffer);
3637
3638
3639 /* Write the real regs for which this one is an alias. */
3640 for (portion = 0; portion < 2; portion++)
d8124050 3641 regcache_raw_write (regcache, base_regnum + portion,
0818c12a
AC		 3642 (temp_buffer
3643 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3644 }
3645
3646 else if (reg_nr >= tdep->FPP0_REGNUM
3647 && reg_nr <= tdep->FPP_LAST_REGNUM)
3648 {
3649 base_regnum = fpp_reg_base_num (reg_nr);
3650
3651 /* Write the real regs for which this one is an alias. */
3652 for (portion = 0; portion < 2; portion++)
d8124050
AC		 3653 regcache_raw_write (regcache, base_regnum + portion,
3654 ((char *) buffer
0818c12a 3655 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3656 }
3657
3658 else if (reg_nr >= tdep->FV0_REGNUM
3659 && reg_nr <= tdep->FV_LAST_REGNUM)
3660 {
3661 base_regnum = fv_reg_base_num (reg_nr);
3662
3663 /* Write the real regs for which this one is an alias. */
3664 for (portion = 0; portion < 4; portion++)
d8124050
AC		 3665 regcache_raw_write (regcache, base_regnum + portion,
3666 ((char *) buffer
0818c12a 3667 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3668 }
3669
3670 /* sh compact general pseudo registers. 1-to-1 with a shmedia
3671 register but only 4 bytes of it. */
3672 else if (reg_nr >= tdep->R0_C_REGNUM
3673 && reg_nr <= tdep->T_C_REGNUM)
3674 {
3675 base_regnum = sh64_compact_reg_base_num (reg_nr);
3676 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
3677 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3678 offset = 4;
3679 else
3680 offset = 0;
3681 /* Let's read the value of the base register into a temporary
3682 buffer, so that overwriting the last four bytes with the new
3683 value of the pseudo will leave the upper 4 bytes unchanged. */
d8124050 3684 regcache_raw_read (regcache, base_regnum, temp_buffer);
283150cd
EZ		 3685 /* Write as an 8 byte quantity */
3686 memcpy (temp_buffer + offset, buffer, 4);
d8124050 3687 regcache_raw_write (regcache, base_regnum, temp_buffer);
283150cd
EZ		 3688 }
3689
3690 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
3691 registers. Both are 4 bytes. */
3692 else if (reg_nr >= tdep->FP0_C_REGNUM
3693 && reg_nr <= tdep->FP_LAST_C_REGNUM)
3694 {
3695 base_regnum = sh64_compact_reg_base_num (reg_nr);
d8124050 3696 regcache_raw_write (regcache, base_regnum, buffer);
283150cd
EZ		 3697 }
3698
3699 else if (reg_nr >= tdep->DR0_C_REGNUM
3700 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3701 {
3702 base_regnum = sh64_compact_reg_base_num (reg_nr);
3703 for (portion = 0; portion < 2; portion++)
3704 {
3705 /* We must pay attention to the endiannes. */
3706 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3707 buffer, temp_buffer);
3708
d8124050 3709 regcache_raw_write (regcache, base_regnum + portion,
0818c12a
AC		 3710 (temp_buffer
3711 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3712 }
3713 }
3714
3715 else if (reg_nr >= tdep->FV0_C_REGNUM
3716 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3717 {
3718 base_regnum = sh64_compact_reg_base_num (reg_nr);
3719
3720 for (portion = 0; portion < 4; portion++)
3721 {
d8124050
AC		 3722 regcache_raw_write (regcache, base_regnum + portion,
3723 ((char *) buffer
0818c12a 3724 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3725 }
3726 }
3727
3728 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3729 {
3730 int fpscr_base_regnum;
3731 int sr_base_regnum;
3732 unsigned int fpscr_value;
3733 unsigned int sr_value;
3734 unsigned int old_fpscr_value;
3735 unsigned int old_sr_value;
3736 unsigned int fpscr_c_value;
3737 unsigned int fpscr_mask;
3738 unsigned int sr_mask;
3739
3740 fpscr_base_regnum = tdep->FPSCR_REGNUM;
3741 sr_base_regnum = tdep->SR_REGNUM;
3742
3743 /* FPSCR_C is a very weird register that contains sparse bits
3744 from the FPSCR and the SR architectural registers.
3745 Specifically: */
3746 /* *INDENT-OFF* */
3747 /*
3748 FPSRC_C bit
3749 0 Bit 0 of FPSCR
3750 1 reserved
3751 2-17 Bit 2-18 of FPSCR
3752 18-20 Bits 12,13,14 of SR
3753 21-31 reserved
3754 */
3755 /* *INDENT-ON* */
3756 /* Get value as an int. */
3757 fpscr_c_value = extract_unsigned_integer (buffer, 4);
3758
3759 /* Build the new values. */
3760 fpscr_mask = 0x0003fffd;
3761 sr_mask = 0x001c0000;
3762
3763 fpscr_value = fpscr_c_value & fpscr_mask;
3764 sr_value = (fpscr_value & sr_mask) >> 6;
3765
d8124050 3766 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
283150cd
EZ		 3767 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
3768 old_fpscr_value &= 0xfffc0002;
3769 fpscr_value |= old_fpscr_value;
3770 store_unsigned_integer (temp_buffer, 4, fpscr_value);
d8124050 3771 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
283150cd 3772
d8124050 3773 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
283150cd
EZ		 3774 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
3775 old_sr_value &= 0xffff8fff;
3776 sr_value |= old_sr_value;
3777 store_unsigned_integer (temp_buffer, 4, sr_value);
d8124050 3778 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
283150cd
EZ		 3779 }
3780
3781 else if (reg_nr == tdep->FPUL_C_REGNUM)
3782 {
3783 base_regnum = sh64_compact_reg_base_num (reg_nr);
d8124050 3784 regcache_raw_write (regcache, base_regnum, buffer);
283150cd
EZ		 3785 }
3786}
3787
3bbfbb92 3788/* Floating point vector of 4 float registers. */
53116e27
EZ		 3789static void
3790do_fv_register_info (int fv_regnum)
3791{
3792 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
3793 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3794 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM,
3795 (int) read_register (first_fp_reg_num),
3796 (int) read_register (first_fp_reg_num + 1),
3797 (int) read_register (first_fp_reg_num + 2),
3798 (int) read_register (first_fp_reg_num + 3));
3799}
3800
283150cd
EZ		 3801/* Floating point vector of 4 float registers, compact mode. */
3802static void
3803do_fv_c_register_info (int fv_regnum)
3804{
3805 int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum);
3806 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3807 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_C_REGNUM,
3808 (int) read_register (first_fp_reg_num),
3809 (int) read_register (first_fp_reg_num + 1),
3810 (int) read_register (first_fp_reg_num + 2),
3811 (int) read_register (first_fp_reg_num + 3));
3812}
3813
3814/* Pairs of single regs. The DR are instead double precision
3815 registers. */
3816static void
3817do_fpp_register_info (int fpp_regnum)
3818{
3819 int first_fp_reg_num = fpp_reg_base_num (fpp_regnum);
3820
3821 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
3822 fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM,
3823 (int) read_register (first_fp_reg_num),
3824 (int) read_register (first_fp_reg_num + 1));
3825}
3826
3bbfbb92 3827/* Double precision registers. */
53116e27
EZ		 3828static void
3829do_dr_register_info (int dr_regnum)
3830{
3831 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
3832
3833 printf_filtered ("dr%d\t0x%08x%08x\n",
3834 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM,
3835 (int) read_register (first_fp_reg_num),
3836 (int) read_register (first_fp_reg_num + 1));
3837}
3838
283150cd
EZ		 3839/* Double precision registers, compact mode. */
3840static void
3841do_dr_c_register_info (int dr_regnum)
3842{
3843 int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum);
3844
3845 printf_filtered ("dr%d_c\t0x%08x%08x\n",
3846 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_C_REGNUM,
3847 (int) read_register (first_fp_reg_num),
3848 (int) read_register (first_fp_reg_num +1));
3849}
3850
3851/* General register in compact mode. */
3852static void
3853do_r_c_register_info (int r_c_regnum)
3854{
3855 int regnum = sh64_compact_reg_base_num (r_c_regnum);
3856
3857 printf_filtered ("r%d_c\t0x%08x\n",
3858 r_c_regnum - gdbarch_tdep (current_gdbarch)->R0_C_REGNUM,
3859 /*FIXME!!!*/ (int) read_register (regnum));
3860}
3861
3862/* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
3863 shmedia REGISTERS. */
3864/* Control registers, compact mode. */
3865static void
3866do_cr_c_register_info (int cr_c_regnum)
3867{
3868 switch (cr_c_regnum)
3869 {
3870 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3871 break;
3872 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3873 break;
3874 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3875 break;
3876 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3877 break;
3878 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3879 break;
3880 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3881 break;
3882 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3883 break;
3884 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum));
3885 break;
3886 }
3887}
3888
53116e27
EZ		 3889static void
3890sh_do_pseudo_register (int regnum)
3891{
f81353e4
EZ		 3892 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3893
53116e27 3894 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e65ff28
AC		 3895 internal_error (__FILE__, __LINE__,
3896 "Invalid pseudo register number %d\n", regnum);
f81353e4
EZ		 3897 else if (regnum >= tdep->DR0_REGNUM
3898 && regnum < tdep->DR_LAST_REGNUM)
53116e27 3899 do_dr_register_info (regnum);
f81353e4
EZ		 3900 else if (regnum >= tdep->FV0_REGNUM
3901 && regnum <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 3902 do_fv_register_info (regnum);
3903}
3904
53116e27
EZ		 3905static void
3906sh_do_fp_register (int regnum)
3907{ /* do values for FP (float) regs */
3908 char *raw_buffer;
3909 double flt; /* double extracted from raw hex data */
3910 int inv;
3911 int j;
3912
3913 /* Allocate space for the float. */
3914 raw_buffer = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
3915
3916 /* Get the data in raw format. */
6e7f8b9c 3917 if (!frame_register_read (deprecated_selected_frame, regnum, raw_buffer))
53116e27
EZ		 3918 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
3919
3920 /* Get the register as a number */
3921 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
3922
3923 /* Print the name and some spaces. */
3924 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
3925 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
3926
3927 /* Print the value. */
93d56215
AC		 3928 if (inv)
3929 printf_filtered ("<invalid float>");
3930 else
3931 printf_filtered ("%-10.9g", flt);
53116e27
EZ		 3932
3933 /* Print the fp register as hex. */
3934 printf_filtered ("\t(raw 0x");
3935 for (j = 0; j < REGISTER_RAW_SIZE (regnum); j++)
3936 {
d7449b42 3937 register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
53116e27
EZ		 3938 : REGISTER_RAW_SIZE (regnum) - 1 - j;
3939 printf_filtered ("%02x", (unsigned char) raw_buffer[idx]);
3940 }
3941 printf_filtered (")");
3942 printf_filtered ("\n");
3943}
3944
283150cd
EZ		 3945static void
3946sh64_do_pseudo_register (int regnum)
3947{
3948 /* All the sh64-compact mode registers are pseudo registers. */
3949 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3950
3951 if (regnum < NUM_REGS
3952 || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT)
3953 internal_error (__FILE__, __LINE__,
3954 "Invalid pseudo register number %d\n", regnum);
3955
3956 else if ((regnum >= tdep->DR0_REGNUM
3957 && regnum <= tdep->DR_LAST_REGNUM))
3958 do_dr_register_info (regnum);
3959
3960 else if ((regnum >= tdep->DR0_C_REGNUM
3961 && regnum <= tdep->DR_LAST_C_REGNUM))
3962 do_dr_c_register_info (regnum);
3963
3964 else if ((regnum >= tdep->FV0_REGNUM
3965 && regnum <= tdep->FV_LAST_REGNUM))
3966 do_fv_register_info (regnum);
3967
3968 else if ((regnum >= tdep->FV0_C_REGNUM
3969 && regnum <= tdep->FV_LAST_C_REGNUM))
3970 do_fv_c_register_info (regnum);
3971
3972 else if (regnum >= tdep->FPP0_REGNUM
3973 && regnum <= tdep->FPP_LAST_REGNUM)
3974 do_fpp_register_info (regnum);
3975
3976 else if (regnum >= tdep->R0_C_REGNUM
3977 && regnum <= tdep->R_LAST_C_REGNUM)
3978 do_r_c_register_info (regnum); /* FIXME, this function will not print the right format */
3979
3980 else if (regnum >= tdep->FP0_C_REGNUM
3981 && regnum <= tdep->FP_LAST_C_REGNUM)
3982 sh_do_fp_register (regnum); /* this should work also for pseudoregs */
3983
3984 else if (regnum >= tdep->PC_C_REGNUM
3985 && regnum <= tdep->FPUL_C_REGNUM)
3986 do_cr_c_register_info (regnum);
3987
3988}
3989
53116e27
EZ		 3990static void
3991sh_do_register (int regnum)
3992{
3993 char raw_buffer[MAX_REGISTER_RAW_SIZE];
3994
3995 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
3996 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
3997
3998 /* Get the data in raw format. */
6e7f8b9c 3999 if (!frame_register_read (deprecated_selected_frame, regnum, raw_buffer))
53116e27
EZ		 4000 printf_filtered ("*value not available*\n");
4001
4002 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
4003 gdb_stdout, 'x', 1, 0, Val_pretty_default);
4004 printf_filtered ("\t");
4005 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
4006 gdb_stdout, 0, 1, 0, Val_pretty_default);
4007 printf_filtered ("\n");
4008}
4009
4010static void
4011sh_print_register (int regnum)
4012{
4013 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e65ff28
AC		 4014 internal_error (__FILE__, __LINE__,
4015 "Invalid register number %d\n", regnum);
53116e27 4016
e30839fe 4017 else if (regnum >= 0 && regnum < NUM_REGS)
53116e27
EZ		 4018 {
4019 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4020 sh_do_fp_register (regnum); /* FP regs */
4021 else
4022 sh_do_register (regnum); /* All other regs */
4023 }
4024
4025 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
3bbfbb92 4026 do_pseudo_register (regnum);
53116e27
EZ		 4027}
4028
4029void
4030sh_do_registers_info (int regnum, int fpregs)
4031{
4032 if (regnum != -1) /* do one specified register */
4033 {
4034 if (*(REGISTER_NAME (regnum)) == '\0')
4035 error ("Not a valid register for the current processor type");
4036
4037 sh_print_register (regnum);
4038 }
4039 else
4040 /* do all (or most) registers */
4041 {
4042 regnum = 0;
4043 while (regnum < NUM_REGS)
4044 {
4045 /* If the register name is empty, it is undefined for this
4046 processor, so don't display anything. */
4047 if (REGISTER_NAME (regnum) == NULL
4048 || *(REGISTER_NAME (regnum)) == '\0')
4049 {
4050 regnum++;
4051 continue;
4052 }
4053
4054 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4055 {
4056 if (fpregs)
4057 {
4058 /* true for "INFO ALL-REGISTERS" command */
4059 sh_do_fp_register (regnum); /* FP regs */
4060 regnum ++;
4061 }
4062 else
e6c42fda 4063 regnum += (gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
53116e27
EZ		 4064 }
4065 else
4066 {
4067 sh_do_register (regnum); /* All other regs */
4068 regnum++;
4069 }
4070 }
4071
4072 if (fpregs)
4073 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4074 {
3bbfbb92 4075 do_pseudo_register (regnum);
53116e27
EZ		 4076 regnum++;
4077 }
4078 }
4079}
4080
283150cd
EZ		 4081void
4082sh_compact_do_registers_info (int regnum, int fpregs)
4083{
4084 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4085 if (regnum != -1) /* do one specified register */
4086 {
4087 if (*(REGISTER_NAME (regnum)) == '\0')
4088 error ("Not a valid register for the current processor type");
4089
4090 if (regnum >= 0 && regnum < tdep->R0_C_REGNUM)
4091 error ("Not a valid register for the current processor mode.");
4092
4093 sh_print_register (regnum);
4094 }
4095 else
4096 /* do all compact registers */
4097 {
4098 regnum = tdep->R0_C_REGNUM;
4099 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4100 {
4101 do_pseudo_register (regnum);
4102 regnum++;
4103 }
4104 }
4105}
4106
4107void
4108sh64_do_registers_info (int regnum, int fpregs)
4109{
50abf9e5 4110 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
283150cd
EZ		 4111 sh_do_registers_info (regnum, fpregs);
4112 else
4113 sh_compact_do_registers_info (regnum, fpregs);
4114}
4115
1a8629c7
MS		 4116#ifdef SVR4_SHARED_LIBS
4117
4118/* Fetch (and possibly build) an appropriate link_map_offsets structure
4119 for native i386 linux targets using the struct offsets defined in
4120 link.h (but without actual reference to that file).
4121
4122 This makes it possible to access i386-linux shared libraries from
4123 a gdb that was not built on an i386-linux host (for cross debugging).
4124 */
4125
4126struct link_map_offsets *
4127sh_linux_svr4_fetch_link_map_offsets (void)
4128{
4129 static struct link_map_offsets lmo;
4130 static struct link_map_offsets *lmp = 0;
4131
4132 if (lmp == 0)
4133 {
4134 lmp = &lmo;
4135
4136 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
4137
4138 lmo.r_map_offset = 4;
4139 lmo.r_map_size = 4;
4140
4141 lmo.link_map_size = 20; /* 552 not actual size but all we need */
4142
4143 lmo.l_addr_offset = 0;
4144 lmo.l_addr_size = 4;
4145
4146 lmo.l_name_offset = 4;
4147 lmo.l_name_size = 4;
4148
4149 lmo.l_next_offset = 12;
4150 lmo.l_next_size = 4;
4151
4152 lmo.l_prev_offset = 16;
4153 lmo.l_prev_size = 4;
4154 }
4155
4156 return lmp;
4157}
4158#endif /* SVR4_SHARED_LIBS */
4159
2f14585c
JR		 4160\f
4161enum
4162{
4163 DSP_DSR_REGNUM = 24,
4164 DSP_A0G_REGNUM,
4165 DSP_A0_REGNUM,
4166 DSP_A1G_REGNUM,
4167 DSP_A1_REGNUM,
4168 DSP_M0_REGNUM,
4169 DSP_M1_REGNUM,
4170 DSP_X0_REGNUM,
4171 DSP_X1_REGNUM,
4172 DSP_Y0_REGNUM,
4173 DSP_Y1_REGNUM,
4174
4175 DSP_MOD_REGNUM = 40,
4176
4177 DSP_RS_REGNUM = 43,
4178 DSP_RE_REGNUM,
4179
4180 DSP_R0_BANK_REGNUM = 51,
4181 DSP_R7_BANK_REGNUM = DSP_R0_BANK_REGNUM + 7
4182};
4183
4184static int
4185sh_dsp_register_sim_regno (int nr)
4186{
4187 if (legacy_register_sim_regno (nr) < 0)
4188 return legacy_register_sim_regno (nr);
4189 if (nr >= DSP_DSR_REGNUM && nr < DSP_Y1_REGNUM)
4190 return nr - DSP_DSR_REGNUM + SIM_SH_DSR_REGNUM;
4191 if (nr == DSP_MOD_REGNUM)
4192 return SIM_SH_MOD_REGNUM;
4193 if (nr == DSP_RS_REGNUM)
4194 return SIM_SH_RS_REGNUM;
4195 if (nr == DSP_RE_REGNUM)
4196 return SIM_SH_RE_REGNUM;
4197 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
4198 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
4199 return nr;
4200}
d658f924 4201\f
cc17453a
EZ		 4202static gdbarch_init_ftype sh_gdbarch_init;
4203
4204static struct gdbarch *
fba45db2 4205sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a
EZ		 4206{
4207 static LONGEST sh_call_dummy_words[] = {0};
4208 struct gdbarch *gdbarch;
4209 struct gdbarch_tdep *tdep;
4210 gdbarch_register_name_ftype *sh_register_name;
ebba8386 4211 gdbarch_deprecated_store_return_value_ftype *sh_store_return_value;
cc17453a 4212 gdbarch_register_virtual_type_ftype *sh_register_virtual_type;
70f80edf 4213 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
d658f924
JT		 4214
4215 /* Try to determine the ABI of the object we are loading. */
4216
4217 if (info.abfd != NULL)
4218 {
70f80edf
JT		 4219 osabi = gdbarch_lookup_osabi (info.abfd);
4220 /* If we get "unknown" back, just leave it that way. */
d658f924 4221 }
cc17453a
EZ		 4222
4223 /* Find a candidate among the list of pre-declared architectures. */
d658f924
JT		 4224 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4225 arches != NULL;
4226 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4227 {
4228 /* Make sure the ABI selection matches. */
4229 tdep = gdbarch_tdep (arches->gdbarch);
70f80edf 4230 if (tdep && tdep->osabi == osabi)
d658f924
JT		 4231 return arches->gdbarch;
4232 }
cc17453a
EZ		 4233
4234 /* None found, create a new architecture from the information
4235 provided. */
4236 tdep = XMALLOC (struct gdbarch_tdep);
4237 gdbarch = gdbarch_alloc (&info, tdep);
4238
a5afb99f
AC		 4239 /* NOTE: cagney/2002-12-06: This can be deleted when this arch is
4240 ready to unwind the PC first (see frame.c:get_prev_frame()). */
4241 set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default);
4242
70f80edf 4243 tdep->osabi = osabi;
d658f924 4244
cc17453a
EZ		 4245 /* Initialize the register numbers that are not common to all the
4246 variants to -1, if necessary thse will be overwritten in the case
4247 statement below. */
4248 tdep->FPUL_REGNUM = -1;
4249 tdep->FPSCR_REGNUM = -1;
3bbfbb92 4250 tdep->PR_REGNUM = 17;
c62a7c7b 4251 tdep->SR_REGNUM = 22;
cc17453a 4252 tdep->DSR_REGNUM = -1;
e6c42fda 4253 tdep->FP_LAST_REGNUM = -1;
cc17453a
EZ		 4254 tdep->A0G_REGNUM = -1;
4255 tdep->A0_REGNUM = -1;
4256 tdep->A1G_REGNUM = -1;
4257 tdep->A1_REGNUM = -1;
4258 tdep->M0_REGNUM = -1;
4259 tdep->M1_REGNUM = -1;
4260 tdep->X0_REGNUM = -1;
4261 tdep->X1_REGNUM = -1;
4262 tdep->Y0_REGNUM = -1;
4263 tdep->Y1_REGNUM = -1;
4264 tdep->MOD_REGNUM = -1;
4265 tdep->RS_REGNUM = -1;
4266 tdep->RE_REGNUM = -1;
4267 tdep->SSR_REGNUM = -1;
4268 tdep->SPC_REGNUM = -1;
53116e27 4269 tdep->DR0_REGNUM = -1;
e6c42fda 4270 tdep->DR_LAST_REGNUM = -1;
53116e27 4271 tdep->FV0_REGNUM = -1;
e6c42fda 4272 tdep->FV_LAST_REGNUM = -1;
3bbfbb92
EZ		 4273 tdep->ARG0_REGNUM = 4;
4274 tdep->ARGLAST_REGNUM = 7;
4275 tdep->RETURN_REGNUM = 0;
4276 tdep->FLOAT_ARGLAST_REGNUM = -1;
a38d2a54 4277
283150cd
EZ		 4278 tdep->sh_abi = SH_ABI_UNKNOWN;
4279
cc17453a 4280 set_gdbarch_fp0_regnum (gdbarch, -1);
53116e27
EZ		 4281 set_gdbarch_num_pseudo_regs (gdbarch, 0);
4282 set_gdbarch_max_register_raw_size (gdbarch, 4);
4283 set_gdbarch_max_register_virtual_size (gdbarch, 4);
ec920329 4284 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
a38d2a54 4285 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
88e04cc1 4286 set_gdbarch_num_regs (gdbarch, SH_DEFAULT_NUM_REGS);
a38d2a54
EZ		 4287 set_gdbarch_sp_regnum (gdbarch, 15);
4288 set_gdbarch_fp_regnum (gdbarch, 14);
4289 set_gdbarch_pc_regnum (gdbarch, 16);
4290 set_gdbarch_register_size (gdbarch, 4);
88e04cc1 4291 set_gdbarch_register_bytes (gdbarch, SH_DEFAULT_NUM_REGS * 4);
903ad3a6 4292 set_gdbarch_deprecated_do_registers_info (gdbarch, sh_do_registers_info);
eaf90c5d 4293 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
3bbfbb92 4294 set_gdbarch_frame_chain (gdbarch, sh_frame_chain);
bdcdd535 4295 set_gdbarch_get_saved_register (gdbarch, deprecated_generic_get_saved_register);
3bbfbb92 4296 set_gdbarch_init_extra_frame_info (gdbarch, sh_init_extra_frame_info);
26e9b323 4297 set_gdbarch_deprecated_extract_return_value (gdbarch, sh_extract_return_value);
3bbfbb92
EZ		 4298 set_gdbarch_push_arguments (gdbarch, sh_push_arguments);
4299 set_gdbarch_store_struct_return (gdbarch, sh_store_struct_return);
4300 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
26e9b323 4301 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
3bbfbb92 4302 set_gdbarch_pop_frame (gdbarch, sh_pop_frame);
2bf0cb65 4303 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2f14585c 4304 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
3bbfbb92
EZ		 4305 skip_prologue_hard_way = sh_skip_prologue_hard_way;
4306 do_pseudo_register = sh_do_pseudo_register;
cc17453a
EZ		 4307
4308 switch (info.bfd_arch_info->mach)
8db62801 4309 {
cc17453a
EZ		 4310 case bfd_mach_sh:
4311 sh_register_name = sh_sh_register_name;
4312 sh_show_regs = sh_generic_show_regs;
4313 sh_store_return_value = sh_default_store_return_value;
4314 sh_register_virtual_type = sh_default_register_virtual_type;
4315 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 4316 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4317 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4318 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 4319 break;
4320 case bfd_mach_sh2:
4321 sh_register_name = sh_sh_register_name;
4322 sh_show_regs = sh_generic_show_regs;
4323 sh_store_return_value = sh_default_store_return_value;
4324 sh_register_virtual_type = sh_default_register_virtual_type;
4325 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 4326 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4327 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4328 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 4329 break;
4330 case bfd_mach_sh_dsp:
4331 sh_register_name = sh_sh_dsp_register_name;
4332 sh_show_regs = sh_dsp_show_regs;
4333 sh_store_return_value = sh_default_store_return_value;
4334 sh_register_virtual_type = sh_default_register_virtual_type;
4335 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 4336 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4337 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4338 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
2f14585c 4339 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a
EZ		 4340 tdep->DSR_REGNUM = 24;
4341 tdep->A0G_REGNUM = 25;
4342 tdep->A0_REGNUM = 26;
4343 tdep->A1G_REGNUM = 27;
4344 tdep->A1_REGNUM = 28;
4345 tdep->M0_REGNUM = 29;
4346 tdep->M1_REGNUM = 30;
4347 tdep->X0_REGNUM = 31;
4348 tdep->X1_REGNUM = 32;
4349 tdep->Y0_REGNUM = 33;
4350 tdep->Y1_REGNUM = 34;
4351 tdep->MOD_REGNUM = 40;
4352 tdep->RS_REGNUM = 43;
4353 tdep->RE_REGNUM = 44;
4354 break;
4355 case bfd_mach_sh3:
4356 sh_register_name = sh_sh3_register_name;
4357 sh_show_regs = sh3_show_regs;
4358 sh_store_return_value = sh_default_store_return_value;
4359 sh_register_virtual_type = sh_default_register_virtual_type;
4360 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 4361 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4362 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4363 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 4364 tdep->SSR_REGNUM = 41;
4365 tdep->SPC_REGNUM = 42;
4366 break;
4367 case bfd_mach_sh3e:
4368 sh_register_name = sh_sh3e_register_name;
4369 sh_show_regs = sh3e_show_regs;
4370 sh_store_return_value = sh3e_sh4_store_return_value;
4371 sh_register_virtual_type = sh_sh3e_register_virtual_type;
4372 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
53116e27
EZ		 4373 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4374 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4375 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
26e9b323 4376 set_gdbarch_deprecated_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
cc17453a
EZ		 4377 set_gdbarch_fp0_regnum (gdbarch, 25);
4378 tdep->FPUL_REGNUM = 23;
4379 tdep->FPSCR_REGNUM = 24;
e6c42fda 4380 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 4381 tdep->SSR_REGNUM = 41;
4382 tdep->SPC_REGNUM = 42;
4383 break;
4384 case bfd_mach_sh3_dsp:
4385 sh_register_name = sh_sh3_dsp_register_name;
4386 sh_show_regs = sh3_dsp_show_regs;
4387 sh_store_return_value = sh_default_store_return_value;
4388 sh_register_virtual_type = sh_default_register_virtual_type;
4389 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 4390 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4391 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4392 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 4393 tdep->DSR_REGNUM = 24;
4394 tdep->A0G_REGNUM = 25;
4395 tdep->A0_REGNUM = 26;
4396 tdep->A1G_REGNUM = 27;
4397 tdep->A1_REGNUM = 28;
4398 tdep->M0_REGNUM = 29;
4399 tdep->M1_REGNUM = 30;
4400 tdep->X0_REGNUM = 31;
4401 tdep->X1_REGNUM = 32;
4402 tdep->Y0_REGNUM = 33;
4403 tdep->Y1_REGNUM = 34;
4404 tdep->MOD_REGNUM = 40;
4405 tdep->RS_REGNUM = 43;
4406 tdep->RE_REGNUM = 44;
4407 tdep->SSR_REGNUM = 41;
4408 tdep->SPC_REGNUM = 42;
4409 break;
4410 case bfd_mach_sh4:
53116e27
EZ		 4411 sh_register_name = sh_sh4_register_name;
4412 sh_show_regs = sh4_show_regs;
cc17453a 4413 sh_store_return_value = sh3e_sh4_store_return_value;
53116e27 4414 sh_register_virtual_type = sh_sh4_register_virtual_type;
cc17453a 4415 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
26e9b323 4416 set_gdbarch_deprecated_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
cc17453a 4417 set_gdbarch_fp0_regnum (gdbarch, 25);
53116e27
EZ		 4418 set_gdbarch_register_raw_size (gdbarch, sh_sh4_register_raw_size);
4419 set_gdbarch_register_virtual_size (gdbarch, sh_sh4_register_raw_size);
4420 set_gdbarch_register_byte (gdbarch, sh_sh4_register_byte);
4421 set_gdbarch_num_pseudo_regs (gdbarch, 12);
4422 set_gdbarch_max_register_raw_size (gdbarch, 4 * 4);
4423 set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4);
d8124050
AC		 4424 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
4425 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
cc17453a
EZ		 4426 tdep->FPUL_REGNUM = 23;
4427 tdep->FPSCR_REGNUM = 24;
e6c42fda 4428 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 4429 tdep->SSR_REGNUM = 41;
4430 tdep->SPC_REGNUM = 42;
53116e27 4431 tdep->DR0_REGNUM = 59;
e6c42fda 4432 tdep->DR_LAST_REGNUM = 66;
53116e27 4433 tdep->FV0_REGNUM = 67;
e6c42fda 4434 tdep->FV_LAST_REGNUM = 70;
cc17453a 4435 break;
283150cd
EZ		 4436 case bfd_mach_sh5:
4437 tdep->PR_REGNUM = 18;
4438 tdep->SR_REGNUM = 65;
4439 tdep->FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM;
4440 tdep->FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1;
4441 tdep->SSR_REGNUM = SIM_SH64_SSR_REGNUM;
4442 tdep->SPC_REGNUM = SIM_SH64_SPC_REGNUM;
4443 tdep->TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7;
4444 tdep->FPP0_REGNUM = 173;
4445 tdep->FPP_LAST_REGNUM = 204;
4446 tdep->DR0_REGNUM = 141;
4447 tdep->DR_LAST_REGNUM = 172;
4448 tdep->FV0_REGNUM = 205;
4449 tdep->FV_LAST_REGNUM = 220;
4450 tdep->R0_C_REGNUM = 221;
4451 tdep->R_LAST_C_REGNUM = 236;
4452 tdep->PC_C_REGNUM = 237;
4453 tdep->GBR_C_REGNUM = 238;
4454 tdep->MACH_C_REGNUM = 239;
4455 tdep->MACL_C_REGNUM = 240;
4456 tdep->PR_C_REGNUM = 241;
4457 tdep->T_C_REGNUM = 242;
4458 tdep->FPSCR_C_REGNUM = 243;
4459 tdep->FPUL_C_REGNUM = 244;
4460 tdep->FP0_C_REGNUM = 245;
4461 tdep->FP_LAST_C_REGNUM = 260;
4462 tdep->DR0_C_REGNUM = 261;
4463 tdep->DR_LAST_C_REGNUM = 268;
4464 tdep->FV0_C_REGNUM = 269;
4465 tdep->FV_LAST_C_REGNUM = 272;
4466 tdep->ARG0_REGNUM = 2;
4467 tdep->ARGLAST_REGNUM = 9;
4468 tdep->RETURN_REGNUM = 2;
4469 tdep->FLOAT_ARGLAST_REGNUM = 11;
4470
4471 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT);
4472 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
4473 set_gdbarch_pc_regnum (gdbarch, 64);
4474
4475 /* Determine the ABI */
4476 if (bfd_get_arch_size (info.abfd) == 64)
4477 {
4478 /* If the ABI is the 64-bit one, it can only be sh-media. */
4479 tdep->sh_abi = SH_ABI_64;
4480 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4481 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4482 }
4483 else
4484 {
4485 /* If the ABI is the 32-bit one it could be either media or
4486 compact. */
4487 tdep->sh_abi = SH_ABI_32;
4488 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4489 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4490 }
4491
4492 /* the number of real registers is the same whether we are in
4493 ISA16(compact) or ISA32(media). */
4494 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
4495 set_gdbarch_register_size (gdbarch, 8); /*????*/
4496 set_gdbarch_register_bytes (gdbarch,
4497 ((SIM_SH64_NR_FP_REGS + 1) * 4)
4498 + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8);
4499
4500 sh_register_name = sh_sh64_register_name;
4501 sh_show_regs = sh64_show_regs;
4502 sh_register_virtual_type = sh_sh64_register_virtual_type;
4503 sh_store_return_value = sh64_store_return_value;
4504 skip_prologue_hard_way = sh64_skip_prologue_hard_way;
4505 do_pseudo_register = sh64_do_pseudo_register;
283150cd
EZ		 4506 set_gdbarch_register_raw_size (gdbarch, sh_sh64_register_raw_size);
4507 set_gdbarch_register_virtual_size (gdbarch, sh_sh64_register_raw_size);
4508 set_gdbarch_register_byte (gdbarch, sh_sh64_register_byte);
4509 /* This seems awfully wrong!*/
4510 /*set_gdbarch_max_register_raw_size (gdbarch, 8);*/
4511 /* should include the size of the pseudo regs. */
4512 set_gdbarch_max_register_raw_size (gdbarch, 4 * 4);
4513 /* Or should that go in the virtual_size? */
4514 /*set_gdbarch_max_register_virtual_size (gdbarch, 8);*/
4515 set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4);
d8124050
AC		 4516 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
4517 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
283150cd 4518
903ad3a6 4519 set_gdbarch_deprecated_do_registers_info (gdbarch, sh64_do_registers_info);
283150cd
EZ		 4520 set_gdbarch_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs);
4521 set_gdbarch_breakpoint_from_pc (gdbarch, sh_sh64_breakpoint_from_pc);
4522 set_gdbarch_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info);
4523 set_gdbarch_frame_chain (gdbarch, sh64_frame_chain);
4524 set_gdbarch_get_saved_register (gdbarch, sh64_get_saved_register);
26e9b323 4525 set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value);
283150cd
EZ		 4526 set_gdbarch_push_arguments (gdbarch, sh64_push_arguments);
4527 /*set_gdbarch_store_struct_return (gdbarch, sh64_store_struct_return);*/
26e9b323 4528 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address);
283150cd
EZ		 4529 set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention);
4530 set_gdbarch_pop_frame (gdbarch, sh64_pop_frame);
4531 set_gdbarch_elf_make_msymbol_special (gdbarch,
4532 sh64_elf_make_msymbol_special);
4533 break;
cc17453a
EZ		 4534 default:
4535 sh_register_name = sh_generic_register_name;
4536 sh_show_regs = sh_generic_show_regs;
4537 sh_store_return_value = sh_default_store_return_value;
4538 sh_register_virtual_type = sh_default_register_virtual_type;
4539 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 4540 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4541 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4542 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a 4543 break;
8db62801 4544 }
cc17453a
EZ		 4545
4546 set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
4547 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
4548 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
cc17453a
EZ		 4549 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
4550 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
4551
cc17453a 4552 set_gdbarch_register_name (gdbarch, sh_register_name);
cc17453a
EZ		 4553 set_gdbarch_register_virtual_type (gdbarch, sh_register_virtual_type);
4554
cc17453a
EZ		 4555 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
4556 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
cc17453a
EZ		 4557 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4558 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4559 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
7079c36c 4560 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
cc17453a 4561
cc17453a 4562 set_gdbarch_call_dummy_length (gdbarch, 0);
cc17453a
EZ		 4563 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
4564 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); /*???*/
4565 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
4566 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
cc17453a
EZ		 4567 set_gdbarch_call_dummy_words (gdbarch, sh_call_dummy_words);
4568 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (sh_call_dummy_words));
4569 set_gdbarch_call_dummy_p (gdbarch, 1);
4570 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
cc17453a 4571 set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
cc17453a 4572
cc17453a
EZ		 4573 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
4574 set_gdbarch_push_return_address (gdbarch, sh_push_return_address);
4575
ebba8386 4576 set_gdbarch_deprecated_store_return_value (gdbarch, sh_store_return_value);
cc17453a
EZ		 4577 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
4578 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4579 set_gdbarch_decr_pc_after_break (gdbarch, 0);
4580 set_gdbarch_function_start_offset (gdbarch, 0);
cc17453a
EZ		 4581
4582 set_gdbarch_frame_args_skip (gdbarch, 0);
4583 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
cc17453a
EZ		 4584 set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid);
4585 set_gdbarch_frame_saved_pc (gdbarch, sh_frame_saved_pc);
cc17453a
EZ		 4586 set_gdbarch_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
4587 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
4588 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
cc17453a 4589
70f80edf 4590 /* Hook in ABI-specific overrides, if they have been registered.
d658f924 4591
70f80edf
JT		 4592 FIXME: if the ABI is unknown, this is probably an embedded target,
4593 so we should not warn about this situation. */
4594 gdbarch_init_osabi (info, gdbarch, osabi);
d658f924 4595
cc17453a 4596 return gdbarch;
8db62801
EZ		 4597}
4598
d658f924
JT		 4599static void
4600sh_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
4601{
4602 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4603
4604 if (tdep == NULL)
4605 return;
4606
70f80edf
JT		 4607 fprintf_unfiltered (file, "sh_dump_tdep: OS ABI = %s\n",
4608 gdbarch_osabi_name (tdep->osabi));
d658f924
JT		 4609}
4610
c906108c 4611void
fba45db2 4612_initialize_sh_tdep (void)
c906108c
SS		 4613{
4614 struct cmd_list_element *c;
cc17453a 4615
d658f924 4616 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, sh_dump_tdep);
c906108c 4617
53116e27 4618 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
c906108c 4619}
Empty description
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