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c906108c 1/* Target-dependent code for Hitachi Super-H, for GDB.
538a76d6 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3116c80a 3 Free Software Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b
JM		 17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
c906108c
SS		 21
22/*
c5aa993b
JM		 23 Contributed by Steve Chamberlain
24 [email protected]
c906108c
SS		 25 */
26
27#include "defs.h"
28#include "frame.h"
29#include "obstack.h"
30#include "symtab.h"
31#include "symfile.h"
32#include "gdbtypes.h"
33#include "gdbcmd.h"
34#include "gdbcore.h"
35#include "value.h"
36#include "dis-asm.h"
37#include "inferior.h" /* for BEFORE_TEXT_END etc. */
38#include "gdb_string.h"
b4a20239 39#include "arch-utils.h"
fb409745 40#include "floatformat.h"
4e052eda 41#include "regcache.h"
d16aafd8 42#include "doublest.h"
c906108c 43
ab3b8126
JT		 44#include "sh-tdep.h"
45
d658f924 46#include "elf-bfd.h"
1a8629c7
MS		 47#include "solib-svr4.h"
48
283150cd
EZ		 49/* sh64 flags */
50#include "elf/sh.h"
51/* registers numbers shared with the simulator */
1c922164 52#include "gdb/sim-sh.h"
283150cd 53
53116e27 54void (*sh_show_regs) (void);
3bbfbb92
EZ		 55CORE_ADDR (*skip_prologue_hard_way) (CORE_ADDR);
56void (*do_pseudo_register) (int);
cc17453a 57
88e04cc1
EZ		 58#define SH_DEFAULT_NUM_REGS 59
59
cc17453a
EZ		 60/* Define other aspects of the stack frame.
61 we keep a copy of the worked out return pc lying around, since it
62 is a useful bit of info */
63
64struct frame_extra_info
65{
66 CORE_ADDR return_pc;
67 int leaf_function;
68 int f_offset;
63978407 69};
c906108c 70
cc17453a
EZ		 71static char *
72sh_generic_register_name (int reg_nr)
c5aa993b 73{
cc17453a 74 static char *register_names[] =
c5aa993b 75 {
cc17453a
EZ		 76 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
77 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
78 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
79 "fpul", "fpscr",
80 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
81 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
82 "ssr", "spc",
83 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
84 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
85 };
86 if (reg_nr < 0)
87 return NULL;
88 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
89 return NULL;
90 return register_names[reg_nr];
91}
92
93static char *
94sh_sh_register_name (int reg_nr)
95{
96 static char *register_names[] =
63978407 97 {
cc17453a
EZ		 98 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
99 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
100 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
101 "", "",
102 "", "", "", "", "", "", "", "",
103 "", "", "", "", "", "", "", "",
104 "", "",
105 "", "", "", "", "", "", "", "",
106 "", "", "", "", "", "", "", "",
107 };
108 if (reg_nr < 0)
109 return NULL;
110 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
111 return NULL;
112 return register_names[reg_nr];
113}
114
115static char *
116sh_sh3_register_name (int reg_nr)
117{
118 static char *register_names[] =
c5aa993b 119 {
cc17453a
EZ		 120 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
121 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
122 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
123 "", "",
124 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
126 "ssr", "spc",
127 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
128 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
129 };
130 if (reg_nr < 0)
131 return NULL;
132 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
133 return NULL;
134 return register_names[reg_nr];
135}
136
137static char *
138sh_sh3e_register_name (int reg_nr)
139{
140 static char *register_names[] =
63978407 141 {
cc17453a
EZ		 142 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
143 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
144 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
145 "fpul", "fpscr",
146 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
147 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
148 "ssr", "spc",
149 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
150 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
151 };
152 if (reg_nr < 0)
153 return NULL;
154 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
155 return NULL;
156 return register_names[reg_nr];
157}
158
159static char *
160sh_sh_dsp_register_name (int reg_nr)
161{
162 static char *register_names[] =
c5aa993b 163 {
cc17453a
EZ		 164 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
165 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
166 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
167 "", "dsr",
168 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
169 "y0", "y1", "", "", "", "", "", "mod",
170 "", "",
171 "rs", "re", "", "", "", "", "", "",
172 "", "", "", "", "", "", "", "",
173 };
174 if (reg_nr < 0)
175 return NULL;
176 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
177 return NULL;
178 return register_names[reg_nr];
179}
180
181static char *
182sh_sh3_dsp_register_name (int reg_nr)
183{
184 static char *register_names[] =
c5aa993b 185 {
cc17453a
EZ		 186 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
187 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
188 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
189 "", "dsr",
190 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
191 "y0", "y1", "", "", "", "", "", "mod",
192 "ssr", "spc",
193 "rs", "re", "", "", "", "", "", "",
194 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
195 "", "", "", "", "", "", "", "",
196 };
197 if (reg_nr < 0)
198 return NULL;
199 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
200 return NULL;
201 return register_names[reg_nr];
202}
203
53116e27
EZ		 204static char *
205sh_sh4_register_name (int reg_nr)
206{
207 static char *register_names[] =
208 {
a38d2a54 209 /* general registers 0-15 */
53116e27
EZ		 210 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
211 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 212 /* 16 - 22 */
53116e27 213 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 214 /* 23, 24 */
53116e27 215 "fpul", "fpscr",
a38d2a54 216 /* floating point registers 25 - 40 */
53116e27
EZ		 217 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
218 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 219 /* 41, 42 */
53116e27 220 "ssr", "spc",
a38d2a54 221 /* bank 0 43 - 50 */
53116e27 222 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 223 /* bank 1 51 - 58 */
53116e27 224 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
a38d2a54 225 /* double precision (pseudo) 59 - 66 */
fe9f384f 226 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 227 /* vectors (pseudo) 67 - 70 */
fe9f384f 228 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ		 229 /* FIXME: missing XF 71 - 86 */
230 /* FIXME: missing XD 87 - 94 */
53116e27
EZ		 231 };
232 if (reg_nr < 0)
233 return NULL;
234 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
235 return NULL;
236 return register_names[reg_nr];
237}
238
283150cd
EZ		 239static char *
240sh_sh64_register_name (int reg_nr)
241{
242 static char *register_names[] =
243 {
244 /* SH MEDIA MODE (ISA 32) */
245 /* general registers (64-bit) 0-63 */
246 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
247 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
248 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
249 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
250 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
251 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
252 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
253 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
254
255 /* pc (64-bit) 64 */
256 "pc",
257
258 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
259 "sr", "ssr", "spc",
260
261 /* target registers (64-bit) 68-75*/
262 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
263
264 /* floating point state control register (32-bit) 76 */
265 "fpscr",
266
267 /* single precision floating point registers (32-bit) 77-140*/
268 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
269 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
270 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
271 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
272 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
273 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
274 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
275 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
276
277 /* double precision registers (pseudo) 141-172 */
278 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
279 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
280 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
281 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
282
283 /* floating point pairs (pseudo) 173-204*/
284 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
285 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
286 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
287 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
288
289 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
290 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
291 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
292
293 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
294 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
295 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
296 "pc_c",
297 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
298 "fpscr_c", "fpul_c",
299 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
300 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
301 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
302 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
303 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
304 };
305
306 if (reg_nr < 0)
307 return NULL;
308 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
309 return NULL;
310 return register_names[reg_nr];
311}
312
313#define NUM_PSEUDO_REGS_SH_MEDIA 80
314#define NUM_PSEUDO_REGS_SH_COMPACT 51
315
3117ed25 316static const unsigned char *
fba45db2 317sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
cc17453a
EZ		 318{
319 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
320 static unsigned char breakpoint[] = {0xc3, 0xc3};
321
322 *lenptr = sizeof (breakpoint);
323 return breakpoint;
324}
c906108c 325
283150cd
EZ		 326/* Macros and functions for setting and testing a bit in a minimal
327 symbol that marks it as 32-bit function. The MSB of the minimal
328 symbol's "info" field is used for this purpose. This field is
329 already being used to store the symbol size, so the assumption is
330 that the symbol size cannot exceed 2^31.
331
332 ELF_MAKE_MSYMBOL_SPECIAL
333 tests whether an ELF symbol is "special", i.e. refers
334 to a 32-bit function, and sets a "special" bit in a
335 minimal symbol to mark it as a 32-bit function
336 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
337 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
338 the "info" field with the "special" bit masked out */
339
340#define MSYMBOL_IS_SPECIAL(msym) \
341 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
342
343void
344sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
345{
346 if (msym == NULL)
347 return;
348
349 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
350 {
351 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000);
352 SYMBOL_VALUE_ADDRESS (msym) |= 1;
353 }
354}
355
356/* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
357 are some macros to test, set, or clear bit 0 of addresses. */
358#define IS_ISA32_ADDR(addr) ((addr) & 1)
359#define MAKE_ISA32_ADDR(addr) ((addr) | 1)
360#define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
361
362static int
363pc_is_isa32 (bfd_vma memaddr)
364{
365 struct minimal_symbol *sym;
366
367 /* If bit 0 of the address is set, assume this is a
368 ISA32 (shmedia) address. */
369 if (IS_ISA32_ADDR (memaddr))
370 return 1;
371
372 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
373 the high bit of the info field. Use this to decide if the function is
374 ISA16 or ISA32. */
375 sym = lookup_minimal_symbol_by_pc (memaddr);
376 if (sym)
377 return MSYMBOL_IS_SPECIAL (sym);
378 else
379 return 0;
380}
381
382static const unsigned char *
383sh_sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
384{
385 /* The BRK instruction for shmedia is
386 01101111 11110101 11111111 11110000
387 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
388 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
389
390 /* The BRK instruction for shcompact is
391 00000000 00111011
392 which translates in big endian mode to 0x0, 0x3b
393 and in little endian mode to 0x3b, 0x0*/
394
395 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
396 {
397 if (pc_is_isa32 (*pcptr))
398 {
399 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
400 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
401 *lenptr = sizeof (big_breakpoint_media);
402 return big_breakpoint_media;
403 }
404 else
405 {
406 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
407 *lenptr = sizeof (big_breakpoint_compact);
408 return big_breakpoint_compact;
409 }
410 }
411 else
412 {
413 if (pc_is_isa32 (*pcptr))
414 {
415 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
416 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
417 *lenptr = sizeof (little_breakpoint_media);
418 return little_breakpoint_media;
419 }
420 else
421 {
422 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
423 *lenptr = sizeof (little_breakpoint_compact);
424 return little_breakpoint_compact;
425 }
426 }
427}
428
c906108c 429/* Prologue looks like
c5aa993b
JM		 430 [mov.l <regs>,@-r15]...
431 [sts.l pr,@-r15]
432 [mov.l r14,@-r15]
433 [mov r15,r14]
8db62801
EZ		 434
435 Actually it can be more complicated than this. For instance, with
436 newer gcc's:
437
438 mov.l r14,@-r15
439 add #-12,r15
440 mov r15,r14
441 mov r4,r1
442 mov r5,r2
443 mov.l r6,@(4,r14)
444 mov.l r7,@(8,r14)
445 mov.b r1,@r14
446 mov r14,r1
447 mov r14,r1
448 add #2,r1
449 mov.w r2,@r1
450
c5aa993b 451 */
c906108c 452
283150cd
EZ		 453/* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
454 with l=1 and n = 18 0110101111110001010010100aaa0000 */
455#define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
456
457/* STS.L PR,@-r0 0100000000100010
458 r0-4-->r0, PR-->(r0) */
459#define IS_STS_R0(x) ((x) == 0x4022)
460
461/* STS PR, Rm 0000mmmm00101010
462 PR-->Rm */
463#define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
464
465/* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
466 Rm-->(dispx4+r15) */
467#define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
468
469/* MOV.L R14,@(disp,r15) 000111111110dddd
470 R14-->(dispx4+r15) */
471#define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
472
473/* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
474 R18-->(dispx8+R14) */
475#define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
476
477/* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
478 R18-->(dispx8+R15) */
479#define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
480
481/* ST.L R15, disp, R18 101010001111dddddddddd0100100000
482 R18-->(dispx4+R15) */
483#define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
484
485/* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
486 R14-->(dispx8+R15) */
487#define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
488
489/* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
490 R14-->(dispx4+R15) */
491#define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
492
493/* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
494 R15 + imm --> R15 */
495#define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
496
497/* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
498 R15 + imm --> R15 */
499#define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
500
501/* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
502 R15 + R63 --> R14 */
503#define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
504
505/* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
506 R15 + R63 --> R14 */
507#define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
508
509#define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
510
511/* MOV #imm, R0 1110 0000 ssss ssss
512 #imm-->R0 */
513#define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
514
515/* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
516#define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
517
518/* ADD r15,r0 0011 0000 1111 1100
519 r15+r0-->r0 */
520#define IS_ADD_SP_R0(x) ((x) == 0x30fc)
521
522/* MOV.L R14 @-R0 0010 0000 1110 0110
523 R14-->(R0-4), R0-4-->R0 */
524#define IS_MOV_R14_R0(x) ((x) == 0x20e6)
525
526/* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
527 where Rm is one of r2-r9 which are the argument registers. */
528/* FIXME: Recognize the float and double register moves too! */
529#define IS_MEDIA_IND_ARG_MOV(x) \
530((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
531
532/* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
533 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
534 where Rm is one of r2-r9 which are the argument registers. */
535#define IS_MEDIA_ARG_MOV(x) \
536(((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
537 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
538
539/* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
540/* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
541/* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
542/* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
543/* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
544#define IS_MEDIA_MOV_TO_R14(x) \
545((((x) & 0xfffffc0f) == 0xa0e00000) \
546|| (((x) & 0xfffffc0f) == 0xa4e00000) \
547|| (((x) & 0xfffffc0f) == 0xa8e00000) \
548|| (((x) & 0xfffffc0f) == 0xb4e00000) \
549|| (((x) & 0xfffffc0f) == 0xbce00000))
550
551/* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
552 where Rm is r2-r9 */
553#define IS_COMPACT_IND_ARG_MOV(x) \
554((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
555
556/* compact direct arg move!
557 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
558#define IS_COMPACT_ARG_MOV(x) \
559(((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
560
561/* MOV.B Rm, @R14 0010 1110 mmmm 0000
562 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
563#define IS_COMPACT_MOV_TO_R14(x) \
564((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
565
566#define IS_JSR_R0(x) ((x) == 0x400b)
567#define IS_NOP(x) ((x) == 0x0009)
568
569
8db62801
EZ		 570/* STS.L PR,@-r15 0100111100100010
571 r15-4-->r15, PR-->(r15) */
c906108c 572#define IS_STS(x) ((x) == 0x4f22)
8db62801
EZ		 573
574/* MOV.L Rm,@-r15 00101111mmmm0110
575 r15-4-->r15, Rm-->(R15) */
c906108c 576#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 577
c906108c 578#define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
8db62801
EZ		 579
580/* MOV r15,r14 0110111011110011
581 r15-->r14 */
c906108c 582#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 583
584/* ADD #imm,r15 01111111iiiiiiii
585 r15+imm-->r15 */
c906108c 586#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 587
c906108c
SS		 588#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
589#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 590
591/* ADD r3,r15 0011111100111100
592 r15+r3-->r15 */
c906108c 593#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 594
595/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 596 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 597 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
c906108c 598#define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
c906108c 599
8db62801 600/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
8db62801 601 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
8db62801
EZ		 602 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
603 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
604#define IS_ARG_MOV(x) \
605(((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
cc17453a
EZ		 606 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
607 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
8db62801
EZ		 608
609/* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
610 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
3bbfbb92 611#define IS_MOV_TO_R14(x) \
cc17453a 612 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
8db62801
EZ		 613
614#define FPSCR_SZ (1 << 20)
c906108c 615
c906108c
SS		 616/* Skip any prologue before the guts of a function */
617
8db62801
EZ		 618/* Skip the prologue using the debug information. If this fails we'll
619 fall back on the 'guess' method below. */
620static CORE_ADDR
fba45db2 621after_prologue (CORE_ADDR pc)
8db62801
EZ		 622{
623 struct symtab_and_line sal;
624 CORE_ADDR func_addr, func_end;
625
626 /* If we can not find the symbol in the partial symbol table, then
627 there is no hope we can determine the function's start address
628 with this code. */
629 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
630 return 0;
631
632 /* Get the line associated with FUNC_ADDR. */
633 sal = find_pc_line (func_addr, 0);
634
635 /* There are only two cases to consider. First, the end of the source line
636 is within the function bounds. In that case we return the end of the
637 source line. Second is the end of the source line extends beyond the
638 bounds of the current function. We need to use the slow code to
639 examine instructions in that case. */
640 if (sal.end < func_end)
641 return sal.end;
642 else
643 return 0;
644}
645
646/* Here we look at each instruction in the function, and try to guess
647 where the prologue ends. Unfortunately this is not always
648 accurate. */
649static CORE_ADDR
3bbfbb92 650sh_skip_prologue_hard_way (CORE_ADDR start_pc)
c906108c 651{
2bfa91ee 652 CORE_ADDR here, end;
8db62801 653 int updated_fp = 0;
2bfa91ee
EZ		 654
655 if (!start_pc)
656 return 0;
657
658 for (here = start_pc, end = start_pc + (2 * 28); here < end;)
c906108c 659 {
2bfa91ee
EZ		 660 int w = read_memory_integer (here, 2);
661 here += 2;
662 if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w)
8db62801 663 || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w)
3bbfbb92 664 || IS_ARG_MOV (w) || IS_MOV_TO_R14 (w))
2bfa91ee
EZ		 665 {
666 start_pc = here;
2bfa91ee 667 }
8db62801
EZ		 668 else if (IS_MOV_SP_FP (w))
669 {
670 start_pc = here;
671 updated_fp = 1;
672 }
673 else
674 /* Don't bail out yet, if we are before the copy of sp. */
675 if (updated_fp)
676 break;
c906108c
SS		 677 }
678
679 return start_pc;
680}
681
283150cd
EZ		 682static CORE_ADDR
683look_for_args_moves (CORE_ADDR start_pc, int media_mode)
684{
685 CORE_ADDR here, end;
686 int w;
687 int insn_size = (media_mode ? 4 : 2);
688
689 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
690 {
691 if (media_mode)
692 {
693 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
694 here += insn_size;
695 if (IS_MEDIA_IND_ARG_MOV (w))
696 {
697 /* This must be followed by a store to r14, so the argument
698 is where the debug info says it is. This can happen after
699 the SP has been saved, unfortunately. */
700
701 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
702 insn_size);
703 here += insn_size;
704 if (IS_MEDIA_MOV_TO_R14 (next_insn))
705 start_pc = here;
706 }
707 else if (IS_MEDIA_ARG_MOV (w))
708 {
709 /* These instructions store directly the argument in r14. */
710 start_pc = here;
711 }
712 else
713 break;
714 }
715 else
716 {
717 w = read_memory_integer (here, insn_size);
718 w = w & 0xffff;
719 here += insn_size;
720 if (IS_COMPACT_IND_ARG_MOV (w))
721 {
722 /* This must be followed by a store to r14, so the argument
723 is where the debug info says it is. This can happen after
724 the SP has been saved, unfortunately. */
725
726 int next_insn = 0xffff & read_memory_integer (here, insn_size);
727 here += insn_size;
728 if (IS_COMPACT_MOV_TO_R14 (next_insn))
729 start_pc = here;
730 }
731 else if (IS_COMPACT_ARG_MOV (w))
732 {
733 /* These instructions store directly the argument in r14. */
734 start_pc = here;
735 }
736 else if (IS_MOVL_R0 (w))
737 {
738 /* There is a function that gcc calls to get the arguments
739 passed correctly to the function. Only after this
740 function call the arguments will be found at the place
741 where they are supposed to be. This happens in case the
742 argument has to be stored into a 64-bit register (for
743 instance doubles, long longs). SHcompact doesn't have
744 access to the full 64-bits, so we store the register in
745 stack slot and store the address of the stack slot in
746 the register, then do a call through a wrapper that
747 loads the memory value into the register. A SHcompact
748 callee calls an argument decoder
749 (GCC_shcompact_incoming_args) that stores the 64-bit
750 value in a stack slot and stores the address of the
751 stack slot in the register. GCC thinks the argument is
752 just passed by transparent reference, but this is only
753 true after the argument decoder is called. Such a call
754 needs to be considered part of the prologue. */
755
756 /* This must be followed by a JSR @r0 instruction and by
757 a NOP instruction. After these, the prologue is over! */
758
759 int next_insn = 0xffff & read_memory_integer (here, insn_size);
760 here += insn_size;
761 if (IS_JSR_R0 (next_insn))
762 {
763 next_insn = 0xffff & read_memory_integer (here, insn_size);
764 here += insn_size;
765
766 if (IS_NOP (next_insn))
767 start_pc = here;
768 }
769 }
770 else
771 break;
772 }
773 }
774
775 return start_pc;
776}
777
778static CORE_ADDR
779sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
780{
781 CORE_ADDR here, end;
782 int updated_fp = 0;
783 int insn_size = 4;
784 int media_mode = 1;
785
786 if (!start_pc)
787 return 0;
788
789 if (pc_is_isa32 (start_pc) == 0)
790 {
791 insn_size = 2;
792 media_mode = 0;
793 }
794
795 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
796 {
797
798 if (media_mode)
799 {
800 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
801 here += insn_size;
802 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
803 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
804 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
805 {
806 start_pc = here;
807 }
808 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
809 {
810 start_pc = here;
811 updated_fp = 1;
812 }
813 else
814 if (updated_fp)
815 {
816 /* Don't bail out yet, we may have arguments stored in
817 registers here, according to the debug info, so that
818 gdb can print the frames correctly. */
819 start_pc = look_for_args_moves (here - insn_size, media_mode);
820 break;
821 }
822 }
823 else
824 {
825 int w = 0xffff & read_memory_integer (here, insn_size);
826 here += insn_size;
827
828 if (IS_STS_R0 (w) || IS_STS_PR (w)
829 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
830 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
831 {
832 start_pc = here;
833 }
834 else if (IS_MOV_SP_FP (w))
835 {
836 start_pc = here;
837 updated_fp = 1;
838 }
839 else
840 if (updated_fp)
841 {
842 /* Don't bail out yet, we may have arguments stored in
843 registers here, according to the debug info, so that
844 gdb can print the frames correctly. */
845 start_pc = look_for_args_moves (here - insn_size, media_mode);
846 break;
847 }
848 }
849 }
850
851 return start_pc;
852}
853
cc17453a 854static CORE_ADDR
fba45db2 855sh_skip_prologue (CORE_ADDR pc)
8db62801
EZ		 856{
857 CORE_ADDR post_prologue_pc;
858
859 /* See if we can determine the end of the prologue via the symbol table.
860 If so, then return either PC, or the PC after the prologue, whichever
861 is greater. */
8db62801
EZ		 862 post_prologue_pc = after_prologue (pc);
863
864 /* If after_prologue returned a useful address, then use it. Else
865 fall back on the instruction skipping code. */
866 if (post_prologue_pc != 0)
867 return max (pc, post_prologue_pc);
868 else
869 return (skip_prologue_hard_way (pc));
870}
871
cc17453a
EZ		 872/* Immediately after a function call, return the saved pc.
873 Can't always go through the frames for this because on some machines
874 the new frame is not set up until the new function executes
875 some instructions.
876
877 The return address is the value saved in the PR register + 4 */
878static CORE_ADDR
fba45db2 879sh_saved_pc_after_call (struct frame_info *frame)
cc17453a 880{
3bbfbb92 881 return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM)));
cc17453a
EZ		 882}
883
884/* Should call_function allocate stack space for a struct return? */
885static int
fba45db2 886sh_use_struct_convention (int gcc_p, struct type *type)
cc17453a
EZ		 887{
888 return (TYPE_LENGTH (type) > 1);
889}
890
283150cd
EZ		 891static int
892sh64_use_struct_convention (int gcc_p, struct type *type)
893{
894 return (TYPE_LENGTH (type) > 8);
895}
896
cc17453a
EZ		 897/* Store the address of the place in which to copy the structure the
898 subroutine will return. This is called from call_function.
899
3bbfbb92 900 We store structs through a pointer passed in R2 */
cc17453a 901static void
fba45db2 902sh_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
cc17453a
EZ		 903{
904 write_register (STRUCT_RETURN_REGNUM, (addr));
905}
c906108c 906
cc17453a
EZ		 907/* Disassemble an instruction. */
908static int
fba45db2 909gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
c906108c 910{
1c509ca8
JR		 911 info->endian = TARGET_BYTE_ORDER;
912 return print_insn_sh (memaddr, info);
283150cd
EZ		 913}
914
c906108c
SS		 915/* Given a GDB frame, determine the address of the calling function's frame.
916 This will be used to create a new GDB frame struct, and then
917 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
918
919 For us, the frame address is its stack pointer value, so we look up
920 the function prologue to determine the caller's sp value, and return it. */
cc17453a 921static CORE_ADDR
fba45db2 922sh_frame_chain (struct frame_info *frame)
c906108c
SS		 923{
924 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
925 return frame->frame; /* dummy frame same as caller's frame */
2bfa91ee 926 if (frame->pc && !inside_entry_file (frame->pc))
cc17453a 927 return read_memory_integer (FRAME_FP (frame) + frame->extra_info->f_offset, 4);
c906108c
SS		 928 else
929 return 0;
930}
931
283150cd
EZ		 932/* Given a register number RN as it appears in an assembly
933 instruction, find the corresponding register number in the GDB
934 scheme. */
935static int
936translate_insn_rn (int rn, int media_mode)
937{
938 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
939
940 /* FIXME: this assumes that the number rn is for a not pseudo
941 register only. */
942 if (media_mode)
943 return rn;
944 else
945 {
946 /* These registers don't have a corresponding compact one. */
947 /* FIXME: This is probably not enough. */
948#if 0
949 if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140))
950 return rn;
951#endif
952 if (rn >= 0 && rn <= tdep->R0_C_REGNUM)
953 return tdep->R0_C_REGNUM + rn;
954 else
955 return rn;
956 }
957}
958
959static CORE_ADDR
960sh64_frame_chain (struct frame_info *frame)
961{
962 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
963 return frame->frame; /* dummy frame same as caller's frame */
964 if (frame->pc && !inside_entry_file (frame->pc))
965 {
966 int media_mode = pc_is_isa32 (frame->pc);
967 int size;
968 if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
969 size = 4;
970 else
971 size = REGISTER_RAW_SIZE (translate_insn_rn (FP_REGNUM, media_mode));
972 return read_memory_integer (FRAME_FP (frame) + frame->extra_info->f_offset, size);
973 }
974 else
975 return 0;
976}
977
c906108c
SS		 978/* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
979 we might want to do here is to check REGNUM against the clobber mask, and
980 somehow flag it as invalid if it isn't saved on the stack somewhere. This
981 would provide a graceful failure mode when trying to get the value of
982 caller-saves registers for an inner frame. */
cc17453a 983static CORE_ADDR
fba45db2 984sh_find_callers_reg (struct frame_info *fi, int regnum)
c906108c 985{
c906108c
SS		 986 for (; fi; fi = fi->next)
987 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
988 /* When the caller requests PR from the dummy frame, we return PC because
c5aa993b 989 that's where the previous routine appears to have done a call from. */
c906108c 990 return generic_read_register_dummy (fi->pc, fi->frame, regnum);
c5aa993b 991 else
c906108c 992 {
cc17453a 993 FRAME_INIT_SAVED_REGS (fi);
2bfa91ee
EZ		 994 if (!fi->pc)
995 return 0;
cc17453a
EZ		 996 if (fi->saved_regs[regnum] != 0)
997 return read_memory_integer (fi->saved_regs[regnum],
c5aa993b 998 REGISTER_RAW_SIZE (regnum));
c906108c
SS		 999 }
1000 return read_register (regnum);
1001}
1002
283150cd
EZ		 1003static CORE_ADDR
1004sh64_get_saved_pr (struct frame_info *fi, int pr_regnum)
1005{
1006 int media_mode = 0;
1007
1008 for (; fi; fi = fi->next)
1009 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
1010 /* When the caller requests PR from the dummy frame, we return PC because
1011 that's where the previous routine appears to have done a call from. */
1012 return generic_read_register_dummy (fi->pc, fi->frame, pr_regnum);
1013 else
1014 {
1015 FRAME_INIT_SAVED_REGS (fi);
1016 if (!fi->pc)
1017 return 0;
1018
1019 media_mode = pc_is_isa32 (fi->pc);
1020
1021 if (fi->saved_regs[pr_regnum] != 0)
1022 {
1023 int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode);
1024 int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
1025 ? 4
1026 : REGISTER_RAW_SIZE (gdb_reg_num));
1027 return read_memory_integer (fi->saved_regs[pr_regnum], size);
1028 }
1029 }
1030 return read_register (pr_regnum);
1031}
1032
c906108c
SS		 1033/* Put here the code to store, into a struct frame_saved_regs, the
1034 addresses of the saved registers of frame described by FRAME_INFO.
1035 This includes special registers such as pc and fp saved in special
1036 ways in the stack frame. sp is even more special: the address we
1037 return for it IS the sp for the next frame. */
cc17453a 1038static void
fba45db2 1039sh_nofp_frame_init_saved_regs (struct frame_info *fi)
c906108c 1040{
e7d717c0 1041 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof(int));
c906108c
SS		 1042 int rn;
1043 int have_fp = 0;
1044 int depth;
1045 int pc;
1046 int opc;
1047 int insn;
1048 int r3_val = 0;
c5aa993b 1049 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
cc17453a
EZ		 1050
1051 if (fi->saved_regs == NULL)
1052 frame_saved_regs_zalloc (fi);
1053 else
1054 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
1055
1056 if (dummy_regs)
1057 {
1058 /* DANGER! This is ONLY going to work if the char buffer format of
1059 the saved registers is byte-for-byte identical to the
1060 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1061 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
1062 return;
1063 }
1064
1065 fi->extra_info->leaf_function = 1;
1066 fi->extra_info->f_offset = 0;
1067
cd4bffcf 1068 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
cc17453a
EZ		 1069 where[rn] = -1;
1070
1071 depth = 0;
1072
1073 /* Loop around examining the prologue insns until we find something
1074 that does not appear to be part of the prologue. But give up
1075 after 20 of them, since we're getting silly then. */
1076
1077 pc = get_pc_function_start (fi->pc);
1078 if (!pc)
1079 {
1080 fi->pc = 0;
1081 return;
1082 }
1083
1084 for (opc = pc + (2 * 28); pc < opc; pc += 2)
1085 {
1086 insn = read_memory_integer (pc, 2);
1087 /* See where the registers will be saved to */
1088 if (IS_PUSH (insn))
1089 {
1090 rn = GET_PUSHED_REG (insn);
1091 where[rn] = depth;
1092 depth += 4;
1093 }
1094 else if (IS_STS (insn))
1095 {
3bbfbb92 1096 where[gdbarch_tdep (current_gdbarch)->PR_REGNUM] = depth;
cc17453a
EZ		 1097 /* If we're storing the pr then this isn't a leaf */
1098 fi->extra_info->leaf_function = 0;
1099 depth += 4;
1100 }
1101 else if (IS_MOV_R3 (insn))
1102 {
1103 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
1104 }
1105 else if (IS_SHLL_R3 (insn))
1106 {
1107 r3_val <<= 1;
1108 }
1109 else if (IS_ADD_R3SP (insn))
1110 {
1111 depth += -r3_val;
1112 }
1113 else if (IS_ADD_SP (insn))
1114 {
1115 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1116 }
1117 else if (IS_MOV_SP_FP (insn))
1118 break;
1119#if 0 /* This used to just stop when it found an instruction that
1120 was not considered part of the prologue. Now, we just
1121 keep going looking for likely instructions. */
1122 else
1123 break;
1124#endif
1125 }
1126
1127 /* Now we know how deep things are, we can work out their addresses */
1128
cd4bffcf 1129 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
cc17453a
EZ		 1130 {
1131 if (where[rn] >= 0)
1132 {
1133 if (rn == FP_REGNUM)
1134 have_fp = 1;
c906108c 1135
cc17453a
EZ		 1136 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
1137 }
1138 else
1139 {
1140 fi->saved_regs[rn] = 0;
1141 }
1142 }
1143
1144 if (have_fp)
1145 {
1146 fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
1147 }
1148 else
1149 {
1150 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
1151 }
1152
1153 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
1154 /* Work out the return pc - either from the saved pr or the pr
1155 value */
1156}
1157
3bbfbb92
EZ		 1158/* For vectors of 4 floating point registers. */
1159static int
1160fv_reg_base_num (int fv_regnum)
1161{
1162 int fp_regnum;
1163
1164 fp_regnum = FP0_REGNUM +
1165 (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4;
1166 return fp_regnum;
1167}
1168
1169/* For double precision floating point registers, i.e 2 fp regs.*/
1170static int
1171dr_reg_base_num (int dr_regnum)
1172{
1173 int fp_regnum;
1174
1175 fp_regnum = FP0_REGNUM +
1176 (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2;
1177 return fp_regnum;
1178}
1179
283150cd
EZ		 1180/* For pairs of floating point registers */
1181static int
1182fpp_reg_base_num (int fpp_regnum)
1183{
1184 int fp_regnum;
1185
1186 fp_regnum = FP0_REGNUM +
1187 (fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM) * 2;
1188 return fp_regnum;
1189}
1190
1191static int
1192is_media_pseudo (int rn)
1193{
1194 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1195
1196 return (rn >= tdep->DR0_REGNUM
1197 && rn <= tdep->FV_LAST_REGNUM);
1198}
1199
1200int
1201sh64_get_gdb_regnum (int gcc_regnum, CORE_ADDR pc)
1202{
1203 return translate_insn_rn (gcc_regnum, pc_is_isa32 (pc));
1204}
1205
1206static int
1207sh64_media_reg_base_num (int reg_nr)
1208{
1209 int base_regnum = -1;
1210 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1211
1212 if (reg_nr >= tdep->DR0_REGNUM
1213 && reg_nr <= tdep->DR_LAST_REGNUM)
1214 base_regnum = dr_reg_base_num (reg_nr);
1215
1216 else if (reg_nr >= tdep->FPP0_REGNUM
1217 && reg_nr <= tdep->FPP_LAST_REGNUM)
1218 base_regnum = fpp_reg_base_num (reg_nr);
1219
1220 else if (reg_nr >= tdep->FV0_REGNUM
1221 && reg_nr <= tdep->FV_LAST_REGNUM)
1222 base_regnum = fv_reg_base_num (reg_nr);
1223
1224 return base_regnum;
1225}
1226
1227/* *INDENT-OFF* */
1228/*
1229 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1230 GDB_REGNUM BASE_REGNUM
1231 r0_c 221 0
1232 r1_c 222 1
1233 r2_c 223 2
1234 r3_c 224 3
1235 r4_c 225 4
1236 r5_c 226 5
1237 r6_c 227 6
1238 r7_c 228 7
1239 r8_c 229 8
1240 r9_c 230 9
1241 r10_c 231 10
1242 r11_c 232 11
1243 r12_c 233 12
1244 r13_c 234 13
1245 r14_c 235 14
1246 r15_c 236 15
1247
1248 pc_c 237 64
1249 gbr_c 238 16
1250 mach_c 239 17
1251 macl_c 240 17
1252 pr_c 241 18
1253 t_c 242 19
1254 fpscr_c 243 76
1255 fpul_c 244 109
1256
1257 fr0_c 245 77
1258 fr1_c 246 78
1259 fr2_c 247 79
1260 fr3_c 248 80
1261 fr4_c 249 81
1262 fr5_c 250 82
1263 fr6_c 251 83
1264 fr7_c 252 84
1265 fr8_c 253 85
1266 fr9_c 254 86
1267 fr10_c 255 87
1268 fr11_c 256 88
1269 fr12_c 257 89
1270 fr13_c 258 90
1271 fr14_c 259 91
1272 fr15_c 260 92
1273
1274 dr0_c 261 77
1275 dr2_c 262 79
1276 dr4_c 263 81
1277 dr6_c 264 83
1278 dr8_c 265 85
1279 dr10_c 266 87
1280 dr12_c 267 89
1281 dr14_c 268 91
1282
1283 fv0_c 269 77
1284 fv4_c 270 81
1285 fv8_c 271 85
1286 fv12_c 272 91
1287*/
1288/* *INDENT-ON* */
1289static int
1290sh64_compact_reg_base_num (int reg_nr)
1291{
1292 int base_regnum = -1;
1293 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1294
1295 /* general register N maps to general register N */
1296 if (reg_nr >= tdep->R0_C_REGNUM
1297 && reg_nr <= tdep->R_LAST_C_REGNUM)
1298 base_regnum = reg_nr - tdep->R0_C_REGNUM;
1299
1300 /* floating point register N maps to floating point register N */
1301 else if (reg_nr >= tdep->FP0_C_REGNUM
1302 && reg_nr <= tdep->FP_LAST_C_REGNUM)
1303 base_regnum = reg_nr - tdep->FP0_C_REGNUM + FP0_REGNUM;
1304
1305 /* double prec register N maps to base regnum for double prec register N */
1306 else if (reg_nr >= tdep->DR0_C_REGNUM
1307 && reg_nr <= tdep->DR_LAST_C_REGNUM)
1308 base_regnum = dr_reg_base_num (tdep->DR0_REGNUM
1309 + reg_nr - tdep->DR0_C_REGNUM);
1310
1311 /* vector N maps to base regnum for vector register N */
1312 else if (reg_nr >= tdep->FV0_C_REGNUM
1313 && reg_nr <= tdep->FV_LAST_C_REGNUM)
1314 base_regnum = fv_reg_base_num (tdep->FV0_REGNUM
1315 + reg_nr - tdep->FV0_C_REGNUM);
1316
1317 else if (reg_nr == tdep->PC_C_REGNUM)
1318 base_regnum = PC_REGNUM;
1319
1320 else if (reg_nr == tdep->GBR_C_REGNUM)
1321 base_regnum = 16;
1322
1323 else if (reg_nr == tdep->MACH_C_REGNUM
1324 || reg_nr == tdep->MACL_C_REGNUM)
1325 base_regnum = 17;
1326
1327 else if (reg_nr == tdep->PR_C_REGNUM)
1328 base_regnum = 18;
1329
1330 else if (reg_nr == tdep->T_C_REGNUM)
1331 base_regnum = 19;
1332
1333 else if (reg_nr == tdep->FPSCR_C_REGNUM)
1334 base_regnum = tdep->FPSCR_REGNUM; /*???? this register is a mess. */
1335
1336 else if (reg_nr == tdep->FPUL_C_REGNUM)
1337 base_regnum = FP0_REGNUM + 32;
1338
1339 return base_regnum;
1340}
1341
1342/* Given a register number RN (according to the gdb scheme) , return
1343 its corresponding architectural register. In media mode, only a
1344 subset of the registers is pseudo registers. For compact mode, all
1345 the registers are pseudo. */
1346static int
1347translate_rn_to_arch_reg_num (int rn, int media_mode)
1348{
1349
1350 if (media_mode)
1351 {
1352 if (!is_media_pseudo (rn))
1353 return rn;
1354 else
1355 return sh64_media_reg_base_num (rn);
1356 }
1357 else
1358 /* All compact registers are pseudo. */
1359 return sh64_compact_reg_base_num (rn);
1360}
1361
1362static int
1363sign_extend (int value, int bits)
1364{
1365 value = value & ((1 << bits) - 1);
1366 return (value & (1 << (bits - 1))
1367 ? value | (~((1 << bits) - 1))
1368 : value);
1369}
1370
cc17453a 1371static void
283150cd 1372sh64_nofp_frame_init_saved_regs (struct frame_info *fi)
cc17453a 1373{
ddde02bd 1374 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
cc17453a
EZ		 1375 int rn;
1376 int have_fp = 0;
283150cd
EZ		 1377 int fp_regnum;
1378 int sp_regnum;
1379 int depth;
1380 int pc;
1381 int opc;
1382 int insn;
1383 int r0_val = 0;
1384 int media_mode = 0;
1385 int insn_size;
1386 int gdb_register_number;
1387 int register_number;
1388 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
1389 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1390
1391 if (fi->saved_regs == NULL)
1392 frame_saved_regs_zalloc (fi);
1393 else
1394 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
1395
1396 if (dummy_regs)
1397 {
1398 /* DANGER! This is ONLY going to work if the char buffer format of
1399 the saved registers is byte-for-byte identical to the
1400 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1401 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
1402 return;
1403 }
1404
1405 fi->extra_info->leaf_function = 1;
1406 fi->extra_info->f_offset = 0;
1407
1408 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1409 where[rn] = -1;
1410
1411 depth = 0;
1412
1413 /* Loop around examining the prologue insns until we find something
1414 that does not appear to be part of the prologue. But give up
1415 after 20 of them, since we're getting silly then. */
1416
1417 pc = get_pc_function_start (fi->pc);
1418 if (!pc)
1419 {
1420 fi->pc = 0;
1421 return;
1422 }
1423
1424 if (pc_is_isa32 (pc))
1425 {
1426 media_mode = 1;
1427 insn_size = 4;
1428 }
1429 else
1430 {
1431 media_mode = 0;
1432 insn_size = 2;
1433 }
1434
1435 /* The frame pointer register is general register 14 in shmedia and
1436 shcompact modes. In sh compact it is a pseudo register. Same goes
1437 for the stack pointer register, which is register 15. */
1438 fp_regnum = translate_insn_rn (FP_REGNUM, media_mode);
1439 sp_regnum = translate_insn_rn (SP_REGNUM, media_mode);
1440
1441 for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size)
1442 {
1443 insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc,
1444 insn_size);
1445
1446 if (media_mode == 0)
1447 {
1448 if (IS_STS_PR (insn))
1449 {
1450 int next_insn = read_memory_integer (pc + insn_size, insn_size);
1451 if (IS_MOV_TO_R15 (next_insn))
1452 {
1453 int reg_nr = tdep->PR_C_REGNUM;
1454
1455 where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
1456 fi->extra_info->leaf_function = 0;
1457 pc += insn_size;
1458 }
1459 }
1460 else if (IS_MOV_R14 (insn))
1461 {
1462 where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
1463 }
1464
1465 else if (IS_MOV_R0 (insn))
1466 {
1467 /* Put in R0 the offset from SP at which to store some
1468 registers. We are interested in this value, because it
1469 will tell us where the given registers are stored within
1470 the frame. */
1471 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
1472 }
1473 else if (IS_ADD_SP_R0 (insn))
1474 {
1475 /* This instruction still prepares r0, but we don't care.
1476 We already have the offset in r0_val. */
1477 }
1478 else if (IS_STS_R0 (insn))
1479 {
1480 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1481 int reg_nr = tdep->PR_C_REGNUM;
1482 where[reg_nr] = depth - (r0_val - 4);
1483 r0_val -= 4;
1484 fi->extra_info->leaf_function = 0;
1485 }
1486 else if (IS_MOV_R14_R0 (insn))
1487 {
1488 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1489 where[fp_regnum] = depth - (r0_val - 4);
1490 r0_val -= 4;
1491 }
1492
1493 else if (IS_ADD_SP (insn))
1494 {
1495 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1496 }
1497 else if (IS_MOV_SP_FP (insn))
1498 break;
1499 }
1500 else
1501 {
1502 if (IS_ADDIL_SP_MEDIA (insn)
1503 || IS_ADDI_SP_MEDIA (insn))
1504 {
1505 depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1506 }
1507
1508 else if (IS_STQ_R18_R15 (insn))
1509 {
1510 where[tdep->PR_REGNUM] =
1511 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1512 fi->extra_info->leaf_function = 0;
1513 }
1514
1515 else if (IS_STL_R18_R15 (insn))
1516 {
1517 where[tdep->PR_REGNUM] =
1518 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1519 fi->extra_info->leaf_function = 0;
1520 }
1521
1522 else if (IS_STQ_R14_R15 (insn))
1523 {
1524 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1525 }
1526
1527 else if (IS_STL_R14_R15 (insn))
1528 {
1529 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1530 }
1531
1532 else if (IS_MOV_SP_FP_MEDIA (insn))
1533 break;
1534 }
1535 }
1536
1537 /* Now we know how deep things are, we can work out their addresses. */
1538 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1539 {
1540 register_number = translate_rn_to_arch_reg_num (rn, media_mode);
1541
1542 if (where[rn] >= 0)
1543 {
1544 if (rn == fp_regnum)
1545 have_fp = 1;
1546
1547 /* Watch out! saved_regs is only for the real registers, and
1548 doesn't include space for the pseudo registers. */
1549 fi->saved_regs[register_number]= fi->frame - where[rn] + depth;
1550
1551 }
1552 else
1553 fi->saved_regs[register_number] = 0;
1554 }
1555
1556 if (have_fp)
1557 {
1558 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1559 shcompact 15 is the arch register corresponding to the pseudo
1560 register r15 which still is the SP register. */
1561 /* The place on the stack where fp is stored contains the sp of
1562 the caller. */
1563 /* Again, saved_registers contains only space for the real registers,
1564 so we store in FP_REGNUM position. */
1565 int size;
1566 if (tdep->sh_abi == SH_ABI_32)
1567 size = 4;
1568 else
1569 size = REGISTER_RAW_SIZE (fp_regnum);
1570 fi->saved_regs[sp_regnum] = read_memory_integer (fi->saved_regs[fp_regnum], size);
1571 }
1572 else
1573 fi->saved_regs[sp_regnum] = fi->frame;
1574
1575 fi->extra_info->f_offset = depth - where[fp_regnum];
1576}
1577
1578static void
1579sh_fp_frame_init_saved_regs (struct frame_info *fi)
1580{
ddde02bd 1581 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
283150cd
EZ		 1582 int rn;
1583 int have_fp = 0;
cc17453a
EZ		 1584 int depth;
1585 int pc;
1586 int opc;
1587 int insn;
1588 int r3_val = 0;
1589 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
f81353e4 1590 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
cc17453a
EZ		 1591
1592 if (fi->saved_regs == NULL)
1593 frame_saved_regs_zalloc (fi);
1594 else
1595 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
1596
c906108c
SS		 1597 if (dummy_regs)
1598 {
1599 /* DANGER! This is ONLY going to work if the char buffer format of
c5aa993b
JM		 1600 the saved registers is byte-for-byte identical to the
1601 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
cc17453a 1602 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
c906108c
SS		 1603 return;
1604 }
1605
cc17453a
EZ		 1606 fi->extra_info->leaf_function = 1;
1607 fi->extra_info->f_offset = 0;
c906108c 1608
cd4bffcf 1609 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
c906108c
SS		 1610 where[rn] = -1;
1611
1612 depth = 0;
1613
1614 /* Loop around examining the prologue insns until we find something
1615 that does not appear to be part of the prologue. But give up
1616 after 20 of them, since we're getting silly then. */
1617
2bfa91ee
EZ		 1618 pc = get_pc_function_start (fi->pc);
1619 if (!pc)
c906108c 1620 {
2bfa91ee
EZ		 1621 fi->pc = 0;
1622 return;
1623 }
1624
1625 for (opc = pc + (2 * 28); pc < opc; pc += 2)
1626 {
1627 insn = read_memory_integer (pc, 2);
c906108c
SS		 1628 /* See where the registers will be saved to */
1629 if (IS_PUSH (insn))
1630 {
c906108c
SS		 1631 rn = GET_PUSHED_REG (insn);
1632 where[rn] = depth;
c906108c
SS		 1633 depth += 4;
1634 }
1635 else if (IS_STS (insn))
1636 {
f81353e4 1637 where[tdep->PR_REGNUM] = depth;
c906108c 1638 /* If we're storing the pr then this isn't a leaf */
cc17453a 1639 fi->extra_info->leaf_function = 0;
c906108c
SS		 1640 depth += 4;
1641 }
1642 else if (IS_MOV_R3 (insn))
1643 {
1644 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 1645 }
1646 else if (IS_SHLL_R3 (insn))
1647 {
1648 r3_val <<= 1;
c906108c
SS		 1649 }
1650 else if (IS_ADD_R3SP (insn))
1651 {
1652 depth += -r3_val;
c906108c
SS		 1653 }
1654 else if (IS_ADD_SP (insn))
1655 {
c906108c 1656 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 1657 }
1658 else if (IS_FMOV (insn))
1659 {
f81353e4 1660 if (read_register (tdep->FPSCR_REGNUM) & FPSCR_SZ)
c906108c
SS		 1661 {
1662 depth += 8;
1663 }
1664 else
1665 {
1666 depth += 4;
1667 }
1668 }
2bfa91ee
EZ		 1669 else if (IS_MOV_SP_FP (insn))
1670 break;
1671#if 0 /* This used to just stop when it found an instruction that
1672 was not considered part of the prologue. Now, we just
1673 keep going looking for likely instructions. */
c906108c
SS		 1674 else
1675 break;
2bfa91ee 1676#endif
c906108c
SS		 1677 }
1678
1679 /* Now we know how deep things are, we can work out their addresses */
1680
cd4bffcf 1681 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
c906108c
SS		 1682 {
1683 if (where[rn] >= 0)
1684 {
1685 if (rn == FP_REGNUM)
1686 have_fp = 1;
1687
cc17453a 1688 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
c906108c
SS		 1689 }
1690 else
1691 {
cc17453a 1692 fi->saved_regs[rn] = 0;
c906108c
SS		 1693 }
1694 }
1695
1696 if (have_fp)
1697 {
cd4bffcf
EZ		 1698 fi->saved_regs[SP_REGNUM] =
1699 read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
c906108c
SS		 1700 }
1701 else
1702 {
cc17453a 1703 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
c906108c
SS		 1704 }
1705
cc17453a 1706 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
c906108c
SS		 1707 /* Work out the return pc - either from the saved pr or the pr
1708 value */
1709}
1710
cc17453a
EZ		 1711/* Initialize the extra info saved in a FRAME */
1712static void
fba45db2 1713sh_init_extra_frame_info (int fromleaf, struct frame_info *fi)
c906108c 1714{
cc17453a
EZ		 1715
1716 fi->extra_info = (struct frame_extra_info *)
1717 frame_obstack_alloc (sizeof (struct frame_extra_info));
c906108c
SS		 1718
1719 if (fi->next)
1720 fi->pc = FRAME_SAVED_PC (fi->next);
1721
1722 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
1723 {
1724 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
c5aa993b
JM		 1725 by assuming it's always FP. */
1726 fi->frame = generic_read_register_dummy (fi->pc, fi->frame,
1727 SP_REGNUM);
cd4bffcf
EZ		 1728 fi->extra_info->return_pc = generic_read_register_dummy (fi->pc,
1729 fi->frame,
cc17453a
EZ		 1730 PC_REGNUM);
1731 fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
1732 fi->extra_info->leaf_function = 0;
c906108c
SS		 1733 return;
1734 }
1735 else
1736 {
cc17453a 1737 FRAME_INIT_SAVED_REGS (fi);
cd4bffcf
EZ		 1738 fi->extra_info->return_pc =
1739 sh_find_callers_reg (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
c906108c
SS		 1740 }
1741}
1742
283150cd
EZ		 1743static void
1744sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1745{
1746 int media_mode = pc_is_isa32 (fi->pc);
1747
1748 fi->extra_info = (struct frame_extra_info *)
1749 frame_obstack_alloc (sizeof (struct frame_extra_info));
1750
1751 if (fi->next)
1752 fi->pc = FRAME_SAVED_PC (fi->next);
1753
1754 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
1755 {
1756 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1757 by assuming it's always FP. */
1758 fi->frame = generic_read_register_dummy (fi->pc, fi->frame,
1759 SP_REGNUM);
1760 fi->extra_info->return_pc =
1761 generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM);
1762 fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
1763 fi->extra_info->leaf_function = 0;
1764 return;
1765 }
1766 else
1767 {
1768 FRAME_INIT_SAVED_REGS (fi);
1769 fi->extra_info->return_pc =
1770 sh64_get_saved_pr (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
1771 }
1772}
1773
1774void
1775sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp,
1776 struct frame_info *frame, int regnum,
1777 enum lval_type *lval)
1778{
1779 int media_mode;
1780 int live_regnum = regnum;
1781 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1782
1783 if (!target_has_registers)
1784 error ("No registers.");
1785
1786 /* Normal systems don't optimize out things with register numbers. */
1787 if (optimized != NULL)
1788 *optimized = 0;
1789
1790 if (addrp) /* default assumption: not found in memory */
1791 *addrp = 0;
1792
1793 if (raw_buffer)
1794 memset (raw_buffer, 0, sizeof (raw_buffer));
1795
1796 /* We must do this here, before the following while loop changes
1797 frame, and makes it NULL. If this is a media register number,
1798 but we are in compact mode, it will become the corresponding
1799 compact pseudo register. If there is no corresponding compact
1800 pseudo-register what do we do?*/
1801 media_mode = pc_is_isa32 (frame->pc);
1802 live_regnum = translate_insn_rn (regnum, media_mode);
1803
1804 /* Note: since the current frame's registers could only have been
1805 saved by frames INTERIOR TO the current frame, we skip examining
1806 the current frame itself: otherwise, we would be getting the
1807 previous frame's registers which were saved by the current frame. */
1808
1809 while (frame && ((frame = frame->next) != NULL))
1810 {
1811 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
1812 {
1813 if (lval) /* found it in a CALL_DUMMY frame */
1814 *lval = not_lval;
1815 if (raw_buffer)
1816 memcpy (raw_buffer,
1817 generic_find_dummy_frame (frame->pc, frame->frame) +
1818 REGISTER_BYTE (regnum),
1819 REGISTER_RAW_SIZE (regnum));
1820 return;
1821 }
1822
1823 FRAME_INIT_SAVED_REGS (frame);
1824 if (frame->saved_regs != NULL
1825 && frame->saved_regs[regnum] != 0)
1826 {
1827 if (lval) /* found it saved on the stack */
1828 *lval = lval_memory;
1829 if (regnum == SP_REGNUM)
1830 {
1831 if (raw_buffer) /* SP register treated specially */
1832 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum),
1833 frame->saved_regs[regnum]);
1834 }
1835 else
1836 { /* any other register */
1837
1838 if (addrp)
1839 *addrp = frame->saved_regs[regnum];
1840 if (raw_buffer)
1841 {
1842 int size;
1843 if (tdep->sh_abi == SH_ABI_32
1844 && (live_regnum == FP_REGNUM
1845 || live_regnum == tdep->PR_REGNUM))
1846 size = 4;
1847 else
1848 size = REGISTER_RAW_SIZE (live_regnum);
1849 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1850 read_memory (frame->saved_regs[regnum], raw_buffer, size);
1851 else
1852 read_memory (frame->saved_regs[regnum],
1853 raw_buffer
1854 + REGISTER_RAW_SIZE (live_regnum)
1855 - size,
1856 size);
1857 }
1858 }
1859 return;
1860 }
1861 }
1862
1863 /* If we get thru the loop to this point, it means the register was
1864 not saved in any frame. Return the actual live-register value. */
1865
1866 if (lval) /* found it in a live register */
1867 *lval = lval_register;
1868 if (addrp)
1869 *addrp = REGISTER_BYTE (live_regnum);
1870 if (raw_buffer)
1871 read_register_gen (live_regnum, raw_buffer);
1872}
1873
cc17453a
EZ		 1874/* Extract from an array REGBUF containing the (raw) register state
1875 the address in which a function should return its structure value,
1876 as a CORE_ADDR (or an expression that can be used as one). */
b3df3fff 1877static CORE_ADDR
0c8053b6 1878sh_extract_struct_value_address (char *regbuf)
cc17453a
EZ		 1879{
1880 return (extract_address ((regbuf), REGISTER_RAW_SIZE (0)));
1881}
1882
283150cd
EZ		 1883static CORE_ADDR
1884sh64_extract_struct_value_address (char *regbuf)
1885{
1886 return (extract_address ((regbuf + REGISTER_BYTE (STRUCT_RETURN_REGNUM)),
1887 REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM)));
1888}
1889
cc17453a 1890static CORE_ADDR
fba45db2 1891sh_frame_saved_pc (struct frame_info *frame)
cc17453a
EZ		 1892{
1893 return ((frame)->extra_info->return_pc);
1894}
1895
c906108c
SS		 1896/* Discard from the stack the innermost frame,
1897 restoring all saved registers. */
cc17453a 1898static void
fba45db2 1899sh_pop_frame (void)
c906108c
SS		 1900{
1901 register struct frame_info *frame = get_current_frame ();
1902 register CORE_ADDR fp;
1903 register int regnum;
c906108c
SS		 1904
1905 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
1906 generic_pop_dummy_frame ();
1907 else
c5aa993b
JM		 1908 {
1909 fp = FRAME_FP (frame);
cc17453a 1910 FRAME_INIT_SAVED_REGS (frame);
c906108c 1911
c5aa993b 1912 /* Copy regs from where they were saved in the frame */
cd4bffcf 1913 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
cc17453a 1914 if (frame->saved_regs[regnum])
cd4bffcf
EZ		 1915 write_register (regnum,
1916 read_memory_integer (frame->saved_regs[regnum], 4));
c906108c 1917
cc17453a 1918 write_register (PC_REGNUM, frame->extra_info->return_pc);
c5aa993b
JM		 1919 write_register (SP_REGNUM, fp + 4);
1920 }
c906108c
SS		 1921 flush_cached_frames ();
1922}
1923
283150cd
EZ		 1924/* Used in the 'return' command. */
1925static void
1926sh64_pop_frame (void)
1927{
1928 register struct frame_info *frame = get_current_frame ();
1929 register CORE_ADDR fp;
1930 register int regnum;
1931 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1932
1933 int media_mode = pc_is_isa32 (frame->pc);
1934
1935 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
1936 generic_pop_dummy_frame ();
1937 else
1938 {
1939 fp = FRAME_FP (frame);
1940 FRAME_INIT_SAVED_REGS (frame);
1941
1942 /* Copy regs from where they were saved in the frame */
1943 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
1944 if (frame->saved_regs[regnum])
1945 {
1946 int size;
1947 if (tdep->sh_abi == SH_ABI_32
1948 && (regnum == FP_REGNUM
1949 || regnum == tdep->PR_REGNUM))
1950 size = 4;
1951 else
1952 size = REGISTER_RAW_SIZE (translate_insn_rn (regnum,
1953 media_mode));
1954 write_register (regnum,
1955 read_memory_integer (frame->saved_regs[regnum],
1956 size));
1957 }
1958
1959 write_register (PC_REGNUM, frame->extra_info->return_pc);
1960 write_register (SP_REGNUM, fp + 8);
1961 }
1962 flush_cached_frames ();
1963}
1964
c906108c
SS		 1965/* Function: push_arguments
1966 Setup the function arguments for calling a function in the inferior.
1967
1968 On the Hitachi SH architecture, there are four registers (R4 to R7)
1969 which are dedicated for passing function arguments. Up to the first
1970 four arguments (depending on size) may go into these registers.
1971 The rest go on the stack.
1972
1973 Arguments that are smaller than 4 bytes will still take up a whole
1974 register or a whole 32-bit word on the stack, and will be
1975 right-justified in the register or the stack word. This includes
1976 chars, shorts, and small aggregate types.
1977
1978 Arguments that are larger than 4 bytes may be split between two or
1979 more registers. If there are not enough registers free, an argument
1980 may be passed partly in a register (or registers), and partly on the
1981 stack. This includes doubles, long longs, and larger aggregates.
1982 As far as I know, there is no upper limit to the size of aggregates
1983 that will be passed in this way; in other words, the convention of
1984 passing a pointer to a large aggregate instead of a copy is not used.
1985
1986 An exceptional case exists for struct arguments (and possibly other
1987 aggregates such as arrays) if the size is larger than 4 bytes but
1988 not a multiple of 4 bytes. In this case the argument is never split
1989 between the registers and the stack, but instead is copied in its
1990 entirety onto the stack, AND also copied into as many registers as
1991 there is room for. In other words, space in registers permitting,
1992 two copies of the same argument are passed in. As far as I can tell,
1993 only the one on the stack is used, although that may be a function
1994 of the level of compiler optimization. I suspect this is a compiler
1995 bug. Arguments of these odd sizes are left-justified within the
1996 word (as opposed to arguments smaller than 4 bytes, which are
1997 right-justified).
c5aa993b 1998
c906108c
SS		 1999 If the function is to return an aggregate type such as a struct, it
2000 is either returned in the normal return value register R0 (if its
2001 size is no greater than one byte), or else the caller must allocate
2002 space into which the callee will copy the return value (if the size
2003 is greater than one byte). In this case, a pointer to the return
2004 value location is passed into the callee in register R2, which does
2005 not displace any of the other arguments passed in via registers R4
2006 to R7. */
2007
cc17453a 2008static CORE_ADDR
34e9d9bb 2009sh_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
3bbfbb92 2010 int struct_return, CORE_ADDR struct_addr)
c906108c
SS		 2011{
2012 int stack_offset, stack_alloc;
2013 int argreg;
2014 int argnum;
2015 struct type *type;
2016 CORE_ADDR regval;
2017 char *val;
2018 char valbuf[4];
2019 int len;
2020 int odd_sized_struct;
f81353e4 2021 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
c906108c
SS		 2022
2023 /* first force sp to a 4-byte alignment */
2024 sp = sp & ~3;
2025
2026 /* The "struct return pointer" pseudo-argument has its own dedicated
2027 register */
2028 if (struct_return)
c5aa993b 2029 write_register (STRUCT_RETURN_REGNUM, struct_addr);
c906108c
SS		 2030
2031 /* Now make sure there's space on the stack */
cc17453a 2032 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
c5aa993b
JM		 2033 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
2034 sp -= stack_alloc; /* make room on stack for args */
c906108c 2035
c906108c
SS		 2036 /* Now load as many as possible of the first arguments into
2037 registers, and push the rest onto the stack. There are 16 bytes
2038 in four registers available. Loop thru args from first to last. */
2039
f81353e4 2040 argreg = tdep->ARG0_REGNUM;
c906108c
SS		 2041 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
2042 {
2043 type = VALUE_TYPE (args[argnum]);
c5aa993b
JM		 2044 len = TYPE_LENGTH (type);
2045 memset (valbuf, 0, sizeof (valbuf));
c906108c 2046 if (len < 4)
cc17453a
EZ		 2047 {
2048 /* value gets right-justified in the register or stack word */
c5aa993b
JM		 2049 memcpy (valbuf + (4 - len),
2050 (char *) VALUE_CONTENTS (args[argnum]), len);
2051 val = valbuf;
2052 }
c906108c 2053 else
c5aa993b 2054 val = (char *) VALUE_CONTENTS (args[argnum]);
c906108c
SS		 2055
2056 if (len > 4 && (len & 3) != 0)
c5aa993b
JM		 2057 odd_sized_struct = 1; /* such structs go entirely on stack */
2058 else
c906108c
SS		 2059 odd_sized_struct = 0;
2060 while (len > 0)
2061 {
f81353e4 2062 if (argreg > tdep->ARGLAST_REGNUM
3bbfbb92
EZ		 2063 || odd_sized_struct)
2064 {
2065 /* must go on the stack */
c906108c
SS		 2066 write_memory (sp + stack_offset, val, 4);
2067 stack_offset += 4;
2068 }
2069 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2070 That's because some *&^%$ things get passed on the stack
2071 AND in the registers! */
f81353e4 2072 if (argreg <= tdep->ARGLAST_REGNUM)
3bbfbb92
EZ		 2073 {
2074 /* there's room in a register */
c5aa993b 2075 regval = extract_address (val, REGISTER_RAW_SIZE (argreg));
c906108c
SS		 2076 write_register (argreg++, regval);
2077 }
2078 /* Store the value 4 bytes at a time. This means that things
2079 larger than 4 bytes may go partly in registers and partly
2080 on the stack. */
c5aa993b
JM		 2081 len -= REGISTER_RAW_SIZE (argreg);
2082 val += REGISTER_RAW_SIZE (argreg);
c906108c
SS		 2083 }
2084 }
2085 return sp;
2086}
2087
283150cd
EZ		 2088/* R2-R9 for integer types and integer equivalent (char, pointers) and
2089 non-scalar (struct, union) elements (even if the elements are
2090 floats).
2091 FR0-FR11 for single precision floating point (float)
2092 DR0-DR10 for double precision floating point (double)
2093
2094 If a float is argument number 3 (for instance) and arguments number
2095 1,2, and 4 are integer, the mapping will be:
2096 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
2097
2098 If a float is argument number 10 (for instance) and arguments number
2099 1 through 10 are integer, the mapping will be:
2100 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
2101 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
2102 I.e. there is hole in the stack.
2103
2104 Different rules apply for variable arguments functions, and for functions
2105 for which the prototype is not known. */
2106
2107static CORE_ADDR
2108sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
2109 int struct_return, CORE_ADDR struct_addr)
2110{
2111 int stack_offset, stack_alloc;
2112 int int_argreg;
2113 int float_argreg;
2114 int double_argreg;
2115 int float_arg_index = 0;
2116 int double_arg_index = 0;
2117 int argnum;
2118 struct type *type;
2119 CORE_ADDR regval;
2120 char *val;
2121 char valbuf[8];
2122 char valbuf_tmp[8];
2123 int len;
2124 int argreg_size;
2125 int fp_args[12];
2126 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2127
2128 memset (fp_args, 0, sizeof (fp_args));
2129
2130 /* first force sp to a 8-byte alignment */
2131 sp = sp & ~7;
2132
2133 /* The "struct return pointer" pseudo-argument has its own dedicated
2134 register */
2135
2136 if (struct_return)
2137 write_register (STRUCT_RETURN_REGNUM, struct_addr);
2138
2139 /* Now make sure there's space on the stack */
2140 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
2141 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7);
2142 sp -= stack_alloc; /* make room on stack for args */
2143
2144 /* Now load as many as possible of the first arguments into
2145 registers, and push the rest onto the stack. There are 64 bytes
2146 in eight registers available. Loop thru args from first to last. */
2147
2148 int_argreg = tdep->ARG0_REGNUM;
2149 float_argreg = FP0_REGNUM;
2150 double_argreg = tdep->DR0_REGNUM;
2151
2152 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
2153 {
2154 type = VALUE_TYPE (args[argnum]);
2155 len = TYPE_LENGTH (type);
2156 memset (valbuf, 0, sizeof (valbuf));
2157
2158 if (TYPE_CODE (type) != TYPE_CODE_FLT)
2159 {
2160 argreg_size = REGISTER_RAW_SIZE (int_argreg);
2161
2162 if (len < argreg_size)
2163 {
2164 /* value gets right-justified in the register or stack word */
2165 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2166 memcpy (valbuf + argreg_size - len,
2167 (char *) VALUE_CONTENTS (args[argnum]), len);
2168 else
2169 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
2170
2171 val = valbuf;
2172 }
2173 else
2174 val = (char *) VALUE_CONTENTS (args[argnum]);
2175
2176 while (len > 0)
2177 {
2178 if (int_argreg > tdep->ARGLAST_REGNUM)
2179 {
2180 /* must go on the stack */
2181 write_memory (sp + stack_offset, val, argreg_size);
2182 stack_offset += 8;/*argreg_size;*/
2183 }
2184 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2185 That's because some *&^%$ things get passed on the stack
2186 AND in the registers! */
2187 if (int_argreg <= tdep->ARGLAST_REGNUM)
2188 {
2189 /* there's room in a register */
2190 regval = extract_address (val, argreg_size);
2191 write_register (int_argreg, regval);
2192 }
2193 /* Store the value 8 bytes at a time. This means that
2194 things larger than 8 bytes may go partly in registers
2195 and partly on the stack. FIXME: argreg is incremented
2196 before we use its size. */
2197 len -= argreg_size;
2198 val += argreg_size;
2199 int_argreg++;
2200 }
2201 }
2202 else
2203 {
2204 val = (char *) VALUE_CONTENTS (args[argnum]);
2205 if (len == 4)
2206 {
2207 /* Where is it going to be stored? */
2208 while (fp_args[float_arg_index])
2209 float_arg_index ++;
2210
2211 /* Now float_argreg points to the register where it
2212 should be stored. Are we still within the allowed
2213 register set? */
2214 if (float_arg_index <= tdep->FLOAT_ARGLAST_REGNUM)
2215 {
2216 /* Goes in FR0...FR11 */
2217 write_register_gen (FP0_REGNUM + float_arg_index, val);
2218 fp_args[float_arg_index] = 1;
2219 /* Skip the corresponding general argument register. */
2220 int_argreg ++;
2221 }
2222 else
2223 ;
2224 /* Store it as the integers, 8 bytes at the time, if
2225 necessary spilling on the stack. */
2226
2227 }
2228 else if (len == 8)
2229 {
2230 /* Where is it going to be stored? */
2231 while (fp_args[double_arg_index])
2232 double_arg_index += 2;
2233 /* Now double_argreg points to the register
2234 where it should be stored.
2235 Are we still within the allowed register set? */
2236 if (double_arg_index < tdep->FLOAT_ARGLAST_REGNUM)
2237 {
2238 /* Goes in DR0...DR10 */
2239 /* The numbering of the DRi registers is consecutive,
2240 i.e. includes odd numbers. */
2241 int double_register_offset = double_arg_index / 2;
2242 int regnum = tdep->DR0_REGNUM +
2243 double_register_offset;
2244#if 0
2245 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2246 {
2247 memset (valbuf_tmp, 0, sizeof (valbuf_tmp));
2248 REGISTER_CONVERT_TO_VIRTUAL (regnum,
2249 type, val, valbuf_tmp);
2250 val = valbuf_tmp;
2251 }
2252#endif
2253 /* Note: must use write_register_gen here instead
2254 of regcache_write, because regcache_write works
2255 only for real registers, not pseudo.
2256 write_register_gen will call the gdbarch
2257 function to do register writes, and that will
2258 properly know how to deal with pseudoregs. */
2259 write_register_gen (regnum, val);
2260 fp_args[double_arg_index] = 1;
2261 fp_args[double_arg_index + 1] = 1;
2262 /* Skip the corresponding general argument register. */
2263 int_argreg ++;
2264 }
2265 else
2266 ;
2267 /* Store it as the integers, 8 bytes at the time, if
2268 necessary spilling on the stack. */
2269 }
2270 }
2271 }
2272 return sp;
2273}
2274
c906108c
SS		 2275/* Function: push_return_address (pc)
2276 Set up the return address for the inferior function call.
2277 Needed for targets where we don't actually execute a JSR/BSR instruction */
2278
cc17453a 2279static CORE_ADDR
fba45db2 2280sh_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
c906108c 2281{
283150cd
EZ		 2282 write_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM,
2283 CALL_DUMMY_ADDRESS ());
c906108c
SS		 2284 return sp;
2285}
2286
2287/* Function: fix_call_dummy
2288 Poke the callee function's address into the destination part of
2289 the CALL_DUMMY. The address is actually stored in a data word
2290 following the actualy CALL_DUMMY instructions, which will load
2291 it into a register using PC-relative addressing. This function
2292 expects the CALL_DUMMY to look like this:
2293
c5aa993b
JM		 2294 mov.w @(2,PC), R8
2295 jsr @R8
2296 nop
2297 trap
2298 <destination>
2299 */
c906108c
SS		 2300
2301#if 0
2302void
fba45db2 2303sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
ea7c478f 2304 struct value **args, struct type *type, int gcc_p)
c906108c
SS		 2305{
2306 *(unsigned long *) (dummy + 8) = fun;
2307}
2308#endif
2309
cc17453a
EZ		 2310static int
2311sh_coerce_float_to_double (struct type *formal, struct type *actual)
2312{
2313 return 1;
2314}
c906108c 2315
cc17453a
EZ		 2316/* Find a function's return value in the appropriate registers (in
2317 regbuf), and copy it into valbuf. Extract from an array REGBUF
2318 containing the (raw) register state a function return value of type
2319 TYPE, and copy that, in virtual format, into VALBUF. */
2320static void
fba45db2 2321sh_extract_return_value (struct type *type, char *regbuf, char *valbuf)
c906108c 2322{
cc17453a 2323 int len = TYPE_LENGTH (type);
3116c80a
EZ		 2324 int return_register = R0_REGNUM;
2325 int offset;
2326
cc17453a 2327 if (len <= 4)
3116c80a 2328 {
d7449b42 2329 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 2330 offset = REGISTER_BYTE (return_register) + 4 - len;
2331 else
2332 offset = REGISTER_BYTE (return_register);
2333 memcpy (valbuf, regbuf + offset, len);
2334 }
cc17453a 2335 else if (len <= 8)
3116c80a 2336 {
d7449b42 2337 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 2338 offset = REGISTER_BYTE (return_register) + 8 - len;
2339 else
2340 offset = REGISTER_BYTE (return_register);
2341 memcpy (valbuf, regbuf + offset, len);
2342 }
2343 else
2344 error ("bad size for return value");
2345}
2346
2347static void
2348sh3e_sh4_extract_return_value (struct type *type, char *regbuf, char *valbuf)
2349{
2350 int return_register;
2351 int offset;
2352 int len = TYPE_LENGTH (type);
2353
2354 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2355 return_register = FP0_REGNUM;
2356 else
2357 return_register = R0_REGNUM;
2358
2359 if (len == 8 && TYPE_CODE (type) == TYPE_CODE_FLT)
2360 {
2361 DOUBLEST val;
778eb05e 2362 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
3116c80a
EZ		 2363 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2364 (char *) regbuf + REGISTER_BYTE (return_register),
2365 &val);
2366 else
2367 floatformat_to_doublest (&floatformat_ieee_double_big,
2368 (char *) regbuf + REGISTER_BYTE (return_register),
2369 &val);
2370 store_floating (valbuf, len, val);
2371 }
2372 else if (len <= 4)
2373 {
d7449b42 2374 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 2375 offset = REGISTER_BYTE (return_register) + 4 - len;
2376 else
2377 offset = REGISTER_BYTE (return_register);
2378 memcpy (valbuf, regbuf + offset, len);
2379 }
2380 else if (len <= 8)
2381 {
d7449b42 2382 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 2383 offset = REGISTER_BYTE (return_register) + 8 - len;
2384 else
2385 offset = REGISTER_BYTE (return_register);
2386 memcpy (valbuf, regbuf + offset, len);
2387 }
cc17453a
EZ		 2388 else
2389 error ("bad size for return value");
2390}
c906108c 2391
283150cd
EZ		 2392static void
2393sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf)
2394{
2395 int offset;
2396 int return_register;
2397 int len = TYPE_LENGTH (type);
2398 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2399
2400 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2401 {
2402 if (len == 4)
2403 {
2404 /* Return value stored in FP0_REGNUM */
2405 return_register = FP0_REGNUM;
2406 offset = REGISTER_BYTE (return_register);
2407 memcpy (valbuf, (char *) regbuf + offset, len);
2408 }
2409 else if (len == 8)
2410 {
2411 /* return value stored in DR0_REGNUM */
2412 DOUBLEST val;
2413
2414 return_register = tdep->DR0_REGNUM;
2415 offset = REGISTER_BYTE (return_register);
2416
2417 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2418 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2419 (char *) regbuf + offset, &val);
2420 else
2421 floatformat_to_doublest (&floatformat_ieee_double_big,
2422 (char *) regbuf + offset, &val);
2423 store_floating (valbuf, len, val);
2424 }
2425 }
2426 else
2427 {
2428 if (len <= 8)
2429 {
2430 /* Result is in register 2. If smaller than 8 bytes, it is padded
2431 at the most significant end. */
2432 return_register = tdep->RETURN_REGNUM;
2433 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2434 offset = REGISTER_BYTE (return_register) +
2435 REGISTER_RAW_SIZE (return_register) - len;
2436 else
2437 offset = REGISTER_BYTE (return_register);
2438 memcpy (valbuf, (char *) regbuf + offset, len);
2439 }
2440 else
2441 error ("bad size for return value");
2442 }
2443}
2444
cc17453a
EZ		 2445/* Write into appropriate registers a function return value
2446 of type TYPE, given in virtual format.
2447 If the architecture is sh4 or sh3e, store a function's return value
2448 in the R0 general register or in the FP0 floating point register,
2449 depending on the type of the return value. In all the other cases
3bbfbb92 2450 the result is stored in r0, left-justified. */
cc17453a
EZ		 2451static void
2452sh_default_store_return_value (struct type *type, char *valbuf)
2453{
d19b71be
MS		 2454 char buf[32]; /* more than enough... */
2455
2456 if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (R0_REGNUM))
2457 {
2458 /* Add leading zeros to the value. */
2459 memset (buf, 0, REGISTER_RAW_SIZE (R0_REGNUM));
2460 memcpy (buf + REGISTER_RAW_SIZE (R0_REGNUM) - TYPE_LENGTH (type),
2461 valbuf, TYPE_LENGTH (type));
2462 write_register_bytes (REGISTER_BYTE (R0_REGNUM), buf,
2463 REGISTER_RAW_SIZE (R0_REGNUM));
2464 }
2465 else
2466 write_register_bytes (REGISTER_BYTE (R0_REGNUM), valbuf,
2467 TYPE_LENGTH (type));
cc17453a 2468}
c906108c 2469
cc17453a
EZ		 2470static void
2471sh3e_sh4_store_return_value (struct type *type, char *valbuf)
2472{
2473 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2474 write_register_bytes (REGISTER_BYTE (FP0_REGNUM),
2475 valbuf, TYPE_LENGTH (type));
2476 else
d19b71be 2477 sh_default_store_return_value (type, valbuf);
c906108c
SS		 2478}
2479
283150cd
EZ		 2480static void
2481sh64_store_return_value (struct type *type, char *valbuf)
2482{
2483 char buf[64]; /* more than enough... */
2484 int len = TYPE_LENGTH (type);
2485
2486 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2487 {
2488 if (len == 4)
2489 {
2490 /* Return value stored in FP0_REGNUM */
2491 write_register_gen (FP0_REGNUM, valbuf);
2492 }
2493 if (len == 8)
2494 {
2495 /* return value stored in DR0_REGNUM */
2496 /* FIXME: Implement */
2497 }
2498 }
2499 else
2500 {
2501 int return_register = gdbarch_tdep (current_gdbarch)->RETURN_REGNUM;
2502 int offset = 0;
2503
2504 if (len <= REGISTER_RAW_SIZE (return_register))
2505 {
2506 /* Pad with zeros. */
2507 memset (buf, 0, REGISTER_RAW_SIZE (return_register));
2508 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2509 offset = 0; /*REGISTER_RAW_SIZE (return_register) - len;*/
2510 else
2511 offset = REGISTER_RAW_SIZE (return_register) - len;
2512
2513 memcpy (buf + offset, valbuf, len);
2514 write_register_gen (return_register, buf);
2515 }
2516 else
2517 write_register_gen (return_register, valbuf);
2518 }
2519}
2520
c906108c
SS		 2521/* Print the registers in a form similar to the E7000 */
2522
2523static void
fba45db2 2524sh_generic_show_regs (void)
c906108c 2525{
f81353e4
EZ		 2526 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2527
cc17453a
EZ		 2528 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2529 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 2530 (long) read_register (tdep->SR_REGNUM),
2531 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 2532 (long) read_register (MACH_REGNUM),
2533 (long) read_register (MACL_REGNUM));
2534
2535 printf_filtered ("GBR=%08lx VBR=%08lx",
2536 (long) read_register (GBR_REGNUM),
2537 (long) read_register (VBR_REGNUM));
2538
2539 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2540 (long) read_register (0),
2541 (long) read_register (1),
2542 (long) read_register (2),
2543 (long) read_register (3),
2544 (long) read_register (4),
2545 (long) read_register (5),
2546 (long) read_register (6),
2547 (long) read_register (7));
2548 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2549 (long) read_register (8),
2550 (long) read_register (9),
2551 (long) read_register (10),
2552 (long) read_register (11),
2553 (long) read_register (12),
2554 (long) read_register (13),
2555 (long) read_register (14),
2556 (long) read_register (15));
2557}
c906108c 2558
cc17453a 2559static void
fba45db2 2560sh3_show_regs (void)
cc17453a 2561{
f81353e4
EZ		 2562 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2563
d4f3574e
SS		 2564 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2565 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 2566 (long) read_register (tdep->SR_REGNUM),
2567 (long) read_register (tdep->PR_REGNUM),
d4f3574e
SS		 2568 (long) read_register (MACH_REGNUM),
2569 (long) read_register (MACL_REGNUM));
2570
2571 printf_filtered ("GBR=%08lx VBR=%08lx",
2572 (long) read_register (GBR_REGNUM),
2573 (long) read_register (VBR_REGNUM));
cc17453a 2574 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 2575 (long) read_register (tdep->SSR_REGNUM),
2576 (long) read_register (tdep->SPC_REGNUM));
c906108c 2577
d4f3574e
SS		 2578 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2579 (long) read_register (0),
2580 (long) read_register (1),
2581 (long) read_register (2),
2582 (long) read_register (3),
2583 (long) read_register (4),
2584 (long) read_register (5),
2585 (long) read_register (6),
2586 (long) read_register (7));
2587 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2588 (long) read_register (8),
2589 (long) read_register (9),
2590 (long) read_register (10),
2591 (long) read_register (11),
2592 (long) read_register (12),
2593 (long) read_register (13),
2594 (long) read_register (14),
2595 (long) read_register (15));
c906108c
SS		 2596}
2597
53116e27 2598
cc17453a 2599static void
fba45db2 2600sh3e_show_regs (void)
cc17453a 2601{
f81353e4
EZ		 2602 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2603
cc17453a
EZ		 2604 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2605 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 2606 (long) read_register (tdep->SR_REGNUM),
2607 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 2608 (long) read_register (MACH_REGNUM),
2609 (long) read_register (MACL_REGNUM));
2610
2611 printf_filtered ("GBR=%08lx VBR=%08lx",
2612 (long) read_register (GBR_REGNUM),
2613 (long) read_register (VBR_REGNUM));
2614 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 2615 (long) read_register (tdep->SSR_REGNUM),
2616 (long) read_register (tdep->SPC_REGNUM));
cc17453a 2617 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
f81353e4
EZ		 2618 (long) read_register (tdep->FPUL_REGNUM),
2619 (long) read_register (tdep->FPSCR_REGNUM));
c906108c 2620
cc17453a
EZ		 2621 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2622 (long) read_register (0),
2623 (long) read_register (1),
2624 (long) read_register (2),
2625 (long) read_register (3),
2626 (long) read_register (4),
2627 (long) read_register (5),
2628 (long) read_register (6),
2629 (long) read_register (7));
2630 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2631 (long) read_register (8),
2632 (long) read_register (9),
2633 (long) read_register (10),
2634 (long) read_register (11),
2635 (long) read_register (12),
2636 (long) read_register (13),
2637 (long) read_register (14),
2638 (long) read_register (15));
2639
2640 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2641 (long) read_register (FP0_REGNUM + 0),
2642 (long) read_register (FP0_REGNUM + 1),
2643 (long) read_register (FP0_REGNUM + 2),
2644 (long) read_register (FP0_REGNUM + 3),
2645 (long) read_register (FP0_REGNUM + 4),
2646 (long) read_register (FP0_REGNUM + 5),
2647 (long) read_register (FP0_REGNUM + 6),
2648 (long) read_register (FP0_REGNUM + 7));
2649 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2650 (long) read_register (FP0_REGNUM + 8),
2651 (long) read_register (FP0_REGNUM + 9),
2652 (long) read_register (FP0_REGNUM + 10),
2653 (long) read_register (FP0_REGNUM + 11),
2654 (long) read_register (FP0_REGNUM + 12),
2655 (long) read_register (FP0_REGNUM + 13),
2656 (long) read_register (FP0_REGNUM + 14),
2657 (long) read_register (FP0_REGNUM + 15));
2658}
2659
2660static void
fba45db2 2661sh3_dsp_show_regs (void)
c906108c 2662{
f81353e4
EZ		 2663 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2664
cc17453a
EZ		 2665 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2666 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 2667 (long) read_register (tdep->SR_REGNUM),
2668 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 2669 (long) read_register (MACH_REGNUM),
2670 (long) read_register (MACL_REGNUM));
c906108c 2671
cc17453a
EZ		 2672 printf_filtered ("GBR=%08lx VBR=%08lx",
2673 (long) read_register (GBR_REGNUM),
2674 (long) read_register (VBR_REGNUM));
2675
2676 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 2677 (long) read_register (tdep->SSR_REGNUM),
2678 (long) read_register (tdep->SPC_REGNUM));
cc17453a
EZ		 2679
2680 printf_filtered (" DSR=%08lx",
f81353e4 2681 (long) read_register (tdep->DSR_REGNUM));
cc17453a
EZ		 2682
2683 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2684 (long) read_register (0),
2685 (long) read_register (1),
2686 (long) read_register (2),
2687 (long) read_register (3),
2688 (long) read_register (4),
2689 (long) read_register (5),
2690 (long) read_register (6),
2691 (long) read_register (7));
2692 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2693 (long) read_register (8),
2694 (long) read_register (9),
2695 (long) read_register (10),
2696 (long) read_register (11),
2697 (long) read_register (12),
2698 (long) read_register (13),
2699 (long) read_register (14),
2700 (long) read_register (15));
2701
2702 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
f81353e4
EZ		 2703 (long) read_register (tdep->A0G_REGNUM) & 0xff,
2704 (long) read_register (tdep->A0_REGNUM),
2705 (long) read_register (tdep->M0_REGNUM),
2706 (long) read_register (tdep->X0_REGNUM),
2707 (long) read_register (tdep->Y0_REGNUM),
2708 (long) read_register (tdep->RS_REGNUM),
2709 (long) read_register (tdep->MOD_REGNUM));
cc17453a 2710 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
f81353e4
EZ		 2711 (long) read_register (tdep->A1G_REGNUM) & 0xff,
2712 (long) read_register (tdep->A1_REGNUM),
2713 (long) read_register (tdep->M1_REGNUM),
2714 (long) read_register (tdep->X1_REGNUM),
2715 (long) read_register (tdep->Y1_REGNUM),
2716 (long) read_register (tdep->RE_REGNUM));
c906108c
SS		 2717}
2718
cc17453a 2719static void
fba45db2 2720sh4_show_regs (void)
cc17453a 2721{
f81353e4
EZ		 2722 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2723
2724 int pr = read_register (tdep->FPSCR_REGNUM) & 0x80000;
cc17453a
EZ		 2725 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2726 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 2727 (long) read_register (tdep->SR_REGNUM),
2728 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 2729 (long) read_register (MACH_REGNUM),
2730 (long) read_register (MACL_REGNUM));
2731
2732 printf_filtered ("GBR=%08lx VBR=%08lx",
2733 (long) read_register (GBR_REGNUM),
2734 (long) read_register (VBR_REGNUM));
2735 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 2736 (long) read_register (tdep->SSR_REGNUM),
2737 (long) read_register (tdep->SPC_REGNUM));
cc17453a 2738 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
f81353e4
EZ		 2739 (long) read_register (tdep->FPUL_REGNUM),
2740 (long) read_register (tdep->FPSCR_REGNUM));
cc17453a
EZ		 2741
2742 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2743 (long) read_register (0),
2744 (long) read_register (1),
2745 (long) read_register (2),
2746 (long) read_register (3),
2747 (long) read_register (4),
2748 (long) read_register (5),
2749 (long) read_register (6),
2750 (long) read_register (7));
2751 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2752 (long) read_register (8),
2753 (long) read_register (9),
2754 (long) read_register (10),
2755 (long) read_register (11),
2756 (long) read_register (12),
2757 (long) read_register (13),
2758 (long) read_register (14),
2759 (long) read_register (15));
2760
2761 printf_filtered ((pr
2762 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2763 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2764 (long) read_register (FP0_REGNUM + 0),
2765 (long) read_register (FP0_REGNUM + 1),
2766 (long) read_register (FP0_REGNUM + 2),
2767 (long) read_register (FP0_REGNUM + 3),
2768 (long) read_register (FP0_REGNUM + 4),
2769 (long) read_register (FP0_REGNUM + 5),
2770 (long) read_register (FP0_REGNUM + 6),
2771 (long) read_register (FP0_REGNUM + 7));
2772 printf_filtered ((pr
2773 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2774 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2775 (long) read_register (FP0_REGNUM + 8),
2776 (long) read_register (FP0_REGNUM + 9),
2777 (long) read_register (FP0_REGNUM + 10),
2778 (long) read_register (FP0_REGNUM + 11),
2779 (long) read_register (FP0_REGNUM + 12),
2780 (long) read_register (FP0_REGNUM + 13),
2781 (long) read_register (FP0_REGNUM + 14),
2782 (long) read_register (FP0_REGNUM + 15));
2783}
2784
2785static void
fba45db2 2786sh_dsp_show_regs (void)
cc17453a 2787{
f81353e4
EZ		 2788 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2789
cc17453a
EZ		 2790 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2791 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 2792 (long) read_register (tdep->SR_REGNUM),
2793 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 2794 (long) read_register (MACH_REGNUM),
2795 (long) read_register (MACL_REGNUM));
2796
2797 printf_filtered ("GBR=%08lx VBR=%08lx",
2798 (long) read_register (GBR_REGNUM),
2799 (long) read_register (VBR_REGNUM));
2800
2801 printf_filtered (" DSR=%08lx",
f81353e4 2802 (long) read_register (tdep->DSR_REGNUM));
cc17453a
EZ		 2803
2804 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2805 (long) read_register (0),
2806 (long) read_register (1),
2807 (long) read_register (2),
2808 (long) read_register (3),
2809 (long) read_register (4),
2810 (long) read_register (5),
2811 (long) read_register (6),
2812 (long) read_register (7));
2813 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2814 (long) read_register (8),
2815 (long) read_register (9),
2816 (long) read_register (10),
2817 (long) read_register (11),
2818 (long) read_register (12),
2819 (long) read_register (13),
2820 (long) read_register (14),
2821 (long) read_register (15));
2822
2823 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
f81353e4
EZ		 2824 (long) read_register (tdep->A0G_REGNUM) & 0xff,
2825 (long) read_register (tdep->A0_REGNUM),
2826 (long) read_register (tdep->M0_REGNUM),
2827 (long) read_register (tdep->X0_REGNUM),
2828 (long) read_register (tdep->Y0_REGNUM),
2829 (long) read_register (tdep->RS_REGNUM),
2830 (long) read_register (tdep->MOD_REGNUM));
cc17453a 2831 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
f81353e4
EZ		 2832 (long) read_register (tdep->A1G_REGNUM) & 0xff,
2833 (long) read_register (tdep->A1_REGNUM),
2834 (long) read_register (tdep->M1_REGNUM),
2835 (long) read_register (tdep->X1_REGNUM),
2836 (long) read_register (tdep->Y1_REGNUM),
2837 (long) read_register (tdep->RE_REGNUM));
cc17453a
EZ		 2838}
2839
283150cd
EZ		 2840static void
2841sh64_show_media_regs (void)
2842{
2843 int i;
2844 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2845
2846 printf_filtered ("PC=%s SR=%016llx \n",
2847 paddr (read_register (PC_REGNUM)),
2848 (long long) read_register (tdep->SR_REGNUM));
2849
2850 printf_filtered ("SSR=%016llx SPC=%016llx \n",
2851 (long long) read_register (tdep->SSR_REGNUM),
2852 (long long) read_register (tdep->SPC_REGNUM));
2853 printf_filtered ("FPSCR=%016lx\n ",
2854 (long) read_register (tdep->FPSCR_REGNUM));
2855
2856 for (i = 0; i < 64; i = i + 4)
2857 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
2858 i, i + 3,
2859 (long long) read_register (i + 0),
2860 (long long) read_register (i + 1),
2861 (long long) read_register (i + 2),
2862 (long long) read_register (i + 3));
2863
2864 printf_filtered ("\n");
2865
2866 for (i = 0; i < 64; i = i + 8)
2867 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2868 i, i + 7,
2869 (long) read_register (FP0_REGNUM + i + 0),
2870 (long) read_register (FP0_REGNUM + i + 1),
2871 (long) read_register (FP0_REGNUM + i + 2),
2872 (long) read_register (FP0_REGNUM + i + 3),
2873 (long) read_register (FP0_REGNUM + i + 4),
2874 (long) read_register (FP0_REGNUM + i + 5),
2875 (long) read_register (FP0_REGNUM + i + 6),
2876 (long) read_register (FP0_REGNUM + i + 7));
2877}
2878
2879static void
2880sh64_show_compact_regs (void)
2881{
2882 int i;
2883 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2884
2885 printf_filtered ("PC=%s \n",
2886 paddr (read_register (tdep->PC_C_REGNUM)));
2887
2888 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
2889 (long) read_register (tdep->GBR_C_REGNUM),
2890 (long) read_register (tdep->MACH_C_REGNUM),
2891 (long) read_register (tdep->MACL_C_REGNUM),
2892 (long) read_register (tdep->PR_C_REGNUM),
2893 (long) read_register (tdep->T_C_REGNUM));
2894 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
2895 (long) read_register (tdep->FPSCR_REGNUM),
2896 (long) read_register (tdep->FPUL_REGNUM));
2897
2898 for (i = 0; i < 16; i = i + 4)
2899 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
2900 i, i + 3,
2901 (long) read_register (i + 0),
2902 (long) read_register (i + 1),
2903 (long) read_register (i + 2),
2904 (long) read_register (i + 3));
2905
2906 printf_filtered ("\n");
2907
2908 for (i = 0; i < 16; i = i + 8)
2909 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2910 i, i + 7,
2911 (long) read_register (FP0_REGNUM + i + 0),
2912 (long) read_register (FP0_REGNUM + i + 1),
2913 (long) read_register (FP0_REGNUM + i + 2),
2914 (long) read_register (FP0_REGNUM + i + 3),
2915 (long) read_register (FP0_REGNUM + i + 4),
2916 (long) read_register (FP0_REGNUM + i + 5),
2917 (long) read_register (FP0_REGNUM + i + 6),
2918 (long) read_register (FP0_REGNUM + i + 7));
2919}
2920
2921/*FIXME!!! This only shows the registers for shmedia, excluding the
2922 pseudo registers. */
2923static void
2924sh64_show_regs (void)
2925{
2926 if (pc_is_isa32 (selected_frame->pc))
2927 sh64_show_media_regs ();
2928 else
2929 sh64_show_compact_regs ();
2930}
2931
53116e27
EZ		 2932void sh_show_regs_command (char *args, int from_tty)
2933{
2934 if (sh_show_regs)
2935 (*sh_show_regs)();
2936}
2937
cc17453a
EZ		 2938/* Index within `registers' of the first byte of the space for
2939 register N. */
2940static int
fba45db2 2941sh_default_register_byte (int reg_nr)
8db62801 2942{
cc17453a
EZ		 2943 return (reg_nr * 4);
2944}
2945
53116e27 2946static int
fba45db2 2947sh_sh4_register_byte (int reg_nr)
53116e27 2948{
f81353e4
EZ		 2949 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2950
2951 if (reg_nr >= tdep->DR0_REGNUM
2952 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27 2953 return (dr_reg_base_num (reg_nr) * 4);
f81353e4
EZ		 2954 else if (reg_nr >= tdep->FV0_REGNUM
2955 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 2956 return (fv_reg_base_num (reg_nr) * 4);
2957 else
2958 return (reg_nr * 4);
2959}
2960
283150cd
EZ		 2961/* *INDENT-OFF* */
2962/*
2963 SH MEDIA MODE (ISA 32)
2964 general registers (64-bit) 0-63
29650 r0, r1, r2, r3, r4, r5, r6, r7,
296664 r8, r9, r10, r11, r12, r13, r14, r15,
2967128 r16, r17, r18, r19, r20, r21, r22, r23,
2968192 r24, r25, r26, r27, r28, r29, r30, r31,
2969256 r32, r33, r34, r35, r36, r37, r38, r39,
2970320 r40, r41, r42, r43, r44, r45, r46, r47,
2971384 r48, r49, r50, r51, r52, r53, r54, r55,
2972448 r56, r57, r58, r59, r60, r61, r62, r63,
2973
2974 pc (64-bit) 64
2975512 pc,
2976
2977 status reg., saved status reg., saved pc reg. (64-bit) 65-67
2978520 sr, ssr, spc,
2979
2980 target registers (64-bit) 68-75
2981544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
2982
2983 floating point state control register (32-bit) 76
2984608 fpscr,
2985
2986 single precision floating point registers (32-bit) 77-140
2987612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
2988644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
2989676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
2990708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
2991740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
2992772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
2993804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
2994836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
2995
2996TOTAL SPACE FOR REGISTERS: 868 bytes
2997
2998From here on they are all pseudo registers: no memory allocated.
2999REGISTER_BYTE returns the register byte for the base register.
3000
3001 double precision registers (pseudo) 141-172
3002 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
3003 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
3004 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
3005 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
3006
3007 floating point pairs (pseudo) 173-204
3008 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
3009 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
3010 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
3011 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
3012
3013 floating point vectors (4 floating point regs) (pseudo) 205-220
3014 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
3015 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
3016
3017 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
3018 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
3019 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
3020 pc_c,
3021 gbr_c, mach_c, macl_c, pr_c, t_c,
3022 fpscr_c, fpul_c,
3023 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
3024 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
3025 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
3026 fv0_c, fv4_c, fv8_c, fv12_c
3027*/
3028/* *INDENT-ON* */
3029static int
3030sh_sh64_register_byte (int reg_nr)
3031{
3032 int base_regnum = -1;
3033 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3034
3035 /* If it is a pseudo register, get the number of the first floating
3036 point register that is part of it. */
3037 if (reg_nr >= tdep->DR0_REGNUM
3038 && reg_nr <= tdep->DR_LAST_REGNUM)
3039 base_regnum = dr_reg_base_num (reg_nr);
3040
3041 else if (reg_nr >= tdep->FPP0_REGNUM
3042 && reg_nr <= tdep->FPP_LAST_REGNUM)
3043 base_regnum = fpp_reg_base_num (reg_nr);
3044
3045 else if (reg_nr >= tdep->FV0_REGNUM
3046 && reg_nr <= tdep->FV_LAST_REGNUM)
3047 base_regnum = fv_reg_base_num (reg_nr);
3048
3049 /* sh compact pseudo register. FPSCR is a pathological case, need to
3050 treat it as special. */
3051 else if ((reg_nr >= tdep->R0_C_REGNUM
3052 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3053 && reg_nr != tdep->FPSCR_C_REGNUM)
3054 base_regnum = sh64_compact_reg_base_num (reg_nr);
3055
3056 /* Now return the offset in bytes within the register cache. */
3057 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
3058 if (reg_nr >= tdep->DR0_REGNUM
3059 && reg_nr <= tdep->FV_LAST_REGNUM)
3060 return (base_regnum - FP0_REGNUM + 1) * 4
3061 + (tdep->TR7_REGNUM + 1) * 8;
3062
3063 /* sh compact pseudo register: general register */
3064 if ((reg_nr >= tdep->R0_C_REGNUM
3065 && reg_nr <= tdep->R_LAST_C_REGNUM))
3066 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3067 ? base_regnum * 8 + 4
3068 : base_regnum * 8);
3069
3070 /* sh compact pseudo register: */
3071 if (reg_nr == tdep->PC_C_REGNUM
3072 || reg_nr == tdep->GBR_C_REGNUM
3073 || reg_nr == tdep->MACL_C_REGNUM
3074 || reg_nr == tdep->PR_C_REGNUM)
3075 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3076 ? base_regnum * 8 + 4
3077 : base_regnum * 8);
3078
3079 if (reg_nr == tdep->MACH_C_REGNUM)
3080 return base_regnum * 8;
3081
3082 if (reg_nr == tdep->T_C_REGNUM)
3083 return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */
3084
3085 /* sh compact pseudo register: floating point register */
3086 else if (reg_nr >=tdep->FP0_C_REGNUM
3087 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3088 return (base_regnum - FP0_REGNUM) * 4
3089 + (tdep->TR7_REGNUM + 1) * 8 + 4;
3090
3091 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3092 /* This is complicated, for now return the beginning of the
3093 architectural FPSCR register. */
3094 return (tdep->TR7_REGNUM + 1) * 8;
3095
3096 else if (reg_nr == tdep->FPUL_C_REGNUM)
3097 return ((base_regnum - FP0_REGNUM) * 4 +
3098 (tdep->TR7_REGNUM + 1) * 8 + 4);
3099
3100 /* It is not a pseudo register. */
3101 /* It is a 64 bit register. */
3102 else if (reg_nr <= tdep->TR7_REGNUM)
3103 return reg_nr * 8;
3104
3105 /* It is a 32 bit register. */
3106 else
3107 if (reg_nr == tdep->FPSCR_REGNUM)
3108 return (tdep->FPSCR_REGNUM * 8);
3109
3110 /* It is floating point 32-bit register */
3111 else
3112 return ((tdep->TR7_REGNUM + 1) * 8
3113 + (reg_nr - FP0_REGNUM + 1) * 4);
3114}
3115
cc17453a
EZ		 3116/* Number of bytes of storage in the actual machine representation for
3117 register REG_NR. */
3118static int
fba45db2 3119sh_default_register_raw_size (int reg_nr)
cc17453a
EZ		 3120{
3121 return 4;
3122}
3123
53116e27 3124static int
fba45db2 3125sh_sh4_register_raw_size (int reg_nr)
53116e27 3126{
f81353e4
EZ		 3127 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3128
3129 if (reg_nr >= tdep->DR0_REGNUM
3130 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27 3131 return 8;
f81353e4
EZ		 3132 else if (reg_nr >= tdep->FV0_REGNUM
3133 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 3134 return 16;
3135 else
3136 return 4;
3137}
3138
283150cd
EZ		 3139static int
3140sh_sh64_register_raw_size (int reg_nr)
3141{
3142 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3143
3144 if ((reg_nr >= tdep->DR0_REGNUM
3145 && reg_nr <= tdep->DR_LAST_REGNUM)
3146 || (reg_nr >= tdep->FPP0_REGNUM
3147 && reg_nr <= tdep->FPP_LAST_REGNUM)
3148 || (reg_nr >= tdep->DR0_C_REGNUM
3149 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3150 || (reg_nr <= tdep->TR7_REGNUM))
3151 return 8;
3152
3153 else if ((reg_nr >= tdep->FV0_REGNUM
3154 && reg_nr <= tdep->FV_LAST_REGNUM)
3155 || (reg_nr >= tdep->FV0_C_REGNUM
3156 && reg_nr <= tdep->FV_LAST_C_REGNUM))
3157 return 16;
3158
3159 else /* this covers also the 32-bit SH compact registers. */
3160 return 4;
3161}
3162
cc17453a
EZ		 3163/* Number of bytes of storage in the program's representation
3164 for register N. */
3165static int
fba45db2 3166sh_register_virtual_size (int reg_nr)
cc17453a
EZ		 3167{
3168 return 4;
3169}
3170
283150cd
EZ		 3171/* ??????? FIXME */
3172static int
3173sh_sh64_register_virtual_size (int reg_nr)
3174{
3175 if (reg_nr >= FP0_REGNUM
3176 && reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM)
3177 return 4;
3178 else
3179 return 8;
3180}
3181
cc17453a
EZ		 3182/* Return the GDB type object for the "standard" data type
3183 of data in register N. */
cc17453a 3184static struct type *
fba45db2 3185sh_sh3e_register_virtual_type (int reg_nr)
cc17453a 3186{
f81353e4
EZ		 3187 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3188
cc17453a 3189 if ((reg_nr >= FP0_REGNUM
f81353e4
EZ		 3190 && (reg_nr <= tdep->FP_LAST_REGNUM))
3191 || (reg_nr == tdep->FPUL_REGNUM))
cc17453a 3192 return builtin_type_float;
8db62801 3193 else
cc17453a
EZ		 3194 return builtin_type_int;
3195}
3196
7f4dbe94
EZ		 3197static struct type *
3198sh_sh4_build_float_register_type (int high)
3199{
3200 struct type *temp;
3201
3202 temp = create_range_type (NULL, builtin_type_int, 0, high);
3203 return create_array_type (NULL, builtin_type_float, temp);
3204}
3205
53116e27 3206static struct type *
fba45db2 3207sh_sh4_register_virtual_type (int reg_nr)
53116e27 3208{
f81353e4
EZ		 3209 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3210
53116e27 3211 if ((reg_nr >= FP0_REGNUM
f81353e4
EZ		 3212 && (reg_nr <= tdep->FP_LAST_REGNUM))
3213 || (reg_nr == tdep->FPUL_REGNUM))
53116e27 3214 return builtin_type_float;
f81353e4
EZ		 3215 else if (reg_nr >= tdep->DR0_REGNUM
3216 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27 3217 return builtin_type_double;
f81353e4
EZ		 3218 else if (reg_nr >= tdep->FV0_REGNUM
3219 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 3220 return sh_sh4_build_float_register_type (3);
3221 else
3222 return builtin_type_int;
3223}
3224
283150cd
EZ		 3225static struct type *
3226sh_sh64_register_virtual_type (int reg_nr)
3227{
3228 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3229
3230 if ((reg_nr >= FP0_REGNUM
3231 && reg_nr <= tdep->FP_LAST_REGNUM)
3232 || (reg_nr >= tdep->FP0_C_REGNUM
3233 && reg_nr <= tdep->FP_LAST_C_REGNUM))
3234 return builtin_type_float;
3235 else if ((reg_nr >= tdep->DR0_REGNUM
3236 && reg_nr <= tdep->DR_LAST_REGNUM)
3237 || (reg_nr >= tdep->DR0_C_REGNUM
3238 && reg_nr <= tdep->DR_LAST_C_REGNUM))
3239 return builtin_type_double;
3240 else if (reg_nr >= tdep->FPP0_REGNUM
3241 && reg_nr <= tdep->FPP_LAST_REGNUM)
3242 return sh_sh4_build_float_register_type (1);
3243 else if ((reg_nr >= tdep->FV0_REGNUM
3244 && reg_nr <= tdep->FV_LAST_REGNUM)
3245 ||(reg_nr >= tdep->FV0_C_REGNUM
3246 && reg_nr <= tdep->FV_LAST_C_REGNUM))
3247 return sh_sh4_build_float_register_type (3);
3248 else if (reg_nr == tdep->FPSCR_REGNUM)
3249 return builtin_type_int;
3250 else if (reg_nr >= tdep->R0_C_REGNUM
3251 && reg_nr < tdep->FP0_C_REGNUM)
3252 return builtin_type_int;
3253 else
3254 return builtin_type_long_long;
3255}
3256
cc17453a 3257static struct type *
fba45db2 3258sh_default_register_virtual_type (int reg_nr)
cc17453a
EZ		 3259{
3260 return builtin_type_int;
3261}
3262
fb409745
EZ		 3263/* On the sh4, the DRi pseudo registers are problematic if the target
3264 is little endian. When the user writes one of those registers, for
3265 instance with 'ser var $dr0=1', we want the double to be stored
3266 like this:
3267 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3268 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3269
3270 This corresponds to little endian byte order & big endian word
3271 order. However if we let gdb write the register w/o conversion, it
3272 will write fr0 and fr1 this way:
3273 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3274 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3275 because it will consider fr0 and fr1 as a single LE stretch of memory.
3276
3277 To achieve what we want we must force gdb to store things in
3278 floatformat_ieee_double_littlebyte_bigword (which is defined in
3279 include/floatformat.h and libiberty/floatformat.c.
3280
3281 In case the target is big endian, there is no problem, the
3282 raw bytes will look like:
3283 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
3284 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3285
3286 The other pseudo registers (the FVs) also don't pose a problem
3287 because they are stored as 4 individual FP elements. */
3288
7bd872fe 3289static void
fb409745
EZ		 3290sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
3291 char *from, char *to)
3292{
f81353e4
EZ		 3293 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3294
3295 if (regnum >= tdep->DR0_REGNUM
3296 && regnum <= tdep->DR_LAST_REGNUM)
fb409745
EZ		 3297 {
3298 DOUBLEST val;
3299 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
3bbfbb92 3300 store_floating (to, TYPE_LENGTH (type), val);
fb409745
EZ		 3301 }
3302 else
3bbfbb92 3303 error ("sh_register_convert_to_virtual called with non DR register number");
fb409745
EZ		 3304}
3305
283150cd
EZ		 3306void
3307sh_sh64_register_convert_to_virtual (int regnum, struct type *type,
3308 char *from, char *to)
3309{
3310 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3311
3312 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
3313 {
3314 /* It is a no-op. */
3315 memcpy (to, from, REGISTER_RAW_SIZE (regnum));
3316 return;
3317 }
3318
3319 if ((regnum >= tdep->DR0_REGNUM
3320 && regnum <= tdep->DR_LAST_REGNUM)
3321 || (regnum >= tdep->DR0_C_REGNUM
3322 && regnum <= tdep->DR_LAST_C_REGNUM))
3323 {
3324 DOUBLEST val;
3325 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
3326 store_floating(to, TYPE_LENGTH(type), val);
3327 }
3328 else
3329 error("sh_register_convert_to_virtual called with non DR register number");
3330}
3331
3332static void
3333sh_sh4_register_convert_to_raw (struct type *type, int regnum,
3334 char *from, char *to)
3335{
3336 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3337
3338 if (regnum >= tdep->DR0_REGNUM
3339 && regnum <= tdep->DR_LAST_REGNUM)
3340 {
3341 DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
3342 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
3343 }
3344 else
3345 error("sh_register_convert_to_raw called with non DR register number");
3346}
3347
3348void
3349sh_sh64_register_convert_to_raw (struct type *type, int regnum,
3350 char *from, char *to)
fb409745 3351{
f81353e4
EZ		 3352 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3353
283150cd
EZ		 3354 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
3355 {
3356 /* It is a no-op. */
3357 memcpy (to, from, REGISTER_RAW_SIZE (regnum));
3358 return;
3359 }
3360
3361 if ((regnum >= tdep->DR0_REGNUM
3362 && regnum <= tdep->DR_LAST_REGNUM)
3363 || (regnum >= tdep->DR0_C_REGNUM
3364 && regnum <= tdep->DR_LAST_C_REGNUM))
fb409745
EZ		 3365 {
3366 DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
3367 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
3368 }
3369 else
3370 error("sh_register_convert_to_raw called with non DR register number");
3371}
3372
53116e27 3373void
7bd872fe 3374sh_pseudo_register_read (int reg_nr, char *buffer)
53116e27
EZ		 3375{
3376 int base_regnum, portion;
7bd872fe 3377 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
f81353e4 3378 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
53116e27 3379
7bd872fe
EZ		 3380 if (reg_nr >= tdep->DR0_REGNUM
3381 && reg_nr <= tdep->DR_LAST_REGNUM)
3382 {
3383 base_regnum = dr_reg_base_num (reg_nr);
3384
3385 /* Build the value in the provided buffer. */
3386 /* Read the real regs for which this one is an alias. */
3387 for (portion = 0; portion < 2; portion++)
3388 regcache_read (base_regnum + portion,
3389 temp_buffer
3390 + REGISTER_RAW_SIZE (base_regnum) * portion);
3391 /* We must pay attention to the endiannes. */
3392 sh_sh4_register_convert_to_virtual (reg_nr,
3393 REGISTER_VIRTUAL_TYPE (reg_nr),
3394 temp_buffer, buffer);
3395 }
3396 else if (reg_nr >= tdep->FV0_REGNUM
3397 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27 3398 {
7bd872fe
EZ		 3399 base_regnum = fv_reg_base_num (reg_nr);
3400
3401 /* Read the real regs for which this one is an alias. */
3402 for (portion = 0; portion < 4; portion++)
3403 regcache_read (base_regnum + portion,
3404 buffer + REGISTER_RAW_SIZE (base_regnum) * portion);
53116e27
EZ		 3405 }
3406}
3407
7bd872fe
EZ		 3408static void
3409sh4_register_read (struct gdbarch *gdbarch, int reg_nr, char *buffer)
3410{
3411 if (reg_nr >= 0 && reg_nr < gdbarch_tdep (current_gdbarch)->DR0_REGNUM)
3412 /* It is a regular register. */
3413 regcache_read (reg_nr, buffer);
3414 else
3415 /* It is a pseudo register and we need to construct its value */
3416 sh_pseudo_register_read (reg_nr, buffer);
3417}
3418
283150cd
EZ		 3419static void
3420sh64_pseudo_register_read (int reg_nr, char *buffer)
3421{
3422 int base_regnum;
3423 int portion;
3424 int offset = 0;
3425 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
3426 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3427
3428 if (reg_nr >= tdep->DR0_REGNUM
3429 && reg_nr <= tdep->DR_LAST_REGNUM)
3430 {
3431 base_regnum = dr_reg_base_num (reg_nr);
3432
3433 /* Build the value in the provided buffer. */
3434 /* DR regs are double precision registers obtained by
3435 concatenating 2 single precision floating point registers. */
3436 for (portion = 0; portion < 2; portion++)
3437 regcache_read (base_regnum + portion,
3438 temp_buffer
3439 + REGISTER_RAW_SIZE (base_regnum) * portion);
3440
3441 /* We must pay attention to the endiannes. */
3442 sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr),
3443 temp_buffer, buffer);
3444
3445 }
3446
3447 else if (reg_nr >= tdep->FPP0_REGNUM
3448 && reg_nr <= tdep->FPP_LAST_REGNUM)
3449 {
3450 base_regnum = fpp_reg_base_num (reg_nr);
3451
3452 /* Build the value in the provided buffer. */
3453 /* FPP regs are pairs of single precision registers obtained by
3454 concatenating 2 single precision floating point registers. */
3455 for (portion = 0; portion < 2; portion++)
3456 regcache_read (base_regnum + portion,
3457 buffer + REGISTER_RAW_SIZE (base_regnum) * portion);
3458 }
3459
3460 else if (reg_nr >= tdep->FV0_REGNUM
3461 && reg_nr <= tdep->FV_LAST_REGNUM)
3462 {
3463 base_regnum = fv_reg_base_num (reg_nr);
3464
3465 /* Build the value in the provided buffer. */
3466 /* FV regs are vectors of single precision registers obtained by
3467 concatenating 4 single precision floating point registers. */
3468 for (portion = 0; portion < 4; portion++)
3469 regcache_read (base_regnum + portion,
3470 buffer + REGISTER_RAW_SIZE (base_regnum) * portion);
3471 }
3472
3473 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
3474 else if (reg_nr >= tdep->R0_C_REGNUM
3475 && reg_nr <= tdep->T_C_REGNUM)
3476 {
3477 base_regnum = sh64_compact_reg_base_num (reg_nr);
3478
3479 /* Build the value in the provided buffer. */
3480 regcache_read (base_regnum, temp_buffer);
3481 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3482 offset = 4;
3483 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
3484 }
3485
3486 else if (reg_nr >= tdep->FP0_C_REGNUM
3487 && reg_nr <= tdep->FP_LAST_C_REGNUM)
3488 {
3489 base_regnum = sh64_compact_reg_base_num (reg_nr);
3490
3491 /* Build the value in the provided buffer. */
3492 /* Floating point registers map 1-1 to the media fp regs,
3493 they have the same size and endienness. */
3494 regcache_read (base_regnum, buffer);
3495 }
3496
3497 else if (reg_nr >= tdep->DR0_C_REGNUM
3498 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3499 {
3500 base_regnum = sh64_compact_reg_base_num (reg_nr);
3501
3502 /* DR_C regs are double precision registers obtained by
3503 concatenating 2 single precision floating point registers. */
3504 for (portion = 0; portion < 2; portion++)
3505 regcache_read (base_regnum + portion,
3506 temp_buffer
3507 + REGISTER_RAW_SIZE (base_regnum) * portion);
3508
3509 /* We must pay attention to the endiannes. */
3510 sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr),
3511 temp_buffer, buffer);
3512 }
3513
3514 else if (reg_nr >= tdep->FV0_C_REGNUM
3515 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3516 {
3517 base_regnum = sh64_compact_reg_base_num (reg_nr);
3518
3519 /* Build the value in the provided buffer. */
3520 /* FV_C regs are vectors of single precision registers obtained by
3521 concatenating 4 single precision floating point registers. */
3522 for (portion = 0; portion < 4; portion++)
3523 regcache_read (base_regnum + portion,
3524 buffer + REGISTER_RAW_SIZE (base_regnum) * portion);
3525 }
3526
3527 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3528 {
3529 int fpscr_base_regnum;
3530 int sr_base_regnum;
3531 unsigned int fpscr_value;
3532 unsigned int sr_value;
3533 unsigned int fpscr_c_value;
3534 unsigned int fpscr_c_part1_value;
3535 unsigned int fpscr_c_part2_value;
3536
3537 fpscr_base_regnum = tdep->FPSCR_REGNUM;
3538 sr_base_regnum = tdep->SR_REGNUM;
3539
3540 /* Build the value in the provided buffer. */
3541 /* FPSCR_C is a very weird register that contains sparse bits
3542 from the FPSCR and the SR architectural registers.
3543 Specifically: */
3544 /* *INDENT-OFF* */
3545 /*
3546 FPSRC_C bit
3547 0 Bit 0 of FPSCR
3548 1 reserved
3549 2-17 Bit 2-18 of FPSCR
3550 18-20 Bits 12,13,14 of SR
3551 21-31 reserved
3552 */
3553 /* *INDENT-ON* */
3554 /* Get FPSCR into a local buffer */
3555 regcache_read (fpscr_base_regnum, temp_buffer);
3556 /* Get value as an int. */
3557 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
3558 /* Get SR into a local buffer */
3559 regcache_read (sr_base_regnum, temp_buffer);
3560 /* Get value as an int. */
3561 sr_value = extract_unsigned_integer (temp_buffer, 4);
3562 /* Build the new value. */
3563 fpscr_c_part1_value = fpscr_value & 0x3fffd;
3564 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
3565 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
3566 /* Store that in out buffer!!! */
3567 store_unsigned_integer (buffer, 4, fpscr_c_value);
3568 /* FIXME There is surely an endianness gotcha here. */
3569 }
3570
3571 else if (reg_nr == tdep->FPUL_C_REGNUM)
3572 {
3573 base_regnum = sh64_compact_reg_base_num (reg_nr);
3574
3575 /* FPUL_C register is floating point register 32,
3576 same size, same endianness. */
3577 regcache_read (base_regnum, buffer);
3578 }
3579}
3580
3581static void
3582sh64_register_read (struct gdbarch *gdbarch, int reg_nr, char *buffer)
3583{
3584
3585 if (reg_nr >= 0 && reg_nr < gdbarch_tdep (current_gdbarch)->DR0_REGNUM)
3586 /* It is a regular register. */
3587 regcache_read (reg_nr, buffer);
3588 else
3589 /* It is a pseudo register and we need to construct its value */
3590 sh64_pseudo_register_read (reg_nr, buffer);
3591}
3592
53116e27 3593void
7bd872fe 3594sh_pseudo_register_write (int reg_nr, char *buffer)
53116e27
EZ		 3595{
3596 int base_regnum, portion;
7bd872fe 3597 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
f81353e4 3598 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
53116e27 3599
f81353e4
EZ		 3600 if (reg_nr >= tdep->DR0_REGNUM
3601 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27
EZ		 3602 {
3603 base_regnum = dr_reg_base_num (reg_nr);
3604
7bd872fe
EZ		 3605 /* We must pay attention to the endiannes. */
3606 sh_sh4_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3607 buffer, temp_buffer);
3608
53116e27
EZ		 3609 /* Write the real regs for which this one is an alias. */
3610 for (portion = 0; portion < 2; portion++)
7bd872fe
EZ		 3611 regcache_write (base_regnum + portion,
3612 temp_buffer + REGISTER_RAW_SIZE (base_regnum) * portion);
53116e27 3613 }
f81353e4
EZ		 3614 else if (reg_nr >= tdep->FV0_REGNUM
3615 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 3616 {
3617 base_regnum = fv_reg_base_num (reg_nr);
3618
3619 /* Write the real regs for which this one is an alias. */
3620 for (portion = 0; portion < 4; portion++)
7bd872fe
EZ		 3621 regcache_write (base_regnum + portion,
3622 buffer + REGISTER_RAW_SIZE (base_regnum) * portion);
53116e27
EZ		 3623 }
3624}
3625
7bd872fe
EZ		 3626static void
3627sh4_register_write (struct gdbarch *gdbarch, int reg_nr, char *buffer)
3628{
3629 if (reg_nr >= 0 && reg_nr < gdbarch_tdep (current_gdbarch)->DR0_REGNUM)
3630 /* It is a regular register. */
3631 regcache_write (reg_nr, buffer);
3632 else
3633 /* It is a pseudo register and we need to construct its value */
3634 sh_pseudo_register_write (reg_nr, buffer);
3635}
3636
283150cd
EZ		 3637void
3638sh64_pseudo_register_write (int reg_nr, char *buffer)
3639{
3640 int base_regnum, portion;
3641 int offset;
3642 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
3643 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3644
3645 if (reg_nr >= tdep->DR0_REGNUM
3646 && reg_nr <= tdep->DR_LAST_REGNUM)
3647 {
3648 base_regnum = dr_reg_base_num (reg_nr);
3649 /* We must pay attention to the endiannes. */
3650 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3651 buffer, temp_buffer);
3652
3653
3654 /* Write the real regs for which this one is an alias. */
3655 for (portion = 0; portion < 2; portion++)
3656 regcache_write (base_regnum + portion,
3657 temp_buffer + REGISTER_RAW_SIZE (base_regnum) * portion);
3658 }
3659
3660 else if (reg_nr >= tdep->FPP0_REGNUM
3661 && reg_nr <= tdep->FPP_LAST_REGNUM)
3662 {
3663 base_regnum = fpp_reg_base_num (reg_nr);
3664
3665 /* Write the real regs for which this one is an alias. */
3666 for (portion = 0; portion < 2; portion++)
3667 regcache_write (base_regnum + portion,
3668 buffer + REGISTER_RAW_SIZE (base_regnum) * portion);
3669 }
3670
3671 else if (reg_nr >= tdep->FV0_REGNUM
3672 && reg_nr <= tdep->FV_LAST_REGNUM)
3673 {
3674 base_regnum = fv_reg_base_num (reg_nr);
3675
3676 /* Write the real regs for which this one is an alias. */
3677 for (portion = 0; portion < 4; portion++)
3678 regcache_write (base_regnum + portion,
3679 buffer + REGISTER_RAW_SIZE (base_regnum) * portion);
3680 }
3681
3682 /* sh compact general pseudo registers. 1-to-1 with a shmedia
3683 register but only 4 bytes of it. */
3684 else if (reg_nr >= tdep->R0_C_REGNUM
3685 && reg_nr <= tdep->T_C_REGNUM)
3686 {
3687 base_regnum = sh64_compact_reg_base_num (reg_nr);
3688 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
3689 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3690 offset = 4;
3691 else
3692 offset = 0;
3693 /* Let's read the value of the base register into a temporary
3694 buffer, so that overwriting the last four bytes with the new
3695 value of the pseudo will leave the upper 4 bytes unchanged. */
3696 regcache_read (base_regnum, temp_buffer);
3697 /* Write as an 8 byte quantity */
3698 memcpy (temp_buffer + offset, buffer, 4);
3699 regcache_write (base_regnum, temp_buffer);
3700 }
3701
3702 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
3703 registers. Both are 4 bytes. */
3704 else if (reg_nr >= tdep->FP0_C_REGNUM
3705 && reg_nr <= tdep->FP_LAST_C_REGNUM)
3706 {
3707 base_regnum = sh64_compact_reg_base_num (reg_nr);
3708 regcache_write (base_regnum, buffer);
3709 }
3710
3711 else if (reg_nr >= tdep->DR0_C_REGNUM
3712 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3713 {
3714 base_regnum = sh64_compact_reg_base_num (reg_nr);
3715 for (portion = 0; portion < 2; portion++)
3716 {
3717 /* We must pay attention to the endiannes. */
3718 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3719 buffer, temp_buffer);
3720
3721 regcache_write (base_regnum + portion,
3722 temp_buffer + REGISTER_RAW_SIZE (base_regnum) * portion);
3723 }
3724 }
3725
3726 else if (reg_nr >= tdep->FV0_C_REGNUM
3727 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3728 {
3729 base_regnum = sh64_compact_reg_base_num (reg_nr);
3730
3731 for (portion = 0; portion < 4; portion++)
3732 {
3733 regcache_write (base_regnum + portion,
3734 buffer + REGISTER_RAW_SIZE (base_regnum) * portion);
3735 }
3736 }
3737
3738 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3739 {
3740 int fpscr_base_regnum;
3741 int sr_base_regnum;
3742 unsigned int fpscr_value;
3743 unsigned int sr_value;
3744 unsigned int old_fpscr_value;
3745 unsigned int old_sr_value;
3746 unsigned int fpscr_c_value;
3747 unsigned int fpscr_mask;
3748 unsigned int sr_mask;
3749
3750 fpscr_base_regnum = tdep->FPSCR_REGNUM;
3751 sr_base_regnum = tdep->SR_REGNUM;
3752
3753 /* FPSCR_C is a very weird register that contains sparse bits
3754 from the FPSCR and the SR architectural registers.
3755 Specifically: */
3756 /* *INDENT-OFF* */
3757 /*
3758 FPSRC_C bit
3759 0 Bit 0 of FPSCR
3760 1 reserved
3761 2-17 Bit 2-18 of FPSCR
3762 18-20 Bits 12,13,14 of SR
3763 21-31 reserved
3764 */
3765 /* *INDENT-ON* */
3766 /* Get value as an int. */
3767 fpscr_c_value = extract_unsigned_integer (buffer, 4);
3768
3769 /* Build the new values. */
3770 fpscr_mask = 0x0003fffd;
3771 sr_mask = 0x001c0000;
3772
3773 fpscr_value = fpscr_c_value & fpscr_mask;
3774 sr_value = (fpscr_value & sr_mask) >> 6;
3775
3776 regcache_read (fpscr_base_regnum, temp_buffer);
3777 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
3778 old_fpscr_value &= 0xfffc0002;
3779 fpscr_value |= old_fpscr_value;
3780 store_unsigned_integer (temp_buffer, 4, fpscr_value);
3781 regcache_write (fpscr_base_regnum, temp_buffer);
3782
3783 regcache_read (sr_base_regnum, temp_buffer);
3784 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
3785 old_sr_value &= 0xffff8fff;
3786 sr_value |= old_sr_value;
3787 store_unsigned_integer (temp_buffer, 4, sr_value);
3788 regcache_write (sr_base_regnum, temp_buffer);
3789 }
3790
3791 else if (reg_nr == tdep->FPUL_C_REGNUM)
3792 {
3793 base_regnum = sh64_compact_reg_base_num (reg_nr);
3794 regcache_write (base_regnum, buffer);
3795 }
3796}
3797
3798static void
3799sh64_register_write (struct gdbarch *gdbarch, int reg_nr, char *buffer)
3800{
3801 if (reg_nr >= 0 && reg_nr < gdbarch_tdep (current_gdbarch)->DR0_REGNUM)
3802 /* It is a regular register. */
3803 regcache_write (reg_nr, buffer);
3804 else
3805 /* It is a pseudo register and we need to construct its value */
3806 sh64_pseudo_register_write (reg_nr, buffer);
3807}
3808
3bbfbb92 3809/* Floating point vector of 4 float registers. */
53116e27
EZ		 3810static void
3811do_fv_register_info (int fv_regnum)
3812{
3813 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
3814 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3815 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM,
3816 (int) read_register (first_fp_reg_num),
3817 (int) read_register (first_fp_reg_num + 1),
3818 (int) read_register (first_fp_reg_num + 2),
3819 (int) read_register (first_fp_reg_num + 3));
3820}
3821
283150cd
EZ		 3822/* Floating point vector of 4 float registers, compact mode. */
3823static void
3824do_fv_c_register_info (int fv_regnum)
3825{
3826 int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum);
3827 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3828 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_C_REGNUM,
3829 (int) read_register (first_fp_reg_num),
3830 (int) read_register (first_fp_reg_num + 1),
3831 (int) read_register (first_fp_reg_num + 2),
3832 (int) read_register (first_fp_reg_num + 3));
3833}
3834
3835/* Pairs of single regs. The DR are instead double precision
3836 registers. */
3837static void
3838do_fpp_register_info (int fpp_regnum)
3839{
3840 int first_fp_reg_num = fpp_reg_base_num (fpp_regnum);
3841
3842 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
3843 fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM,
3844 (int) read_register (first_fp_reg_num),
3845 (int) read_register (first_fp_reg_num + 1));
3846}
3847
3bbfbb92 3848/* Double precision registers. */
53116e27
EZ		 3849static void
3850do_dr_register_info (int dr_regnum)
3851{
3852 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
3853
3854 printf_filtered ("dr%d\t0x%08x%08x\n",
3855 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM,
3856 (int) read_register (first_fp_reg_num),
3857 (int) read_register (first_fp_reg_num + 1));
3858}
3859
283150cd
EZ		 3860/* Double precision registers, compact mode. */
3861static void
3862do_dr_c_register_info (int dr_regnum)
3863{
3864 int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum);
3865
3866 printf_filtered ("dr%d_c\t0x%08x%08x\n",
3867 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_C_REGNUM,
3868 (int) read_register (first_fp_reg_num),
3869 (int) read_register (first_fp_reg_num +1));
3870}
3871
3872/* General register in compact mode. */
3873static void
3874do_r_c_register_info (int r_c_regnum)
3875{
3876 int regnum = sh64_compact_reg_base_num (r_c_regnum);
3877
3878 printf_filtered ("r%d_c\t0x%08x\n",
3879 r_c_regnum - gdbarch_tdep (current_gdbarch)->R0_C_REGNUM,
3880 /*FIXME!!!*/ (int) read_register (regnum));
3881}
3882
3883/* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
3884 shmedia REGISTERS. */
3885/* Control registers, compact mode. */
3886static void
3887do_cr_c_register_info (int cr_c_regnum)
3888{
3889 switch (cr_c_regnum)
3890 {
3891 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3892 break;
3893 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3894 break;
3895 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3896 break;
3897 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3898 break;
3899 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3900 break;
3901 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3902 break;
3903 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3904 break;
3905 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum));
3906 break;
3907 }
3908}
3909
53116e27
EZ		 3910static void
3911sh_do_pseudo_register (int regnum)
3912{
f81353e4
EZ		 3913 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3914
53116e27 3915 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e65ff28
AC		 3916 internal_error (__FILE__, __LINE__,
3917 "Invalid pseudo register number %d\n", regnum);
f81353e4
EZ		 3918 else if (regnum >= tdep->DR0_REGNUM
3919 && regnum < tdep->DR_LAST_REGNUM)
53116e27 3920 do_dr_register_info (regnum);
f81353e4
EZ		 3921 else if (regnum >= tdep->FV0_REGNUM
3922 && regnum <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 3923 do_fv_register_info (regnum);
3924}
3925
53116e27
EZ		 3926static void
3927sh_do_fp_register (int regnum)
3928{ /* do values for FP (float) regs */
3929 char *raw_buffer;
3930 double flt; /* double extracted from raw hex data */
3931 int inv;
3932 int j;
3933
3934 /* Allocate space for the float. */
3935 raw_buffer = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
3936
3937 /* Get the data in raw format. */
cda5a58a 3938 if (!frame_register_read (selected_frame, regnum, raw_buffer))
53116e27
EZ		 3939 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
3940
3941 /* Get the register as a number */
3942 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
3943
3944 /* Print the name and some spaces. */
3945 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
3946 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
3947
3948 /* Print the value. */
93d56215
AC		 3949 if (inv)
3950 printf_filtered ("<invalid float>");
3951 else
3952 printf_filtered ("%-10.9g", flt);
53116e27
EZ		 3953
3954 /* Print the fp register as hex. */
3955 printf_filtered ("\t(raw 0x");
3956 for (j = 0; j < REGISTER_RAW_SIZE (regnum); j++)
3957 {
d7449b42 3958 register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
53116e27
EZ		 3959 : REGISTER_RAW_SIZE (regnum) - 1 - j;
3960 printf_filtered ("%02x", (unsigned char) raw_buffer[idx]);
3961 }
3962 printf_filtered (")");
3963 printf_filtered ("\n");
3964}
3965
283150cd
EZ		 3966static void
3967sh64_do_pseudo_register (int regnum)
3968{
3969 /* All the sh64-compact mode registers are pseudo registers. */
3970 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3971
3972 if (regnum < NUM_REGS
3973 || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT)
3974 internal_error (__FILE__, __LINE__,
3975 "Invalid pseudo register number %d\n", regnum);
3976
3977 else if ((regnum >= tdep->DR0_REGNUM
3978 && regnum <= tdep->DR_LAST_REGNUM))
3979 do_dr_register_info (regnum);
3980
3981 else if ((regnum >= tdep->DR0_C_REGNUM
3982 && regnum <= tdep->DR_LAST_C_REGNUM))
3983 do_dr_c_register_info (regnum);
3984
3985 else if ((regnum >= tdep->FV0_REGNUM
3986 && regnum <= tdep->FV_LAST_REGNUM))
3987 do_fv_register_info (regnum);
3988
3989 else if ((regnum >= tdep->FV0_C_REGNUM
3990 && regnum <= tdep->FV_LAST_C_REGNUM))
3991 do_fv_c_register_info (regnum);
3992
3993 else if (regnum >= tdep->FPP0_REGNUM
3994 && regnum <= tdep->FPP_LAST_REGNUM)
3995 do_fpp_register_info (regnum);
3996
3997 else if (regnum >= tdep->R0_C_REGNUM
3998 && regnum <= tdep->R_LAST_C_REGNUM)
3999 do_r_c_register_info (regnum); /* FIXME, this function will not print the right format */
4000
4001 else if (regnum >= tdep->FP0_C_REGNUM
4002 && regnum <= tdep->FP_LAST_C_REGNUM)
4003 sh_do_fp_register (regnum); /* this should work also for pseudoregs */
4004
4005 else if (regnum >= tdep->PC_C_REGNUM
4006 && regnum <= tdep->FPUL_C_REGNUM)
4007 do_cr_c_register_info (regnum);
4008
4009}
4010
53116e27
EZ		 4011static void
4012sh_do_register (int regnum)
4013{
4014 char raw_buffer[MAX_REGISTER_RAW_SIZE];
4015
4016 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
4017 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
4018
4019 /* Get the data in raw format. */
cda5a58a 4020 if (!frame_register_read (selected_frame, regnum, raw_buffer))
53116e27
EZ		 4021 printf_filtered ("*value not available*\n");
4022
4023 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
4024 gdb_stdout, 'x', 1, 0, Val_pretty_default);
4025 printf_filtered ("\t");
4026 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
4027 gdb_stdout, 0, 1, 0, Val_pretty_default);
4028 printf_filtered ("\n");
4029}
4030
4031static void
4032sh_print_register (int regnum)
4033{
4034 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e65ff28
AC		 4035 internal_error (__FILE__, __LINE__,
4036 "Invalid register number %d\n", regnum);
53116e27 4037
e30839fe 4038 else if (regnum >= 0 && regnum < NUM_REGS)
53116e27
EZ		 4039 {
4040 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4041 sh_do_fp_register (regnum); /* FP regs */
4042 else
4043 sh_do_register (regnum); /* All other regs */
4044 }
4045
4046 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
3bbfbb92 4047 do_pseudo_register (regnum);
53116e27
EZ		 4048}
4049
4050void
4051sh_do_registers_info (int regnum, int fpregs)
4052{
4053 if (regnum != -1) /* do one specified register */
4054 {
4055 if (*(REGISTER_NAME (regnum)) == '\0')
4056 error ("Not a valid register for the current processor type");
4057
4058 sh_print_register (regnum);
4059 }
4060 else
4061 /* do all (or most) registers */
4062 {
4063 regnum = 0;
4064 while (regnum < NUM_REGS)
4065 {
4066 /* If the register name is empty, it is undefined for this
4067 processor, so don't display anything. */
4068 if (REGISTER_NAME (regnum) == NULL
4069 || *(REGISTER_NAME (regnum)) == '\0')
4070 {
4071 regnum++;
4072 continue;
4073 }
4074
4075 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4076 {
4077 if (fpregs)
4078 {
4079 /* true for "INFO ALL-REGISTERS" command */
4080 sh_do_fp_register (regnum); /* FP regs */
4081 regnum ++;
4082 }
4083 else
e6c42fda 4084 regnum += (gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
53116e27
EZ		 4085 }
4086 else
4087 {
4088 sh_do_register (regnum); /* All other regs */
4089 regnum++;
4090 }
4091 }
4092
4093 if (fpregs)
4094 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4095 {
3bbfbb92 4096 do_pseudo_register (regnum);
53116e27
EZ		 4097 regnum++;
4098 }
4099 }
4100}
4101
283150cd
EZ		 4102void
4103sh_compact_do_registers_info (int regnum, int fpregs)
4104{
4105 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4106 if (regnum != -1) /* do one specified register */
4107 {
4108 if (*(REGISTER_NAME (regnum)) == '\0')
4109 error ("Not a valid register for the current processor type");
4110
4111 if (regnum >= 0 && regnum < tdep->R0_C_REGNUM)
4112 error ("Not a valid register for the current processor mode.");
4113
4114 sh_print_register (regnum);
4115 }
4116 else
4117 /* do all compact registers */
4118 {
4119 regnum = tdep->R0_C_REGNUM;
4120 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4121 {
4122 do_pseudo_register (regnum);
4123 regnum++;
4124 }
4125 }
4126}
4127
4128void
4129sh64_do_registers_info (int regnum, int fpregs)
4130{
4131 if (pc_is_isa32 (selected_frame->pc))
4132 sh_do_registers_info (regnum, fpregs);
4133 else
4134 sh_compact_do_registers_info (regnum, fpregs);
4135}
4136
1a8629c7
MS		 4137#ifdef SVR4_SHARED_LIBS
4138
4139/* Fetch (and possibly build) an appropriate link_map_offsets structure
4140 for native i386 linux targets using the struct offsets defined in
4141 link.h (but without actual reference to that file).
4142
4143 This makes it possible to access i386-linux shared libraries from
4144 a gdb that was not built on an i386-linux host (for cross debugging).
4145 */
4146
4147struct link_map_offsets *
4148sh_linux_svr4_fetch_link_map_offsets (void)
4149{
4150 static struct link_map_offsets lmo;
4151 static struct link_map_offsets *lmp = 0;
4152
4153 if (lmp == 0)
4154 {
4155 lmp = &lmo;
4156
4157 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
4158
4159 lmo.r_map_offset = 4;
4160 lmo.r_map_size = 4;
4161
4162 lmo.link_map_size = 20; /* 552 not actual size but all we need */
4163
4164 lmo.l_addr_offset = 0;
4165 lmo.l_addr_size = 4;
4166
4167 lmo.l_name_offset = 4;
4168 lmo.l_name_size = 4;
4169
4170 lmo.l_next_offset = 12;
4171 lmo.l_next_size = 4;
4172
4173 lmo.l_prev_offset = 16;
4174 lmo.l_prev_size = 4;
4175 }
4176
4177 return lmp;
4178}
4179#endif /* SVR4_SHARED_LIBS */
4180
d658f924
JT		 4181\f
4182/* This table matches the indices assigned to enum sh_osabi. Keep
4183 them in sync. */
4184static const char * const sh_osabi_names[] =
4185{
4186 "<unknown>",
4187 "GNU/Linux",
4188 "NetBSD ELF",
4189 NULL
4190};
4191
4192static void
4193process_note_abi_tag_sections (bfd *abfd, asection *sect, void *obj)
4194{
4195 enum sh_osabi *os_ident_ptr = obj;
4196 const char *name;
4197 unsigned int sectsize;
4198
4199 name = bfd_get_section_name (abfd, sect);
4200 sectsize = bfd_section_size (abfd, sect);
4201
4202 if (strcmp (name, ".note.ABI-tag") == 0 && sectsize > 0)
4203 {
4204 unsigned int name_length, data_length, note_type;
4205 char *note;
4206
4207 /* If the section is larger than this, it's probably not what we are
4208 looking for. */
4209 if (sectsize > 128)
4210 sectsize = 128;
4211
4212 note = alloca (sectsize);
4213
4214 bfd_get_section_contents (abfd, sect, note,
4215 (file_ptr) 0, (bfd_size_type) sectsize);
4216
4217 name_length = bfd_h_get_32 (abfd, note);
4218 data_length = bfd_h_get_32 (abfd, note + 4);
4219 note_type = bfd_h_get_32 (abfd, note + 8);
4220
4221 if (name_length == 4 && data_length == 16 && note_type == NT_GNU_ABI_TAG
4222 && strcmp (note + 12, "GNU") == 0)
4223 {
4224 int os_number = bfd_h_get_32 (abfd, note + 16);
4225
4226 /* The case numbers are from abi-tags in glibc. */
4227 switch (os_number)
4228 {
4229 case GNU_ABI_TAG_LINUX:
4230 *os_ident_ptr = SH_OSABI_LINUX;
4231 break;
4232
4233 case GNU_ABI_TAG_HURD:
4234 internal_error
4235 (__FILE__, __LINE__,
4236 "process_note_abi_sections: Hurd objects not supported");
4237 break;
4238
4239 case GNU_ABI_TAG_SOLARIS:
4240 internal_error
4241 (__FILE__, __LINE__,
4242 "process_note_abi_sections: Solaris objects not supported");
4243 break;
4244
4245 default:
4246 internal_error
4247 (__FILE__, __LINE__,
4248 "process_note_abi_sections: unknown OS number %d",
4249 os_number);
4250 }
4251 }
4252 }
4253 /* NetBSD uses a similar trick. */
4254 else if (strcmp (name, ".note.netbsd.ident") == 0 && sectsize > 0)
4255 {
4256 unsigned int name_length, desc_length, note_type;
4257 char *note;
4258
4259 /* If the section is larger than this, it's probably not what we are
4260 looking for. */
4261 if (sectsize > 128)
4262 sectsize = 128;
4263
4264 note = alloca (sectsize);
4265
4266 bfd_get_section_contents (abfd, sect, note,
4267 (file_ptr) 0, (bfd_size_type) sectsize);
4268
4269 name_length = bfd_h_get_32 (abfd, note);
4270 desc_length = bfd_h_get_32 (abfd, note + 4);
4271 note_type = bfd_h_get_32 (abfd, note + 8);
4272
4273 if (name_length == 7 && desc_length == 4 && note_type == NT_NETBSD_IDENT
4274 && strcmp (note + 12, "NetBSD") == 0)
4275 /* XXX Should we check the version here?
4276 Probably not necessary yet. */
4277 *os_ident_ptr = SH_OSABI_NETBSD_ELF;
4278 }
4279}
4280
4281static int
4282get_elfosabi (bfd *abfd)
4283{
4284 int elfosabi;
4285 enum sh_osabi sh_osabi = SH_OSABI_UNKNOWN;
4286
4287 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
4288
4289 switch (elfosabi)
4290 {
4291 case ELFOSABI_NONE:
4292 /* When elfosabi is 0 (ELFOSABI_NONE), this is supposed to indicate
4293 that we're on a SYSV system. However, some systems use note sections
4294 to record OS/ABI info, but leave e_ident[EI_OSABI] zero. So we
4295 have to check the note sections too. */
4296 bfd_map_over_sections (abfd,
4297 process_note_abi_tag_sections,
4298 &sh_osabi);
4299 break;
4300
4301 case ELFOSABI_NETBSD:
4302 sh_osabi = SH_OSABI_NETBSD_ELF;
4303 break;
4304
4305 case ELFOSABI_LINUX:
4306 sh_osabi = SH_OSABI_LINUX;
4307 break;
4308 }
4309
4310 return (sh_osabi);
4311}
4312
4313struct sh_osabi_handler
4314{
4315 struct sh_osabi_handler *next;
4316 enum sh_osabi abi;
4317 void (*init_osabi)(struct gdbarch_info, struct gdbarch *);
4318};
4319
4320struct sh_osabi_handler *sh_osabi_handler_list = NULL;
4321
4322void
4323sh_gdbarch_register_os_abi (enum sh_osabi abi,
4324 void (*init_osabi)(struct gdbarch_info,
4325 struct gdbarch *))
4326{
4327 struct sh_osabi_handler **handler_p;
4328
4329 for (handler_p = &sh_osabi_handler_list; *handler_p != NULL;
4330 handler_p = &(*handler_p)->next)
4331 {
4332 if ((*handler_p)->abi == abi)
4333 {
4334 internal_error
4335 (__FILE__, __LINE__,
4336 "sh_gdbarch_register_os_abi: A handler for this ABI variant "
4337 "(%d) has already been registered", (int) abi);
4338 /* If user wants to continue, override previous definition. */
4339 (*handler_p)->init_osabi = init_osabi;
4340 return;
4341 }
4342 }
4343
4344 (*handler_p)
4345 = (struct sh_osabi_handler *) xmalloc (sizeof (struct sh_osabi_handler));
4346 (*handler_p)->next = NULL;
4347 (*handler_p)->abi = abi;
4348 (*handler_p)->init_osabi = init_osabi;
4349}
4350
cc17453a
EZ		 4351static gdbarch_init_ftype sh_gdbarch_init;
4352
4353static struct gdbarch *
fba45db2 4354sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a
EZ		 4355{
4356 static LONGEST sh_call_dummy_words[] = {0};
4357 struct gdbarch *gdbarch;
4358 struct gdbarch_tdep *tdep;
4359 gdbarch_register_name_ftype *sh_register_name;
4360 gdbarch_store_return_value_ftype *sh_store_return_value;
4361 gdbarch_register_virtual_type_ftype *sh_register_virtual_type;
d658f924
JT		 4362 enum sh_osabi sh_osabi = SH_OSABI_UNKNOWN;
4363 struct sh_osabi_handler *osabi_handler;
4364
4365 /* Try to determine the ABI of the object we are loading. */
4366
4367 if (info.abfd != NULL)
4368 {
4369 switch (bfd_get_flavour (info.abfd))
4370 {
4371 case bfd_target_elf_flavour:
4372 sh_osabi = get_elfosabi (info.abfd);
4373 break;
4374
4375 default:
4376 /* Just leave it as "unkown". */
4377 break;
4378 }
4379 }
cc17453a
EZ		 4380
4381 /* Find a candidate among the list of pre-declared architectures. */
d658f924
JT		 4382 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4383 arches != NULL;
4384 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4385 {
4386 /* Make sure the ABI selection matches. */
4387 tdep = gdbarch_tdep (arches->gdbarch);
4388 if (tdep && tdep->sh_osabi == sh_osabi)
4389 return arches->gdbarch;
4390 }
cc17453a
EZ		 4391
4392 /* None found, create a new architecture from the information
4393 provided. */
4394 tdep = XMALLOC (struct gdbarch_tdep);
4395 gdbarch = gdbarch_alloc (&info, tdep);
4396
d658f924
JT		 4397 tdep->sh_osabi = sh_osabi;
4398 if (sh_osabi < SH_OSABI_INVALID)
4399 tdep->osabi_name = sh_osabi_names[sh_osabi];
4400 else
4401 {
4402 internal_error (__FILE__, __LINE__, "Invalid setting of sh_osabi %d",
4403 (int) sh_osabi);
4404 tdep->osabi_name = "<invalid>";
4405 }
4406
cc17453a
EZ		 4407 /* Initialize the register numbers that are not common to all the
4408 variants to -1, if necessary thse will be overwritten in the case
4409 statement below. */
4410 tdep->FPUL_REGNUM = -1;
4411 tdep->FPSCR_REGNUM = -1;
3bbfbb92 4412 tdep->PR_REGNUM = 17;
c62a7c7b 4413 tdep->SR_REGNUM = 22;
cc17453a 4414 tdep->DSR_REGNUM = -1;
e6c42fda 4415 tdep->FP_LAST_REGNUM = -1;
cc17453a
EZ		 4416 tdep->A0G_REGNUM = -1;
4417 tdep->A0_REGNUM = -1;
4418 tdep->A1G_REGNUM = -1;
4419 tdep->A1_REGNUM = -1;
4420 tdep->M0_REGNUM = -1;
4421 tdep->M1_REGNUM = -1;
4422 tdep->X0_REGNUM = -1;
4423 tdep->X1_REGNUM = -1;
4424 tdep->Y0_REGNUM = -1;
4425 tdep->Y1_REGNUM = -1;
4426 tdep->MOD_REGNUM = -1;
4427 tdep->RS_REGNUM = -1;
4428 tdep->RE_REGNUM = -1;
4429 tdep->SSR_REGNUM = -1;
4430 tdep->SPC_REGNUM = -1;
53116e27 4431 tdep->DR0_REGNUM = -1;
e6c42fda 4432 tdep->DR_LAST_REGNUM = -1;
53116e27 4433 tdep->FV0_REGNUM = -1;
e6c42fda 4434 tdep->FV_LAST_REGNUM = -1;
3bbfbb92
EZ		 4435 tdep->ARG0_REGNUM = 4;
4436 tdep->ARGLAST_REGNUM = 7;
4437 tdep->RETURN_REGNUM = 0;
4438 tdep->FLOAT_ARGLAST_REGNUM = -1;
a38d2a54 4439
283150cd
EZ		 4440 tdep->sh_abi = SH_ABI_UNKNOWN;
4441
cc17453a 4442 set_gdbarch_fp0_regnum (gdbarch, -1);
53116e27
EZ		 4443 set_gdbarch_num_pseudo_regs (gdbarch, 0);
4444 set_gdbarch_max_register_raw_size (gdbarch, 4);
4445 set_gdbarch_max_register_virtual_size (gdbarch, 4);
ec920329 4446 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
a38d2a54 4447 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
88e04cc1 4448 set_gdbarch_num_regs (gdbarch, SH_DEFAULT_NUM_REGS);
a38d2a54
EZ		 4449 set_gdbarch_sp_regnum (gdbarch, 15);
4450 set_gdbarch_fp_regnum (gdbarch, 14);
4451 set_gdbarch_pc_regnum (gdbarch, 16);
4452 set_gdbarch_register_size (gdbarch, 4);
88e04cc1 4453 set_gdbarch_register_bytes (gdbarch, SH_DEFAULT_NUM_REGS * 4);
c5f7d19c 4454 set_gdbarch_do_registers_info (gdbarch, sh_do_registers_info);
eaf90c5d 4455 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
3bbfbb92
EZ		 4456 set_gdbarch_frame_chain (gdbarch, sh_frame_chain);
4457 set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
4458 set_gdbarch_init_extra_frame_info (gdbarch, sh_init_extra_frame_info);
3116c80a 4459 set_gdbarch_extract_return_value (gdbarch, sh_extract_return_value);
3bbfbb92
EZ		 4460 set_gdbarch_push_arguments (gdbarch, sh_push_arguments);
4461 set_gdbarch_store_struct_return (gdbarch, sh_store_struct_return);
4462 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
4463 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4464 set_gdbarch_pop_frame (gdbarch, sh_pop_frame);
2bf0cb65 4465 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
3bbfbb92
EZ		 4466 skip_prologue_hard_way = sh_skip_prologue_hard_way;
4467 do_pseudo_register = sh_do_pseudo_register;
cc17453a
EZ		 4468
4469 switch (info.bfd_arch_info->mach)
8db62801 4470 {
cc17453a
EZ		 4471 case bfd_mach_sh:
4472 sh_register_name = sh_sh_register_name;
4473 sh_show_regs = sh_generic_show_regs;
4474 sh_store_return_value = sh_default_store_return_value;
4475 sh_register_virtual_type = sh_default_register_virtual_type;
4476 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 4477 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4478 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4479 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 4480 break;
4481 case bfd_mach_sh2:
4482 sh_register_name = sh_sh_register_name;
4483 sh_show_regs = sh_generic_show_regs;
4484 sh_store_return_value = sh_default_store_return_value;
4485 sh_register_virtual_type = sh_default_register_virtual_type;
4486 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 4487 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4488 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4489 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 4490 break;
4491 case bfd_mach_sh_dsp:
4492 sh_register_name = sh_sh_dsp_register_name;
4493 sh_show_regs = sh_dsp_show_regs;
4494 sh_store_return_value = sh_default_store_return_value;
4495 sh_register_virtual_type = sh_default_register_virtual_type;
4496 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 4497 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4498 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4499 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 4500 tdep->DSR_REGNUM = 24;
4501 tdep->A0G_REGNUM = 25;
4502 tdep->A0_REGNUM = 26;
4503 tdep->A1G_REGNUM = 27;
4504 tdep->A1_REGNUM = 28;
4505 tdep->M0_REGNUM = 29;
4506 tdep->M1_REGNUM = 30;
4507 tdep->X0_REGNUM = 31;
4508 tdep->X1_REGNUM = 32;
4509 tdep->Y0_REGNUM = 33;
4510 tdep->Y1_REGNUM = 34;
4511 tdep->MOD_REGNUM = 40;
4512 tdep->RS_REGNUM = 43;
4513 tdep->RE_REGNUM = 44;
4514 break;
4515 case bfd_mach_sh3:
4516 sh_register_name = sh_sh3_register_name;
4517 sh_show_regs = sh3_show_regs;
4518 sh_store_return_value = sh_default_store_return_value;
4519 sh_register_virtual_type = sh_default_register_virtual_type;
4520 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 4521 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4522 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4523 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 4524 tdep->SSR_REGNUM = 41;
4525 tdep->SPC_REGNUM = 42;
4526 break;
4527 case bfd_mach_sh3e:
4528 sh_register_name = sh_sh3e_register_name;
4529 sh_show_regs = sh3e_show_regs;
4530 sh_store_return_value = sh3e_sh4_store_return_value;
4531 sh_register_virtual_type = sh_sh3e_register_virtual_type;
4532 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
53116e27
EZ		 4533 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4534 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4535 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
3bbfbb92 4536 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
cc17453a
EZ		 4537 set_gdbarch_fp0_regnum (gdbarch, 25);
4538 tdep->FPUL_REGNUM = 23;
4539 tdep->FPSCR_REGNUM = 24;
e6c42fda 4540 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 4541 tdep->SSR_REGNUM = 41;
4542 tdep->SPC_REGNUM = 42;
4543 break;
4544 case bfd_mach_sh3_dsp:
4545 sh_register_name = sh_sh3_dsp_register_name;
4546 sh_show_regs = sh3_dsp_show_regs;
4547 sh_store_return_value = sh_default_store_return_value;
4548 sh_register_virtual_type = sh_default_register_virtual_type;
4549 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 4550 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4551 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4552 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 4553 tdep->DSR_REGNUM = 24;
4554 tdep->A0G_REGNUM = 25;
4555 tdep->A0_REGNUM = 26;
4556 tdep->A1G_REGNUM = 27;
4557 tdep->A1_REGNUM = 28;
4558 tdep->M0_REGNUM = 29;
4559 tdep->M1_REGNUM = 30;
4560 tdep->X0_REGNUM = 31;
4561 tdep->X1_REGNUM = 32;
4562 tdep->Y0_REGNUM = 33;
4563 tdep->Y1_REGNUM = 34;
4564 tdep->MOD_REGNUM = 40;
4565 tdep->RS_REGNUM = 43;
4566 tdep->RE_REGNUM = 44;
4567 tdep->SSR_REGNUM = 41;
4568 tdep->SPC_REGNUM = 42;
4569 break;
4570 case bfd_mach_sh4:
53116e27
EZ		 4571 sh_register_name = sh_sh4_register_name;
4572 sh_show_regs = sh4_show_regs;
cc17453a 4573 sh_store_return_value = sh3e_sh4_store_return_value;
53116e27 4574 sh_register_virtual_type = sh_sh4_register_virtual_type;
cc17453a 4575 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
3bbfbb92 4576 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
cc17453a 4577 set_gdbarch_fp0_regnum (gdbarch, 25);
53116e27
EZ		 4578 set_gdbarch_register_raw_size (gdbarch, sh_sh4_register_raw_size);
4579 set_gdbarch_register_virtual_size (gdbarch, sh_sh4_register_raw_size);
4580 set_gdbarch_register_byte (gdbarch, sh_sh4_register_byte);
4581 set_gdbarch_num_pseudo_regs (gdbarch, 12);
4582 set_gdbarch_max_register_raw_size (gdbarch, 4 * 4);
4583 set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4);
7bd872fe
EZ		 4584 set_gdbarch_register_read (gdbarch, sh4_register_read);
4585 set_gdbarch_register_write (gdbarch, sh4_register_write);
cc17453a
EZ		 4586 tdep->FPUL_REGNUM = 23;
4587 tdep->FPSCR_REGNUM = 24;
e6c42fda 4588 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 4589 tdep->SSR_REGNUM = 41;
4590 tdep->SPC_REGNUM = 42;
53116e27 4591 tdep->DR0_REGNUM = 59;
e6c42fda 4592 tdep->DR_LAST_REGNUM = 66;
53116e27 4593 tdep->FV0_REGNUM = 67;
e6c42fda 4594 tdep->FV_LAST_REGNUM = 70;
cc17453a 4595 break;
283150cd
EZ		 4596 case bfd_mach_sh5:
4597 tdep->PR_REGNUM = 18;
4598 tdep->SR_REGNUM = 65;
4599 tdep->FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM;
4600 tdep->FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1;
4601 tdep->SSR_REGNUM = SIM_SH64_SSR_REGNUM;
4602 tdep->SPC_REGNUM = SIM_SH64_SPC_REGNUM;
4603 tdep->TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7;
4604 tdep->FPP0_REGNUM = 173;
4605 tdep->FPP_LAST_REGNUM = 204;
4606 tdep->DR0_REGNUM = 141;
4607 tdep->DR_LAST_REGNUM = 172;
4608 tdep->FV0_REGNUM = 205;
4609 tdep->FV_LAST_REGNUM = 220;
4610 tdep->R0_C_REGNUM = 221;
4611 tdep->R_LAST_C_REGNUM = 236;
4612 tdep->PC_C_REGNUM = 237;
4613 tdep->GBR_C_REGNUM = 238;
4614 tdep->MACH_C_REGNUM = 239;
4615 tdep->MACL_C_REGNUM = 240;
4616 tdep->PR_C_REGNUM = 241;
4617 tdep->T_C_REGNUM = 242;
4618 tdep->FPSCR_C_REGNUM = 243;
4619 tdep->FPUL_C_REGNUM = 244;
4620 tdep->FP0_C_REGNUM = 245;
4621 tdep->FP_LAST_C_REGNUM = 260;
4622 tdep->DR0_C_REGNUM = 261;
4623 tdep->DR_LAST_C_REGNUM = 268;
4624 tdep->FV0_C_REGNUM = 269;
4625 tdep->FV_LAST_C_REGNUM = 272;
4626 tdep->ARG0_REGNUM = 2;
4627 tdep->ARGLAST_REGNUM = 9;
4628 tdep->RETURN_REGNUM = 2;
4629 tdep->FLOAT_ARGLAST_REGNUM = 11;
4630
4631 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT);
4632 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
4633 set_gdbarch_pc_regnum (gdbarch, 64);
4634
4635 /* Determine the ABI */
4636 if (bfd_get_arch_size (info.abfd) == 64)
4637 {
4638 /* If the ABI is the 64-bit one, it can only be sh-media. */
4639 tdep->sh_abi = SH_ABI_64;
4640 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4641 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4642 }
4643 else
4644 {
4645 /* If the ABI is the 32-bit one it could be either media or
4646 compact. */
4647 tdep->sh_abi = SH_ABI_32;
4648 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4649 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4650 }
4651
4652 /* the number of real registers is the same whether we are in
4653 ISA16(compact) or ISA32(media). */
4654 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
4655 set_gdbarch_register_size (gdbarch, 8); /*????*/
4656 set_gdbarch_register_bytes (gdbarch,
4657 ((SIM_SH64_NR_FP_REGS + 1) * 4)
4658 + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8);
4659
4660 sh_register_name = sh_sh64_register_name;
4661 sh_show_regs = sh64_show_regs;
4662 sh_register_virtual_type = sh_sh64_register_virtual_type;
4663 sh_store_return_value = sh64_store_return_value;
4664 skip_prologue_hard_way = sh64_skip_prologue_hard_way;
4665 do_pseudo_register = sh64_do_pseudo_register;
283150cd
EZ		 4666 set_gdbarch_register_raw_size (gdbarch, sh_sh64_register_raw_size);
4667 set_gdbarch_register_virtual_size (gdbarch, sh_sh64_register_raw_size);
4668 set_gdbarch_register_byte (gdbarch, sh_sh64_register_byte);
4669 /* This seems awfully wrong!*/
4670 /*set_gdbarch_max_register_raw_size (gdbarch, 8);*/
4671 /* should include the size of the pseudo regs. */
4672 set_gdbarch_max_register_raw_size (gdbarch, 4 * 4);
4673 /* Or should that go in the virtual_size? */
4674 /*set_gdbarch_max_register_virtual_size (gdbarch, 8);*/
4675 set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4);
4676 set_gdbarch_register_read (gdbarch, sh64_register_read);
4677 set_gdbarch_register_write (gdbarch, sh64_register_write);
4678
4679 set_gdbarch_do_registers_info (gdbarch, sh64_do_registers_info);
4680 set_gdbarch_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs);
4681 set_gdbarch_breakpoint_from_pc (gdbarch, sh_sh64_breakpoint_from_pc);
4682 set_gdbarch_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info);
4683 set_gdbarch_frame_chain (gdbarch, sh64_frame_chain);
4684 set_gdbarch_get_saved_register (gdbarch, sh64_get_saved_register);
4685 set_gdbarch_extract_return_value (gdbarch, sh64_extract_return_value);
4686 set_gdbarch_push_arguments (gdbarch, sh64_push_arguments);
4687 /*set_gdbarch_store_struct_return (gdbarch, sh64_store_struct_return);*/
4688 set_gdbarch_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address);
4689 set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention);
4690 set_gdbarch_pop_frame (gdbarch, sh64_pop_frame);
4691 set_gdbarch_elf_make_msymbol_special (gdbarch,
4692 sh64_elf_make_msymbol_special);
4693 break;
cc17453a
EZ		 4694 default:
4695 sh_register_name = sh_generic_register_name;
4696 sh_show_regs = sh_generic_show_regs;
4697 sh_store_return_value = sh_default_store_return_value;
4698 sh_register_virtual_type = sh_default_register_virtual_type;
4699 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 4700 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4701 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4702 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a 4703 break;
8db62801 4704 }
cc17453a
EZ		 4705
4706 set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
4707 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
4708 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
cc17453a
EZ		 4709 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
4710 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
4711
cc17453a 4712 set_gdbarch_register_name (gdbarch, sh_register_name);
cc17453a
EZ		 4713 set_gdbarch_register_virtual_type (gdbarch, sh_register_virtual_type);
4714
cc17453a
EZ		 4715 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
4716 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
cc17453a
EZ		 4717 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4718 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4719 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
a38d2a54 4720 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);/*??should be 8?*/
cc17453a
EZ		 4721
4722 set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
4723 set_gdbarch_call_dummy_length (gdbarch, 0);
4724 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
4725 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
4726 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); /*???*/
4727 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
4728 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
4729 set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
4730 set_gdbarch_call_dummy_words (gdbarch, sh_call_dummy_words);
4731 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (sh_call_dummy_words));
4732 set_gdbarch_call_dummy_p (gdbarch, 1);
4733 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
cc17453a
EZ		 4734 set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
4735 set_gdbarch_coerce_float_to_double (gdbarch,
4736 sh_coerce_float_to_double);
4737
cc17453a
EZ		 4738 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
4739 set_gdbarch_push_return_address (gdbarch, sh_push_return_address);
4740
cc17453a 4741 set_gdbarch_store_return_value (gdbarch, sh_store_return_value);
cc17453a
EZ		 4742 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
4743 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4744 set_gdbarch_decr_pc_after_break (gdbarch, 0);
4745 set_gdbarch_function_start_offset (gdbarch, 0);
cc17453a
EZ		 4746
4747 set_gdbarch_frame_args_skip (gdbarch, 0);
4748 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
cc17453a
EZ		 4749 set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid);
4750 set_gdbarch_frame_saved_pc (gdbarch, sh_frame_saved_pc);
c347ee3e
MS		 4751 set_gdbarch_frame_args_address (gdbarch, default_frame_address);
4752 set_gdbarch_frame_locals_address (gdbarch, default_frame_address);
cc17453a
EZ		 4753 set_gdbarch_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
4754 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
4755 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
cc17453a 4756
d658f924
JT		 4757 /* Hook in ABI-specific overrides, if they have been registered. If
4758 the ABI is unknown, this is probably an embedded target, so we
4759 should not warn about this situation. */
4760 if (sh_osabi != SH_OSABI_UNKNOWN)
4761 {
4762 for (osabi_handler = sh_osabi_handler_list; osabi_handler != NULL;
4763 osabi_handler = osabi_handler->next)
4764 if (osabi_handler->abi == sh_osabi)
4765 break;
4766
4767 if (osabi_handler)
4768 osabi_handler->init_osabi (info, gdbarch);
4769 else
4770 {
4771 /* We assume that if GDB_MULTI_ARCH is less than
4772 GDB_MULTI_ARCH_TM that an ABI variant can be supported by
4773 overriding definitions in this file. */
4774 if (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
4775 fprintf_filtered
4776 (gdb_stderr,
4777 "A handler for the ABI variant \"%s\" is not built into this "
4778 "configuration of GDB. "
4779 "Attempting to continue with the default SuperH settings",
4780 sh_osabi_names[sh_osabi]);
4781 }
4782 }
4783
cc17453a 4784 return gdbarch;
8db62801
EZ		 4785}
4786
d658f924
JT		 4787static void
4788sh_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
4789{
4790 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4791
4792 if (tdep == NULL)
4793 return;
4794
4795 if (tdep->osabi_name != NULL)
4796 fprintf_unfiltered (file, "sh_dump_tdep: OS ABI = %s\n", tdep->osabi_name);
4797 else
4798 internal_error (__FILE__, __LINE__,
4799 "sh_dump_tdep: illegal setting of tdep->sh_osabi (%d)",
4800 (int) tdep->sh_osabi);
4801}
4802
c906108c 4803void
fba45db2 4804_initialize_sh_tdep (void)
c906108c
SS		 4805{
4806 struct cmd_list_element *c;
cc17453a 4807
d658f924 4808 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, sh_dump_tdep);
c906108c 4809
53116e27 4810 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
c906108c 4811}
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