rockchip: rk3288: grf: Fix shift for RK3288_TXCLK_DLY_ENA_GMAC_ENABLE

RK3288_TXCLK_DLY_ENA_GMAC_ENABLE, in GRF_SOC_CON3, is supposed to be bit
0xe and not 0xf. Otherwise, it is RGMII RX clock delayline enable and
introduces random delays and data lose.

This commit fixes the issue by replacing RK3288_TXCLK_DLY_ENA_GMAC_ENABLE
with the right shift.

Signed-off-by: Romain Perier <[email protected]>
Reviewed-by: Simon Glass <[email protected]>

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
index 7d56b8ced0a916c21d1a95667ef2ca83ed1632bc..fbc4a0d80f8e94d0f65bf7c618987368efe50d7b 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
@@ -813,7 +813,7 @@ enum {
                (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
        RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
        RK3288_TXCLK_DLY_ENA_GMAC_ENABLE =
-               (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
+               (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
 
        RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
        RK3288_CLK_RX_DL_CFG_GMAC_MASK =