resets = <&rcc UART8_R>;
};
-&usbotg_hs {
- compatible = "st,stm32mp1-hsotg", "snps,dwc2";
-};
Optional properties:
- vbus-supply : reference to the VBUS regulator;
+ - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
+ bit1 for u3port1, ... etc;
+ - mediatek,u2p-dis-msk : mask to disable u2ports, bit0 for u2port0,
+ bit1 for u2port1, ... etc;
Example:
xhci: usb@1a0c0000 {
static const struct udevice_id dwc2_udc_otg_ids[] = {
{ .compatible = "snps,dwc2" },
{ .compatible = "brcm,bcm2835-usb" },
- { .compatible = "st,stm32mp1-hsotg",
+ { .compatible = "st,stm32mp15-hsotg",
.data = (ulong)dwc2_set_stm32mp1_hsotg_params },
{},
};
struct phy_bulk phys;
int num_u2ports;
int num_u3ports;
+ u32 u3p_dis_msk;
+ u32 u2p_dis_msk;
};
static int xhci_mtk_host_enable(struct mtk_xhci *mtk)
{
+ int u3_ports_disabed = 0;
u32 value;
u32 check_val;
int ret;
/* power on host ip */
clrbits_le32(mtk->ippc + IPPC_IP_PW_CTRL1, CTRL1_IP_HOST_PDN);
- /* power on and enable all u3 ports */
+ /* power on and enable u3 ports except skipped ones */
for (i = 0; i < mtk->num_u3ports; i++) {
+ if (BIT(i) & mtk->u3p_dis_msk) {
+ u3_ports_disabed++;
+ continue;
+ }
+
clrsetbits_le32(mtk->ippc + IPPC_U3_CTRL(i),
CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS,
CTRL_U3_PORT_HOST_SEL);
}
- /* power on and enable all u2 ports */
+ /* power on and enable u2 ports except skipped ones */
for (i = 0; i < mtk->num_u2ports; i++) {
+ if (BIT(i) & mtk->u2p_dis_msk)
+ continue;
+
clrsetbits_le32(mtk->ippc + IPPC_U2_CTRL(i),
CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS,
CTRL_U2_PORT_HOST_SEL);
check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
STS1_SYS125_RST | STS1_XHCI_RST;
- if (mtk->num_u3ports)
+ if (mtk->num_u3ports > u3_ports_disabed)
check_val |= STS1_U3_MAC_RST;
ret = readl_poll_timeout(mtk->ippc + IPPC_IP_PW_STS1, value,
if (ret)
debug("can't get vbus regulator %d!\n", ret);
+ /* optional properties to disable ports, ignore the error */
+ dev_read_u32(dev, "mediatek,u3p-dis-msk", &mtk->u3p_dis_msk);
+ dev_read_u32(dev, "mediatek,u2p-dis-msk", &mtk->u2p_dis_msk);
+ dev_info(dev, "ports disabled mask: u3p-0x%x, u2p-0x%x\n",
+ mtk->u3p_dis_msk, mtk->u2p_dis_msk);
+
return 0;
}
#include <usb.h>
#include <usb/xhci.h>
-static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
- struct xhci_hcor **ret_hcor)
+static int xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
+ struct xhci_hcor **ret_hcor)
{
struct xhci_hccr *hccr;
struct xhci_hcor *hcor;
hccr = (struct xhci_hccr *)dm_pci_map_bar(dev,
PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+ if (!hccr) {
+ printf("xhci-pci init cannot map PCI mem bar\n");
+ return -EIO;
+ }
+
hcor = (struct xhci_hcor *)((uintptr_t) hccr +
HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
dm_pci_read_config32(dev, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_MASTER;
dm_pci_write_config32(dev, PCI_COMMAND, cmd);
+ return 0;
}
static int xhci_pci_probe(struct udevice *dev)
{
struct xhci_hccr *hccr;
struct xhci_hcor *hcor;
+ int ret;
- xhci_pci_init(dev, &hccr, &hcor);
+ ret = xhci_pci_init(dev, &hccr, &hcor);
+ if (ret)
+ return ret;
return xhci_register(dev, hccr, hcor);
}
return -ETIMEDOUT;
}
- if ((uintptr_t)(le64_to_cpu(event->trans_event.buffer))
- != (uintptr_t)last_transfer_trb_addr) {
+ if ((uintptr_t)(le64_to_cpu(event->trans_event.buffer)) !=
+ (uintptr_t)virt_to_phys(last_transfer_trb_addr)) {
available_length -=
(int)EVENT_TRB_LEN(le32_to_cpu(event->trans_event.transfer_len));
xhci_acknowledge_event(ctrl);