T: git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git
F: arch/riscv/
F: cmd/riscv/
+F: drivers/timer/andes_plmt_timer.c
F: tools/prelink-riscv.c
RISC-V KENDRYTE
The Andes PLIC block holds memory-mapped claim and pending registers
associated with software interrupt.
-config ANDES_PLMT
- bool
- depends on RISCV_MMODE || SPL_RISCV_MMODE
- help
- The Andes PLMT block holds memory-mapped mtime register
- associated with timer tick.
-
config SYS_MALLOC_F_LEN
default 0x1000
ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
-obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
else
obj-$(CONFIG_SBI) += sbi.o
obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *
- * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
- * The PLMT block holds memory-mapped mtime register
- * associated with timer tick.
- */
-
-#include <common.h>
-#include <dm.h>
-#include <timer.h>
-#include <asm/io.h>
-#include <linux/err.h>
-
-/* mtime register */
-#define MTIME_REG(base) ((ulong)(base))
-
-static u64 andes_plmt_get_count(struct udevice *dev)
-{
- return readq((void __iomem *)MTIME_REG(dev->priv));
-}
-
-static const struct timer_ops andes_plmt_ops = {
- .get_count = andes_plmt_get_count,
-};
-
-static int andes_plmt_probe(struct udevice *dev)
-{
- dev->priv = dev_read_addr_ptr(dev);
- if (!dev->priv)
- return -EINVAL;
-
- return timer_timebase_fallback(dev);
-}
-
-static const struct udevice_id andes_plmt_ids[] = {
- { .compatible = "riscv,plmt0" },
- { }
-};
-
-U_BOOT_DRIVER(andes_plmt) = {
- .name = "andes_plmt",
- .id = UCLASS_TIMER,
- .of_match = andes_plmt_ids,
- .ops = &andes_plmt_ops,
- .probe = andes_plmt_probe,
- .flags = DM_FLAG_PRE_RELOC,
-};
Select this to enable a timer for Altera devices. Please find
details on the "Embedded Peripherals IP User Guide" of Altera.
+config ANDES_PLMT
+ bool
+ depends on RISCV_MMODE || SPL_RISCV_MMODE
+ help
+ The Andes PLMT block holds memory-mapped mtime register
+ associated with timer tick.
+
config ARC_TIMER
bool "ARC timer support"
depends on TIMER && ARC && CLK
obj-y += timer-uclass.o
obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
+obj-$(CONFIG_ANDES_PLMT) += andes_plmt_timer.o
obj-$(CONFIG_ARC_TIMER) += arc_timer.o
obj-$(CONFIG_AST_TIMER) += ast_timer.o
obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
+ * The PLMT block holds memory-mapped mtime register
+ * associated with timer tick.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <timer.h>
+#include <asm/io.h>
+#include <linux/err.h>
+
+/* mtime register */
+#define MTIME_REG(base) ((ulong)(base))
+
+static u64 andes_plmt_get_count(struct udevice *dev)
+{
+ return readq((void __iomem *)MTIME_REG(dev->priv));
+}
+
+static const struct timer_ops andes_plmt_ops = {
+ .get_count = andes_plmt_get_count,
+};
+
+static int andes_plmt_probe(struct udevice *dev)
+{
+ dev->priv = dev_read_addr_ptr(dev);
+ if (!dev->priv)
+ return -EINVAL;
+
+ return timer_timebase_fallback(dev);
+}
+
+static const struct udevice_id andes_plmt_ids[] = {
+ { .compatible = "riscv,plmt0" },
+ { }
+};
+
+U_BOOT_DRIVER(andes_plmt) = {
+ .name = "andes_plmt",
+ .id = UCLASS_TIMER,
+ .of_match = andes_plmt_ids,
+ .ops = &andes_plmt_ops,
+ .probe = andes_plmt_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};