]> Git Repo - J-u-boot.git/commitdiff
riscv: Move Andes PLMT driver to drivers/timer
authorSean Anderson <[email protected]>
Mon, 26 Oct 2020 01:46:56 +0000 (21:46 -0400)
committerAndes <[email protected]>
Mon, 26 Oct 2020 02:01:28 +0000 (10:01 +0800)
This is a regular timer driver, and should live with the other timer
drivers.

Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
MAINTAINERS
arch/riscv/Kconfig
arch/riscv/lib/Makefile
arch/riscv/lib/andes_plmt.c [deleted file]
drivers/timer/Kconfig
drivers/timer/Makefile
drivers/timer/andes_plmt_timer.c [new file with mode: 0644]

index fc4fad46eee56dab736bfb2922a1f779664e4f05..5d022352c433c89a875d1151a2f044adcd56f098 100644 (file)
@@ -938,6 +938,7 @@ S:  Maintained
 T:     git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git
 F:     arch/riscv/
 F:     cmd/riscv/
+F:     drivers/timer/andes_plmt_timer.c
 F:     tools/prelink-riscv.c
 
 RISC-V KENDRYTE
index 756047636d0fdcc5f5fe06eefcfdc204eaae014b..30b05408b1445d079fa69e4bb28a18c3d6037c06 100644 (file)
@@ -170,13 +170,6 @@ config ANDES_PLIC
          The Andes PLIC block holds memory-mapped claim and pending registers
          associated with software interrupt.
 
-config ANDES_PLMT
-       bool
-       depends on RISCV_MMODE || SPL_RISCV_MMODE
-       help
-         The Andes PLMT block holds memory-mapped mtime register
-         associated with timer tick.
-
 config SYS_MALLOC_F_LEN
        default 0x1000
 
index 10ac5b06d3c022e826ba088caf4f944b65d876ed..12c14f20198812a6e6b95687401a6b7c3d20f70d 100644 (file)
@@ -13,7 +13,6 @@ obj-y += cache.o
 ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
 obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
-obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
 else
 obj-$(CONFIG_SBI) += sbi.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
deleted file mode 100644 (file)
index cec8671..0000000
+++ /dev/null
@@ -1,50 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019, Rick Chen <[email protected]>
- * Copyright (C) 2020, Sean Anderson <[email protected]>
- *
- * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
- * The PLMT block holds memory-mapped mtime register
- * associated with timer tick.
- */
-
-#include <common.h>
-#include <dm.h>
-#include <timer.h>
-#include <asm/io.h>
-#include <linux/err.h>
-
-/* mtime register */
-#define MTIME_REG(base)                        ((ulong)(base))
-
-static u64 andes_plmt_get_count(struct udevice *dev)
-{
-       return readq((void __iomem *)MTIME_REG(dev->priv));
-}
-
-static const struct timer_ops andes_plmt_ops = {
-       .get_count = andes_plmt_get_count,
-};
-
-static int andes_plmt_probe(struct udevice *dev)
-{
-       dev->priv = dev_read_addr_ptr(dev);
-       if (!dev->priv)
-               return -EINVAL;
-
-       return timer_timebase_fallback(dev);
-}
-
-static const struct udevice_id andes_plmt_ids[] = {
-       { .compatible = "riscv,plmt0" },
-       { }
-};
-
-U_BOOT_DRIVER(andes_plmt) = {
-       .name           = "andes_plmt",
-       .id             = UCLASS_TIMER,
-       .of_match       = andes_plmt_ids,
-       .ops            = &andes_plmt_ops,
-       .probe          = andes_plmt_probe,
-       .flags          = DM_FLAG_PRE_RELOC,
-};
index f8fa4aa71f4ba7079877bb206b2e9d2b7ceb0cd0..6b8e4c9dc01c3973c315b1a9a40e4c05cb5ad7f8 100644 (file)
@@ -53,6 +53,13 @@ config ALTERA_TIMER
          Select this to enable a timer for Altera devices. Please find
          details on the "Embedded Peripherals IP User Guide" of Altera.
 
+config ANDES_PLMT
+       bool
+       depends on RISCV_MMODE || SPL_RISCV_MMODE
+       help
+         The Andes PLMT block holds memory-mapped mtime register
+         associated with timer tick.
+
 config ARC_TIMER
        bool "ARC timer support"
        depends on TIMER && ARC && CLK
index 3a4d74b996b4c5039e3ade823e400cb0d3379fad..dd4f9cc1d401cd1b46fbe9b1b56ccdfe50b0cf34 100644 (file)
@@ -5,6 +5,7 @@
 obj-y += timer-uclass.o
 obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
 obj-$(CONFIG_ALTERA_TIMER)     += altera_timer.o
+obj-$(CONFIG_ANDES_PLMT) += andes_plmt_timer.o
 obj-$(CONFIG_ARC_TIMER)        += arc_timer.o
 obj-$(CONFIG_AST_TIMER)        += ast_timer.o
 obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o
diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c
new file mode 100644 (file)
index 0000000..cec8671
--- /dev/null
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Rick Chen <[email protected]>
+ * Copyright (C) 2020, Sean Anderson <[email protected]>
+ *
+ * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
+ * The PLMT block holds memory-mapped mtime register
+ * associated with timer tick.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <timer.h>
+#include <asm/io.h>
+#include <linux/err.h>
+
+/* mtime register */
+#define MTIME_REG(base)                        ((ulong)(base))
+
+static u64 andes_plmt_get_count(struct udevice *dev)
+{
+       return readq((void __iomem *)MTIME_REG(dev->priv));
+}
+
+static const struct timer_ops andes_plmt_ops = {
+       .get_count = andes_plmt_get_count,
+};
+
+static int andes_plmt_probe(struct udevice *dev)
+{
+       dev->priv = dev_read_addr_ptr(dev);
+       if (!dev->priv)
+               return -EINVAL;
+
+       return timer_timebase_fallback(dev);
+}
+
+static const struct udevice_id andes_plmt_ids[] = {
+       { .compatible = "riscv,plmt0" },
+       { }
+};
+
+U_BOOT_DRIVER(andes_plmt) = {
+       .name           = "andes_plmt",
+       .id             = UCLASS_TIMER,
+       .of_match       = andes_plmt_ids,
+       .ops            = &andes_plmt_ops,
+       .probe          = andes_plmt_probe,
+       .flags          = DM_FLAG_PRE_RELOC,
+};
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