#endif
#ifdef CONFIG_SYS_FSL_HAS_RGMII
/* some dpmacs in armv8a based freescale layerscape SOCs can be
- * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
+ * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
* EC*_PMUX(rgmii) bits in RCW.
* e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
* serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
- Hardware buffer management for buffer allocation and de-allocation (BMan)
- Cryptography acceleration (SEC)
- Ethernet interfaces by FMan
- - Up to 1 x XFI supporting 10G interface
+ - Up to 1 x 10GBase-R supporting 10G interface
- Up to 1 x QSGMII
- Up to 4 x SGMII supporting 1000Mbps
- Up to 2 x SGMII supporting 2500Mbps
- Two PLLs per four-lane SerDes
- Support for 10G operation
- Ethernet interfaces by FMan
- - Up to 2 x XFI supporting 10G interface (MAC 9, 10)
+ - Up to 2 x 10GBase-R supporting 10G interface (MAC 9, 10)
- Up to 1 x QSGMII (MAC 5, 6, 10, 1)
- Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
- Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
Single WRIOP tile supporting 130Gbps using 18 MACs
Support for 10G-SXGMII (aka USXGMII).
Support for SGMII (and 1000Base-KX)
- Support for XFI (and 10GBase-KR)
+ Support for 10GBase-R (and 10GBase-KR)
Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G).
Support for XLAUI (and 40GBase-KR4) for 40G.
Support for two RGMII parallel interfaces.
Ethernet interfaces
Support for 10G-SXGMII (aka USXGMII).
Support for SGMII (and 1000Base-KX)
- Support for XFI (and 10GBase-KR)
+ Support for 10GBase-R (and 10GBase-KR)
Support for CAUI2 (50G) and 25G-AUI(25G).
Support for XLAUI (and 40GBase-KR4) for 40G.
Support for two RGMII parallel interfaces.
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
/*
- * LS1044A/1048A support only one XFI port
+ * LS1044A/1048A support only one 10GBase-R port
* Disable MAC1 for LS1044A/1048A
*/
if (serdes == FSL_SRDS_1 && lane == 2) {
/*
* NXP LS1028A-QDS device tree fragment for RCW 1xxx
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
/*
* NXP LS1028A-QDS device tree fragment for RCW 6xxx
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
&enetc0 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
&mscc_felix_port0 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
};
&mscc_felix_port1 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
};
&mscc_felix_port2 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};
/*
* NXP LS1028A-QDS device tree fragment for RCW 7xx7
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
&slot1 {
&mscc_felix_port0 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};
/*
* NXP LS1028A-QDS device tree fragment for RCW 8xxx
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
/*
* NXP LS1028A-QDS device tree fragment for RCW 9999
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
/*
* NXP LS1028A-QDS device tree fragment for RCW 9999
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*
*/
/*
* NXP LS1028A-QDS device tree fragment for RCW x3xx
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
/*
* NXP LS1028A-QDS device tree fragment for RCW x5xx
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
&slot2 {
&mscc_felix_port1 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
};
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
&slot3 {
&mscc_felix_port2 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
};
&dpmac1 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac4 {
&dpmac1 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac1 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac3 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac4 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac5 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac6 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac7 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac8 {
status = "okay";
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac1 {
status = "okay";
phy-handle = <&mdio1_phy1>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
phy-handle = <&mdio1_phy2>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac3 {
status = "okay";
phy-handle = <&mdio1_phy3>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac4 {
status = "okay";
phy-handle = <&mdio1_phy4>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac5 {
status = "okay";
phy-handle = <&mdio2_phy1>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac6 {
status = "okay";
phy-handle = <&mdio2_phy2>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac7 {
status = "okay";
phy-handle = <&mdio2_phy3>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&dpmac8 {
status = "okay";
phy-handle = <&mdio2_phy4>;
- phy-connection-type = "xfi";
+ phy-connection-type = "10gbase-r";
};
&emdio1 {
/*
* Device tree fragment for RCW SCH-24801 card
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
/*
* Device tree fragment for RCW SCH-28021 card
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
/*
* Device tree fragment for RCW SCH-30841 card
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
* SCH-30841 is a 4 port add-on card used with various FSL QDS boards.
* It integrates a AQR412C quad PHY which supports 4 interfaces either muxed
* together on a single lane or mapped 1:1 to serdes lanes.
- * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI.
+ * It supports several protocols - SGMII, 2500base-X, USXGMII, M-USX, 10GBase-R.
* PHY addresses are 0x00 - 0x03.
* On the card the first port is the bottom port (closest to PEX connector).
*/
/*
* Device tree fragment for RCW SCH-30842 card
*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
/*
* SCH-30842 is a single port add-on card used with various FSL QDS boards.
* It integrates a AQR112 PHY, which supports several protocols - SGMII,
- * SGMII-2500, USXGMII, XFI.
+ * 2500base-x, USXGMII, 10GBase-R.
* PHY address is 0x02.
*/
phy@02 {
// SPDX-License-Identifier: GPL-2.0
-/* Copyright 2016-2018 NXP Semiconductors
+/* Copyright 2016-2018 NXP
*/
case CVMX_QLM_MODE_XFI:
case CVMX_QLM_MODE_RGMII_XFI:
case CVMX_QLM_MODE_RGMII_XFI_1X1:
- type_str = "xfi";
+ type_str = "10gbase-r";
break;
case CVMX_QLM_MODE_10G_KR:
case CVMX_QLM_MODE_RGMII_10G_KR:
if (pmd_control.s.train_en)
type_str = "10G_KR";
else
- type_str = "xfi";
+ type_str = "10gbase-r";
break;
case 4:
if (pmd_control.s.train_en)
speed[qlm] = 103125;
}
printf("QLM %d: XLAUI\n", qlm);
- } else if (!strncmp(mode_str, "xfi", 3)) {
+ } else if (!strncmp(mode_str, "10gbase-r", 3)) {
bool rgmii = false;
speed[qlm] = 103125;
bus = miiphy_get_dev_by_name(mdio_name);
pfe_set_mdio(1, bus);
pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR,
- PHY_INTERFACE_MODE_SGMII_2500);
+ PHY_INTERFACE_MODE_2500BASEX);
data8 = QIXIS_READ(brdcfg[12]);
data8 |= 0x20;
pfe_set_mdio(0, bus);
pfe_set_phy_address_mode(0,
CONFIG_PFE_SGMII_2500_PHY1_ADDR,
- PHY_INTERFACE_MODE_SGMII_2500);
+ PHY_INTERFACE_MODE_2500BASEX);
}
break;
ETH_1_2_5G_MDIO_MUX);
prop_val.phy_mask = cpu_to_fdt32(
ETH_2_5G_MDIO_PHY_MASK);
- prop_val.phy_mode = "sgmii-2500";
+ prop_val.phy_mode = "2500base-x";
pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
ETH_1_MDIO);
} else {
ETH_2_2_5G_MDIO_MUX);
prop_val.phy_mask = cpu_to_fdt32(
ETH_2_5G_MDIO_PHY_MASK);
- prop_val.phy_mode = "sgmii-2500";
+ prop_val.phy_mode = "2500base-x";
pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
ETH_2_MDIO);
}
#define ETH_1_2_5G_PHY_ID 0x1
#define ETH_1_2_5G_MDIO_MUX 0x2
#define ETH_2_5G_MDIO_PHY_MASK 0xFFFFFFF9
-#define ETH_2_5G_PHY_MODE "sgmii-2500"
+#define ETH_2_5G_PHY_MODE "2500base-x"
#define ETH_2_2_5G_BUS_ID 0x1
#define ETH_2_2_5G_PHY_ID 0x2
#define ETH_2_2_5G_MDIO_MUX 0x3
/* MAC1 */
pfe_set_phy_address_mode(priv->gemac_port,
CONFIG_PFE_EMAC1_PHY_ADDR,
- PHY_INTERFACE_MODE_SGMII_2500);
+ PHY_INTERFACE_MODE_2500BASEX);
} else {
/* MAC2 */
pfe_set_phy_address_mode(priv->gemac_port,
CONFIG_PFE_EMAC2_PHY_ADDR,
- PHY_INTERFACE_MODE_SGMII_2500);
+ PHY_INTERFACE_MODE_2500BASEX);
}
break;
default:
// SPDX-License-Identifier: GPL-2.0
-/* Copyright 2016-2019 NXP Semiconductors
+/* Copyright 2016-2019 NXP
*/
#include <common.h>
#include <clock_legacy.h>
- SGMII, SGMII 2.5
- QSGMII
- SATA 3.0
- - XFI
+ - 10GBase-R
- DDR Controller
- 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s
-IFC/Local Bus
"sgmii-riser-s4-p1");
}
} else if (fm_info_get_enet_if(port) ==
- PHY_INTERFACE_MODE_SGMII_2500) {
+ PHY_INTERFACE_MODE_2500BASEX) {
/* 2.5G SGMII interface */
f_link.phy_id = cpu_to_fdt32(port);
f_link.duplex = cpu_to_fdt32(1);
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
fdt_setprop_string(fdt, offset, "phy-connection-type",
- "sgmii-2500");
+ "2500base-x");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
switch (mdio_mux[port]) {
case EMI1_SLOT1:
"qsgmii");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
port == FM1_10GEC1) {
- /* XFI interface */
+ /* 10GBase-R interface */
f_link.phy_id = cpu_to_fdt32(port);
f_link.duplex = cpu_to_fdt32(1);
f_link.link_speed = cpu_to_fdt32(10000);
f_link.pause = 0;
f_link.asym_pause = 0;
- /* no PHY for XFI */
+ /* no PHY for 10GBase-R */
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_2500BASEX:
case PHY_INTERFACE_MODE_QSGMII:
if (interface == PHY_INTERFACE_MODE_SGMII) {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC1 + idx);
- } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
+ } else if (interface == PHY_INTERFACE_MODE_2500BASEX) {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_2500_FM1_DTSEC1 + idx);
} else {
- PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and
standard PCIe card
- QSGMII with x4 RJ45 connector
- - XFI with x1 RJ45 connector
+ - 10GBase-R with x1 RJ45 connector
- DDR Controller
- 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
-IFC/Local Bus
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
fm_info_set_mdio(i, dev);
- /* XFI on lane A, MAC 9 */
+ /* 10GBase-R on lane A, MAC 9 */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(FM1_10GEC1, dev);
- SGMII, SGMII 2.5
- QSGMII
- SATA 3.0
- - XFI
+ - 10GBase-R
- DDR Controller
- 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
-IFC/Local Bus
default:
break;
}
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) {
/* 2.5G SGMII interface */
f_link.phy_id = cpu_to_fdt32(port);
f_link.duplex = cpu_to_fdt32(1);
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
fdt_setprop_string(fdt, offset, "phy-connection-type",
- "sgmii-2500");
+ "2500base-x");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
switch (port) {
case FM1_DTSEC1:
/* Backplane KR mode: skip fixups */
printf("Interface %d in backplane KR mode\n", port);
} else {
- /* XFI interface */
+ /* 10GBase-R interface */
f_link.phy_id = cpu_to_fdt32(port);
f_link.duplex = cpu_to_fdt32(1);
f_link.link_speed = cpu_to_fdt32(10000);
f_link.pause = 0;
f_link.asym_pause = 0;
- /* no PHY for XFI */
+ /* no PHY for 10GBase-R */
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link,
sizeof(f_link));
LS1046ARDB board Overview
-----------------------
- SERDES1 Connections, 4 lanes supporting:
- - Lane0: XFI with x1 RJ45 connector
- - Lane1: XFI Cage
+ - Lane0: 10GBase-R with x1 RJ45 connector
+ - Lane1: 10GBase-R Cage
- Lane2: SGMII.5
- Lane3: SGMII.6
- SERDES2 Connections, 4 lanes supporting:
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
fm_info_set_mdio(i, dev);
- /* XFI on lane A, MAC 9 */
+ /* 10GBase-R on lane A, MAC 9 */
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(FM1_10GEC1, dev);
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
- SATA 3.0
- - XFI
+ - 10GBase-R
- QSGMII
- DDR Controller
- One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
- SATA 3.0
- - 2 XFI
+ - 2 10GBase-R
- QSGMII, SGMII with help for Riser card
- 2 RGMII
- 5 slot for Riser card or PCIe NIC
switch (srds_s1) {
case 0x1D:
/*
- * XFI does not need a PHY to work, but to avoid U-boot use
- * default PHY address which is zero to a MAC when it found
- * a MAC has no PHY address, we give a PHY address to XFI
+ * 10GBase-R does not need a PHY to work, but to avoid U-boot
+ * use default PHY address which is zero to a MAC when it found
+ * a MAC has no PHY address, we give a PHY address to 10GBase-R
* MAC error.
*/
wriop_set_phy_address(WRIOP1_DPMAC1, 0, 0x0a);
- QSGMII
- SATA 3.0
- XAUI
- - XFI
+ - 10GBase-R
- DDR Controller
- Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
chip-selects and two DIMM connectors. Support is up to 2133MT/s.
case 0x4B:
case 0x4C:
/*
- * XFI does not need a PHY to work, but to avoid U-Boot use
- * default PHY address which is zero to a MAC when it found
- * a MAC has no PHY address, we give a PHY address to XFI
- * MAC, and should not use a real XAUI PHY address, since
- * MDIO can access it successfully, and then MDIO thinks
- * the XAUI card is used for the XFI MAC, which will cause
- * error.
+ * 10GBase-R does not need a PHY to work, but to avoid U-Boot
+ * use default PHY address which is zero to a MAC when it found
+ * a MAC has no PHY address, we give a PHY address to 10GBase-R
+ * MAC, and should not use a real XAUI PHY address, since MDIO
+ * can access it successfully, and then MDIO thinks the XAUI
+ * card is used for the 10GBase-R MAC, which will cause error.
*/
wriop_set_phy_address(i, 0, i + 4);
ls2080a_qds_enable_SFP_TX(SFP_TX);
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
- SATA 3.0
- - XFI
+ - 10GBase-R
- DDR Controller
- Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
chip-selects and two DIMM connectors. Support is up to 2133MT/s.
- One QSGMII interface
- Four SGMII interface supporting 1000 Mbps
- Three SGMII interfaces supporting up to 2500 Mbps
- - 10GbE XFI or 10Base-KR interface
+ - 10GBase-R or 10Base-KR interface
- Additional peripheral interfaces
- Two USB 2.0 controllers with integrated PHY
- SD/eSDHC/eMMC
/* set the on-board RGMII2 PHY */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
- /* set 10G XFI with Aquantia AQR105 PHY */
+ /* set 10GBase-R with Aquantia AQR105 PHY */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
break;
#endif
#endif
fm_info_set_mdio(i, dev);
break;
- case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_2500BASEX:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
enum fm_port port, int offset)
{
#if defined(CONFIG_TARGET_T1024RDB)
- if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
+ if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) ||
(fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
(port == FM1_DTSEC3)) {
fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
fdt_setprop_string(fdt, offset, "phy-connection-type",
- "sgmii-2500");
+ "2500base-x");
fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
}
#endif
- Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
Ethernet interfaces:
- Two 1Gbps RGMII on-board ports
- - Four 10Gbps XFI on-board cages
+ - Four 10GBase-R on-board cages
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes:
- 16 lanes up to 10.3125GHz
- - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
+ - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, 10GBase-R and XAUI
IFC:
- 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
eSPI:
- QIXIS-II FPGA system controll
Debug Features:
- Support Legacy, COP/JTAG, Aurora, Event and EVT
-XFI:
- - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
+10GBase-R:
+ - 10GBase-R is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
a on-board SFP+ cages, which to house optical module (fiber cable) or
direct attach cable(copper), the copper cable is used to emulate
10GBASE-KR scenario.
- So, for XFI usage, there are two scenarios, one will use fiber cable,
+ So, for 10GBase-R usage, there are two scenarios, one will use fiber cable,
another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
- introduced to indicate a XFI port will use copper cable, and U-Boot
+ introduced to indicate a 10GBase-R port will use copper cable, and U-Boot
will fixup the dtb accordingly.
It's used as: fsl_10gkr_copper:<10g_mac_name>
The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they
"fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
will be used by default.
for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in
- hwconfig, then both four XFI ports will use copper cable.
+ hwconfig, then both four 10GBase-R ports will use copper cable.
set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
- XFI ports will use copper cable, the other two XFI ports will use fiber
- cable.
+ 10GBase-R ports will use copper cable, the other two 10GBase-R ports will use
+ fiber cable.
1000BASE-KX(1G-KX):
- T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
switch (srds_s1) {
- case 0x66: /* XFI interface */
+ case 0x66: /* 10GBase-R interface */
case 0x6b:
case 0x6c:
case 0x6d:
case 0x71:
/*
- * if the 10G is XFI, check hwconfig to see what is the
- * media type, there are two types, fiber or copper,
- * fix the dtb accordingly.
- */
+ * Check hwconfig to see what is the media type, there
+ * are two types, fiber or copper, fix the dtb
+ * accordingly.
+ */
switch (port) {
case FM1_10GEC1:
if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
printf("Interface %d in backplane KR mode\n",
port);
} else {
- /* fixed-link for XFI fiber cable */
+ /* fixed-link for 10GBase-R fiber cable */
f_link.phy_id = port;
f_link.duplex = 1;
f_link.link_speed = 10000;
case 0x66:
case 0x67:
/*
- * XFI does not need a PHY to work, but to avoid U-Boot use
- * default PHY address which is zero to a MAC when it found
- * a MAC has no PHY address, we give a PHY address to XFI
+ * 10GBase-R does not need a PHY to work, but to avoid U-Boot
+ * use default PHY address which is zero to a MAC when it found
+ * a MAC has no PHY address, we give a PHY address to 10GBase-R
* MAC, and should not use a real XAUI PHY address, since
* MDIO can access it successfully, and then MDIO thinks
- * the XAUI card is used for the XFI MAC, which will cause
+ * the XAUI card is used for the 10GBase-R MAC, which will cause
* error.
*/
fm_info_set_phy_address(FM1_10GEC1, 4);
(srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
(srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
(srds_s1 == 0x71)) {
- /* As XFI is in cage intead of a slot, so
+ /* As 10GBase-R is in cage intead of a slot, so
* ensure doesn't disable the corresponding port
*/
break;
break;
case 0x66:
case 0x67:
- /* SD1(A:D) => XFI cage
+ /* SD1(A:D) => 10GBase-R cage
* SD1(E:H) => SLOT1 PCIe4
*/
QIXIS_WRITE(brdcfg[12], 0xfe);
break;
case 0x6a:
case 0x6b:
- /* SD1(A:D) => XFI cage
+ /* SD1(A:D) => 10GBase-R cage
* SD1(E) => SLOT1 PCIe4
* SD1(F:H) => SLOT2 SGMII
*/
break;
case 0x6c:
case 0x6d:
- /* SD1(A:B) => XFI cage
+ /* SD1(A:B) => 10GBase-R cage
* SD1(C:D) => SLOT3 SGMII
* SD1(E:H) => SLOT1 PCIe4
*/
QIXIS_WRITE(brdcfg[12], 0xda);
break;
case 0x6e:
- /* SD1(A:B) => SFP Module, XFI
+ /* SD1(A:B) => SFP Module, 10GBase-R
* SD1(C:D) => SLOT3 SGMII
* SD1(E:F) => SLOT1 PCIe4 x2
* SD1(G:H) => SLOT2 SGMII
T2080PCIe-RDB board Overview
----------------------------
- SERDES Configuration
- - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
+ - SerDes-1 Lane A-B: to two 10GBase-R fiber (MAC9 & MAC10)
- SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
- SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
- SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
- SerDes-2 Lane G-H: to SATA1 & SATA2
- Ethernet
- Two on-board 10M/100M/1G RGMII ethernet ports
- - Two on-board 10Gbps XFI fiber ports
+ - Two on-board 10GBase-R fiber ports
- Two on-board 10Gbps Base-T copper ports
- DDR Memory
- Supports 72bit 4GB DDR3-LP SODIMM
#if (CONFIG_SYS_NUM_FMAN == 2)
if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
- /* SGMII && XFI */
+ /* SGMII && 10GBase-R */
fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name,
- name,
- MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, name, MDIO_NAME_LEN);
mdiodev->read = bb_miiphy_read;
mdiodev->write = bb_miiphy_write;
* "2500base-x",
* "rxaui"
* "xaui"
- * "10gbase-kr" (10GBASE-KR, XFI, SFI)
+ * "10gbase-r" (This is the IEEE 802.3 Clause 49 defined 10GBASE-R protocol
+ used with various different mediums. Please refer to the IEEE standard for
+ a definition of this. Note: 10GBASE-R is just one protocol that can be used
+ with XFI and SFI. XFI and SFI permit multiple protocols over a single
+ SERDES lane, and also defines the electrical characteristics of the signals
+ with a host compliance board plugged into the host XFP/SFP connector.
+ Therefore, XFI and SFI are not PHY interface types in their own right.)
+ * "10gbase-kr" (This is the IEEE 802.3 Clause 49 defined 10GBASE-R with
+ Clause 73 autonegotiation. Please refer to the IEEE standard for further
+ information. Note: due to legacy usage, some 10GBASE-R usage incorrectly
+ makes use of this definition).
- phy-connection-type: the same as "phy-mode" property but described in the
Devicetree Specification;
- phy-handle: phandle, specifies a reference to a node representing a PHY
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = smi_reg_read;
mdiodev->write = smi_reg_write;
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = eth->miiphy_read;
mdiodev->write = eth->miiphy_write;
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
#include <asm/eth.h>
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, priv->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, priv->name, MDIO_NAME_LEN);
mdiodev->read = eepro100_miiphy_read;
mdiodev->write = eepro100_miiphy_write;
mdiodev->priv = priv;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, "ep93xx_eth0", MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, "ep93xx_eth0", MDIO_NAME_LEN);
mdiodev->read = ep93xx_miiphy_read;
mdiodev->write = ep93xx_miiphy_write;
env_get_f("hwconfig", buffer, sizeof(buffer));
buf = buffer;
- /* check if XFI interface enable in hwconfig for 10g */
+ /* check if 10GBase-R interface enable in hwconfig for 10g */
if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
"sfp_amc", "sfp", buf)) {
if ((port == FM1_10GEC1 ||
u32 value;
struct mii_dev bus;
bool sgmii_2500 = (priv->enet_if ==
- PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
+ PHY_INTERFACE_MODE_2500BASEX) ? true : false;
int i = 0, j;
#ifndef CONFIG_DM_ETH
if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
- fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
+ fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX)
dtsec_configure_serdes(fm_eth);
}
/* For some reason we need to set SPEED_100 */
if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
- (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
+ (fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX) ||
(fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
mac->set_if_mode)
mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
if (fm_eth->type == FM_ETH_10G_E)
supported = PHY_10G_FEATURES;
- if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
+ if (fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX)
supported |= SUPPORTED_2500baseX_Full;
#endif
if (fm_eth->num != 0)
break;
case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_2500BASEX:
fm_eth->pcs_mdio = fm_get_internal_mdio(dev);
break;
default:
case FM1_DTSEC2:
if ((port == FM1_DTSEC2) &&
is_serdes_configured(SGMII_2500_FM1_DTSEC2))
- return PHY_INTERFACE_MODE_SGMII_2500;
+ return PHY_INTERFACE_MODE_2500BASEX;
case FM1_DTSEC5:
case FM1_DTSEC6:
case FM1_DTSEC9:
return PHY_INTERFACE_MODE_SGMII;
else if ((port == FM1_DTSEC9) &&
is_serdes_configured(SGMII_2500_FM1_DTSEC9))
- return PHY_INTERFACE_MODE_SGMII_2500;
+ return PHY_INTERFACE_MODE_2500BASEX;
break;
default:
break;
case FM1_DTSEC10:
if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 +
port - FM1_DTSEC5))
- return PHY_INTERFACE_MODE_SGMII_2500;
+ return PHY_INTERFACE_MODE_2500BASEX;
break;
default:
break;
if_mode |= (IF_MODE_GMII | IF_MODE_RM);
break;
case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_2500BASEX:
case PHY_INTERFACE_MODE_QSGMII:
if_mode &= ~IF_MODE_MASK;
if_mode |= (IF_MODE_GMII);
break;
- case PHY_INTERFACE_MODE_XFI:
+ case PHY_INTERFACE_MODE_10GBASER:
case PHY_INTERFACE_MODE_XGMII:
if_mode &= ~IF_MODE_MASK;
if_mode |= IF_MODE_XGMII;
break;
}
/* Enable automatic speed selection for Non-XGMII */
- if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_XFI)
+ if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_10GBASER)
if_mode |= IF_MODE_EN_AUTO;
if (type == PHY_INTERFACE_MODE_RGMII ||
return PHY_INTERFACE_MODE_SGMII;
else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1
+ port - FM1_DTSEC1))
- return PHY_INTERFACE_MODE_SGMII_2500;
+ return PHY_INTERFACE_MODE_2500BASEX;
break;
default:
break;
if (!enetc_has_imdio(dev))
return 0;
- if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500)
+ if (priv->if_type == PHY_INTERFACE_MODE_2500BASEX)
is2500 = true;
/*
case PHY_INTERFACE_MODE_RGMII_TXID:
enetc_init_rgmii(dev, phydev);
break;
- case PHY_INTERFACE_MODE_XGMII:
case PHY_INTERFACE_MODE_USXGMII:
- case PHY_INTERFACE_MODE_XFI:
+ case PHY_INTERFACE_MODE_10GBASER:
/* set ifmode to (US)XGMII */
if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
if_mode &= ~ENETC_PM_IF_IFMODE_MASK;
priv->imdio.read = enetc_mdio_read;
priv->imdio.write = enetc_mdio_write;
priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE;
- strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
+ strlcpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
if (!miiphy_get_dev_by_name(priv->imdio.name))
mdio_register(&priv->imdio);
}
switch (priv->if_type) {
case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_2500BASEX:
enetc_init_sgmii(dev);
break;
- case PHY_INTERFACE_MODE_XGMII:
case PHY_INTERFACE_MODE_USXGMII:
- case PHY_INTERFACE_MODE_XFI:
+ case PHY_INTERFACE_MODE_10GBASER:
enetc_init_sxgmii(dev);
break;
};
info->bus = mdio_alloc();
if (!info->bus)
return -ENOMEM;
- strncpy(info->bus->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(info->bus->name, dev->name, MDIO_NAME_LEN);
info->bus->read = mcffec_miiphy_read;
info->bus->write = mcffec_miiphy_write;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = ftmac110_mdio_read;
mdiodev->write = ftmac110_mdio_write;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = mii_reg_read;
mdiodev->write = mii_reg_write;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
mdiodev->read = macb_miiphy_read;
mdiodev->write = macb_miiphy_write;
macb->bus = mdio_alloc();
if (!macb->bus)
return -ENOMEM;
- strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
macb->bus->read = macb_miiphy_read;
macb->bus->write = macb_miiphy_write;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = fec8xx_miiphy_read;
mdiodev->write = fec8xx_miiphy_write;
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Felix (VSC9959) Ethernet switch driver
- * Copyright 2018-2021 NXP Semiconductors
+ * Copyright 2018-2021 NXP
*/
/*
bool autoneg = true;
if (phy->phy_id == PHY_FIXED_ID ||
- phy->interface == PHY_INTERFACE_MODE_SGMII_2500)
+ phy->interface == PHY_INTERFACE_MODE_2500BASEX)
autoneg = false;
switch (phy->interface) {
case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_2500BASEX:
case PHY_INTERFACE_MODE_QSGMII:
felix_init_sgmii(imdio, port, autoneg);
break;
- case PHY_INTERFACE_MODE_XGMII:
- case PHY_INTERFACE_MODE_XFI:
+ case PHY_INTERFACE_MODE_10GBASER:
case PHY_INTERFACE_MODE_USXGMII:
if (felix_init_sxgmii(imdio, port))
dev_err(dev, "PCS reset timeout on port %d\n", port);
}
}
-void felix_init(struct udevice *dev)
+static void felix_init(struct udevice *dev)
{
struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
struct felix_priv *priv = dev_get_priv(dev);
priv->imdio.read = felix_mdio_read;
priv->imdio.write = felix_mdio_write;
priv->imdio.priv = priv->imdio_base + FELIX_PM_IMDIO_BASE;
- strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
+ strlcpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
/* set up CPU port */
out_le32(base + FELIX_QSYS_SYSTEM_EXT_CPU_CFG,
static int felix_probe(struct udevice *dev)
{
struct felix_priv *priv = dev_get_priv(dev);
+ int err;
if (ofnode_valid(dev_ofnode(dev)) &&
!ofnode_is_available(dev_ofnode(dev))) {
struct mii_dev *mii_bus;
mii_bus = mdio_alloc();
+ if (!mii_bus)
+ return -ENOMEM;
+
mii_bus->read = felix_mdio_read;
mii_bus->write = felix_mdio_write;
mii_bus->priv = priv->imdio_base + FELIX_PM_IMDIO_BASE;
- strncpy(mii_bus->name, dev->name, MDIO_NAME_LEN);
- mdio_register(mii_bus);
+ strlcpy(mii_bus->name, dev->name, MDIO_NAME_LEN);
+ err = mdio_register(mii_bus);
+ if (err) {
+ mdio_free(mii_bus);
+ return err;
+ }
}
dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
return 0;
}
+static int felix_port_probe(struct udevice *dev, int port,
+ struct phy_device *phy)
+{
+ int supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
+ struct felix_priv *priv = dev_get_priv(dev);
+
+ phy->supported &= supported;
+ phy->advertising &= supported;
+
+ felix_start_pcs(dev, port, phy, &priv->imdio);
+
+ return phy_config(phy);
+}
+
static int felix_port_enable(struct udevice *dev, int port,
struct phy_device *phy)
{
- int supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
struct felix_priv *priv = dev_get_priv(dev);
void *base = priv->regs_base;
FELIX_QSYS_SYSTEM_SW_PORT_LOSSY |
FELIX_QSYS_SYSTEM_SW_PORT_SCH(1));
- felix_start_pcs(dev, port, phy, &priv->imdio);
-
- phy->supported &= supported;
- phy->advertising &= supported;
- phy_config(phy);
-
- phy_startup(phy);
-
- return 0;
+ return phy_startup(phy);
}
static void felix_port_disable(struct udevice *dev, int pidx,
}
static const struct dsa_ops felix_dsa_ops = {
+ .port_probe = felix_port_probe,
.port_enable = felix_port_enable,
.port_disable = felix_port_disable,
.xmit = felix_xmit,
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = smi_reg_read;
mdiodev->write = smi_reg_write;
int value, sgmii_2500 = 0;
struct gemac_s *gem = priv->gem;
- if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500)
+ if (gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX)
sgmii_2500 = 1;
/* Configure SGMII PCS */
if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII ||
- gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) {
+ gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
out_be32(&scfg->mdioselcr, 0x00000000);
pfe_configure_serdes(priv);
}
} aquantia_syscfg[PHY_INTERFACE_MODE_COUNT] = {
[PHY_INTERFACE_MODE_SGMII] = {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
AQUANTIA_VND1_GSTART_RATE_1G},
- [PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
+ [PHY_INTERFACE_MODE_2500BASEX] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
AQUANTIA_VND1_GSTART_RATE_2_5G},
- [PHY_INTERFACE_MODE_XFI] = {0x100, AQUANTIA_VND1_GSYSCFG_10G,
+ [PHY_INTERFACE_MODE_10GBASER] = {0x100, AQUANTIA_VND1_GSYSCFG_10G,
AQUANTIA_VND1_GSTART_RATE_10G},
[PHY_INTERFACE_MODE_USXGMII] = {0x080, AQUANTIA_VND1_GSYSCFG_10G,
AQUANTIA_VND1_GSTART_RATE_10G},
return ret;
}
/*
- * for backward compatibility convert XGMII into either XFI or USX based
- * on FW config
+ * for backward compatibility convert XGMII into either 10GBase-R or
+ * USXGMII based on FW config
*/
if (interface == PHY_INTERFACE_MODE_XGMII) {
- debug("use XFI or USXGMII SI protos, XGMII is not valid\n");
+ debug("use 10GBase-R or USXGMII SI protos, XGMII is not valid\n");
reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
AQUANTIA_SYSTEM_INTERFACE_SR);
if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII)
interface = PHY_INTERFACE_MODE_USXGMII;
else
- interface = PHY_INTERFACE_MODE_XFI;
+ interface = PHY_INTERFACE_MODE_10GBASER;
}
/*
case PHY_INTERFACE_MODE_USXGMII:
usx_an = 1;
/* FALLTHROUGH */
- case PHY_INTERFACE_MODE_XFI:
+ case PHY_INTERFACE_MODE_10GBASER:
/* 10GBASE-T mode */
phydev->advertising = SUPPORTED_10000baseT_Full;
phydev->supported = phydev->advertising;
phydev->dev->name);
} else {
reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA;
- debug("%s: system interface XFI\n",
+ debug("%s: system interface 10GBase-R\n",
phydev->dev->name);
}
phy_write(phydev, MDIO_MMD_PHYXS,
AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1);
break;
- case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_2500BASEX:
/* 2.5GBASE-T mode */
phydev->advertising = SUPPORTED_1000baseT_Full;
phydev->supported = phydev->advertising;
.shutdown = genphy_shutdown,
};
-int genphy_init(void)
+static int genphy_init(void)
{
return phy_register(&genphy_driver);
}
mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = bb_miiphy_read;
mdiodev->write = bb_miiphy_write;
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN);
mdiodev->read = smc911x_miiphy_read;
mdiodev->write = smc911x_miiphy_write;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN);
mdiodev->read = davinci_mii_phy_read;
mdiodev->write = davinci_mii_phy_write;
return priv->phydev->link ? 0 : -1;
}
-static phy_interface_t tsec_get_interface(struct tsec_private *priv)
+static phy_interface_t __maybe_unused tsec_get_interface(struct tsec_private *priv)
{
struct tsec __iomem *regs = priv->regs;
u32 ecntrl;
/* Assign a Physical address to the TBI */
out_be32(®s->tbipa, priv->tbiaddr);
- priv->interface = tsec_get_interface(priv);
-
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
tsec_configure_serdes(priv);
priv->tbiaddr = tbiaddr;
phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
+ if (!phy_mode)
+ phy_mode = dev_read_prop(dev, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- printf("Invalid PHY interface '%s'\n", phy_mode);
- return -EINVAL;
- }
+ if (pdata->phy_interface == -1)
+ pdata->phy_interface = tsec_get_interface(priv);
+
priv->interface = pdata->phy_interface;
/* Check for speed limit, default is 1000Mbps */
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = uec_miiphy_read;
mdiodev->write = uec_miiphy_write;
/* SPDX-License-Identifier: GPL-2.0
- * Copyright 2016-2019 NXP Semiconductors
+ * Copyright 2016-2019 NXP
*/
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2019-2021 NXP Semiconductors
+ * Copyright 2019-2021 NXP
*/
#ifndef __DSA_H__
/**
* struct dsa_ops - DSA operations
*
- * @port_enable: Initialize a switch port for I/O.
+ * @port_probe: Initialize a switch port.
+ * @port_enable: Enable I/O for a port.
* @port_disable: Disable I/O for a port.
* @xmit: Insert the DSA tag for transmission.
* DSA drivers receive a copy of the packet with headroom and
* master including any additional headers.
*/
struct dsa_ops {
+ int (*port_probe)(struct udevice *dev, int port,
+ struct phy_device *phy);
int (*port_enable)(struct udevice *dev, int port,
struct phy_device *phy);
void (*port_disable)(struct udevice *dev, int port,
{
return interface == PHY_INTERFACE_MODE_XGMII ||
interface == PHY_INTERFACE_MODE_USXGMII ||
- interface == PHY_INTERFACE_MODE_XFI;
+ interface == PHY_INTERFACE_MODE_10GBASER;
}
#endif
PHY_INTERFACE_MODE_CAUI2,
PHY_INTERFACE_MODE_CAUI4,
PHY_INTERFACE_MODE_NCSI,
- PHY_INTERFACE_MODE_XFI,
+ PHY_INTERFACE_MODE_10GBASER,
PHY_INTERFACE_MODE_USXGMII,
PHY_INTERFACE_MODE_NONE, /* Must be last */
[PHY_INTERFACE_MODE_CAUI2] = "caui2",
[PHY_INTERFACE_MODE_CAUI4] = "caui4",
[PHY_INTERFACE_MODE_NCSI] = "NC-SI",
- [PHY_INTERFACE_MODE_XFI] = "xfi",
+ [PHY_INTERFACE_MODE_10GBASER] = "10gbase-r",
[PHY_INTERFACE_MODE_USXGMII] = "usxgmii",
[PHY_INTERFACE_MODE_NONE] = "",
};
port_pdata = dev_get_parent_plat(pdev);
ops->port_disable(dev, port_pdata->index, port_pdata->phy);
- ops->port_disable(dev, priv->cpu_port, NULL);
+ ops->port_disable(dev, priv->cpu_port, priv->cpu_port_fixed_phy);
}
eth_get_ops(master)->stop(master);
static int dsa_port_of_to_pdata(struct udevice *pdev)
{
struct dsa_port_pdata *port_pdata;
- struct dsa_pdata *dsa_pdata;
struct eth_pdata *eth_pdata;
- struct udevice *dev;
const char *label;
u32 index;
int err;
if (err)
return err;
- dev = dev_get_parent(pdev);
- dsa_pdata = dev_get_uclass_plat(dev);
-
port_pdata = dev_get_parent_plat(pdev);
port_pdata->index = index;
label = ofnode_read_string(dev_ofnode(pdev), "label");
if (label)
- strncpy(port_pdata->name, label, DSA_PORT_NAME_LENGTH);
+ strlcpy(port_pdata->name, label, DSA_PORT_NAME_LENGTH);
eth_pdata = dev_get_plat(pdev);
eth_pdata->priv_pdata = port_pdata;
.free_pkt = dsa_port_free_pkt,
};
-static int dsa_port_probe(struct udevice *pdev)
+/*
+ * Inherit port's hwaddr from the DSA master, unless the port already has a
+ * unique MAC address specified in the environment.
+ */
+static void dsa_port_set_hwaddr(struct udevice *pdev, struct udevice *master)
{
- struct udevice *dev = dev_get_parent(pdev);
struct eth_pdata *eth_pdata, *master_pdata;
unsigned char env_enetaddr[ARP_HLEN];
+
+ eth_env_get_enetaddr_by_index("eth", dev_seq(pdev), env_enetaddr);
+ if (!is_zero_ethaddr(env_enetaddr)) {
+ /* individual port mac addrs require master to be promisc */
+ struct eth_ops *eth_ops = eth_get_ops(master);
+
+ if (eth_ops->set_promisc)
+ eth_ops->set_promisc(master, 1);
+
+ return;
+ }
+
+ master_pdata = dev_get_plat(master);
+ eth_pdata = dev_get_plat(pdev);
+ memcpy(eth_pdata->enetaddr, master_pdata->enetaddr, ARP_HLEN);
+ eth_env_set_enetaddr_by_index("eth", dev_seq(pdev),
+ master_pdata->enetaddr);
+}
+
+static int dsa_port_probe(struct udevice *pdev)
+{
+ struct udevice *dev = dev_get_parent(pdev);
+ struct dsa_ops *ops = dsa_get_ops(dev);
struct dsa_port_pdata *port_pdata;
- struct dsa_priv *dsa_priv;
struct udevice *master;
- int ret;
+ int err;
port_pdata = dev_get_parent_plat(pdev);
- dsa_priv = dev_get_uclass_priv(dev);
port_pdata->phy = dm_eth_phy_connect(pdev);
if (!port_pdata->phy)
* TODO: we assume the master device is always there and doesn't get
* removed during runtime.
*/
- ret = device_probe(master);
- if (ret)
- return ret;
-
- /*
- * Inherit port's hwaddr from the DSA master, unless the port already
- * has a unique MAC address specified in the environment.
- */
- eth_env_get_enetaddr_by_index("eth", dev_seq(pdev), env_enetaddr);
- if (!is_zero_ethaddr(env_enetaddr)) {
- /* individual port mac addrs require master to be promisc */
- struct eth_ops *eth_ops = eth_get_ops(master);
+ err = device_probe(master);
+ if (err)
+ return err;
- if (eth_ops->set_promisc)
- eth_ops->set_promisc(master, 1);
+ dsa_port_set_hwaddr(pdev, master);
- return 0;
+ if (ops->port_probe) {
+ err = ops->port_probe(dev, port_pdata->index,
+ port_pdata->phy);
+ if (err)
+ return err;
}
- master_pdata = dev_get_plat(master);
- eth_pdata = dev_get_plat(pdev);
- memcpy(eth_pdata->enetaddr, master_pdata->enetaddr, ARP_HLEN);
- eth_env_set_enetaddr_by_index("eth", dev_seq(pdev),
- master_pdata->enetaddr);
-
return 0;
}
static int dsa_port_remove(struct udevice *pdev)
{
- struct udevice *dev = dev_get_parent(pdev);
- struct dsa_port_pdata *port_pdata;
- struct dsa_priv *dsa_priv;
-
- port_pdata = dev_get_parent_plat(pdev);
- dsa_priv = dev_get_uclass_priv(dev);
+ struct dsa_port_pdata *port_pdata = dev_get_parent_plat(pdev);
port_pdata->phy = NULL;
struct dsa_port_pdata *port_pdata;
port_pdata = dev_get_parent_plat(pdev);
- strncpy(port_pdata->name, name, DSA_PORT_NAME_LENGTH);
+ strlcpy(port_pdata->name, name, DSA_PORT_NAME_LENGTH);
pdev->name = port_pdata->name;
}
pdata->mii_bus->write = mdio_write;
pdata->mii_bus->reset = mdio_reset;
pdata->mii_bus->priv = dev;
- strncpy(pdata->mii_bus->name, dev->name, MDIO_NAME_LEN - 1);
+ strlcpy(pdata->mii_bus->name, dev->name, MDIO_NAME_LEN);
return mdio_register(pdata->mii_bus);
}
- miiphy_register(devname, readfunc, writefunc);
+ struct mii_dev *mdiodev = mdio_alloc();
+ if (!mdiodev) return -ENOMEM;
-+ strncpy(mdiodev->name, devname, MDIO_NAME_LEN);
++ strlcpy(mdiodev->name, devname, MDIO_NAME_LEN);
+ mdiodev->read = readfunc;
+ mdiodev->write = writefunc;
+
+ retval = mdio_register(mdiodev);
-+ if (retval < 0) return retval;
++ if (retval < 0) { mdio_free(mdiodev); return retval; }
@ update_read_sig @
identifier mii_reg.readfunc;
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright 2020-2021 NXP Semiconductors
+ * Copyright 2020-2021 NXP
*/
#include <net/dsa.h>
projects / J-u-boot.git / commitdiff