davinci_dvevm \
davinci_schmoogie \
davinci_sonata \
+ pmdra \
"
#########################################################################
cp1136 \
omap2420h4 \
apollon \
+ imx31_litekit \
+ imx31_phycore \
+ mx31ads \
"
#########################################################################
davinci_sonata_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci
+pmdra_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs pmdra prodrive davinci
+
omap1610inn_config \
omap1610inn_cs0boot_config \
omap1610inn_cs3boot_config \
## ARM1136 Systems
#########################################################################
omap2420h4_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4
+ @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
apollon_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_ONENAND_U_BOOT" > $(obj)include/config.h
- @$(MKCONFIG) $(@:_config=) arm arm1136 apollon
+ @$(MKCONFIG) $(@:_config=) arm arm1136 apollon NULL omap24xx
@echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk
+imx31_litekit_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
+
+imx31_phycore_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
+
+mx31ads_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads NULL mx31
+
#========================================================================
# i386
#========================================================================
--- /dev/null
+#
+# (C) Copyright 2000-2008
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundatio; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := imx31_litekit.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#######################################################################
+##
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
--- /dev/null
+TEXT_BASE = 0x87f00000
--- /dev/null
+/*
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+int board_init(void)
+{
+ __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
+ __REG(CSCR_L(0)) = 0xa0330d01;
+ __REG(CSCR_A(0)) = 0x00220800;
+
+ __REG(CSCR_U(4)) = 0x0000dcf6; /* CS4: Network Controller */
+ __REG(CSCR_L(4)) = 0x444a4541;
+ __REG(CSCR_A(4)) = 0x44443302;
+
+ /* setup pins for UART1 */
+ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+ mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+ mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+ mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
+
+ gd->bd->bi_arch_number = 447; /* board id for linux */
+ gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: i.MX31 Litekit\n");
+ return 0;
+}
--- /dev/null
+/*
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+
+.macro REG reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ strb r3, [r2]
+.endm
+
+.macro DELAY loops
+ ldr r2, =\loops
+1:
+ subs r2, r2, #1
+ nop
+ bcs 1b
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+
+ REG IPU_CONF, IPU_CONF_DI_EN
+ REG CCM_CCMR, 0x074B0BF5
+
+ DELAY 0x40000
+
+ REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
+ REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+ REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
+ PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | \
+ PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | \
+ PDR0_MCU_PODF(0)
+
+ REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | \
+ PLL_MFN(0x23)
+ REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+ REG 0x43FAC26C, 0 /* SDCLK */
+ REG 0x43FAC270, 0 /* CAS */
+ REG 0x43FAC274, 0 /* RAS */
+ REG 0x43FAC27C, 0x1000 /* CS2 CSD0) */
+ REG 0x43FAC284, 0 /* DQM3 */
+ /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 0x288..0x2DC) */
+ REG 0x43FAC288, 0
+ REG 0x43FAC28C, 0
+ REG 0x43FAC290, 0
+ REG 0x43FAC294, 0
+ REG 0x43FAC298, 0
+ REG 0x43FAC29C, 0
+ REG 0x43FAC2A0, 0
+ REG 0x43FAC2A4, 0
+ REG 0x43FAC2A8, 0
+ REG 0x43FAC2AC, 0
+ REG 0x43FAC2B0, 0
+ REG 0x43FAC2B4, 0
+ REG 0x43FAC2B8, 0
+ REG 0x43FAC2BC, 0
+ REG 0x43FAC2C0, 0
+ REG 0x43FAC2C4, 0
+ REG 0x43FAC2C8, 0
+ REG 0x43FAC2CC, 0
+ REG 0x43FAC2D0, 0
+ REG 0x43FAC2D4, 0
+ REG 0x43FAC2D8, 0
+ REG 0x43FAC2DC, 0
+ REG 0xB8001010, 0x00000004
+ REG 0xB8001004, 0x006ac73a
+ REG 0xB8001000, 0x92100000
+ REG 0x80000f00, 0x12344321
+ REG 0xB8001000, 0xa2100000
+ REG 0x80000000, 0x12344321
+ REG 0x80000000, 0x12344321
+ REG 0xB8001000, 0xb2100000
+ REG8 0x80000033, 0xda
+ REG8 0x81000000, 0xff
--- /dev/null
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm1136/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
--- /dev/null
+#
+# (C) Copyright 2000-2008
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundatio; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := imx31_phycore.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
--- /dev/null
+TEXT_BASE = 0x87f00000
--- /dev/null
+/*
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+int board_init(void)
+{
+ __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
+ __REG(CSCR_L(0)) = 0x10000d03;
+ __REG(CSCR_A(0)) = 0x00720900;
+
+ __REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */
+ __REG(CSCR_L(1)) = 0x444a4541;
+ __REG(CSCR_A(1)) = 0x44443302;
+
+ __REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */
+ __REG(CSCR_L(4)) = 0x22252521;
+ __REG(CSCR_A(4)) = 0x22220a00;
+
+ /* setup pins for UART1 */
+ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+ mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+ mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+ mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
+
+ /* setup pins for I2C2 (for EEPROM, RTC) */
+ mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
+ mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SCL);
+
+ gd->bd->bi_arch_number = 447; /* board id for linux */
+ gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: Phytec phyCore i.MX31\n");
+ return 0;
+}
--- /dev/null
+/*
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+
+.macro REG reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ strb r3, [r2]
+.endm
+
+.macro DELAY loops
+ ldr r2, =\loops
+1:
+ subs r2, r2, #1
+ nop
+ bcs 1b
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+
+ REG IPU_CONF, IPU_CONF_DI_EN
+ REG CCM_CCMR, 0x074B0BF5
+
+ DELAY 0x40000
+
+ REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
+ REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+ REG CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) | \
+ PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \
+ PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \
+ PDR0_MCU_PODF(0)
+
+ REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
+
+ REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1)
+
+ REG 0x43FAC26C, 0 /* SDCLK */
+ REG 0x43FAC270, 0 /* CAS */
+ REG 0x43FAC274, 0 /* RAS */
+ REG 0x43FAC27C, 0x1000 /* CS2 CSD0) */
+ REG 0x43FAC284, 0 /* DQM3 */
+ /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 0x288..0x2DC) */
+ REG 0x43FAC288, 0
+ REG 0x43FAC28C, 0
+ REG 0x43FAC290, 0
+ REG 0x43FAC294, 0
+ REG 0x43FAC298, 0
+ REG 0x43FAC29C, 0
+ REG 0x43FAC2A0, 0
+ REG 0x43FAC2A4, 0
+ REG 0x43FAC2A8, 0
+ REG 0x43FAC2AC, 0
+ REG 0x43FAC2B0, 0
+ REG 0x43FAC2B4, 0
+ REG 0x43FAC2B8, 0
+ REG 0x43FAC2BC, 0
+ REG 0x43FAC2C0, 0
+ REG 0x43FAC2C4, 0
+ REG 0x43FAC2C8, 0
+ REG 0x43FAC2CC, 0
+ REG 0x43FAC2D0, 0
+ REG 0x43FAC2D4, 0
+ REG 0x43FAC2D8, 0
+ REG 0x43FAC2DC, 0
+ REG 0xB8001010, 0x00000004
+ REG 0xB8001004, 0x006ac73a
+ REG 0xB8001000, 0x92100000
+ REG 0x80000f00, 0x12344321
+ REG 0xB8001000, 0xa2100000
+ REG 0x80000000, 0x12344321
+ REG 0x80000000, 0x12344321
+ REG 0xB8001000, 0xb2100000
+ REG8 0x80000033, 0xda
+ REG8 0x81000000, 0xff
+ REG 0xB8001000, 0x82226080
+ REG 0x80000000, 0xDEADBEEF
--- /dev/null
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm1136/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
--- /dev/null
+#
+# (C) Copyright 2000-2008
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundatio; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := mx31ads.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+TEXT_BASE = 0x87f00000
--- /dev/null
+/*
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+
+.macro REG reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ strb r3, [r2]
+.endm
+
+.macro DELAY loops
+ ldr r2, =\loops
+1:
+ subs r2, r2, #1
+ nop
+ bcs 1b
+.endm
+
+/* RedBoot: AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, =0x43F00000
+ ldr r1, =0x77777777
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, =0x53F00000
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+
+ /*
+ * Clear the on and off peripheral modules Supervisor Protect bit
+ * for SDMA to access them. Did not change the AIPS control registers
+ * (offset 0x20) access type
+ */
+ ldr r0, =0x43F00000
+ ldr r1, =0x0
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ ldr r1, [r0, #0x50]
+ and r1, r1, #0x00FFFFFF
+ str r1, [r0, #0x50]
+
+ ldr r0, =0x53F00000
+ ldr r1, =0x0
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ ldr r1, [r0, #0x50]
+ and r1, r1, #0x00FFFFFF
+ str r1, [r0, #0x50]
+.endm /* init_aips */
+
+/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+ ldr r0, =0x43F04000
+ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+ ldr r1, =0x00302154
+ str r1, [r0, #0x000] /* for S0 */
+ str r1, [r0, #0x100] /* for S1 */
+ str r1, [r0, #0x200] /* for S2 */
+ str r1, [r0, #0x300] /* for S3 */
+ str r1, [r0, #0x400] /* for S4 */
+ /* SGPCR - always park on last master */
+ ldr r1, =0x10
+ str r1, [r0, #0x010] /* for S0 */
+ str r1, [r0, #0x110] /* for S1 */
+ str r1, [r0, #0x210] /* for S2 */
+ str r1, [r0, #0x310] /* for S3 */
+ str r1, [r0, #0x410] /* for S4 */
+ /* MGPCR - restore default values */
+ ldr r1, =0x0
+ str r1, [r0, #0x800] /* for M0 */
+ str r1, [r0, #0x900] /* for M1 */
+ str r1, [r0, #0xA00] /* for M2 */
+ str r1, [r0, #0xB00] /* for M3 */
+ str r1, [r0, #0xC00] /* for M4 */
+ str r1, [r0, #0xD00] /* for M5 */
+.endm /* init_max */
+
+/* RedBoot: M3IF setup */
+.macro init_m3if
+ /* Configure M3IF registers */
+ ldr r1, =0xB8003000
+ /*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+ ldr r0, =0x00000040
+ str r0, [r1] /* M3IF control reg */
+.endm /* init_m3if */
+
+/* RedBoot: To support 133MHz DDR */
+.macro init_drive_strength
+ /*
+ * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
+ * in SW_PAD_CTL registers
+ */
+
+ /* SDCLK */
+ ldr r1, =0x43FAC200
+ ldr r0, [r1, #0x6C]
+ bic r0, r0, #(1 << 12)
+ str r0, [r1, #0x6C]
+
+ /* CAS */
+ ldr r0, [r1, #0x70]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x70]
+
+ /* RAS */
+ ldr r0, [r1, #0x74]
+ bic r0, r0, #(1 << 2)
+ str r0, [r1, #0x74]
+
+ /* CS2 (CSD0) */
+ ldr r0, [r1, #0x7C]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x7C]
+
+ /* DQM3 */
+ ldr r0, [r1, #0x84]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x84]
+
+ /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+ ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
+pad_loop:
+ ldr r0, [r1, #0x88]
+ bic r0, r0, #(1 << 22)
+ bic r0, r0, #(1 << 12)
+ bic r0, r0, #(1 << 2)
+ str r0, [r1, #0x88]
+ add r1, r1, #4
+ subs r2, r2, #0x1
+ bne pad_loop
+.endm /* init_drive_strength */
+
+/* CPLD on CS4 setup */
+.macro init_cs4
+ ldr r0, =WEIM_BASE
+ ldr r1, =0x0000D843
+ str r1, [r0, #0x40]
+ ldr r1, =0x22252521
+ str r1, [r0, #0x44]
+ ldr r1, =0x22220A00
+ str r1, [r0, #0x48]
+.endm /* init_cs4 */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ /* Redboot initializes very early AIPS, what for?
+ * Then it also initializes Multi-Layer AHB Crossbar Switch,
+ * M3IF */
+ /* Also setup the Peripheral Port Remap register inside the core */
+ ldr r0, =0x40000015 /* start from AIPS 2GB region */
+ mcr p15, 0, r0, c15, c2, 4
+
+ init_aips
+
+ init_max
+
+ init_m3if
+
+ init_drive_strength
+
+ init_cs4
+
+ /* Image Processing Unit: */
+ /* Too early to switch display on? */
+ /* Switch on Display Interface */
+ REG IPU_CONF, IPU_CONF_DI_EN
+ /* Clock Control Module: */
+ /* Use CKIH, MCU PLL off */
+ REG CCM_CCMR, 0x074B0BF5
+
+ DELAY 0x40000
+ /* MCU PLL on */
+ REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
+ /* Switch to MCU PLL */
+ REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+ /* PBC CPLD on CS4 */
+ mov r1, #CS4_BASE
+ ldrh r1, [r1, #0x2]
+ /* Is 27MHz switch set? */
+ ands r1, r1, #0x16
+
+ /* 532-133-66.5 */
+ ldr r0, =CCM_BASE
+ ldr r1, =0xFF871D58
+ /* PDR0 */
+ str r1, [r0, #0x4]
+ ldreq r1, MPCTL_PARAM_532
+ ldrne r1, MPCTL_PARAM_532_27
+ /* MPCTL */
+ str r1, [r0, #0x10]
+
+ /* Set UPLL=240MHz, USB=60MHz */
+ ldr r1, =0x49FCFE7F
+ /* PDR1 */
+ str r1, [r0, #0x8]
+ ldreq r1, UPCTL_PARAM_240
+ ldrne r1, UPCTL_PARAM_240_27
+ /* UPCTL */
+ str r1, [r0, #0x14]
+ /* default CLKO to 1/8 of the ARM core */
+ mov r1, #0x000002C0
+ add r1, r1, #0x00000006
+ /* COSR */
+ str r1, [r0, #0x1c]
+
+ /* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */
+/* REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
+ PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | \
+ PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | \
+ PDR0_MCU_PODF(0)*/
+
+ /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
+/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | \
+ PLL_MFN(0x23)*/
+ /* Default: 1, 4, 12, 1 */
+ REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+ /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
+ REG 0xB8001010, 0x00000004
+ REG 0xB8001004, 0x006ac73a
+ REG 0xB8001000, 0x92100000
+ REG 0x80000f00, 0x12344321
+ REG 0xB8001000, 0xa2100000
+ REG 0x80000000, 0x12344321
+ REG 0x80000000, 0x12344321
+ REG 0xB8001000, 0xb2100000
+ REG8 0x80000033, 0xda
+ REG8 0x81000000, 0xff
+ REG 0xB8001000, 0x82226080
+ REG 0x80000000, 0xDEADBEEF
+ REG 0xB8001010, 0x0000000c
+
+ mov pc, lr
+
+MPCTL_PARAM_532:
+ .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
+MPCTL_PARAM_532_27:
+ .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0))
+UPCTL_PARAM_240:
+ .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
+UPCTL_PARAM_240_27:
+ .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))
--- /dev/null
+/*
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+int board_init(void)
+{
+ int i;
+#if 0
+ /* CS0: Nor Flash */
+ /*
+ * These are values from the RedBoot sources by Freescale. However,
+ * under U-Boot with this configuration 32-bit accesses don't work,
+ * lower 16 bits of data are read twice for each 32-bit read.
+ */
+ __REG(CSCR_U(0)) = 0x23524E80;
+ __REG(CSCR_L(0)) = 0x10000D03; /* WRAP bit (1) is suspicious here, but
+ * disabling it doesn't help either */
+ __REG(CSCR_A(0)) = 0x00720900;
+#endif
+
+ /* setup pins for UART1 */
+ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+ mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+ mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+ mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
+
+ /* PBC setup */
+ /* Enable UART transceivers also reset the Ethernet/external UART */
+ readw(CS4_BASE + 4);
+
+ writew(0x8023, CS4_BASE + 4);
+
+ /* RedBoot also has an empty loop with 100000 iterations here -
+ * clock doesn't run yet */
+ for (i = 0; i < 100000; i++)
+ ;
+
+ /* Clear the reset, toggle the LEDs */
+ writew(0xDF, CS4_BASE + 6);
+
+ /* clock still doesn't run */
+ for (i = 0; i < 100000; i++)
+ ;
+
+ /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */
+ readb(CS4_BASE + 8);
+ readb(CS4_BASE + 7);
+ readb(CS4_BASE + 8);
+ readb(CS4_BASE + 7);
+
+ gd->bd->bi_arch_number = 447; /* board id for linux */
+ gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: MX31ADS\n");
+ return 0;
+}
--- /dev/null
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm1136/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
--- /dev/null
+#
+# (C) Copyright 2003-2006
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := pmdra.o
+SOBJS := board_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2008 Prodrive B.V.
+ *
+ * Board-specific low level initialization code. Called at the very end
+ * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * initialization required.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+.globl dv_board_init
+dv_board_init:
+
+ mov pc, lr
--- /dev/null
+#
+# (C) Copyright 2002
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+#
+# Davinci EVM board (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Davinci EVM has 1 bank of 256 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 9000'0000
+#
+#
+# Visioneering Corp. Sonata board (ARM926EJS) cpu
+#
+# Sonata board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
+#
+# Schmoogie board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+# we load ourself to 8108 '0000
+#
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+TEXT_BASE = 0x81080000
--- /dev/null
+/*
+ *
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ * ---------------------------------------------------------------------------
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ---------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ---------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emac_defs.h>
+
+#define MACH_TYPE_DAVINCI_EVM 901
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void timer_init(void);
+extern int eth_hw_init(void);
+extern phy_t phy;
+
+/* Works on Always On power domain only (no PD argument) */
+void lpsc_on(unsigned int id)
+{
+ dv_reg_p mdstat, mdctl;
+
+ if (id >= DAVINCI_LPSC_GEM)
+ return; /* Don't work on DSP Power Domain */
+
+ mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
+ mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
+
+ while (REG(PSC_PTSTAT) & 0x01) {; }
+
+ if ((*mdstat & 0x1f) == 0x03)
+ return; /* Already on and enabled */
+
+ *mdctl |= 0x03;
+
+ /* Special treatment for some modules as for sprue14 p.7.4.2 */
+ if ((id == DAVINCI_LPSC_VPSSSLV) ||
+ (id == DAVINCI_LPSC_EMAC) ||
+ (id == DAVINCI_LPSC_EMAC_WRAPPER) ||
+ (id == DAVINCI_LPSC_MDIO) ||
+ (id == DAVINCI_LPSC_USB) ||
+ (id == DAVINCI_LPSC_ATA) ||
+ (id == DAVINCI_LPSC_VLYNQ) ||
+ (id == DAVINCI_LPSC_UHPI) ||
+ (id == DAVINCI_LPSC_DDR_EMIF) ||
+ (id == DAVINCI_LPSC_AEMIF) ||
+ (id == DAVINCI_LPSC_MMC_SD) ||
+ (id == DAVINCI_LPSC_MEMSTICK) ||
+ (id == DAVINCI_LPSC_McBSP) ||
+ (id == DAVINCI_LPSC_GPIO))
+ *mdctl |= 0x200;
+
+ REG(PSC_PTCMD) = 0x01;
+
+ while (REG(PSC_PTSTAT) & 0x03) {; }
+ while ((*mdstat & 0x1f) != 0x03) {; } /* Probably an overkill... */
+}
+
+void dsp_on(void)
+{
+ int i;
+
+ if (REG(PSC_PDSTAT1) & 0x1f)
+ return; /* Already on */
+
+ REG(PSC_GBLCTL) |= 0x01;
+ REG(PSC_PDCTL1) |= 0x01;
+ REG(PSC_PDCTL1) &= ~0x100;
+ REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
+ REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
+ REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
+ REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
+ REG(PSC_PTCMD) = 0x02;
+
+ for (i = 0; i < 100; i++) {
+ if (REG(PSC_EPCPR) & 0x02)
+ break;
+ }
+
+ REG(PSC_CHP_SHRTSW) = 0x01;
+ REG(PSC_PDCTL1) |= 0x100;
+ REG(PSC_EPCCR) = 0x02;
+
+ for (i = 0; i < 100; i++) {
+ if (!(REG(PSC_PTSTAT) & 0x02))
+ break;
+ }
+
+ REG(PSC_GBLCTL) &= ~0x1f;
+}
+
+
+int board_init(void)
+{
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /* Workaround for TMS320DM6446 errata 1.3.22 */
+ REG(PSC_SILVER_BULLET) = 0;
+
+ /* Power on required peripherals */
+ lpsc_on(DAVINCI_LPSC_EMAC);
+ lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
+ lpsc_on(DAVINCI_LPSC_MDIO);
+ lpsc_on(DAVINCI_LPSC_I2C);
+ lpsc_on(DAVINCI_LPSC_UART0);
+ lpsc_on(DAVINCI_LPSC_UART2);
+ lpsc_on(DAVINCI_LPSC_TIMER1);
+ lpsc_on(DAVINCI_LPSC_GPIO);
+
+ /* Powerup the DSP */
+ dsp_on();
+
+ /* Bringup UART0 and 2 out of reset */
+ REG(UART0_PWREMU_MGMT) = 0x00006001;
+ REG(UART2_PWREMU_MGMT) = 0x00006001;
+
+ /* Enable GIO3.3V cells used for EMAC */
+ REG(VDD3P3V_PWDN) = 0;
+
+ /* Enable UART0 and 2 MUX lines */
+ REG(PINMUX1) |= 1;
+ REG(PINMUX1) |= 4;
+
+ /* Enable EMAC and AEMIF pins */
+ REG(PINMUX0) = 0x80000c1f;
+
+ /* Enable I2C pin Mux */
+ REG(PINMUX1) |= (1 << 7);
+
+ /* Set the Bus Priority Register to appropriate value */
+ REG(VBPR) = 0x20;
+
+ timer_init();
+
+ return(0);
+}
+
+int misc_init_r(void)
+{
+ int clk = 0;
+
+ clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
+
+ printf("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27)/2);
+ printf("DDR Clock : %dMHz\n", (clk / 2));
+
+ if (!eth_hw_init())
+ printf("ethernet init failed!\n");
+ else
+ printf("ETH PHY : %s\n", phy.name);
+
+ return(0);
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return(0);
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm926ejs/start.o (.text)
+ *(.text)
+ }
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+ . = ALIGN(4);
+ .data : { *(.data) }
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
LIB = $(obj)lib$(CPU).a
START = start.o
-COBJS = interrupts.o cpu.o
+COBJS = cpu.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
#include <common.h>
#include <command.h>
-#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
-#include <asm/arch/omap2420.h>
-#endif
#ifdef CONFIG_USE_IRQ
DECLARE_GLOBAL_DATA_PTR;
unsigned long value;
__asm__ __volatile__(
- "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
- : "=r" (value)
- :
- : "memory");
+ "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
+ : "=r" (value)
+ :
+ : "memory");
return value;
}
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Texas Instruments
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- *
- * (C) Copyright 2002
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/bits.h>
-
-#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
-# include <asm/arch/omap2420.h>
-#endif
-
-#define TIMER_LOAD_VAL 0
-
-/* macro to read the 32 bit timer */
-#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+TCRR))
-
-#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)
-/* Use the IntegratorCP function from board/integratorcp.c */
-#else
-
-static ulong timestamp;
-static ulong lastinc;
-
-/* nothing really to do with interrupts, just starts up a counter. */
-int interrupt_init (void)
-{
- int32_t val;
-
- /* Start the counter ticking up */
- *((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/
- val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/
- *((int32_t *) (CFG_TIMERBASE + TCLR)) = val; /* start timer */
-
- reset_timer_masked(); /* init the timestamp and lastinc value */
-
- return(0);
-}
-/*
- * timer without interrupts
- */
-void reset_timer (void)
-{
- reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
- return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
- timestamp = t;
-}
-
-/* delay x useconds AND perserve advance timstamp value */
-void udelay (unsigned long usec)
-{
- ulong tmo, tmp;
-
- if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
- tmo /= 1000; /* finish normalize. */
- } else { /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CFG_HZ;
- tmo /= (1000*1000);
- }
-
- tmp = get_timer (0); /* get current timestamp */
- if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */
- reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */
- else
- tmo += tmp; /* else, set advancing stamp wake up time */
- while (get_timer_masked () < tmo)/* loop till event */
- /*NOP*/;
-}
-
-void reset_timer_masked (void)
-{
- /* reset time */
- lastinc = READ_TIMER; /* capture current incrementer value time */
- timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked (void)
-{
- ulong now = READ_TIMER; /* current tick value */
-
- if (now >= lastinc) /* normal mode (non roll) */
- timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */
- else /* we have rollover of incrementer */
- timestamp += (0xFFFFFFFF - lastinc) + now;
- lastinc = now;
- return timestamp;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
-{
- ulong tmo;
- ulong endtime;
- signed long diff;
-
- if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
- tmo /= 1000; /* finish normalize. */
- } else { /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CFG_HZ;
- tmo /= (1000*1000);
- }
- endtime = get_timer_masked () + tmo;
-
- do {
- ulong now = get_timer_masked ();
- diff = endtime - now;
- } while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- ulong tbclk;
- tbclk = CFG_HZ;
- return tbclk;
-}
-#endif /* !Integrator/CP */
--- /dev/null
+#
+# (C) Copyright 2000-2008
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundatio; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS = interrupts.o serial.o generic.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#######################################################################
+##
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/mx31-regs.h>
+
+static u32 mx31_decode_pll(u32 reg, u32 infreq)
+{
+ u32 mfi = (reg >> 10) & 0xf;
+ u32 mfn = reg & 0x3f;
+ u32 mfd = (reg >> 16) & 0x3f;
+ u32 pd = (reg >> 26) & 0xf;
+
+ mfi = mfi <= 5 ? 5 : mfi;
+ mfd += 1;
+ pd += 1;
+
+ return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
+ (mfd * pd)) << 10;
+}
+
+u32 mx31_get_mpl_dpdgck_clk(void)
+{
+ u32 infreq;
+
+ if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
+ infreq = CONFIG_MX31_CLK32 * 1024;
+ else
+ infreq = CONFIG_MX31_HCLK_FREQ;
+
+ return mx31_decode_pll(__REG(CCM_MPCTL), infreq); }
+
+u32 mx31_get_mcu_main_clk(void)
+{
+ /* For now we assume mpl_dpdgck_clk == mcu_main_clk
+ * which should be correct for most boards
+ */
+ return mx31_get_mpl_dpdgck_clk();
+}
+
+u32 mx31_get_ipg_clk(void)
+{
+ u32 freq = mx31_get_mcu_main_clk();
+ u32 pdr0 = __REG(CCM_PDR0);
+
+ freq /= ((pdr0 >> 3) & 0x7) + 1;
+ freq /= ((pdr0 >> 6) & 0x3) + 1;
+
+ return freq;
+}
+
+void mx31_dump_clocks(void)
+{
+ u32 cpufreq = mx31_get_mcu_main_clk();
+ printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
+ printf("ipg clock : %dHz\n", mx31_get_ipg_clk());
+}
+
+void mx31_gpio_mux(unsigned long mode)
+{
+ unsigned long reg, shift, tmp;
+
+ reg = IOMUXC_BASE + (mode & 0xfc);
+ shift = (~mode & 0x3) * 8;
+
+ tmp = __REG(reg);
+ tmp &= ~(0xff << shift);
+ tmp |= ((mode >> 8) & 0xff) << shift;
+ __REG(reg) = tmp;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ printf("CPU: Freescale i.MX31 at %d MHz\n",
+ mx31_get_mcu_main_clk() / 1000000);
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/mx31-regs.h>
+
+#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
+
+/* General purpose timers registers */
+#define GPTCR __REG(TIMER_BASE) /* Control register */
+#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */
+#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */
+#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR (1<<15) /* Software reset */
+#define GPTCR_FRR (1<<9) /* Freerun / restart */
+#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
+#define GPTCR_TEN (1) /* Timer enable */
+
+/*
+ * nothing really to do with interrupts, just starts up a counter.
+ */
+int interrupt_init(void)
+{
+ int i;
+
+ /* setup GP Timer 1 */
+ GPTCR = GPTCR_SWR;
+ for (i = 0; i < 100; i++) GPTCR = 0; /* We have no udelay by now */
+ GPTPR = 0; /* 32Khz */
+ /* Freerun Mode, PERCLK1 input */
+ GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
+
+ return 0;
+}
+
+void reset_timer_masked(void)
+{
+ GPTCR = 0;
+ /* Freerun Mode, PERCLK1 input*/
+ GPTCR = GPTCR_CLKSOURCE_32 | GPTCR_TEN;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong val = GPTCNT;
+ return val;
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void udelay(unsigned long usec)
+{
+ ulong tmo, tmp;
+
+ if (usec >= 1000) {
+ /* "big" number, spread normalization to seconds */
+ /* start to normalize for usec to ticks per sec */
+ tmo = usec / 1000;
+ /* find number of "ticks" to wait to achieve target */
+ tmo *= CFG_HZ;
+ tmo /= 1000; /* finish normalize. */
+ } else {
+ /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CFG_HZ;
+ tmo /= (1000*1000);
+ }
+
+ tmp = get_timer(0); /* get current timestamp */
+ if ((tmo + tmp + 1) < tmp)
+ /* setting this forward will roll time stamp */
+ /* reset "advancing" timestamp to 0, set lastinc value */
+ reset_timer_masked();
+ else
+ /* else, set advancing stamp wake up time */
+ tmo += tmp;
+ while (get_timer_masked() < tmo)/* loop till event */
+ /*NOP*/;
+}
+
+void reset_cpu(ulong addr)
+{
+ __REG16(WDOG_BASE) = 4;
+}
--- /dev/null
+/*
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+
+#if defined CONFIG_MX31_UART
+
+#include <asm/arch/mx31.h>
+
+#define __REG(x) (*((volatile u32 *)(x)))
+
+#ifdef CFG_MX31_UART1
+#define UART_PHYS 0x43f90000
+#elif defined(CFG_MX31_UART2)
+#define UART_PHYS 0x43f94000
+#elif defined(CFG_MX31_UART3)
+#define UART_PHYS 0x5000c000
+#elif defined(CFG_MX31_UART4)
+#define UART_PHYS 0x43fb0000
+#elif defined(CFG_MX31_UART5)
+#define UART_PHYS 0x43fb4000
+#else
+#error "define CFG_MX31_UARTx to use the mx31 UART driver"
+#endif
+
+/* Register definitions */
+#define URXD 0x0 /* Receiver Register */
+#define UTXD 0x40 /* Transmitter Register */
+#define UCR1 0x80 /* Control Register 1 */
+#define UCR2 0x84 /* Control Register 2 */
+#define UCR3 0x88 /* Control Register 3 */
+#define UCR4 0x8c /* Control Register 4 */
+#define UFCR 0x90 /* FIFO Control Register */
+#define USR1 0x94 /* Status Register 1 */
+#define USR2 0x98 /* Status Register 2 */
+#define UESC 0x9c /* Escape Character Register */
+#define UTIM 0xa0 /* Escape Timer Register */
+#define UBIR 0xa4 /* BRM Incremental Register */
+#define UBMR 0xa8 /* BRM Modulator Register */
+#define UBRC 0xac /* Baud Rate Count Register */
+#define UTS 0xb4 /* UART Test Register (mx31) */
+
+/* UART Control Register Bit Fields.*/
+#define URXD_CHARRDY (1<<15)
+#define URXD_ERR (1<<14)
+#define URXD_OVRRUN (1<<13)
+#define URXD_FRMERR (1<<12)
+#define URXD_BRK (1<<11)
+#define URXD_PRERR (1<<10)
+#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
+#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
+#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
+#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
+#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
+#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
+#define UCR1_IREN (1<<7) /* Infrared interface enable */
+#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
+#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
+#define UCR1_SNDBRK (1<<4) /* Send break */
+#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
+#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
+#define UCR1_DOZE (1<<1) /* Doze */
+#define UCR1_UARTEN (1<<0) /* UART enabled */
+#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
+#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
+#define UCR2_CTSC (1<<13) /* CTS pin control */
+#define UCR2_CTS (1<<12) /* Clear to send */
+#define UCR2_ESCEN (1<<11) /* Escape enable */
+#define UCR2_PREN (1<<8) /* Parity enable */
+#define UCR2_PROE (1<<7) /* Parity odd/even */
+#define UCR2_STPB (1<<6) /* Stop */
+#define UCR2_WS (1<<5) /* Word size */
+#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
+#define UCR2_TXEN (1<<2) /* Transmitter enabled */
+#define UCR2_RXEN (1<<1) /* Receiver enabled */
+#define UCR2_SRST (1<<0) /* SW reset */
+#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
+#define UCR3_PARERREN (1<<12) /* Parity enable */
+#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
+#define UCR3_DSR (1<<10) /* Data set ready */
+#define UCR3_DCD (1<<9) /* Data carrier detect */
+#define UCR3_RI (1<<8) /* Ring indicator */
+#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
+#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
+#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
+#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
+#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
+#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
+#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
+#define UCR3_BPEN (1<<0) /* Preset registers enable */
+#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
+#define UCR4_INVR (1<<9) /* Inverted infrared reception */
+#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
+#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
+#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
+#define UCR4_IRSC (1<<5) /* IR special case */
+#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
+#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
+#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
+#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
+#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
+#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
+#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
+#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
+#define USR1_RTSS (1<<14) /* RTS pin status */
+#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
+#define USR1_RTSD (1<<12) /* RTS delta */
+#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
+#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
+#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
+#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
+#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
+#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
+#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
+#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
+#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
+#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
+#define USR2_IDLE (1<<12) /* Idle condition */
+#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
+#define USR2_WAKE (1<<7) /* Wake */
+#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
+#define USR2_TXDC (1<<3) /* Transmitter complete */
+#define USR2_BRCD (1<<2) /* Break condition */
+#define USR2_ORE (1<<1) /* Overrun error */
+#define USR2_RDR (1<<0) /* Recv data ready */
+#define UTS_FRCPERR (1<<13) /* Force parity error */
+#define UTS_LOOP (1<<12) /* Loop tx and rx */
+#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
+#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
+#define UTS_TXFULL (1<<4) /* TxFIFO full */
+#define UTS_RXFULL (1<<3) /* RxFIFO full */
+#define UTS_SOFTRST (1<<0) /* Software reset */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void serial_setbrg(void)
+{
+ u32 clk = mx31_get_ipg_clk();
+
+ if (!gd->baudrate)
+ gd->baudrate = CONFIG_BAUDRATE;
+
+ __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */
+ __REG(UART_PHYS + UBIR) = 0xf;
+ __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
+
+}
+
+int serial_getc(void)
+{
+ while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
+ return __REG(UART_PHYS + URXD);
+}
+
+void serial_putc(const char c)
+{
+ __REG(UART_PHYS + UTXD) = c;
+
+ /* wait for transmitter to be ready */
+ while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY));
+
+ /* If \n, also do \r */
+ if (c == '\n')
+ serial_putc('\r');
+}
+
+/*
+ * Test whether a character is in the RX buffer */
+int serial_tstc(void)
+{
+ /* If receive fifo is empty, return false */
+ if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
+ return 0;
+ return 1;
+}
+
+void serial_puts(const char *s)
+{
+ while (*s) {
+ serial_putc(*s++);
+ }
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+int serial_init(void)
+{
+ __REG(UART_PHYS + UCR1) = 0x0;
+ __REG(UART_PHYS + UCR2) = 0x0;
+
+ while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
+
+ __REG(UART_PHYS + UCR3) = 0x0704;
+ __REG(UART_PHYS + UCR4) = 0x8000;
+ __REG(UART_PHYS + UESC) = 0x002b;
+ __REG(UART_PHYS + UTIM) = 0x0;
+
+ __REG(UART_PHYS + UTS) = 0x0;
+
+ serial_setbrg();
+
+ __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | \
+ UCR2_TXEN | UCR2_SRST;
+
+ __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
+
+ return 0;
+}
+
+
+#endif /* CONFIG_MX31 */
--- /dev/null
+#
+# (C) Copyright 2000-2008
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundatio; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS = interrupts.o
+SOBJS = start.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * (C) Copyright 2002
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/omap2420.h>
+
+#define TIMER_LOAD_VAL 0
+
+/* macro to read the 32 bit timer */
+#define READ_TIMER (*((volatile ulong*)(CFG_TIMERBASE+TCRR)))
+
+static ulong timestamp;
+static ulong lastinc;
+
+/*
+ * nothing really to do with interrupts, just starts up a counter.
+ */
+int interrupt_init(void)
+{
+ int32_t val;
+
+ /* Start the counter ticking up */
+ /* reload value on overflow*/
+ *((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL;
+ /* mask to enable timer*/
+ val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0;
+ *((int32_t *) (CFG_TIMERBASE + TCLR)) = val; /* start timer */
+
+ reset_timer_masked(); /* init the timestamp and lastinc value */
+
+ return(0);
+}
+/*
+ * timer without interrupts
+ */
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+ timestamp = t;
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void udelay(unsigned long usec)
+{
+ ulong tmo, tmp;
+
+ /* if "big" number, spread normalization to seconds */
+ if (usec >= 1000) {
+ /* start to normalize for usec to ticks per sec */
+ tmo = usec / 1000;
+ /* find number of "ticks" to wait to achieve target */
+ tmo *= CFG_HZ;
+ /* finish normalize. */
+ tmo /= 1000;
+ } else {
+ /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CFG_HZ;
+ tmo /= (1000*1000);
+ }
+ /* get current timestamp */
+ tmp = get_timer(0);
+ if ((tmo + tmp + 1) < tmp)
+ /* setting this forward will roll time stamp */
+ /* reset "advancing" timestamp to 0, set lastinc value */
+ reset_timer_masked();
+ else
+ /* else, set advancing stamp wake up time */
+ tmo += tmp;
+ while (get_timer_masked() < tmo)/* loop till event */
+ /*NOP*/;
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ /* capture current incrementer value time */
+ lastinc = READ_TIMER;
+ /* start "advancing" time stamp from 0 */
+ timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = READ_TIMER; /* current tick value */
+
+ /* normal mode (non roll) */
+ if (now >= lastinc)
+ /* move stamp forward with absolute diff ticks */
+ timestamp += (now - lastinc);
+ else
+ /* we have rollover of incrementer */
+ timestamp += (0xFFFFFFFF - lastinc) + now;
+ lastinc = now;
+ return timestamp;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked(unsigned long usec)
+{
+ ulong tmo;
+ ulong endtime;
+ signed long diff;
+
+ if (usec >= 1000) {
+ /* "big" number, spread normalization to seconds */
+ /* start to normalize for usec to ticks per sec */
+ tmo = usec / 1000;
+ /* find number of "ticks" to wait to achieve target */
+ tmo *= CFG_HZ;
+ tmo /= 1000;/* finish normalize. */
+ } else {
+ /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CFG_HZ;
+ tmo /= (1000*1000);
+ }
+ endtime = get_timer_masked() + tmo;
+
+ do {
+ ulong now = get_timer_masked();
+ diff = endtime - now;
+ } while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ ulong tbclk;
+ tbclk = CFG_HZ;
+ return tbclk;
+}
--- /dev/null
+/*
+ * armboot - Startup Code for OMP2420/ARM1136 CPU-core
+ *
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/omap2420.h>
+
+.globl reset_cpu
+reset_cpu:
+ ldr r1, rstctl /* get addr for global reset reg */
+ mov r3, #0x2 /* full reset pll+mpu */
+ str r3, [r1] /* force reset */
+ mov r0, r0
+_loop_forever:
+ b _loop_forever
+rstctl:
+ .word PM_RSTCTRL_WKUP
#include <config.h>
#include <version.h>
-#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
-#include <asm/arch/omap2420.h>
-#endif
.globl _start
_start: b reset
#ifdef CONFIG_ONENAND_IPL
arm1136_cache_flush:
mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
mov pc, lr @ back to caller
-
-#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)
-/* Use the IntegratorCP function from board/integratorcp/platform.S */
-#else
-
- .align 5
-.globl reset_cpu
-reset_cpu:
- ldr r1, rstctl /* get addr for global reset reg */
- mov r3, #0x2 /* full reset pll+mpu */
- str r3, [r1] /* force reset */
- mov r0, r0
-_loop_forever:
- b _loop_forever
-rstctl:
- .word PM_RSTCTRL_WKUP
-
-#endif
#endif /* CONFIG_ONENAND_IPL */
*
*
+ * Changed:
+ * Made board specific defines such as DDR timing and PLL
+ * dividers. These should be set in the board config file
+ *
* Partially based on TI sources, original copyrights follow:
*/
/* Program the PLL Multiplier */
ldr r6, PLL2_PLLM
- mov r2, $0x17 /* 162 MHz */
+ mov r2, $CFG_DAVINCI_PLL2_PLLM
str r2, [r6]
/* Program the PLL2 Divisor Value */
ldr r6, PLL2_DIV2
- mov r3, $0x01
+ mov r3, $CFG_DAVINCI_PLL2_DIV2
str r3, [r6]
/* Program the PLL2 Divisor Value */
ldr r6, PLL2_DIV1
- mov r4, $0x0b /* 54 MHz */
+ mov r4, $CFG_DAVINCI_PLL2_DIV1
str r4, [r6]
/* PLL2 DIV2 MMR */
bne checkDDRStatClkStop
/*------------------------------------------------------*
- * Program DDR2 MMRs for 162MHz Setting *
+ * Program DDR2 MMRs *
*------------------------------------------------------*/
/* Program PHY Control Register */
/* Program SDRAM TIM-0 Config Register */
ldr r6, SDTIM0
- ldr r7, SDTIM0_VAL_162MHz
+ ldr r7, SDTIM0_VAL
str r7, [r6]
/* Program SDRAM TIM-1 Config Register */
ldr r6, SDTIM1
- ldr r7, SDTIM1_VAL_162MHz
+ ldr r7, SDTIM1_VAL
str r7, [r6]
/* Program the SDRAM Bank Config Control Register */
/* Program the PLL Multiplier */
ldr r6, PLL1_PLLM
- mov r3, $0x15 /* For 594MHz */
+ mov r3, $CFG_DAVINCI_PLL1_PLLM
str r3, [r6]
/* Wait for PLL to Reset Properly */
nop
/*------------------------------------------------------*
- * AEMIF configuration for NOR Flash (double check) *
+ * AEMIF configuration for NAND/NOR Flash *
*------------------------------------------------------*/
ldr r0, _PINMUX0
ldr r1, _DEV_SETTING
orr r2, r2, r1
str r2, [r0]
+ ldr r0, ACFG2
+ ldr r1, ACFG2_VAL
+ ldr r2, [r0]
+ and r1, r2, r1
+ str r1, [r0]
+
ldr r0, ACFG3
ldr r1, ACFG3_VAL
ldr r2, [r0]
and r1, r2, r1
str r1, [r0]
+ ldr r0, NANDFCR
+ ldr r1, NANDFCR_VAL
+ ldr r2, [r0]
+ and r1, r2, r1
+ str r1, [r0]
+
/*--------------------------------------*
* VTP manual Calibration *
*--------------------------------------*/
.word 0x01c40004 /* Device Configuration Registers */
_DEV_SETTING:
- .word 0x00000c1f
+ .word CFG_DAVINCI_PINMUX_0
WAITCFG:
.word 0x01e00004
WAITCFG_VAL:
- .word 0
+ .word CFG_DAVINCI_WAITCFG
+ACFG2:
+ .word 0x01e00010
+ACFG2_VAL:
+ .word CFG_DAVINCI_ACFG2
ACFG3:
.word 0x01e00014
ACFG3_VAL:
- .word 0x3ffffffd
+ .word CFG_DAVINCI_ACFG3
ACFG4:
.word 0x01e00018
ACFG4_VAL:
- .word 0x3ffffffd
+ .word CFG_DAVINCI_ACFG4
ACFG5:
.word 0x01e0001c
ACFG5_VAL:
- .word 0x3ffffffd
+ .word CFG_DAVINCI_ACFG5
+NANDFCR:
+ .word 0x01e00060
+NANDFCR_VAL:
+#ifdef CFG_DAVINCI_NANDCE
+ .word (1 << (CFG_DAVINCI_NANDCE - 2))
+#else
+ .word 0x00000000
+#endif
MDCTL_DDR2:
.word 0x01c41a34
PSC_GEM_FLAG_CLEAR:
.word 0xfffffeff
-/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
+/* DDR2 MMR & CONFIGURATION VALUES */
DDRCTL:
.word 0x200000e4
DDRCTL_VAL:
- .word 0x50006405
+ .word CFG_DAVINCI_DDRCTL
SDREF:
.word 0x2000000c
SDREF_VAL:
- .word 0x000005c3
+ .word CFG_DAVINCI_SDREF
SDCFG:
.word 0x20000008
SDCFG_VAL:
-#ifdef DDR_4BANKS
- .word 0x00178622
-#elif defined DDR_8BANKS
- .word 0x00178632
-#else
-#error "Unknown DDR configuration!!!"
-#endif
+ .word CFG_DAVINCI_SDCFG
SDTIM0:
.word 0x20000010
-SDTIM0_VAL_162MHz:
- .word 0x28923211
+SDTIM0_VAL:
+ .word CFG_DAVINCI_SDTIM0
SDTIM1:
.word 0x20000014
-SDTIM1_VAL_162MHz:
- .word 0x0016c722
+SDTIM1_VAL:
+ .word CFG_DAVINCI_SDTIM1
VTPIOCR:
.word 0x200000f0 /* VTP IO Control register */
DDRVTPR:
MMARG_BRF0:
.word 0x01c42010 /* BRF margin mode 0 (R/W)*/
MMARG_BRF0_VAL:
- .word 0x00444400
+ .word CFG_DAVINCI_MMARG_BRF0
DDR2_START_ADDR:
.word 0x80000000
dummy = emif_addr->NANDF3ECC;
dummy = emif_addr->NANDF4ECC;
- emif_addr->NANDFCR |= (1 << 8);
+ emif_addr->NANDFCR |= (1 << (CFG_DAVINCI_NANDCE + 6));
}
static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
n = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1;
- region = 1;
+ region = (CFG_DAVINCI_NANDCE - 1);
while (n--) {
tmp = nand_davinci_readecc(mtd, region);
*ecc_code++ = tmp;
static void nand_flash_init(void)
{
- u_int32_t acfg1 = 0x3ffffffc;
- u_int32_t acfg2 = 0x3ffffffc;
- u_int32_t acfg3 = 0x3ffffffc;
- u_int32_t acfg4 = 0x3ffffffc;
- emifregs emif_regs;
-
- /*------------------------------------------------------------------*
- * NAND FLASH CHIP TIMEOUT @ 459 MHz *
- * *
- * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
- * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
- * *
- *------------------------------------------------------------------*/
- acfg1 = 0
- | (0 << 31 ) /* selectStrobe */
- | (0 << 30 ) /* extWait */
- | (1 << 26 ) /* writeSetup 10 ns */
- | (3 << 20 ) /* writeStrobe 40 ns */
- | (1 << 17 ) /* writeHold 10 ns */
- | (1 << 13 ) /* readSetup 10 ns */
- | (5 << 7 ) /* readStrobe 60 ns */
- | (1 << 4 ) /* readHold 10 ns */
- | (3 << 2 ) /* turnAround ?? ns */
- | (0 << 0 ) /* asyncSize 8-bit bus */
- ;
-
- emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
-
- emif_regs->AWCCR |= 0x10000000;
- emif_regs->AB1CR = acfg1; /* 0x08244128 */;
- emif_regs->AB2CR = acfg2;
- emif_regs->AB3CR = acfg3;
- emif_regs->AB4CR = acfg4;
- emif_regs->NANDFCR = 0x00000101;
+ /* All EMIF initialization is done in lowlevel_init.S
+ * and config values are in the board config files
+ */
}
int board_nand_init(struct nand_chip *nand)
typedef volatile struct {
u_int32_t pid12;
- u_int32_t emumgt_clksped;
- u_int32_t gpint_en;
- u_int32_t gpdir_dat;
+ u_int32_t emumgt;
+ u_int32_t na1;
+ u_int32_t na2;
u_int32_t tim12;
u_int32_t tim34;
u_int32_t prd12;
u_int32_t tcr;
u_int32_t tgcr;
u_int32_t wdtcr;
- u_int32_t tlgc;
- u_int32_t tlmr;
} davinci_timer;
davinci_timer *timer = (davinci_timer *)CFG_TIMERBASE;
#define TIMER_LOAD_VAL (CFG_HZ_CLOCK / CFG_HZ)
-#define READ_TIMER timer->tim34
-
-/*
- * Timer runs with CFG_HZ_CLOCK, currently 27MHz. To avoid wrap
- * around of timestamp already after min ~159s, divide it, e.g. by 16.
- * timestamp will then wrap around all min ~42min
- */
-#define DIV(x) ((x) >> 4)
+#define TIM_CLK_DIV 16
static ulong timestamp;
static ulong lastinc;
/* We are using timer34 in unchained 32-bit mode, full speed */
timer->tcr = 0x0;
timer->tgcr = 0x0;
- timer->tgcr = 0x06;
+ timer->tgcr = 0x06 | ((TIM_CLK_DIV - 1) << 8);
timer->tim34 = 0x0;
timer->prd34 = TIMER_LOAD_VAL;
lastinc = 0;
- timer->tcr = 0x80 << 16;
timestamp = 0;
+ timer->tcr = 2 << 22;
return(0);
}
void reset_timer(void)
{
- reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
- return(get_timer_masked() - base);
-}
-
-void set_timer(ulong t)
-{
- timestamp = t;
-}
-
-void udelay(unsigned long usec)
-{
- udelay_masked(usec);
-}
-
-void reset_timer_masked(void)
-{
- lastinc = DIV(READ_TIMER);
+ timer->tcr = 0x0;
+ timer->tim34 = 0;
+ lastinc = 0;
timestamp = 0;
+ timer->tcr = 2 << 22;
}
-ulong get_timer_raw(void)
+static ulong get_timer_raw(void)
{
- ulong now = DIV(READ_TIMER);
+ ulong now = timer->tim34;
if (now >= lastinc) {
/* normal mode */
timestamp += now - lastinc;
} else {
/* overflow ... */
- timestamp += now + DIV(TIMER_LOAD_VAL) - lastinc;
+ timestamp += now + TIMER_LOAD_VAL - lastinc;
}
lastinc = now;
return timestamp;
}
-ulong get_timer_masked(void)
+ulong get_timer(ulong base)
+{
+ return((get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base); }
+
+void set_timer(ulong t)
{
- return(get_timer_raw() / DIV(TIMER_LOAD_VAL));
+ timestamp = t;
}
-void udelay_masked(unsigned long usec)
+void udelay(unsigned long usec)
{
ulong tmo;
ulong endtime;
tmo = CFG_HZ_CLOCK / 1000;
tmo *= usec;
- tmo /= 1000;
+ tmo /= (1000 * TIM_CLK_DIV);
endtime = get_timer_raw() + tmo;
*/
ulong get_tbclk(void)
{
- ulong tbclk;
-
- tbclk = CFG_HZ;
- return(tbclk);
+ return CFG_HZ;
}
COBJS-y += omap1510_i2c.o
COBJS-y += omap24xx_i2c.o
COBJS-y += tsi108_i2c.o
+COBJS-y += mxc_i2c.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * i2c driver for Freescale mx31
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_HARD_I2C) && defined(CONFIG_I2C_MXC)
+
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+#define IADR 0x00
+#define IFDR 0x04
+#define I2CR 0x08
+#define I2SR 0x0c
+#define I2DR 0x10
+
+#define I2CR_IEN (1 << 7)
+#define I2CR_IIEN (1 << 6)
+#define I2CR_MSTA (1 << 5)
+#define I2CR_MTX (1 << 4)
+#define I2CR_TX_NO_AK (1 << 3)
+#define I2CR_RSTA (1 << 2)
+
+#define I2SR_ICF (1 << 7)
+#define I2SR_IBB (1 << 5)
+#define I2SR_IIF (1 << 1)
+#define I2SR_RX_NO_AK (1 << 0)
+
+#ifdef CFG_I2C_MX31_PORT1
+#define I2C_BASE 0x43f80000
+#elif defined(CFG_I2C_MX31_PORT2)
+#define I2C_BASE 0x43f98000
+#elif defined(CFG_I2C_MX31_PORT3)
+#define I2C_BASE 0x43f84000
+#else
+#error "define CFG_I2C_MX31_PORTx to use the mx31 I2C driver"
+#endif
+
+#ifdef DEBUG
+#define DPRINTF(args...) printf(args)
+#else
+#define DPRINTF(args...)
+#endif
+
+static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144,
+ 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960,
+ 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840};
+
+void i2c_init(int speed, int unused)
+{
+ int freq = mx31_get_ipg_clk();
+ int i;
+
+ for (i = 0; i < 0x1f; i++)
+ if (freq / div[i] <= speed)
+ break;
+
+ DPRINTF("%s: speed: %d\n", __FUNCTION__, speed);
+
+ __REG16(I2C_BASE + I2CR) = 0; /* Reset module */
+ __REG16(I2C_BASE + IFDR) = i;
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN;
+ __REG16(I2C_BASE + I2SR) = 0;
+}
+
+static int wait_busy(void)
+{
+ int timeout = 10000;
+
+ while (!(__REG16(I2C_BASE + I2SR) & I2SR_IIF) && --timeout)
+ udelay(1);
+ __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */
+
+ return timeout;
+}
+
+static int tx_byte(u8 byte)
+{
+ __REG16(I2C_BASE + I2DR) = byte;
+
+ if (!wait_busy() || __REG16(I2C_BASE + I2SR) & I2SR_RX_NO_AK)
+ return -1;
+ return 0;
+}
+
+static int rx_byte(void)
+{
+ if (!wait_busy())
+ return -1;
+
+ return __REG16(I2C_BASE + I2DR);
+}
+
+int i2c_probe(uchar chip)
+{
+ int ret;
+
+ __REG16(I2C_BASE + I2CR) = 0; /* Reset module */
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN;
+
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX;
+ ret = tx_byte(chip << 1);
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MTX;
+
+ return ret;
+}
+
+static int i2c_addr(uchar chip, uint addr, int alen)
+{
+ __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX;
+
+ if (tx_byte(chip << 1))
+ return -1;
+
+ while (alen--)
+ if (tx_byte((addr >> (alen * 8)) & 0xff))
+ return -1;
+ return 0;
+}
+
+int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+ int timeout = 10000;
+ int ret;
+
+ DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: +%d\n", \
+ __FUNCTION__, chip, addr, alen, len);
+
+ if (i2c_addr(chip, addr, alen)) {
+ printf("i2c_addr failed\n");
+ return -1;
+ }
+
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | \
+ I2CR_MTX | I2CR_RSTA;
+
+ if (tx_byte(chip << 1 | 1))
+ return -1;
+
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | ((len == 1) \
+ ? I2CR_TX_NO_AK : 0);
+
+ ret = __REG16(I2C_BASE + I2DR);
+
+ while (len--) {
+ if ((ret = rx_byte()) < 0)
+ return -1;
+ *buf++ = ret;
+ if (len <= 1)
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN | \
+ I2CR_MSTA | I2CR_TX_NO_AK;
+ }
+
+ wait_busy();
+
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN;
+
+ while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
+ udelay(1);
+
+ return 0;
+}
+
+int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+ int timeout = 10000;
+ DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", \
+ __FUNCTION__, chip, addr, alen, len);
+
+ if (i2c_addr(chip, addr, alen))
+ return -1;
+
+ while (len--)
+ if (tx_byte(*buf++))
+ return -1;
+
+ __REG16(I2C_BASE + I2CR) = I2CR_IEN;
+
+ while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
+ udelay(1);
+
+ return 0;
+}
+
+#endif /* CONFIG_HARD_I2C */
COBJS-y += rtl8169.o
COBJS-y += s3c4510b_eth.o
COBJS-y += smc91111.o
+COBJS-y += smc911x.o
COBJS-y += tigon3.o
COBJS-y += tsec.o
COBJS-y += tsi108_eth.o
--- /dev/null
+/*
+ * SMSC LAN9[12]1[567] Network driver
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_DRIVER_SMC911X
+
+#include <command.h>
+#include <net.h>
+#include <miiphy.h>
+
+#define mdelay(n) udelay((n)*1000)
+
+#define __REG(x) (*((volatile u32 *)(x)))
+
+/* Below are the register offsets and bit definitions
+ * of the Lan911x memory space
+ */
+#define RX_DATA_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x00)
+
+#define TX_DATA_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x20)
+#define TX_CMD_A_INT_ON_COMP (0x80000000)
+#define TX_CMD_A_INT_BUF_END_ALGN (0x03000000)
+#define TX_CMD_A_INT_4_BYTE_ALGN (0x00000000)
+#define TX_CMD_A_INT_16_BYTE_ALGN (0x01000000)
+#define TX_CMD_A_INT_32_BYTE_ALGN (0x02000000)
+#define TX_CMD_A_INT_DATA_OFFSET (0x001F0000)
+#define TX_CMD_A_INT_FIRST_SEG (0x00002000)
+#define TX_CMD_A_INT_LAST_SEG (0x00001000)
+#define TX_CMD_A_BUF_SIZE (0x000007FF)
+#define TX_CMD_B_PKT_TAG (0xFFFF0000)
+#define TX_CMD_B_ADD_CRC_DISABLE (0x00002000)
+#define TX_CMD_B_DISABLE_PADDING (0x00001000)
+#define TX_CMD_B_PKT_BYTE_LENGTH (0x000007FF)
+
+#define RX_STATUS_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x40)
+#define RX_STS_PKT_LEN (0x3FFF0000)
+#define RX_STS_ES (0x00008000)
+#define RX_STS_BCST (0x00002000)
+#define RX_STS_LEN_ERR (0x00001000)
+#define RX_STS_RUNT_ERR (0x00000800)
+#define RX_STS_MCAST (0x00000400)
+#define RX_STS_TOO_LONG (0x00000080)
+#define RX_STS_COLL (0x00000040)
+#define RX_STS_ETH_TYPE (0x00000020)
+#define RX_STS_WDOG_TMT (0x00000010)
+#define RX_STS_MII_ERR (0x00000008)
+#define RX_STS_DRIBBLING (0x00000004)
+#define RX_STS_CRC_ERR (0x00000002)
+#define RX_STATUS_FIFO_PEEK __REG(CONFIG_DRIVER_SMC911X_BASE + 0x44)
+#define TX_STATUS_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x48)
+#define TX_STS_TAG (0xFFFF0000)
+#define TX_STS_ES (0x00008000)
+#define TX_STS_LOC (0x00000800)
+#define TX_STS_NO_CARR (0x00000400)
+#define TX_STS_LATE_COLL (0x00000200)
+#define TX_STS_MANY_COLL (0x00000100)
+#define TX_STS_COLL_CNT (0x00000078)
+#define TX_STS_MANY_DEFER (0x00000004)
+#define TX_STS_UNDERRUN (0x00000002)
+#define TX_STS_DEFERRED (0x00000001)
+#define TX_STATUS_FIFO_PEEK __REG(CONFIG_DRIVER_SMC911X_BASE + 0x4C)
+#define ID_REV __REG(CONFIG_DRIVER_SMC911X_BASE + 0x50)
+#define ID_REV_CHIP_ID (0xFFFF0000) /* RO */
+#define ID_REV_REV_ID (0x0000FFFF) /* RO */
+
+#define INT_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x54)
+#define INT_CFG_INT_DEAS (0xFF000000) /* R/W */
+#define INT_CFG_INT_DEAS_CLR (0x00004000)
+#define INT_CFG_INT_DEAS_STS (0x00002000)
+#define INT_CFG_IRQ_INT (0x00001000) /* RO */
+#define INT_CFG_IRQ_EN (0x00000100) /* R/W */
+#define INT_CFG_IRQ_POL (0x00000010) /* R/W */
+ /* Not Affected by SW Reset */
+#define INT_CFG_IRQ_TYPE (0x00000001) /* R/W */
+ /* Not Affected by SW Reset */
+
+#define INT_STS __REG(CONFIG_DRIVER_SMC911X_BASE + 0x58)
+#define INT_STS_SW_INT (0x80000000) /* R/WC */
+#define INT_STS_TXSTOP_INT (0x02000000) /* R/WC */
+#define INT_STS_RXSTOP_INT (0x01000000) /* R/WC */
+#define INT_STS_RXDFH_INT (0x00800000) /* R/WC */
+#define INT_STS_RXDF_INT (0x00400000) /* R/WC */
+#define INT_STS_TX_IOC (0x00200000) /* R/WC */
+#define INT_STS_RXD_INT (0x00100000) /* R/WC */
+#define INT_STS_GPT_INT (0x00080000) /* R/WC */
+#define INT_STS_PHY_INT (0x00040000) /* RO */
+#define INT_STS_PME_INT (0x00020000) /* R/WC */
+#define INT_STS_TXSO (0x00010000) /* R/WC */
+#define INT_STS_RWT (0x00008000) /* R/WC */
+#define INT_STS_RXE (0x00004000) /* R/WC */
+#define INT_STS_TXE (0x00002000) /* R/WC */
+/*#define INT_STS_ERX (0x00001000)*/ /* R/WC */
+#define INT_STS_TDFU (0x00000800) /* R/WC */
+#define INT_STS_TDFO (0x00000400) /* R/WC */
+#define INT_STS_TDFA (0x00000200) /* R/WC */
+#define INT_STS_TSFF (0x00000100) /* R/WC */
+#define INT_STS_TSFL (0x00000080) /* R/WC */
+/*#define INT_STS_RXDF (0x00000040)*/ /* R/WC */
+#define INT_STS_RDFO (0x00000040) /* R/WC */
+#define INT_STS_RDFL (0x00000020) /* R/WC */
+#define INT_STS_RSFF (0x00000010) /* R/WC */
+#define INT_STS_RSFL (0x00000008) /* R/WC */
+#define INT_STS_GPIO2_INT (0x00000004) /* R/WC */
+#define INT_STS_GPIO1_INT (0x00000002) /* R/WC */
+#define INT_STS_GPIO0_INT (0x00000001) /* R/WC */
+#define INT_EN __REG(CONFIG_DRIVER_SMC911X_BASE + 0x5C)
+#define INT_EN_SW_INT_EN (0x80000000) /* R/W */
+#define INT_EN_TXSTOP_INT_EN (0x02000000) /* R/W */
+#define INT_EN_RXSTOP_INT_EN (0x01000000) /* R/W */
+#define INT_EN_RXDFH_INT_EN (0x00800000) /* R/W */
+/*#define INT_EN_RXDF_INT_EN (0x00400000)*/ /* R/W */
+#define INT_EN_TIOC_INT_EN (0x00200000) /* R/W */
+#define INT_EN_RXD_INT_EN (0x00100000) /* R/W */
+#define INT_EN_GPT_INT_EN (0x00080000) /* R/W */
+#define INT_EN_PHY_INT_EN (0x00040000) /* R/W */
+#define INT_EN_PME_INT_EN (0x00020000) /* R/W */
+#define INT_EN_TXSO_EN (0x00010000) /* R/W */
+#define INT_EN_RWT_EN (0x00008000) /* R/W */
+#define INT_EN_RXE_EN (0x00004000) /* R/W */
+#define INT_EN_TXE_EN (0x00002000) /* R/W */
+/*#define INT_EN_ERX_EN (0x00001000)*/ /* R/W */
+#define INT_EN_TDFU_EN (0x00000800) /* R/W */
+#define INT_EN_TDFO_EN (0x00000400) /* R/W */
+#define INT_EN_TDFA_EN (0x00000200) /* R/W */
+#define INT_EN_TSFF_EN (0x00000100) /* R/W */
+#define INT_EN_TSFL_EN (0x00000080) /* R/W */
+/*#define INT_EN_RXDF_EN (0x00000040)*/ /* R/W */
+#define INT_EN_RDFO_EN (0x00000040) /* R/W */
+#define INT_EN_RDFL_EN (0x00000020) /* R/W */
+#define INT_EN_RSFF_EN (0x00000010) /* R/W */
+#define INT_EN_RSFL_EN (0x00000008) /* R/W */
+#define INT_EN_GPIO2_INT (0x00000004) /* R/W */
+#define INT_EN_GPIO1_INT (0x00000002) /* R/W */
+#define INT_EN_GPIO0_INT (0x00000001) /* R/W */
+
+#define BYTE_TEST __REG(CONFIG_DRIVER_SMC911X_BASE + 0x64)
+#define FIFO_INT __REG(CONFIG_DRIVER_SMC911X_BASE + 0x68)
+#define FIFO_INT_TX_AVAIL_LEVEL (0xFF000000) /* R/W */
+#define FIFO_INT_TX_STS_LEVEL (0x00FF0000) /* R/W */
+#define FIFO_INT_RX_AVAIL_LEVEL (0x0000FF00) /* R/W */
+#define FIFO_INT_RX_STS_LEVEL (0x000000FF) /* R/W */
+
+#define RX_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x6C)
+#define RX_CFG_RX_END_ALGN (0xC0000000) /* R/W */
+#define RX_CFG_RX_END_ALGN4 (0x00000000) /* R/W */
+#define RX_CFG_RX_END_ALGN16 (0x40000000) /* R/W */
+#define RX_CFG_RX_END_ALGN32 (0x80000000) /* R/W */
+#define RX_CFG_RX_DMA_CNT (0x0FFF0000) /* R/W */
+#define RX_CFG_RX_DUMP (0x00008000) /* R/W */
+#define RX_CFG_RXDOFF (0x00001F00) /* R/W */
+/*#define RX_CFG_RXBAD (0x00000001)*/ /* R/W */
+
+#define TX_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x70)
+/*#define TX_CFG_TX_DMA_LVL (0xE0000000)*/ /* R/W */
+/*#define TX_CFG_TX_DMA_CNT (0x0FFF0000)*/ /* R/W */
+ /* Self Clearing */
+#define TX_CFG_TXS_DUMP (0x00008000)
+ /* Self Clearing */
+#define TX_CFG_TXD_DUMP (0x00004000)
+ /* Self Clearing */
+#define TX_CFG_TXSAO (0x00000004) /* R/W */
+#define TX_CFG_TX_ON (0x00000002) /* R/W */
+#define TX_CFG_STOP_TX (0x00000001)
+ /* Self Clearing */
+
+#define HW_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x74)
+#define HW_CFG_TTM (0x00200000) /* R/W */
+#define HW_CFG_SF (0x00100000) /* R/W */
+#define HW_CFG_TX_FIF_SZ (0x000F0000) /* R/W */
+#define HW_CFG_TR (0x00003000) /* R/W */
+#define HW_CFG_PHY_CLK_SEL (0x00000060) /* R/W */
+#define HW_CFG_PHY_CLK_SEL_INT_PHY (0x00000000) /* R/W */
+#define HW_CFG_PHY_CLK_SEL_EXT_PHY (0x00000020) /* R/W */
+#define HW_CFG_PHY_CLK_SEL_CLK_DIS (0x00000040) /* R/W */
+#define HW_CFG_SMI_SEL (0x00000010) /* R/W */
+#define HW_CFG_EXT_PHY_DET (0x00000008) /* RO */
+#define HW_CFG_EXT_PHY_EN (0x00000004) /* R/W */
+#define HW_CFG_32_16_BIT_MODE (0x00000004) /* RO */
+#define HW_CFG_SRST_TO (0x00000002) /* RO */
+#define HW_CFG_SRST (0x00000001)
+ /* Self Clearing */
+
+#define RX_DP_CTRL __REG(CONFIG_DRIVER_SMC911X_BASE + 0x78)
+#define RX_DP_CTRL_RX_FFWD (0x80000000) /* R/W */
+#define RX_DP_CTRL_FFWD_BUSY (0x80000000) /* RO */
+
+#define RX_FIFO_INF __REG(CONFIG_DRIVER_SMC911X_BASE + 0x7C)
+#define RX_FIFO_INF_RXSUSED (0x00FF0000) /* RO */
+#define RX_FIFO_INF_RXDUSED (0x0000FFFF) /* RO */
+
+#define TX_FIFO_INF __REG(CONFIG_DRIVER_SMC911X_BASE + 0x80)
+#define TX_FIFO_INF_TSUSED (0x00FF0000) /* RO */
+#define TX_FIFO_INF_TDFREE (0x0000FFFF) /* RO */
+
+#define PMT_CTRL __REG(CONFIG_DRIVER_SMC911X_BASE + 0x84)
+#define PMT_CTRL_PM_MODE (0x00003000)
+ /* Self Clearing */
+#define PMT_CTRL_PHY_RST (0x00000400)
+ /* Self Clearing */
+#define PMT_CTRL_WOL_EN (0x00000200) /* R/W */
+#define PMT_CTRL_ED_EN (0x00000100) /* R/W */
+#define PMT_CTRL_PME_TYPE (0x00000040) /* R/W */
+ /* Not Affected by SW Reset */
+#define PMT_CTRL_WUPS (0x00000030) /* R/WC */
+#define PMT_CTRL_WUPS_NOWAKE (0x00000000) /* R/WC */
+#define PMT_CTRL_WUPS_ED (0x00000010) /* R/WC */
+#define PMT_CTRL_WUPS_WOL (0x00000020) /* R/WC */
+#define PMT_CTRL_WUPS_MULTI (0x00000030) /* R/WC */
+#define PMT_CTRL_PME_IND (0x00000008) /* R/W */
+#define PMT_CTRL_PME_POL (0x00000004) /* R/W */
+#define PMT_CTRL_PME_EN (0x00000002) /* R/W */
+ /* Not Affected by SW Reset */
+#define PMT_CTRL_READY (0x00000001) /* RO */
+
+#define GPIO_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x88)
+#define GPIO_CFG_LED3_EN (0x40000000) /* R/W */
+#define GPIO_CFG_LED2_EN (0x20000000) /* R/W */
+#define GPIO_CFG_LED1_EN (0x10000000) /* R/W */
+#define GPIO_CFG_GPIO2_INT_POL (0x04000000) /* R/W */
+#define GPIO_CFG_GPIO1_INT_POL (0x02000000) /* R/W */
+#define GPIO_CFG_GPIO0_INT_POL (0x01000000) /* R/W */
+#define GPIO_CFG_EEPR_EN (0x00700000) /* R/W */
+#define GPIO_CFG_GPIOBUF2 (0x00040000) /* R/W */
+#define GPIO_CFG_GPIOBUF1 (0x00020000) /* R/W */
+#define GPIO_CFG_GPIOBUF0 (0x00010000) /* R/W */
+#define GPIO_CFG_GPIODIR2 (0x00000400) /* R/W */
+#define GPIO_CFG_GPIODIR1 (0x00000200) /* R/W */
+#define GPIO_CFG_GPIODIR0 (0x00000100) /* R/W */
+#define GPIO_CFG_GPIOD4 (0x00000010) /* R/W */
+#define GPIO_CFG_GPIOD3 (0x00000008) /* R/W */
+#define GPIO_CFG_GPIOD2 (0x00000004) /* R/W */
+#define GPIO_CFG_GPIOD1 (0x00000002) /* R/W */
+#define GPIO_CFG_GPIOD0 (0x00000001) /* R/W */
+
+#define GPT_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x8C)
+#define GPT_CFG_TIMER_EN (0x20000000) /* R/W */
+#define GPT_CFG_GPT_LOAD (0x0000FFFF) /* R/W */
+
+#define GPT_CNT __REG(CONFIG_DRIVER_SMC911X_BASE + 0x90)
+#define GPT_CNT_GPT_CNT (0x0000FFFF) /* RO */
+
+#define ENDIAN __REG(CONFIG_DRIVER_SMC911X_BASE + 0x98)
+#define FREE_RUN __REG(CONFIG_DRIVER_SMC911X_BASE + 0x9C)
+#define RX_DROP __REG(CONFIG_DRIVER_SMC911X_BASE + 0xA0)
+#define MAC_CSR_CMD __REG(CONFIG_DRIVER_SMC911X_BASE + 0xA4)
+#define MAC_CSR_CMD_CSR_BUSY (0x80000000)
+ /* Self Clearing */
+#define MAC_CSR_CMD_R_NOT_W (0x40000000) /* R/W */
+#define MAC_CSR_CMD_CSR_ADDR (0x000000FF) /* R/W */
+
+#define MAC_CSR_DATA __REG(CONFIG_DRIVER_SMC911X_BASE + 0xA8)
+#define AFC_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0xAC)
+#define AFC_CFG_AFC_HI (0x00FF0000) /* R/W */
+#define AFC_CFG_AFC_LO (0x0000FF00) /* R/W */
+#define AFC_CFG_BACK_DUR (0x000000F0) /* R/W */
+#define AFC_CFG_FCMULT (0x00000008) /* R/W */
+#define AFC_CFG_FCBRD (0x00000004) /* R/W */
+#define AFC_CFG_FCADD (0x00000002) /* R/W */
+#define AFC_CFG_FCANY (0x00000001) /* R/W */
+
+#define E2P_CMD __REG(CONFIG_DRIVER_SMC911X_BASE + 0xB0)
+#define E2P_CMD_EPC_BUSY (0x80000000)
+ /* Self Clearing */
+#define E2P_CMD_EPC_CMD (0x70000000) /* R/W */
+#define E2P_CMD_EPC_CMD_READ (0x00000000) /* R/W */
+#define E2P_CMD_EPC_CMD_EWDS (0x10000000) /* R/W */
+#define E2P_CMD_EPC_CMD_EWEN (0x20000000) /* R/W */
+#define E2P_CMD_EPC_CMD_WRITE (0x30000000) /* R/W */
+#define E2P_CMD_EPC_CMD_WRAL (0x40000000) /* R/W */
+#define E2P_CMD_EPC_CMD_ERASE (0x50000000) /* R/W */
+#define E2P_CMD_EPC_CMD_ERAL (0x60000000) /* R/W */
+#define E2P_CMD_EPC_CMD_RELOAD (0x70000000) /* R/W */
+#define E2P_CMD_EPC_TIMEOUT (0x00000200) /* RO */
+#define E2P_CMD_MAC_ADDR_LOADED (0x00000100) /* RO */
+#define E2P_CMD_EPC_ADDR (0x000000FF) /* R/W */
+
+#define E2P_DATA __REG(CONFIG_DRIVER_SMC911X_BASE + 0xB4)
+#define E2P_DATA_EEPROM_DATA (0x000000FF) /* R/W */
+/* end of LAN register offsets and bit definitions */
+
+/* MAC Control and Status registers */
+#define MAC_CR (0x01) /* R/W */
+
+/* MAC_CR - MAC Control Register */
+#define MAC_CR_RXALL (0x80000000)
+/* TODO: delete this bit? It is not described in the data sheet. */
+#define MAC_CR_HBDIS (0x10000000)
+#define MAC_CR_RCVOWN (0x00800000)
+#define MAC_CR_LOOPBK (0x00200000)
+#define MAC_CR_FDPX (0x00100000)
+#define MAC_CR_MCPAS (0x00080000)
+#define MAC_CR_PRMS (0x00040000)
+#define MAC_CR_INVFILT (0x00020000)
+#define MAC_CR_PASSBAD (0x00010000)
+#define MAC_CR_HFILT (0x00008000)
+#define MAC_CR_HPFILT (0x00002000)
+#define MAC_CR_LCOLL (0x00001000)
+#define MAC_CR_BCAST (0x00000800)
+#define MAC_CR_DISRTY (0x00000400)
+#define MAC_CR_PADSTR (0x00000100)
+#define MAC_CR_BOLMT_MASK (0x000000C0)
+#define MAC_CR_DFCHK (0x00000020)
+#define MAC_CR_TXEN (0x00000008)
+#define MAC_CR_RXEN (0x00000004)
+
+#define ADDRH (0x02) /* R/W mask 0x0000FFFFUL */
+#define ADDRL (0x03) /* R/W mask 0xFFFFFFFFUL */
+#define HASHH (0x04) /* R/W */
+#define HASHL (0x05) /* R/W */
+
+#define MII_ACC (0x06) /* R/W */
+#define MII_ACC_PHY_ADDR (0x0000F800)
+#define MII_ACC_MIIRINDA (0x000007C0)
+#define MII_ACC_MII_WRITE (0x00000002)
+#define MII_ACC_MII_BUSY (0x00000001)
+
+#define MII_DATA (0x07) /* R/W mask 0x0000FFFFUL */
+
+#define FLOW (0x08) /* R/W */
+#define FLOW_FCPT (0xFFFF0000)
+#define FLOW_FCPASS (0x00000004)
+#define FLOW_FCEN (0x00000002)
+#define FLOW_FCBSY (0x00000001)
+
+#define VLAN1 (0x09) /* R/W mask 0x0000FFFFUL */
+#define VLAN1_VTI1 (0x0000ffff)
+
+#define VLAN2 (0x0A) /* R/W mask 0x0000FFFFUL */
+#define VLAN2_VTI2 (0x0000ffff)
+
+#define WUFF (0x0B) /* WO */
+
+#define WUCSR (0x0C) /* R/W */
+#define WUCSR_GUE (0x00000200)
+#define WUCSR_WUFR (0x00000040)
+#define WUCSR_MPR (0x00000020)
+#define WUCSR_WAKE_EN (0x00000004)
+#define WUCSR_MPEN (0x00000002)
+
+/* Chip ID values */
+#define CHIP_9115 0x115
+#define CHIP_9116 0x116
+#define CHIP_9117 0x117
+#define CHIP_9118 0x118
+#define CHIP_9215 0x115a
+#define CHIP_9216 0x116a
+#define CHIP_9217 0x117a
+#define CHIP_9218 0x118a
+
+struct chip_id {
+ u16 id;
+ char *name;
+};
+
+static const struct chip_id chip_ids[] = {
+ { CHIP_9115, "LAN9115" },
+ { CHIP_9116, "LAN9116" },
+ { CHIP_9117, "LAN9117" },
+ { CHIP_9118, "LAN9118" },
+ { CHIP_9215, "LAN9215" },
+ { CHIP_9216, "LAN9216" },
+ { CHIP_9217, "LAN9217" },
+ { CHIP_9218, "LAN9218" },
+ { 0, NULL },
+};
+
+#define DRIVERNAME "smc911x"
+
+u32 smc911x_get_mac_csr(u8 reg)
+{
+ while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY);
+ MAC_CSR_CMD = MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg;
+ while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY);
+
+ return MAC_CSR_DATA;
+}
+
+void smc911x_set_mac_csr(u8 reg, u32 data)
+{
+ while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY);
+ MAC_CSR_DATA = data;
+ MAC_CSR_CMD = MAC_CSR_CMD_CSR_BUSY | reg;
+ while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY); }
+
+static int smx911x_handle_mac_address(bd_t *bd)
+{
+ unsigned long addrh, addrl;
+ unsigned char *m = bd->bi_enetaddr;
+
+ /* if the environment has a valid mac address then use it */
+ if ((m[0] | m[1] | m[2] | m[3] | m[4] | m[5])) {
+ addrl = m[0] | m[1] << 8 | m[2] << 16 | m[3] << 24;
+ addrh = m[4] | m[5] << 8;
+ smc911x_set_mac_csr(ADDRH, addrh);
+ smc911x_set_mac_csr(ADDRL, addrl);
+ } else {
+ /* if not, try to get one from the eeprom */
+ addrh = smc911x_get_mac_csr(ADDRH);
+ addrl = smc911x_get_mac_csr(ADDRL);
+
+ m[0] = (addrl) & 0xff;
+ m[1] = (addrl >> 8) & 0xff;
+ m[2] = (addrl >> 16) & 0xff;
+ m[3] = (addrl >> 24) & 0xff;
+ m[4] = (addrh) & 0xff;
+ m[5] = (addrh >> 8) & 0xff;
+
+ /* we get 0xff when there is no eeprom connected */
+ if ((m[0] & m[1] & m[2] & m[3] & m[4] & m[5]) == 0xff) {
+ printf(DRIVERNAME ": no valid mac address "
+ "in environment "
+ "and no eeprom found\n");
+ return -1;
+ }
+ }
+
+ printf(DRIVERNAME ": MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
+ m[0], m[1], m[2], m[3], m[4], m[5]);
+
+ return 0;
+}
+
+static int smc911x_miiphy_read(u8 phy, u8 reg, u16 *val)
+{
+ while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY);
+
+ smc911x_set_mac_csr(MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY);
+
+ while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY);
+
+ *val = smc911x_get_mac_csr(MII_DATA);
+
+ return 0;
+}
+
+static int smc911x_miiphy_write(u8 phy, u8 reg, u16 val)
+{
+ while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY);
+
+ smc911x_set_mac_csr(MII_DATA, val);
+ smc911x_set_mac_csr(MII_ACC,
+ phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE);
+
+ while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY);
+ return 0;
+}
+
+static int smc911x_phy_reset(void)
+{
+ u32 reg;
+
+ reg = PMT_CTRL;
+ reg &= ~0xfffff030;
+ reg |= PMT_CTRL_PHY_RST;
+ PMT_CTRL = reg;
+
+ mdelay(100);
+
+ return 0;
+}
+
+static void smc911x_phy_configure(void)
+{
+ int timeout;
+ u16 status;
+
+ smc911x_phy_reset();
+
+ smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_RESET);
+ mdelay(1);
+ smc911x_miiphy_write(1, PHY_ANAR, 0x01e1);
+ smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+
+ timeout = 5000;
+ do {
+ mdelay(1);
+ if ((timeout--) == 0)
+ goto err_out;
+
+ if (smc911x_miiphy_read(1, PHY_BMSR, &status) != 0)
+ goto err_out;
+ } while (!(status & PHY_BMSR_LS));
+
+ printf(DRIVERNAME ": phy initialized\n");
+
+ return;
+
+err_out:
+ printf(DRIVERNAME ": autonegotiation timed out\n"); }
+
+static void smc911x_reset(void)
+{
+ int timeout;
+
+ /* Take out of PM setting first */
+ if (PMT_CTRL & PMT_CTRL_READY) {
+ /* Write to the bytetest will take out of powerdown */
+ BYTE_TEST = 0x0;
+
+ timeout = 10;
+
+ while (timeout-- && !(PMT_CTRL & PMT_CTRL_READY))
+ udelay(10);
+ if (!timeout) {
+ printf(DRIVERNAME
+ ": timeout waiting for PM restore\n");
+ return;
+ }
+ }
+
+ /* Disable interrupts */
+ INT_EN = 0;
+
+ HW_CFG = HW_CFG_SRST;
+
+ timeout = 1000;
+ while (timeout-- && E2P_CMD & E2P_CMD_EPC_BUSY)
+ udelay(10);
+
+ if (!timeout) {
+ printf(DRIVERNAME ": reset timeout\n");
+ return;
+ }
+
+ /* Reset the FIFO level and flow control settings */
+ smc911x_set_mac_csr(FLOW, FLOW_FCPT | FLOW_FCEN);
+ AFC_CFG = 0x0050287F;
+
+ /* Set to LED outputs */
+ GPIO_CFG = 0x70070000;
+}
+
+static void smc911x_enable(void)
+{
+ /* Enable TX */
+ HW_CFG = 8 << 16 | HW_CFG_SF;
+
+ GPT_CFG = GPT_CFG_TIMER_EN | 10000;
+
+ TX_CFG = TX_CFG_TX_ON;
+
+ /* no padding to start of packets */
+ RX_CFG = 0;
+
+ smc911x_set_mac_csr(MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS);
+
+}
+
+int eth_init(bd_t *bd)
+{
+ unsigned long val, i;
+
+ printf(DRIVERNAME ": initializing\n");
+
+ val = BYTE_TEST;
+ if (val != 0x87654321) {
+ printf(DRIVERNAME ": Invalid chip endian 0x08%x\n", val);
+ goto err_out;
+ }
+
+ val = ID_REV >> 16;
+ for (i = 0; chip_ids[i].id != 0; i++) {
+ if (chip_ids[i].id == val)
+ break;
+ }
+ if (!chip_ids[i].id) {
+ printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
+ goto err_out;
+ }
+
+ printf(DRIVERNAME ": detected %s controller\n", chip_ids[i].name);
+
+ smc911x_reset();
+
+ /* Configure the PHY, initialize the link state */
+ smc911x_phy_configure();
+
+ if (smx911x_handle_mac_address(bd))
+ goto err_out;
+
+ /* Turn on Tx + Rx */
+ smc911x_enable();
+
+ return 0;
+
+err_out:
+ return -1;
+}
+
+int eth_send(volatile void *packet, int length)
+{
+ u32 *data = (u32 *)packet;
+ u32 tmplen;
+ u32 status;
+
+ TX_DATA_FIFO = TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length;
+ TX_DATA_FIFO = length;
+
+ tmplen = (length + 3) / 4;
+
+ while (tmplen--)
+ TX_DATA_FIFO = *data++;
+
+ /* wait for transmission */
+ while (!((TX_FIFO_INF & TX_FIFO_INF_TSUSED) >> 16));
+
+ /* get status. Ignore 'no carrier' error, it has no meaning for
+ * full duplex operation
+ */
+ status = TX_STATUS_FIFO & (TX_STS_LOC | TX_STS_LATE_COLL |
+ TX_STS_MANY_COLL | TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
+
+ if (!status)
+ return 0;
+
+ printf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n",
+ status & TX_STS_LOC ? "TX_STS_LOC " : "",
+ status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "",
+ status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "",
+ status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "",
+ status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : "");
+
+ return -1;
+}
+
+void eth_halt(void)
+{
+ smc911x_reset();
+}
+
+int eth_rx(void)
+{
+ u32 *data = (u32 *)NetRxPackets[0];
+ u32 pktlen, tmplen;
+ u32 status;
+
+ if ((RX_FIFO_INF & RX_FIFO_INF_RXSUSED) >> 16) {
+ status = RX_STATUS_FIFO;
+ pktlen = (status & RX_STS_PKT_LEN) >> 16;
+
+ RX_CFG = 0;
+
+ tmplen = (pktlen + 2 + 3) / 4;
+ while (tmplen--)
+ *data++ = RX_DATA_FIFO;
+
+ if (status & RX_STS_ES)
+ printf(DRIVERNAME
+ ": dropped bad packet. Status: 0x%08x\n",
+ status);
+ else
+ NetReceive(NetRxPackets[0], pktlen);
+ }
+
+ return 0;
+}
+
+#endif /* CONFIG_DRIVER_SMC911X */
+++ /dev/null
-/* bits.h
- * Copyright (c) 2004 Texas Instruments
- *
- * This package is free software; you can redistribute it and/or
- * modify it under the terms of the license found in the file
- * named COPYING that should have accompanied this file.
- *
- * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-#ifndef __bits_h
-#define __bits_h 1
-
-#define BIT0 (1<<0)
-#define BIT1 (1<<1)
-#define BIT2 (1<<2)
-#define BIT3 (1<<3)
-#define BIT4 (1<<4)
-#define BIT5 (1<<5)
-#define BIT6 (1<<6)
-#define BIT7 (1<<7)
-#define BIT8 (1<<8)
-#define BIT9 (1<<9)
-#define BIT10 (1<<10)
-#define BIT11 (1<<11)
-#define BIT12 (1<<12)
-#define BIT13 (1<<13)
-#define BIT14 (1<<14)
-#define BIT15 (1<<15)
-#define BIT16 (1<<16)
-#define BIT17 (1<<17)
-#define BIT18 (1<<18)
-#define BIT19 (1<<19)
-#define BIT20 (1<<20)
-#define BIT21 (1<<21)
-#define BIT22 (1<<22)
-#define BIT23 (1<<23)
-#define BIT24 (1<<24)
-#define BIT25 (1<<25)
-#define BIT26 (1<<26)
-#define BIT27 (1<<27)
-#define BIT28 (1<<28)
-#define BIT29 (1<<29)
-#define BIT30 (1<<30)
-#define BIT31 (1<<31)
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP24XX_CLOCKS_H_
-#define _OMAP24XX_CLOCKS_H_
-
-#define COMMIT_DIVIDERS 0x1
-
-#define MODE_BYPASS_FAST 0x2
-#define APLL_LOCK 0xc
-#ifdef CONFIG_APTIX
-#define DPLL_LOCK 0x1 /* stay in bypass mode */
-#else
-#define DPLL_LOCK 0x3 /* DPLL lock */
-#endif
-
-/****************************************************************************;
-; PRCM Scheme II
-;
-; Enable clocks and DPLL for:
-; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50
-; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
-; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0]
-; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0]
-; DSPI=100 6 CM_CLKSEL_DSP[6:5]
-; DSP_S bypass CM_CLKSEL_DSP[7]
-; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8]
-; IVAF=100 auto
-; IVAI auto
-; IVA_MPU auto
-; IVA_S bypass CM_CLKSEL_DSP[13]
-; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0]
-; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20]
-; SSI_SSTF=100 auto
-; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0]
-; L4=100Mhz 6
-; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5]
-***************************************************************************/
-#define II_DPLL_OUT_X2 0x2 /* x2 core out */
-#define II_MPU_DIV 0x2 /* mpu = core/2 */
-#define II_DSP_DIV 0x343 /* dsp & iva divider */
-#define II_GFX_DIV 0x2
-#define II_BUS_DIV 0x04601026
-#define II_DPLL_300 0x01832100
-
-/****************************************************************************;
-; PRCM Scheme III
-;
-; Enable clocks and DPLL for:
-; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266
-; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
-; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0]
-; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0]
-; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5]
-; DSP_S ACTIVATED CM_CLKSEL_DSP[7]
-; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8]
-; IVAF=88.67 auto
-; IVAI auto
-; IVA_MPU auto
-; IVA_S ACTIVATED CM_CLKSEL_DSP[13]
-; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]:
-; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20]
-; SSI_SSTF=88.67 auto
-; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0]
-; L4=66.5Mhz /8
-; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5]
-***************************************************************************/
-#define III_DPLL_OUT_X2 0x2 /* x2 core out */
-#define III_MPU_DIV 0x2 /* mpu = core/2 */
-#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/
-#define III_GFX_DIV 0x2
-#define III_BUS_DIV 0x08301044
-#define III_DPLL_266 0x01885500
-
-/* set defaults for boot up */
-#ifdef PRCM_CONFIG_II
-# define DPLL_OUT II_DPLL_OUT_X2
-# define MPU_DIV II_MPU_DIV
-# define DSP_DIV II_DSP_DIV
-# define GFX_DIV II_GFX_DIV
-# define BUS_DIV II_BUS_DIV
-# define DPLL_VAL II_DPLL_300
-#elif PRCM_CONFIG_III
-# define DPLL_OUT III_DPLL_OUT_X2
-# define MPU_DIV III_MPU_DIV
-# define DSP_DIV III_DSP_DIV
-# define GFX_DIV III_GFX_DIV
-# define BUS_DIV III_BUS_DIV
-# define DPLL_VAL III_DPLL_266
-#endif
-
-/* lock delay time out */
-#define LDELAY 12000000
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP24XX_I2C_H_
-#define _OMAP24XX_I2C_H_
-
-#define I2C_BASE 0x48070000
-#define I2C_BASE2 0x48072000 /* nothing hooked up on h4 */
-
-#define I2C_REV (I2C_BASE + 0x00)
-#define I2C_IE (I2C_BASE + 0x04)
-#define I2C_STAT (I2C_BASE + 0x08)
-#define I2C_IV (I2C_BASE + 0x0c)
-#define I2C_BUF (I2C_BASE + 0x14)
-#define I2C_CNT (I2C_BASE + 0x18)
-#define I2C_DATA (I2C_BASE + 0x1c)
-#define I2C_SYSC (I2C_BASE + 0x20)
-#define I2C_CON (I2C_BASE + 0x24)
-#define I2C_OA (I2C_BASE + 0x28)
-#define I2C_SA (I2C_BASE + 0x2c)
-#define I2C_PSC (I2C_BASE + 0x30)
-#define I2C_SCLL (I2C_BASE + 0x34)
-#define I2C_SCLH (I2C_BASE + 0x38)
-#define I2C_SYSTEST (I2C_BASE + 0x3c)
-
-/* I2C masks */
-
-/* I2C Interrupt Enable Register (I2C_IE): */
-#define I2C_IE_GC_IE (1 << 5)
-#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
-#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
-#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
-#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
-#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
-
-/* I2C Status Register (I2C_STAT): */
-
-#define I2C_STAT_SBD (1 << 15) /* Single byte data */
-#define I2C_STAT_BB (1 << 12) /* Bus busy */
-#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
-#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
-#define I2C_STAT_AAS (1 << 9) /* Address as slave */
-#define I2C_STAT_GC (1 << 5)
-#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
-#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
-#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
-#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
-#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
-
-
-/* I2C Interrupt Code Register (I2C_INTCODE): */
-
-#define I2C_INTCODE_MASK 7
-#define I2C_INTCODE_NONE 0
-#define I2C_INTCODE_AL 1 /* Arbitration lost */
-#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
-#define I2C_INTCODE_ARDY 3 /* Register access ready */
-#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
-#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
-
-/* I2C Buffer Configuration Register (I2C_BUF): */
-
-#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */
-#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */
-
-/* I2C Configuration Register (I2C_CON): */
-
-#define I2C_CON_EN (1 << 15) /* I2C module enable */
-#define I2C_CON_BE (1 << 14) /* Big endian mode */
-#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
-#define I2C_CON_MST (1 << 10) /* Master/slave mode */
-#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */
-#define I2C_CON_XA (1 << 8) /* Expand address */
-#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
-#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
-
-/* I2C System Test Register (I2C_SYSTEST): */
-
-#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
-#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */
-#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
-#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
-#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */
-#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */
-#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
-#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP24XX_MEM_H_
-#define _OMAP24XX_MEM_H_
-
-#define SDRC_CS0_OSET 0x0
-#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */
-
-#ifndef __ASSEMBLY__
-/* struct's for holding data tables for current boards, they are getting used
- early in init when NO global access are there */
-struct sdrc_data_s {
- u32 sdrc_sharing;
- u32 sdrc_mdcfg_0_ddr;
- u32 sdrc_mdcfg_0_sdr;
- u32 sdrc_actim_ctrla_0;
- u32 sdrc_actim_ctrlb_0;
- u32 sdrc_rfr_ctrl;
- u32 sdrc_mr_0_ddr;
- u32 sdrc_mr_0_sdr;
- u32 sdrc_dllab_ctrl;
-} /*__attribute__ ((packed))*/;
-typedef struct sdrc_data_s sdrc_data_t;
-
-typedef enum {
- STACKED = 0,
- IP_DDR = 1,
- COMBO_DDR = 2,
- IP_SDR = 3,
-} mem_t;
-
-#endif
-
-/* Slower full frequency range default timings for x32 operation*/
-#define H4_2420_SDRC_SHARING 0x00000100
-#define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */
-#define H4_2420_SDRC_MR_0_SDR 0x00000031
-#define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */
-#define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */
-#define H4_2420_SDRC_MR_0_DDR 0x00000032
-
-#define H4_2422_SDRC_SHARING 0x00004b00
-#define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked ddr on 2422 */
-#define H4_2422_SDRC_MR_0_DDR 0x00000032
-
-/* ES1 work around timings */
-#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */
-#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020
-#define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */
-
-/* optimized timings good for current shipping parts */
-#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485
-#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e
-#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */
-#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */
-#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01
-#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01
-#define H4_242x_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 72deg, allow DPLLout*1 to work (combo)*/
-#define H4_242x_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 72deg, for ES2 */
-
-#ifdef PRCM_CONFIG_II
-# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
-# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz
-# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
-# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz
-#elif PRCM_CONFIG_III
-# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
-# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
-# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz
-# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_133MHz
-# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
-# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz
-#endif
-
-
-/* GPMC settings */
-#ifdef PRCM_CONFIG_II /* L3 at 100MHz */
-# ifdef CFG_NAND_BOOT
-# define H4_24XX_GPMC_CONFIG1_0 0x0
-# define H4_24XX_GPMC_CONFIG2_0 0x00141400
-# define H4_24XX_GPMC_CONFIG3_0 0x00141400
-# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
-# define H4_24XX_GPMC_CONFIG5_0 0x010C1414
-# define H4_24XX_GPMC_CONFIG6_0 0x00000A80
-# else /* else NOR */
-# define H4_24XX_GPMC_CONFIG1_0 0x3
-# define H4_24XX_GPMC_CONFIG2_0 0x000f0f01
-# define H4_24XX_GPMC_CONFIG3_0 0x00050502
-# define H4_24XX_GPMC_CONFIG4_0 0x0C060C06
-# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
-# endif /* endif CFG_NAND_BOOT */
-# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
-# define H4_24XX_GPMC_CONFIG1_1 0x00011000
-# define H4_24XX_GPMC_CONFIG2_1 0x001F1F00
-# define H4_24XX_GPMC_CONFIG3_1 0x00080802
-# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
-# define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F
-# define H4_24XX_GPMC_CONFIG6_1 0x000003C2
-# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
-#endif /* endif PRCM_CONFIG_II */
-
-#ifdef PRCM_CONFIG_III /* L3 at 133MHz */
-# ifdef CFG_NAND_BOOT
-# define H4_24XX_GPMC_CONFIG1_0 0x0
-# define H4_24XX_GPMC_CONFIG2_0 0x00141400
-# define H4_24XX_GPMC_CONFIG3_0 0x00141400
-# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
-# define H4_24XX_GPMC_CONFIG5_0 0x010C1414
-# define H4_24XX_GPMC_CONFIG6_0 0x00000A80
-# else /* NOR boot */
-# define H4_24XX_GPMC_CONFIG1_0 0x3
-# define H4_24XX_GPMC_CONFIG2_0 0x00151501
-# define H4_24XX_GPMC_CONFIG3_0 0x00060602
-# define H4_24XX_GPMC_CONFIG4_0 0x10081008
-# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
-# define H4_24XX_GPMC_CONFIG6_0 0x000004c4
-# endif /* endif CFG_NAND_BOOT */
-# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
-# define H4_24XX_GPMC_CONFIG1_1 0x00011000
-# define H4_24XX_GPMC_CONFIG2_1 0x001f1f01
-# define H4_24XX_GPMC_CONFIG3_1 0x00080803
-# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
-# define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F
-# define H4_24XX_GPMC_CONFIG6_1 0x000004C4
-# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
-#endif /* endif CFG_PRCM_III */
-
-#endif /* endif _OMAP24XX_MEM_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP2420_MUX_H_
-#define _OMAP2420_MUX_H_
-
-#ifndef __ASSEMBLY__
-typedef unsigned char uint8;
-typedef unsigned int uint32;
-
-void muxSetupSDRC(void);
-void muxSetupGPMC(void);
-void muxSetupUsb0(void);
-void muxSetupUsbHost(void);
-void muxSetupUart3(void);
-void muxSetupI2C1(void);
-void muxSetupUART1(void);
-void muxSetupLCD(void);
-void muxSetupCamera(void);
-void muxSetupMMCSD(void) ;
-void muxSetupTouchScreen(void) ;
-void muxSetupHDQ(void);
-#endif
-
-#define USB_OTG_CTRL ((volatile uint32 *)0x4805E30C)
-
-/* Pin Muxing registers used for HDQ (Smart battery) */
-#define CONTROL_PADCONF_HDQ_SIO ((volatile unsigned char *)0x48000115)
-
-/* Pin Muxing registers used for GPMC */
-#define CONTROL_PADCONF_GPMC_D2_BYTE0 ((volatile unsigned char *)0x48000088)
-#define CONTROL_PADCONF_GPMC_D2_BYTE1 ((volatile unsigned char *)0x48000089)
-#define CONTROL_PADCONF_GPMC_D2_BYTE2 ((volatile unsigned char *)0x4800008A)
-#define CONTROL_PADCONF_GPMC_D2_BYTE3 ((volatile unsigned char *)0x4800008B)
-
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE0 ((volatile unsigned char *)0x4800008C)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE1 ((volatile unsigned char *)0x4800008D)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE2 ((volatile unsigned char *)0x4800008E)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE3 ((volatile unsigned char *)0x4800008F)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE4 (0x48000090)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE5 (0x48000091)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE6 (0x48000092)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE7 (0x48000093)
-
-/* Pin Muxing registers used for SDRC */
-#define CONTROL_PADCONF_SDRC_NCS0_BYTE0 ((volatile unsigned char *)0x480000A0)
-#define CONTROL_PADCONF_SDRC_NCS0_BYTE1 ((volatile unsigned char *)0x480000A1)
-#define CONTROL_PADCONF_SDRC_NCS0_BYTE2 ((volatile unsigned char *)0x480000A2)
-#define CONTROL_PADCONF_SDRC_NCS0_BYTE3 ((volatile unsigned char *)0x480000A3)
-
-#define CONTROL_PADCONF_SDRC_A14_BYTE0 ((volatile unsigned char *)0x48000030)
-#define CONTROL_PADCONF_SDRC_A14_BYTE1 ((volatile unsigned char *)0x48000031)
-#define CONTROL_PADCONF_SDRC_A14_BYTE2 ((volatile unsigned char *)0x48000032)
-#define CONTROL_PADCONF_SDRC_A14_BYTE3 ((volatile unsigned char *)0x48000033)
-
-/* Pin Muxing registers used for Touch Screen (SPI) */
-#define CONTROL_PADCONF_SPI1_CLK ((volatile unsigned char *)0x480000FF)
-#define CONTROL_PADCONF_SPI1_SIMO ((volatile unsigned char *)0x48000100)
-#define CONTROL_PADCONF_SPI1_SOMI ((volatile unsigned char *)0x48000101)
-#define CONTROL_PADCONF_SPI1_NCS0 ((volatile unsigned char *)0x48000102)
-#define CONTROL_PADCONF_SPI1_NCS1 (0x48000103)
-
-#define CONTROL_PADCONF_MCBSP1_FSR ((volatile unsigned char *)0x4800010B)
-
-/* Pin Muxing registers used for MMCSD */
-#define CONTROL_PADCONF_MMC_CLKI ((volatile unsigned char *)0x480000FE)
-#define CONTROL_PADCONF_MMC_CLKO ((volatile unsigned char *)0x480000F3)
-#define CONTROL_PADCONF_MMC_CMD ((volatile unsigned char *)0x480000F4)
-#define CONTROL_PADCONF_MMC_DAT0 ((volatile unsigned char *)0x480000F5)
-#define CONTROL_PADCONF_MMC_DAT1 ((volatile unsigned char *)0x480000F6)
-#define CONTROL_PADCONF_MMC_DAT2 ((volatile unsigned char *)0x480000F7)
-#define CONTROL_PADCONF_MMC_DAT3 ((volatile unsigned char *)0x480000F8)
-#define CONTROL_PADCONF_MMC_DAT_DIR0 ((volatile unsigned char *)0x480000F9)
-#define CONTROL_PADCONF_MMC_DAT_DIR1 ((volatile unsigned char *)0x480000FA)
-#define CONTROL_PADCONF_MMC_DAT_DIR2 ((volatile unsigned char *)0x480000FB)
-#define CONTROL_PADCONF_MMC_DAT_DIR3 ((volatile unsigned char *)0x480000FC)
-#define CONTROL_PADCONF_MMC_CMD_DIR ((volatile unsigned char *)0x480000FD)
-
-#define CONTROL_PADCONF_SDRC_A14 ((volatile unsigned char *)0x48000030)
-#define CONTROL_PADCONF_SDRC_A13 ((volatile unsigned char *)0x48000031)
-
-/* Pin Muxing registers used for CAMERA */
-#define CONTROL_PADCONF_SYS_NRESWARM ((volatile unsigned char *)0x4800012B)
-
-#define CONTROL_PADCONF_CAM_XCLK ((volatile unsigned char *)0x480000DC)
-#define CONTROL_PADCONF_CAM_LCLK ((volatile unsigned char *)0x480000DB)
-#define CONTROL_PADCONF_CAM_VS ((volatile unsigned char *)0x480000DA)
-#define CONTROL_PADCONF_CAM_HS ((volatile unsigned char *)0x480000D9)
-#define CONTROL_PADCONF_CAM_D0 ((volatile unsigned char *)0x480000D8)
-#define CONTROL_PADCONF_CAM_D1 ((volatile unsigned char *)0x480000D7)
-#define CONTROL_PADCONF_CAM_D2 ((volatile unsigned char *)0x480000D6)
-#define CONTROL_PADCONF_CAM_D3 ((volatile unsigned char *)0x480000D5)
-#define CONTROL_PADCONF_CAM_D4 ((volatile unsigned char *)0x480000D4)
-#define CONTROL_PADCONF_CAM_D5 ((volatile unsigned char *)0x480000D3)
-#define CONTROL_PADCONF_CAM_D6 ((volatile unsigned char *)0x480000D2)
-#define CONTROL_PADCONF_CAM_D7 ((volatile unsigned char *)0x480000D1)
-#define CONTROL_PADCONF_CAM_D8 ((volatile unsigned char *)0x480000D0)
-#define CONTROL_PADCONF_CAM_D9 ((volatile unsigned char *)0x480000CF)
-
-/* Pin Muxing registers used for LCD */
-#define CONTROL_PADCONF_DSS_D0 ((volatile unsigned char *)0x480000B3)
-#define CONTROL_PADCONF_DSS_D1 ((volatile unsigned char *)0x480000B4)
-#define CONTROL_PADCONF_DSS_D2 ((volatile unsigned char *)0x480000B5)
-#define CONTROL_PADCONF_DSS_D3 ((volatile unsigned char *)0x480000B6)
-#define CONTROL_PADCONF_DSS_D4 ((volatile unsigned char *)0x480000B7)
-#define CONTROL_PADCONF_DSS_D5 ((volatile unsigned char *)0x480000B8)
-#define CONTROL_PADCONF_DSS_D6 ((volatile unsigned char *)0x480000B9)
-#define CONTROL_PADCONF_DSS_D7 ((volatile unsigned char *)0x480000BA)
-#define CONTROL_PADCONF_DSS_D8 ((volatile unsigned char *)0x480000BB)
-#define CONTROL_PADCONF_DSS_D9 ((volatile unsigned char *)0x480000BC)
-#define CONTROL_PADCONF_DSS_D10 ((volatile unsigned char *)0x480000BD)
-#define CONTROL_PADCONF_DSS_D11 ((volatile unsigned char *)0x480000BE)
-#define CONTROL_PADCONF_DSS_D12 ((volatile unsigned char *)0x480000BF)
-#define CONTROL_PADCONF_DSS_D13 ((volatile unsigned char *)0x480000C0)
-#define CONTROL_PADCONF_DSS_D14 ((volatile unsigned char *)0x480000C1)
-#define CONTROL_PADCONF_DSS_D15 ((volatile unsigned char *)0x480000C2)
-#define CONTROL_PADCONF_DSS_D16 ((volatile unsigned char *)0x480000C3)
-#define CONTROL_PADCONF_DSS_D17 ((volatile unsigned char *)0x480000C4)
-#define CONTROL_PADCONF_DSS_PCLK ((volatile unsigned char *)0x480000CB)
-#define CONTROL_PADCONF_DSS_VSYNC ((volatile unsigned char *)0x480000CC)
-#define CONTROL_PADCONF_DSS_HSYNC ((volatile unsigned char *)0x480000CD)
-#define CONTROL_PADCONF_DSS_ACBIAS ((volatile unsigned char *)0x480000CE)
-
-/* Pin Muxing registers used for UART1 */
-#define CONTROL_PADCONF_UART1_CTS ((volatile unsigned char *)0x480000C5)
-#define CONTROL_PADCONF_UART1_RTS ((volatile unsigned char *)0x480000C6)
-#define CONTROL_PADCONF_UART1_TX ((volatile unsigned char *)0x480000C7)
-#define CONTROL_PADCONF_UART1_RX ((volatile unsigned char *)0x480000C8)
-
-/* Pin Muxing registers used for I2C1 */
-#define CONTROL_PADCONF_I2C1_SCL ((volatile unsigned char *)0x48000111)
-#define CONTROL_PADCONF_I2C1_SDA ((volatile unsigned char *)0x48000112)
-
-/* Pin Muxing registres used for USB0. */
-#define CONTROL_PADCONF_USB0_PUEN ((volatile uint8 *)0x4800011D)
-#define CONTROL_PADCONF_USB0_VP ((volatile uint8 *)0x4800011E)
-#define CONTROL_PADCONF_USB0_VM ((volatile uint8 *)0x4800011F)
-#define CONTROL_PADCONF_USB0_RCV ((volatile uint8 *)0x48000120)
-#define CONTROL_PADCONF_USB0_TXEN ((volatile uint8 *)0x48000121)
-#define CONTROL_PADCONF_USB0_SE0 ((volatile uint8 *)0x48000122)
-#define CONTROL_PADCONF_USB0_DAT ((volatile uint8 *)0x48000123)
-
-/* Pin Muxing registres used for USB1. */
-#define CONTROL_PADCONF_USB1_RCV (0x480000EB)
-#define CONTROL_PADCONF_USB1_TXEN (0x480000EC)
-
-/* Pin Muxing registers used for UART3/IRDA */
-#define CONTROL_PADCONF_UART3_TX_IRTX ((volatile uint8 *)0x48000118)
-#define CONTROL_PADCONF_UART3_RX_IRRX ((volatile uint8 *)0x48000119)
-
-/* Pin Muxing registers used for GPIO */
-#define CONTROL_PADCONF_GPIO69 (0x480000ED)
-#define CONTROL_PADCONF_GPIO70 (0x480000EE)
-#define CONTROL_PADCONF_GPIO102 (0x48000116)
-#define CONTROL_PADCONF_GPIO103 (0x48000117)
-#define CONTROL_PADCONF_GPIO104 (0x48000118)
-#define CONTROL_PADCONF_GPIO105 (0x48000119)
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP2420_SYS_H_
-#define _OMAP2420_SYS_H_
-
-#include <asm/arch/sizes.h>
-
-/*
- * 2420 specific Section
- */
-
-/* L3 Firewall */
-#define A_REQINFOPERM0 0x68005048
-#define A_READPERM0 0x68005050
-#define A_WRITEPERM0 0x68005058
-/* #define GP_DEVICE (BIT8|BIT9) FIXME -- commented out to make compile -- FIXME */
-
-/* L3 Firewall */
-#define A_REQINFOPERM0 0x68005048
-#define A_READPERM0 0x68005050
-#define A_WRITEPERM0 0x68005058
-
-/* CONTROL */
-#define OMAP2420_CTRL_BASE (0x48000000)
-#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8)
-
-/* device type */
-#define TST_DEVICE 0x0
-#define EMU_DEVICE 0x1
-#define HS_DEVICE 0x2
-#define GP_DEVICE 0x3
-
-/* TAP information */
-#define OMAP2420_TAP_BASE (0x48014000)
-#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204)
-#define PRODUCTION_ID (OMAP2420_TAP_BASE+0x208)
-
-/* GPMC */
-#define OMAP2420_GPMC_BASE (0x6800A000)
-#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10)
-#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C)
-#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40)
-#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50)
-#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60)
-#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64)
-#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68)
-#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C)
-#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70)
-#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74)
-#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78)
-#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90)
-#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94)
-#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98)
-#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C)
-#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0)
-#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4)
-#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8)
-#define GPMC_CONFIG1_2 (OMAP2420_GPMC_BASE+0xC0)
-#define GPMC_CONFIG2_2 (OMAP2420_GPMC_BASE+0xC4)
-#define GPMC_CONFIG3_2 (OMAP2420_GPMC_BASE+0xC8)
-#define GPMC_CONFIG4_2 (OMAP2420_GPMC_BASE+0xCC)
-#define GPMC_CONFIG5_2 (OMAP2420_GPMC_BASE+0xD0)
-#define GPMC_CONFIG6_2 (OMAP2420_GPMC_BASE+0xD4)
-#define GPMC_CONFIG7_2 (OMAP2420_GPMC_BASE+0xD8)
-#define GPMC_CONFIG1_3 (OMAP2420_GPMC_BASE+0xF0)
-#define GPMC_CONFIG2_3 (OMAP2420_GPMC_BASE+0xF4)
-#define GPMC_CONFIG3_3 (OMAP2420_GPMC_BASE+0xF8)
-#define GPMC_CONFIG4_3 (OMAP2420_GPMC_BASE+0xFC)
-#define GPMC_CONFIG5_3 (OMAP2420_GPMC_BASE+0x100)
-#define GPMC_CONFIG6_3 (OMAP2420_GPMC_BASE+0x104)
-#define GPMC_CONFIG7_3 (OMAP2420_GPMC_BASE+0x108)
-
-/* SMS */
-#define OMAP2420_SMS_BASE 0x68008000
-#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10)
-#define SMS_CLASS_ARB0 (OMAP2420_SMS_BASE+0xD0)
-# define BURSTCOMPLETE_GROUP7 BIT31
-
-/* SDRC */
-#define OMAP2420_SDRC_BASE 0x68009000
-#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10)
-#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14)
-#define SDRC_CS_CFG (OMAP2420_SDRC_BASE+0x40)
-#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44)
-#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60)
-#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68)
-#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70)
-#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80)
-#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84)
-#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C)
-#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0)
-#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4)
-#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8)
-#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4)
-#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8)
-#define OMAP2420_SDRC_CS0 0x80000000
-#define OMAP2420_SDRC_CS1 0xA0000000
-#define CMD_NOP 0x0
-#define CMD_PRECHARGE 0x1
-#define CMD_AUTOREFRESH 0x2
-#define CMD_ENTR_PWRDOWN 0x3
-#define CMD_EXIT_PWRDOWN 0x4
-#define CMD_ENTR_SRFRSH 0x5
-#define CMD_CKE_HIGH 0x6
-#define CMD_CKE_LOW 0x7
-#define SOFTRESET BIT1
-#define SMART_IDLE (0x2 << 3)
-#define REF_ON_IDLE (0x1 << 6)
-
-
-/* UART */
-#define OMAP2420_UART1 0x4806A000
-#define OMAP2420_UART2 0x4806C000
-#define OMAP2420_UART3 0x4806E000
-
-/* General Purpose Timers */
-#define OMAP2420_GPT1 0x48028000
-#define OMAP2420_GPT2 0x4802A000
-#define OMAP2420_GPT3 0x48078000
-#define OMAP2420_GPT4 0x4807A000
-#define OMAP2420_GPT5 0x4807C000
-#define OMAP2420_GPT6 0x4807E000
-#define OMAP2420_GPT7 0x48080000
-#define OMAP2420_GPT8 0x48082000
-#define OMAP2420_GPT9 0x48084000
-#define OMAP2420_GPT10 0x48086000
-#define OMAP2420_GPT11 0x48088000
-#define OMAP2420_GPT12 0x4808A000
-
-/* timer regs offsets (32 bit regs) */
-#define TIDR 0x0 /* r */
-#define TIOCP_CFG 0x10 /* rw */
-#define TISTAT 0x14 /* r */
-#define TISR 0x18 /* rw */
-#define TIER 0x1C /* rw */
-#define TWER 0x20 /* rw */
-#define TCLR 0x24 /* rw */
-#define TCRR 0x28 /* rw */
-#define TLDR 0x2C /* rw */
-#define TTGR 0x30 /* rw */
-#define TWPS 0x34 /* r */
-#define TMAR 0x38 /* rw */
-#define TCAR1 0x3c /* r */
-#define TSICR 0x40 /* rw */
-#define TCAR2 0x44 /* r */
-
-/* WatchDog Timers (1 secure, 3 GP) */
-#define WD1_BASE 0x48020000
-#define WD2_BASE 0x48022000
-#define WD3_BASE 0x48024000
-#define WD4_BASE 0x48026000
-#define WWPS 0x34 /* r */
-#define WSPR 0x48 /* rw */
-#define WD_UNLOCK1 0xAAAA
-#define WD_UNLOCK2 0x5555
-
-/* PRCM */
-#define OMAP2420_CM_BASE 0x48008000
-#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080)
-#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140)
-#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200)
-#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204)
-#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210)
-#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214)
-#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240)
-#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440)
-#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244)
-#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340)
-#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450)
-#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500)
-#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520)
-#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540)
-#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544)
-#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840)
-
-/*
- * H4 specific Section
- */
-
-/*
- * The 2420's chip selects are programmable. The mask ROM
- * does configure CS0 to 0x08000000 before dispatch. So, if
- * you want your code to live below that address, you have to
- * be prepared to jump though hoops, to reset the base address.
- */
-#if defined(CONFIG_OMAP2420H4)
-/* GPMC */
-#ifdef CONFIG_VIRTIO_A /* Pre version B */
-# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */
-# define H4_CS1_BASE 0x04000000 /* debug board */
-# define H4_CS2_BASE 0x0A000000 /* wifi board */
-#else
-# define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */
-# define H4_CS1_BASE 0x08000000 /* debug board */
-# define H4_CS2_BASE 0x0A000000 /* wifi board */
-#endif
-
-/* base address for indirect vectors (internal boot mode) */
-#define SRAM_OFFSET0 0x40000000
-#define SRAM_OFFSET1 0x00200000
-#define SRAM_OFFSET2 0x0000F800
-#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
-
-/* FPGA on Debug board.*/
-#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b)
-#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c)
-#endif /* endif CONFIG_2420H4 */
-
-#if defined(CONFIG_APOLLON)
-#define APOLLON_CS0_BASE 0x00000000 /* OneNAND */
-#define APOLLON_CS1_BASE 0x08000000 /* ethernet */
-#define APOLLON_CS2_BASE 0x10000000 /* OneNAND */
-#define APOLLON_CS3_BASE 0x18000000 /* NOR */
-
-#define ETH_CONTROL_REG (APOLLON_CS1_BASE + 0x30b)
-#define LAN_RESET_REGISTER (APOLLON_CS1_BASE + 0x1c)
-#endif /* endif CONFIG_APOLLON */
-
-/* Common */
-#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
-
-#define PERIFERAL_PORT_BASE 0x480FE003
-
-#endif
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-/* Size defintions
- * Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h 1
-
-/* handy sizes */
-#define SZ_1K 0x00000400
-#define SZ_4K 0x00001000
-#define SZ_8K 0x00002000
-#define SZ_16K 0x00004000
-#define SZ_32K 0x00008000
-#define SZ_64K 0x00010000
-#define SZ_128K 0x00020000
-#define SZ_256K 0x00040000
-#define SZ_512K 0x00080000
-
-#define SZ_1M 0x00100000
-#define SZ_2M 0x00200000
-#define SZ_4M 0x00400000
-#define SZ_8M 0x00800000
-#define SZ_16M 0x01000000
-#define SZ_31M 0x01F00000
-#define SZ_32M 0x02000000
-#define SZ_64M 0x04000000
-#define SZ_128M 0x08000000
-#define SZ_256M 0x10000000
-#define SZ_512M 0x20000000
-
-#define SZ_1G 0x40000000
-#define SZ_2G 0x80000000
-
-#endif /* __sizes_h */
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP24XX_SYS_INFO_H_
-#define _OMAP24XX_SYS_INFO_H_
-
-typedef struct h4_system_data {
- /* base board info */
- u32 base_b_rev; /* rev from base board i2c */
- /* cpu board info */
- u32 cpu_b_rev; /* rev from cpu board i2c */
- u32 cpu_b_mux; /* mux type on daughter board */
- u32 cpu_b_ddr_type; /* mem type */
- u32 cpu_b_ddr_speed; /* ddr speed rating */
- u32 cpu_b_switches; /* boot ctrl switch settings */
- /* cpu info */
- u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/
- u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/
-} h4_sys_data;
-
-#define XDR_POP 5 /* package on package part */
-#define SDR_DISCRETE 4 /* 128M memory SDR module*/
-#define DDR_STACKED 3 /* stacked part on 2422 */
-#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */
-#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
-
-#define DDR_100 100 /* type found on most mem d-boards */
-#define DDR_111 111 /* some combo parts */
-#define DDR_133 133 /* most combo, some mem d-boards */
-#define DDR_165 165 /* future parts */
-
-#define CPU_2420 0x2420
-#define CPU_2422 0x2422 /* 2420 + 64M stacked */
-#define CPU_2423 0x2423 /* 2420 + 96M stacked */
-
-#define CPU_2422_ES1 1
-#define CPU_2422_ES2 2
-#define CPU_2420_ES1 1
-#define CPU_2420_ES2 2
-#define CPU_2420_2422_ES1 1
-
-#define CPU_2420_CHIPID 0x0B5D9000
-#define CPU_24XX_ID_MASK 0x0FFFF000
-#define CPU_242X_REV_MASK 0xF0000000
-#define CPU_242X_PID_MASK 0x000F0000
-
-#define BOARD_H4_MENELAUS 1
-#define BOARD_H4_SDP 2
-
-#define GPMC_MUXED 1
-#define GPMC_NONMUXED 0
-
-#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */
-#define TYPE_NOR 0x000
-
-#define WIDTH_8BIT 0x0000
-#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
-
-#define I2C_MENELAUS 0x72 /* i2c id for companion chip */
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP24XX_SYS_PROTO_H_
-#define _OMAP24XX_SYS_PROTO_H_
-
-void prcm_init(void);
-void memif_init(void);
-void sdrc_init(void);
-void do_sdrc_init(u32,u32);
-void gpmc_init(void);
-
-void ether_init(void);
-void watchdog_init(void);
-void set_muxconf_regs(void);
-void peripheral_enable(void);
-
-u32 get_cpu_type(void);
-u32 get_cpu_rev(void);
-u32 get_mem_type(void);
-u32 get_sysboot_value(void);
-u32 get_gpmc0_base(void);
-u32 is_gpmc_muxed(void);
-u32 get_gpmc0_type(void);
-u32 get_gpmc0_width(void);
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound);
-u32 get_board_type(void);
-void display_board_info(u32);
-void update_mux(u32,u32);
-u32 get_sdr_cs_size(u32 offset);
-
-u32 running_in_sdram(void);
-u32 running_in_sram(void);
-u32 running_in_flash(void);
-u32 running_from_internal_boot(void);
-u32 get_device_type(void);
-#endif
#define VDD3P3V_PWDN (0x01c40048)
#define UART0_PWREMU_MGMT (0x01c20030)
+#define UART1_PWREMU_MGMT (0x01c20430)
+#define UART2_PWREMU_MGMT (0x01c20830)
#define PSC_SILVER_BULLET (0x01c41a20)
--- /dev/null
+/*
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_MX31_REGS_H
+#define __ASM_ARCH_MX31_REGS_H
+
+#define __REG(x) (*((volatile u32 *)(x)))
+#define __REG16(x) (*((volatile u16 *)(x)))
+#define __REG8(x) (*((volatile u8 *)(x)))
+
+#define CCM_BASE 0x53f80000
+#define CCM_CCMR (CCM_BASE + 0x00)
+#define CCM_PDR0 (CCM_BASE + 0x04)
+#define CCM_PDR1 (CCM_BASE + 0x08)
+#define CCM_RCSR (CCM_BASE + 0x0c)
+#define CCM_MPCTL (CCM_BASE + 0x10)
+#define CCM_UPCTL (CCM_BASE + 0x10)
+#define CCM_SPCTL (CCM_BASE + 0x18)
+#define CCM_COSR (CCM_BASE + 0x1C)
+
+#define CCMR_MDS (1 << 7)
+#define CCMR_SBYCS (1 << 4)
+#define CCMR_MPE (1 << 3)
+#define CCMR_PRCS_MASK (3 << 1)
+#define CCMR_FPM (1 << 1)
+#define CCMR_CKIH (2 << 1)
+
+#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
+#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
+#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
+#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
+#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
+#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
+#define PDR0_MCU_PODF(x) ((x) & 0x7)
+
+#define PLL_PD(x) (((x) & 0xf) << 26)
+#define PLL_MFD(x) (((x) & 0x3ff) << 16)
+#define PLL_MFI(x) (((x) & 0xf) << 10)
+#define PLL_MFN(x) (((x) & 0x3ff) << 0)
+
+#define WEIM_BASE 0xb8002000
+#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
+#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
+#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
+
+#define IOMUXC_BASE 0x43FAC000
+#define IOMUXC_GPR (IOMUXC_BASE + 0x8)
+#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
+#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
+
+#define IPU_BASE 0x53fc0000
+#define IPU_CONF IPU_BASE
+
+#define IPU_CONF_PXL_ENDIAN (1<<8)
+#define IPU_CONF_DU_EN (1<<7)
+#define IPU_CONF_DI_EN (1<<6)
+#define IPU_CONF_ADC_EN (1<<5)
+#define IPU_CONF_SDC_EN (1<<4)
+#define IPU_CONF_PF_EN (1<<3)
+#define IPU_CONF_ROT_EN (1<<2)
+#define IPU_CONF_IC_EN (1<<1)
+#define IPU_CONF_SCI_EN (1<<0)
+
+#define WDOG_BASE 0x53FDC000
+
+/*
+ * Signal Multiplexing (IOMUX)
+ */
+
+/* bits in the SW_MUX_CTL registers */
+#define MUX_CTL_OUT_GPIO_DR (0 << 4)
+#define MUX_CTL_OUT_FUNC (1 << 4)
+#define MUX_CTL_OUT_ALT1 (2 << 4)
+#define MUX_CTL_OUT_ALT2 (3 << 4)
+#define MUX_CTL_OUT_ALT3 (4 << 4)
+#define MUX_CTL_OUT_ALT4 (5 << 4)
+#define MUX_CTL_OUT_ALT5 (6 << 4)
+#define MUX_CTL_OUT_ALT6 (7 << 4)
+#define MUX_CTL_IN_NONE (0 << 0)
+#define MUX_CTL_IN_GPIO (1 << 0)
+#define MUX_CTL_IN_FUNC (2 << 0)
+#define MUX_CTL_IN_ALT1 (4 << 0)
+#define MUX_CTL_IN_ALT2 (8 << 0)
+
+#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
+#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
+#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
+#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
+
+/* Register offsets based on IOMUXC_BASE */
+/* 0x00 .. 0x7b */
+#define MUX_CTL_RTS1 0x7c
+#define MUX_CTL_CTS1 0x7d
+#define MUX_CTL_DTR_DCE1 0x7e
+#define MUX_CTL_DSR_DCE1 0x7f
+#define MUX_CTL_CSPI2_SCLK 0x80
+#define MUX_CTL_CSPI2_SPI_RDY 0x81
+#define MUX_CTL_RXD1 0x82
+#define MUX_CTL_TXD1 0x83
+#define MUX_CTL_CSPI2_MISO 0x84
+/* 0x85 .. 0x8a */
+#define MUX_CTL_CSPI2_MOSI 0x8b
+
+/* The modes a specific pin can be in
+ * these macros can be used in mx31_gpio_mux() and have the form
+ * MUX_[contact name]__[pin function]
+ */
+#define MUX_RXD1__UART1_RXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1)
+#define MUX_TXD1__UART1_TXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1)
+#define MUX_RTS1__UART1_RTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1)
+#define MUX_RTS1__UART1_CTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1)
+
+#define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI)
+#define MUX_CSPI2_MISO__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
+
+/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE 0x70000000
+#define CSD0_BASE 0x80000000
+#define CSD1_BASE 0x90000000
+#define CS0_BASE 0xA0000000
+#define CS1_BASE 0xA8000000
+#define CS2_BASE 0xB0000000
+#define CS3_BASE 0xB2000000
+#define CS4_BASE 0xB4000000
+#define CS4_PSRAM_BASE 0xB5000000
+#define CS5_BASE 0xB6000000
+#define PCMCIA_MEM_BASE 0xC0000000
+
+#endif /* __ASM_ARCH_MX31_REGS_H */
--- /dev/null
+/*
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_MX31_H
+#define __ASM_ARCH_MX31_H
+
+u32 mx31_get_mpl_dpdgck_clk(void);
+u32 mx31_get_mcu_main_clk(void);
+u32 mx31_get_ipg_clk(void);
+void mx31_gpio_mux(unsigned long mode);
+
+#endif /* __ASM_ARCH_MX31_H */
--- /dev/null
+/* bits.h
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * This package is free software; you can redistribute it and/or
+ * modify it under the terms of the license found in the file
+ * named COPYING that should have accompanied this file.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+#ifndef __bits_h
+#define __bits_h 1
+
+#define BIT0 (1<<0)
+#define BIT1 (1<<1)
+#define BIT2 (1<<2)
+#define BIT3 (1<<3)
+#define BIT4 (1<<4)
+#define BIT5 (1<<5)
+#define BIT6 (1<<6)
+#define BIT7 (1<<7)
+#define BIT8 (1<<8)
+#define BIT9 (1<<9)
+#define BIT10 (1<<10)
+#define BIT11 (1<<11)
+#define BIT12 (1<<12)
+#define BIT13 (1<<13)
+#define BIT14 (1<<14)
+#define BIT15 (1<<15)
+#define BIT16 (1<<16)
+#define BIT17 (1<<17)
+#define BIT18 (1<<18)
+#define BIT19 (1<<19)
+#define BIT20 (1<<20)
+#define BIT21 (1<<21)
+#define BIT22 (1<<22)
+#define BIT23 (1<<23)
+#define BIT24 (1<<24)
+#define BIT25 (1<<25)
+#define BIT26 (1<<26)
+#define BIT27 (1<<27)
+#define BIT28 (1<<28)
+#define BIT29 (1<<29)
+#define BIT30 (1<<30)
+#define BIT31 (1<<31)
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP24XX_CLOCKS_H_
+#define _OMAP24XX_CLOCKS_H_
+
+#define COMMIT_DIVIDERS 0x1
+
+#define MODE_BYPASS_FAST 0x2
+#define APLL_LOCK 0xc
+#ifdef CONFIG_APTIX
+#define DPLL_LOCK 0x1 /* stay in bypass mode */
+#else
+#define DPLL_LOCK 0x3 /* DPLL lock */
+#endif
+
+/****************************************************************************;
+; PRCM Scheme II
+;
+; Enable clocks and DPLL for:
+; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50
+; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
+; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0]
+; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0]
+; DSPI=100 6 CM_CLKSEL_DSP[6:5]
+; DSP_S bypass CM_CLKSEL_DSP[7]
+; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8]
+; IVAF=100 auto
+; IVAI auto
+; IVA_MPU auto
+; IVA_S bypass CM_CLKSEL_DSP[13]
+; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0]
+; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20]
+; SSI_SSTF=100 auto
+; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0]
+; L4=100Mhz 6
+; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5]
+***************************************************************************/
+#define II_DPLL_OUT_X2 0x2 /* x2 core out */
+#define II_MPU_DIV 0x2 /* mpu = core/2 */
+#define II_DSP_DIV 0x343 /* dsp & iva divider */
+#define II_GFX_DIV 0x2
+#define II_BUS_DIV 0x04601026
+#define II_DPLL_300 0x01832100
+
+/****************************************************************************;
+; PRCM Scheme III
+;
+; Enable clocks and DPLL for:
+; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266
+; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
+; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0]
+; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0]
+; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5]
+; DSP_S ACTIVATED CM_CLKSEL_DSP[7]
+; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8]
+; IVAF=88.67 auto
+; IVAI auto
+; IVA_MPU auto
+; IVA_S ACTIVATED CM_CLKSEL_DSP[13]
+; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]:
+; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20]
+; SSI_SSTF=88.67 auto
+; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0]
+; L4=66.5Mhz /8
+; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5]
+***************************************************************************/
+#define III_DPLL_OUT_X2 0x2 /* x2 core out */
+#define III_MPU_DIV 0x2 /* mpu = core/2 */
+#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/
+#define III_GFX_DIV 0x2
+#define III_BUS_DIV 0x08301044
+#define III_DPLL_266 0x01885500
+
+/* set defaults for boot up */
+#ifdef PRCM_CONFIG_II
+# define DPLL_OUT II_DPLL_OUT_X2
+# define MPU_DIV II_MPU_DIV
+# define DSP_DIV II_DSP_DIV
+# define GFX_DIV II_GFX_DIV
+# define BUS_DIV II_BUS_DIV
+# define DPLL_VAL II_DPLL_300
+#elif PRCM_CONFIG_III
+# define DPLL_OUT III_DPLL_OUT_X2
+# define MPU_DIV III_MPU_DIV
+# define DSP_DIV III_DSP_DIV
+# define GFX_DIV III_GFX_DIV
+# define BUS_DIV III_BUS_DIV
+# define DPLL_VAL III_DPLL_266
+#endif
+
+/* lock delay time out */
+#define LDELAY 12000000
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP24XX_I2C_H_
+#define _OMAP24XX_I2C_H_
+
+#define I2C_BASE 0x48070000
+#define I2C_BASE2 0x48072000 /* nothing hooked up on h4 */
+
+#define I2C_REV (I2C_BASE + 0x00)
+#define I2C_IE (I2C_BASE + 0x04)
+#define I2C_STAT (I2C_BASE + 0x08)
+#define I2C_IV (I2C_BASE + 0x0c)
+#define I2C_BUF (I2C_BASE + 0x14)
+#define I2C_CNT (I2C_BASE + 0x18)
+#define I2C_DATA (I2C_BASE + 0x1c)
+#define I2C_SYSC (I2C_BASE + 0x20)
+#define I2C_CON (I2C_BASE + 0x24)
+#define I2C_OA (I2C_BASE + 0x28)
+#define I2C_SA (I2C_BASE + 0x2c)
+#define I2C_PSC (I2C_BASE + 0x30)
+#define I2C_SCLL (I2C_BASE + 0x34)
+#define I2C_SCLH (I2C_BASE + 0x38)
+#define I2C_SYSTEST (I2C_BASE + 0x3c)
+
+/* I2C masks */
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+#define I2C_IE_GC_IE (1 << 5)
+#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
+#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
+#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
+#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
+#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C Status Register (I2C_STAT): */
+
+#define I2C_STAT_SBD (1 << 15) /* Single byte data */
+#define I2C_STAT_BB (1 << 12) /* Bus busy */
+#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
+#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
+#define I2C_STAT_AAS (1 << 9) /* Address as slave */
+#define I2C_STAT_GC (1 << 5)
+#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
+#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
+#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
+#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
+#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
+
+
+/* I2C Interrupt Code Register (I2C_INTCODE): */
+
+#define I2C_INTCODE_MASK 7
+#define I2C_INTCODE_NONE 0
+#define I2C_INTCODE_AL 1 /* Arbitration lost */
+#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
+#define I2C_INTCODE_ARDY 3 /* Register access ready */
+#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
+#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
+
+/* I2C Buffer Configuration Register (I2C_BUF): */
+
+#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */
+#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */
+
+/* I2C Configuration Register (I2C_CON): */
+
+#define I2C_CON_EN (1 << 15) /* I2C module enable */
+#define I2C_CON_BE (1 << 14) /* Big endian mode */
+#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
+#define I2C_CON_MST (1 << 10) /* Master/slave mode */
+#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */
+#define I2C_CON_XA (1 << 8) /* Expand address */
+#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
+#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
+
+/* I2C System Test Register (I2C_SYSTEST): */
+
+#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
+#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */
+#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
+#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
+#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */
+#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */
+#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
+#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP24XX_MEM_H_
+#define _OMAP24XX_MEM_H_
+
+#define SDRC_CS0_OSET 0x0
+#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */
+
+#ifndef __ASSEMBLY__
+/* struct's for holding data tables for current boards, they are getting used
+ early in init when NO global access are there */
+struct sdrc_data_s {
+ u32 sdrc_sharing;
+ u32 sdrc_mdcfg_0_ddr;
+ u32 sdrc_mdcfg_0_sdr;
+ u32 sdrc_actim_ctrla_0;
+ u32 sdrc_actim_ctrlb_0;
+ u32 sdrc_rfr_ctrl;
+ u32 sdrc_mr_0_ddr;
+ u32 sdrc_mr_0_sdr;
+ u32 sdrc_dllab_ctrl;
+} /*__attribute__ ((packed))*/;
+typedef struct sdrc_data_s sdrc_data_t;
+
+typedef enum {
+ STACKED = 0,
+ IP_DDR = 1,
+ COMBO_DDR = 2,
+ IP_SDR = 3,
+} mem_t;
+
+#endif
+
+/* Slower full frequency range default timings for x32 operation*/
+#define H4_2420_SDRC_SHARING 0x00000100
+#define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */
+#define H4_2420_SDRC_MR_0_SDR 0x00000031
+#define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */
+#define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */
+#define H4_2420_SDRC_MR_0_DDR 0x00000032
+
+#define H4_2422_SDRC_SHARING 0x00004b00
+#define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked ddr on 2422 */
+#define H4_2422_SDRC_MR_0_DDR 0x00000032
+
+/* ES1 work around timings */
+#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */
+#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020
+#define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */
+
+/* optimized timings good for current shipping parts */
+#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485
+#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e
+#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */
+#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */
+#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01
+#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01
+#define H4_242x_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 72deg, allow DPLLout*1 to work (combo)*/
+#define H4_242x_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 72deg, for ES2 */
+
+#ifdef PRCM_CONFIG_II
+# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
+# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
+# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
+# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz
+# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
+# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
+# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
+# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz
+#elif PRCM_CONFIG_III
+# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
+# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
+# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz
+# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_133MHz
+# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
+# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
+# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
+# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz
+#endif
+
+
+/* GPMC settings */
+#ifdef PRCM_CONFIG_II /* L3 at 100MHz */
+# ifdef CFG_NAND_BOOT
+# define H4_24XX_GPMC_CONFIG1_0 0x0
+# define H4_24XX_GPMC_CONFIG2_0 0x00141400
+# define H4_24XX_GPMC_CONFIG3_0 0x00141400
+# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
+# define H4_24XX_GPMC_CONFIG5_0 0x010C1414
+# define H4_24XX_GPMC_CONFIG6_0 0x00000A80
+# else /* else NOR */
+# define H4_24XX_GPMC_CONFIG1_0 0x3
+# define H4_24XX_GPMC_CONFIG2_0 0x000f0f01
+# define H4_24XX_GPMC_CONFIG3_0 0x00050502
+# define H4_24XX_GPMC_CONFIG4_0 0x0C060C06
+# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
+# endif /* endif CFG_NAND_BOOT */
+# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
+# define H4_24XX_GPMC_CONFIG1_1 0x00011000
+# define H4_24XX_GPMC_CONFIG2_1 0x001F1F00
+# define H4_24XX_GPMC_CONFIG3_1 0x00080802
+# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
+# define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F
+# define H4_24XX_GPMC_CONFIG6_1 0x000003C2
+# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
+#endif /* endif PRCM_CONFIG_II */
+
+#ifdef PRCM_CONFIG_III /* L3 at 133MHz */
+# ifdef CFG_NAND_BOOT
+# define H4_24XX_GPMC_CONFIG1_0 0x0
+# define H4_24XX_GPMC_CONFIG2_0 0x00141400
+# define H4_24XX_GPMC_CONFIG3_0 0x00141400
+# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
+# define H4_24XX_GPMC_CONFIG5_0 0x010C1414
+# define H4_24XX_GPMC_CONFIG6_0 0x00000A80
+# else /* NOR boot */
+# define H4_24XX_GPMC_CONFIG1_0 0x3
+# define H4_24XX_GPMC_CONFIG2_0 0x00151501
+# define H4_24XX_GPMC_CONFIG3_0 0x00060602
+# define H4_24XX_GPMC_CONFIG4_0 0x10081008
+# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
+# define H4_24XX_GPMC_CONFIG6_0 0x000004c4
+# endif /* endif CFG_NAND_BOOT */
+# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
+# define H4_24XX_GPMC_CONFIG1_1 0x00011000
+# define H4_24XX_GPMC_CONFIG2_1 0x001f1f01
+# define H4_24XX_GPMC_CONFIG3_1 0x00080803
+# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
+# define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F
+# define H4_24XX_GPMC_CONFIG6_1 0x000004C4
+# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
+#endif /* endif CFG_PRCM_III */
+
+#endif /* endif _OMAP24XX_MEM_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP2420_MUX_H_
+#define _OMAP2420_MUX_H_
+
+#ifndef __ASSEMBLY__
+typedef unsigned char uint8;
+typedef unsigned int uint32;
+
+void muxSetupSDRC(void);
+void muxSetupGPMC(void);
+void muxSetupUsb0(void);
+void muxSetupUsbHost(void);
+void muxSetupUart3(void);
+void muxSetupI2C1(void);
+void muxSetupUART1(void);
+void muxSetupLCD(void);
+void muxSetupCamera(void);
+void muxSetupMMCSD(void) ;
+void muxSetupTouchScreen(void) ;
+void muxSetupHDQ(void);
+#endif
+
+#define USB_OTG_CTRL ((volatile uint32 *)0x4805E30C)
+
+/* Pin Muxing registers used for HDQ (Smart battery) */
+#define CONTROL_PADCONF_HDQ_SIO ((volatile unsigned char *)0x48000115)
+
+/* Pin Muxing registers used for GPMC */
+#define CONTROL_PADCONF_GPMC_D2_BYTE0 ((volatile unsigned char *)0x48000088)
+#define CONTROL_PADCONF_GPMC_D2_BYTE1 ((volatile unsigned char *)0x48000089)
+#define CONTROL_PADCONF_GPMC_D2_BYTE2 ((volatile unsigned char *)0x4800008A)
+#define CONTROL_PADCONF_GPMC_D2_BYTE3 ((volatile unsigned char *)0x4800008B)
+
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE0 ((volatile unsigned char *)0x4800008C)
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE1 ((volatile unsigned char *)0x4800008D)
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE2 ((volatile unsigned char *)0x4800008E)
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE3 ((volatile unsigned char *)0x4800008F)
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE4 (0x48000090)
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE5 (0x48000091)
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE6 (0x48000092)
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE7 (0x48000093)
+
+/* Pin Muxing registers used for SDRC */
+#define CONTROL_PADCONF_SDRC_NCS0_BYTE0 ((volatile unsigned char *)0x480000A0)
+#define CONTROL_PADCONF_SDRC_NCS0_BYTE1 ((volatile unsigned char *)0x480000A1)
+#define CONTROL_PADCONF_SDRC_NCS0_BYTE2 ((volatile unsigned char *)0x480000A2)
+#define CONTROL_PADCONF_SDRC_NCS0_BYTE3 ((volatile unsigned char *)0x480000A3)
+
+#define CONTROL_PADCONF_SDRC_A14_BYTE0 ((volatile unsigned char *)0x48000030)
+#define CONTROL_PADCONF_SDRC_A14_BYTE1 ((volatile unsigned char *)0x48000031)
+#define CONTROL_PADCONF_SDRC_A14_BYTE2 ((volatile unsigned char *)0x48000032)
+#define CONTROL_PADCONF_SDRC_A14_BYTE3 ((volatile unsigned char *)0x48000033)
+
+/* Pin Muxing registers used for Touch Screen (SPI) */
+#define CONTROL_PADCONF_SPI1_CLK ((volatile unsigned char *)0x480000FF)
+#define CONTROL_PADCONF_SPI1_SIMO ((volatile unsigned char *)0x48000100)
+#define CONTROL_PADCONF_SPI1_SOMI ((volatile unsigned char *)0x48000101)
+#define CONTROL_PADCONF_SPI1_NCS0 ((volatile unsigned char *)0x48000102)
+#define CONTROL_PADCONF_SPI1_NCS1 (0x48000103)
+
+#define CONTROL_PADCONF_MCBSP1_FSR ((volatile unsigned char *)0x4800010B)
+
+/* Pin Muxing registers used for MMCSD */
+#define CONTROL_PADCONF_MMC_CLKI ((volatile unsigned char *)0x480000FE)
+#define CONTROL_PADCONF_MMC_CLKO ((volatile unsigned char *)0x480000F3)
+#define CONTROL_PADCONF_MMC_CMD ((volatile unsigned char *)0x480000F4)
+#define CONTROL_PADCONF_MMC_DAT0 ((volatile unsigned char *)0x480000F5)
+#define CONTROL_PADCONF_MMC_DAT1 ((volatile unsigned char *)0x480000F6)
+#define CONTROL_PADCONF_MMC_DAT2 ((volatile unsigned char *)0x480000F7)
+#define CONTROL_PADCONF_MMC_DAT3 ((volatile unsigned char *)0x480000F8)
+#define CONTROL_PADCONF_MMC_DAT_DIR0 ((volatile unsigned char *)0x480000F9)
+#define CONTROL_PADCONF_MMC_DAT_DIR1 ((volatile unsigned char *)0x480000FA)
+#define CONTROL_PADCONF_MMC_DAT_DIR2 ((volatile unsigned char *)0x480000FB)
+#define CONTROL_PADCONF_MMC_DAT_DIR3 ((volatile unsigned char *)0x480000FC)
+#define CONTROL_PADCONF_MMC_CMD_DIR ((volatile unsigned char *)0x480000FD)
+
+#define CONTROL_PADCONF_SDRC_A14 ((volatile unsigned char *)0x48000030)
+#define CONTROL_PADCONF_SDRC_A13 ((volatile unsigned char *)0x48000031)
+
+/* Pin Muxing registers used for CAMERA */
+#define CONTROL_PADCONF_SYS_NRESWARM ((volatile unsigned char *)0x4800012B)
+
+#define CONTROL_PADCONF_CAM_XCLK ((volatile unsigned char *)0x480000DC)
+#define CONTROL_PADCONF_CAM_LCLK ((volatile unsigned char *)0x480000DB)
+#define CONTROL_PADCONF_CAM_VS ((volatile unsigned char *)0x480000DA)
+#define CONTROL_PADCONF_CAM_HS ((volatile unsigned char *)0x480000D9)
+#define CONTROL_PADCONF_CAM_D0 ((volatile unsigned char *)0x480000D8)
+#define CONTROL_PADCONF_CAM_D1 ((volatile unsigned char *)0x480000D7)
+#define CONTROL_PADCONF_CAM_D2 ((volatile unsigned char *)0x480000D6)
+#define CONTROL_PADCONF_CAM_D3 ((volatile unsigned char *)0x480000D5)
+#define CONTROL_PADCONF_CAM_D4 ((volatile unsigned char *)0x480000D4)
+#define CONTROL_PADCONF_CAM_D5 ((volatile unsigned char *)0x480000D3)
+#define CONTROL_PADCONF_CAM_D6 ((volatile unsigned char *)0x480000D2)
+#define CONTROL_PADCONF_CAM_D7 ((volatile unsigned char *)0x480000D1)
+#define CONTROL_PADCONF_CAM_D8 ((volatile unsigned char *)0x480000D0)
+#define CONTROL_PADCONF_CAM_D9 ((volatile unsigned char *)0x480000CF)
+
+/* Pin Muxing registers used for LCD */
+#define CONTROL_PADCONF_DSS_D0 ((volatile unsigned char *)0x480000B3)
+#define CONTROL_PADCONF_DSS_D1 ((volatile unsigned char *)0x480000B4)
+#define CONTROL_PADCONF_DSS_D2 ((volatile unsigned char *)0x480000B5)
+#define CONTROL_PADCONF_DSS_D3 ((volatile unsigned char *)0x480000B6)
+#define CONTROL_PADCONF_DSS_D4 ((volatile unsigned char *)0x480000B7)
+#define CONTROL_PADCONF_DSS_D5 ((volatile unsigned char *)0x480000B8)
+#define CONTROL_PADCONF_DSS_D6 ((volatile unsigned char *)0x480000B9)
+#define CONTROL_PADCONF_DSS_D7 ((volatile unsigned char *)0x480000BA)
+#define CONTROL_PADCONF_DSS_D8 ((volatile unsigned char *)0x480000BB)
+#define CONTROL_PADCONF_DSS_D9 ((volatile unsigned char *)0x480000BC)
+#define CONTROL_PADCONF_DSS_D10 ((volatile unsigned char *)0x480000BD)
+#define CONTROL_PADCONF_DSS_D11 ((volatile unsigned char *)0x480000BE)
+#define CONTROL_PADCONF_DSS_D12 ((volatile unsigned char *)0x480000BF)
+#define CONTROL_PADCONF_DSS_D13 ((volatile unsigned char *)0x480000C0)
+#define CONTROL_PADCONF_DSS_D14 ((volatile unsigned char *)0x480000C1)
+#define CONTROL_PADCONF_DSS_D15 ((volatile unsigned char *)0x480000C2)
+#define CONTROL_PADCONF_DSS_D16 ((volatile unsigned char *)0x480000C3)
+#define CONTROL_PADCONF_DSS_D17 ((volatile unsigned char *)0x480000C4)
+#define CONTROL_PADCONF_DSS_PCLK ((volatile unsigned char *)0x480000CB)
+#define CONTROL_PADCONF_DSS_VSYNC ((volatile unsigned char *)0x480000CC)
+#define CONTROL_PADCONF_DSS_HSYNC ((volatile unsigned char *)0x480000CD)
+#define CONTROL_PADCONF_DSS_ACBIAS ((volatile unsigned char *)0x480000CE)
+
+/* Pin Muxing registers used for UART1 */
+#define CONTROL_PADCONF_UART1_CTS ((volatile unsigned char *)0x480000C5)
+#define CONTROL_PADCONF_UART1_RTS ((volatile unsigned char *)0x480000C6)
+#define CONTROL_PADCONF_UART1_TX ((volatile unsigned char *)0x480000C7)
+#define CONTROL_PADCONF_UART1_RX ((volatile unsigned char *)0x480000C8)
+
+/* Pin Muxing registers used for I2C1 */
+#define CONTROL_PADCONF_I2C1_SCL ((volatile unsigned char *)0x48000111)
+#define CONTROL_PADCONF_I2C1_SDA ((volatile unsigned char *)0x48000112)
+
+/* Pin Muxing registres used for USB0. */
+#define CONTROL_PADCONF_USB0_PUEN ((volatile uint8 *)0x4800011D)
+#define CONTROL_PADCONF_USB0_VP ((volatile uint8 *)0x4800011E)
+#define CONTROL_PADCONF_USB0_VM ((volatile uint8 *)0x4800011F)
+#define CONTROL_PADCONF_USB0_RCV ((volatile uint8 *)0x48000120)
+#define CONTROL_PADCONF_USB0_TXEN ((volatile uint8 *)0x48000121)
+#define CONTROL_PADCONF_USB0_SE0 ((volatile uint8 *)0x48000122)
+#define CONTROL_PADCONF_USB0_DAT ((volatile uint8 *)0x48000123)
+
+/* Pin Muxing registres used for USB1. */
+#define CONTROL_PADCONF_USB1_RCV (0x480000EB)
+#define CONTROL_PADCONF_USB1_TXEN (0x480000EC)
+
+/* Pin Muxing registers used for UART3/IRDA */
+#define CONTROL_PADCONF_UART3_TX_IRTX ((volatile uint8 *)0x48000118)
+#define CONTROL_PADCONF_UART3_RX_IRRX ((volatile uint8 *)0x48000119)
+
+/* Pin Muxing registers used for GPIO */
+#define CONTROL_PADCONF_GPIO69 (0x480000ED)
+#define CONTROL_PADCONF_GPIO70 (0x480000EE)
+#define CONTROL_PADCONF_GPIO102 (0x48000116)
+#define CONTROL_PADCONF_GPIO103 (0x48000117)
+#define CONTROL_PADCONF_GPIO104 (0x48000118)
+#define CONTROL_PADCONF_GPIO105 (0x48000119)
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP2420_SYS_H_
+#define _OMAP2420_SYS_H_
+
+#include <asm/arch/sizes.h>
+
+/*
+ * 2420 specific Section
+ */
+
+/* L3 Firewall */
+#define A_REQINFOPERM0 0x68005048
+#define A_READPERM0 0x68005050
+#define A_WRITEPERM0 0x68005058
+/* #define GP_DEVICE (BIT8|BIT9) FIXME -- commented out to make compile -- FIXME */
+
+/* L3 Firewall */
+#define A_REQINFOPERM0 0x68005048
+#define A_READPERM0 0x68005050
+#define A_WRITEPERM0 0x68005058
+
+/* CONTROL */
+#define OMAP2420_CTRL_BASE (0x48000000)
+#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8)
+
+/* device type */
+#define TST_DEVICE 0x0
+#define EMU_DEVICE 0x1
+#define HS_DEVICE 0x2
+#define GP_DEVICE 0x3
+
+/* TAP information */
+#define OMAP2420_TAP_BASE (0x48014000)
+#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204)
+#define PRODUCTION_ID (OMAP2420_TAP_BASE+0x208)
+
+/* GPMC */
+#define OMAP2420_GPMC_BASE (0x6800A000)
+#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10)
+#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C)
+#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40)
+#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50)
+#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60)
+#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64)
+#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68)
+#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C)
+#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70)
+#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74)
+#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78)
+#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90)
+#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94)
+#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98)
+#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C)
+#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0)
+#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4)
+#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8)
+#define GPMC_CONFIG1_2 (OMAP2420_GPMC_BASE+0xC0)
+#define GPMC_CONFIG2_2 (OMAP2420_GPMC_BASE+0xC4)
+#define GPMC_CONFIG3_2 (OMAP2420_GPMC_BASE+0xC8)
+#define GPMC_CONFIG4_2 (OMAP2420_GPMC_BASE+0xCC)
+#define GPMC_CONFIG5_2 (OMAP2420_GPMC_BASE+0xD0)
+#define GPMC_CONFIG6_2 (OMAP2420_GPMC_BASE+0xD4)
+#define GPMC_CONFIG7_2 (OMAP2420_GPMC_BASE+0xD8)
+#define GPMC_CONFIG1_3 (OMAP2420_GPMC_BASE+0xF0)
+#define GPMC_CONFIG2_3 (OMAP2420_GPMC_BASE+0xF4)
+#define GPMC_CONFIG3_3 (OMAP2420_GPMC_BASE+0xF8)
+#define GPMC_CONFIG4_3 (OMAP2420_GPMC_BASE+0xFC)
+#define GPMC_CONFIG5_3 (OMAP2420_GPMC_BASE+0x100)
+#define GPMC_CONFIG6_3 (OMAP2420_GPMC_BASE+0x104)
+#define GPMC_CONFIG7_3 (OMAP2420_GPMC_BASE+0x108)
+
+/* SMS */
+#define OMAP2420_SMS_BASE 0x68008000
+#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10)
+#define SMS_CLASS_ARB0 (OMAP2420_SMS_BASE+0xD0)
+# define BURSTCOMPLETE_GROUP7 BIT31
+
+/* SDRC */
+#define OMAP2420_SDRC_BASE 0x68009000
+#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10)
+#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14)
+#define SDRC_CS_CFG (OMAP2420_SDRC_BASE+0x40)
+#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44)
+#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60)
+#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68)
+#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70)
+#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80)
+#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84)
+#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C)
+#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0)
+#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4)
+#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8)
+#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4)
+#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8)
+#define OMAP2420_SDRC_CS0 0x80000000
+#define OMAP2420_SDRC_CS1 0xA0000000
+#define CMD_NOP 0x0
+#define CMD_PRECHARGE 0x1
+#define CMD_AUTOREFRESH 0x2
+#define CMD_ENTR_PWRDOWN 0x3
+#define CMD_EXIT_PWRDOWN 0x4
+#define CMD_ENTR_SRFRSH 0x5
+#define CMD_CKE_HIGH 0x6
+#define CMD_CKE_LOW 0x7
+#define SOFTRESET BIT1
+#define SMART_IDLE (0x2 << 3)
+#define REF_ON_IDLE (0x1 << 6)
+
+
+/* UART */
+#define OMAP2420_UART1 0x4806A000
+#define OMAP2420_UART2 0x4806C000
+#define OMAP2420_UART3 0x4806E000
+
+/* General Purpose Timers */
+#define OMAP2420_GPT1 0x48028000
+#define OMAP2420_GPT2 0x4802A000
+#define OMAP2420_GPT3 0x48078000
+#define OMAP2420_GPT4 0x4807A000
+#define OMAP2420_GPT5 0x4807C000
+#define OMAP2420_GPT6 0x4807E000
+#define OMAP2420_GPT7 0x48080000
+#define OMAP2420_GPT8 0x48082000
+#define OMAP2420_GPT9 0x48084000
+#define OMAP2420_GPT10 0x48086000
+#define OMAP2420_GPT11 0x48088000
+#define OMAP2420_GPT12 0x4808A000
+
+/* timer regs offsets (32 bit regs) */
+#define TIDR 0x0 /* r */
+#define TIOCP_CFG 0x10 /* rw */
+#define TISTAT 0x14 /* r */
+#define TISR 0x18 /* rw */
+#define TIER 0x1C /* rw */
+#define TWER 0x20 /* rw */
+#define TCLR 0x24 /* rw */
+#define TCRR 0x28 /* rw */
+#define TLDR 0x2C /* rw */
+#define TTGR 0x30 /* rw */
+#define TWPS 0x34 /* r */
+#define TMAR 0x38 /* rw */
+#define TCAR1 0x3c /* r */
+#define TSICR 0x40 /* rw */
+#define TCAR2 0x44 /* r */
+
+/* WatchDog Timers (1 secure, 3 GP) */
+#define WD1_BASE 0x48020000
+#define WD2_BASE 0x48022000
+#define WD3_BASE 0x48024000
+#define WD4_BASE 0x48026000
+#define WWPS 0x34 /* r */
+#define WSPR 0x48 /* rw */
+#define WD_UNLOCK1 0xAAAA
+#define WD_UNLOCK2 0x5555
+
+/* PRCM */
+#define OMAP2420_CM_BASE 0x48008000
+#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080)
+#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140)
+#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200)
+#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204)
+#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210)
+#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214)
+#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240)
+#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440)
+#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244)
+#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340)
+#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450)
+#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500)
+#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520)
+#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540)
+#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544)
+#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840)
+
+/*
+ * H4 specific Section
+ */
+
+/*
+ * The 2420's chip selects are programmable. The mask ROM
+ * does configure CS0 to 0x08000000 before dispatch. So, if
+ * you want your code to live below that address, you have to
+ * be prepared to jump though hoops, to reset the base address.
+ */
+#if defined(CONFIG_OMAP2420H4)
+/* GPMC */
+#ifdef CONFIG_VIRTIO_A /* Pre version B */
+# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */
+# define H4_CS1_BASE 0x04000000 /* debug board */
+# define H4_CS2_BASE 0x0A000000 /* wifi board */
+#else
+# define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */
+# define H4_CS1_BASE 0x08000000 /* debug board */
+# define H4_CS2_BASE 0x0A000000 /* wifi board */
+#endif
+
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_OFFSET0 0x40000000
+#define SRAM_OFFSET1 0x00200000
+#define SRAM_OFFSET2 0x0000F800
+#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
+
+/* FPGA on Debug board.*/
+#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b)
+#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c)
+#endif /* endif CONFIG_2420H4 */
+
+#if defined(CONFIG_APOLLON)
+#define APOLLON_CS0_BASE 0x00000000 /* OneNAND */
+#define APOLLON_CS1_BASE 0x08000000 /* ethernet */
+#define APOLLON_CS2_BASE 0x10000000 /* OneNAND */
+#define APOLLON_CS3_BASE 0x18000000 /* NOR */
+
+#define ETH_CONTROL_REG (APOLLON_CS1_BASE + 0x30b)
+#define LAN_RESET_REGISTER (APOLLON_CS1_BASE + 0x1c)
+#endif /* endif CONFIG_APOLLON */
+
+/* Common */
+#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
+
+#define PERIFERAL_PORT_BASE 0x480FE003
+
+#endif
--- /dev/null
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+/* Size defintions
+ * Copyright (C) ARM Limited 1998. All rights reserved.
+ */
+
+#ifndef __sizes_h
+#define __sizes_h 1
+
+/* handy sizes */
+#define SZ_1K 0x00000400
+#define SZ_4K 0x00001000
+#define SZ_8K 0x00002000
+#define SZ_16K 0x00004000
+#define SZ_32K 0x00008000
+#define SZ_64K 0x00010000
+#define SZ_128K 0x00020000
+#define SZ_256K 0x00040000
+#define SZ_512K 0x00080000
+
+#define SZ_1M 0x00100000
+#define SZ_2M 0x00200000
+#define SZ_4M 0x00400000
+#define SZ_8M 0x00800000
+#define SZ_16M 0x01000000
+#define SZ_31M 0x01F00000
+#define SZ_32M 0x02000000
+#define SZ_64M 0x04000000
+#define SZ_128M 0x08000000
+#define SZ_256M 0x10000000
+#define SZ_512M 0x20000000
+
+#define SZ_1G 0x40000000
+#define SZ_2G 0x80000000
+
+#endif /* __sizes_h */
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP24XX_SYS_INFO_H_
+#define _OMAP24XX_SYS_INFO_H_
+
+typedef struct h4_system_data {
+ /* base board info */
+ u32 base_b_rev; /* rev from base board i2c */
+ /* cpu board info */
+ u32 cpu_b_rev; /* rev from cpu board i2c */
+ u32 cpu_b_mux; /* mux type on daughter board */
+ u32 cpu_b_ddr_type; /* mem type */
+ u32 cpu_b_ddr_speed; /* ddr speed rating */
+ u32 cpu_b_switches; /* boot ctrl switch settings */
+ /* cpu info */
+ u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/
+ u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/
+} h4_sys_data;
+
+#define XDR_POP 5 /* package on package part */
+#define SDR_DISCRETE 4 /* 128M memory SDR module*/
+#define DDR_STACKED 3 /* stacked part on 2422 */
+#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */
+#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
+
+#define DDR_100 100 /* type found on most mem d-boards */
+#define DDR_111 111 /* some combo parts */
+#define DDR_133 133 /* most combo, some mem d-boards */
+#define DDR_165 165 /* future parts */
+
+#define CPU_2420 0x2420
+#define CPU_2422 0x2422 /* 2420 + 64M stacked */
+#define CPU_2423 0x2423 /* 2420 + 96M stacked */
+
+#define CPU_2422_ES1 1
+#define CPU_2422_ES2 2
+#define CPU_2420_ES1 1
+#define CPU_2420_ES2 2
+#define CPU_2420_2422_ES1 1
+
+#define CPU_2420_CHIPID 0x0B5D9000
+#define CPU_24XX_ID_MASK 0x0FFFF000
+#define CPU_242X_REV_MASK 0xF0000000
+#define CPU_242X_PID_MASK 0x000F0000
+
+#define BOARD_H4_MENELAUS 1
+#define BOARD_H4_SDP 2
+
+#define GPMC_MUXED 1
+#define GPMC_NONMUXED 0
+
+#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */
+#define TYPE_NOR 0x000
+
+#define WIDTH_8BIT 0x0000
+#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
+
+#define I2C_MENELAUS 0x72 /* i2c id for companion chip */
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP24XX_SYS_PROTO_H_
+#define _OMAP24XX_SYS_PROTO_H_
+
+void prcm_init(void);
+void memif_init(void);
+void sdrc_init(void);
+void do_sdrc_init(u32,u32);
+void gpmc_init(void);
+
+void ether_init(void);
+void watchdog_init(void);
+void set_muxconf_regs(void);
+void peripheral_enable(void);
+
+u32 get_cpu_type(void);
+u32 get_cpu_rev(void);
+u32 get_mem_type(void);
+u32 get_sysboot_value(void);
+u32 get_gpmc0_base(void);
+u32 is_gpmc_muxed(void);
+u32 get_gpmc0_type(void);
+u32 get_gpmc0_width(void);
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound);
+u32 get_board_type(void);
+void display_board_info(u32);
+void update_mux(u32,u32);
+u32 get_sdr_cs_size(u32 offset);
+
+u32 running_in_sdram(void);
+u32 running_in_sram(void);
+u32 running_in_flash(void);
+u32 running_from_internal_boot(void);
+u32 get_device_type(void);
+#endif
#define DV_EVM
#define CFG_NAND_SMALLPAGE
#define CFG_USE_NOR
+#define CFG_USE_INTEL_NOR /* Define this when your DVEVM has Intel
+ * flash instead of AMD flash
+ */
/*===================*/
/* SoC Configuration */
/*===================*/
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CFG_HZ 1000
+#define CFG_DAVINCI_PINMUX_0 0x00000c1f
+#define CFG_DAVINCI_WAITCFG 0x00000000
+#define CFG_DAVINCI_ACFG2 0x3ffffffd /* CE configs */
+#define CFG_DAVINCI_ACFG3 0x3ffffffd
+#define CFG_DAVINCI_ACFG4 0x3ffffffd
+#define CFG_DAVINCI_ACFG5 0x3ffffffd
+#undef CFG_DAVINCI_NANDCE /* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
+#define CFG_DAVINCI_SDREF 0x000005c3
+#define CFG_DAVINCI_SDCFG 0x00178632 /* 8 banks */
+#define CFG_DAVINCI_SDTIM0 0x28923211
+#define CFG_DAVINCI_SDTIM1 0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0 0x00444400
+/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL1_PLLM 0x15
+#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2 0x01
/*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
#ifdef CFG_USE_NAND
#undef CFG_ENV_IS_IN_FLASH
#define CFG_NO_FLASH
-#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
+#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#ifdef CFG_NAND_SMALLPAGE
#define CFG_ENV_SECT_SIZE 512 /* Env sector Size */
#define CFG_ENV_SIZE SZ_16K
#undef CONFIG_SKIP_RELOCATE_UBOOT
#endif
#define CFG_ENV_IS_IN_FLASH
-#undef CFG_NO_FLASH
+#undef CFG_NO_FLASH
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
-#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
-#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*3)
-#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR)
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
-#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
+#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
+#ifdef CFG_USE_INTEL_NOR
+#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size INTEL Flash */
+#define CFG_FLASH_PROTECTION 1
+#else
+#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
+#endif
#endif
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
-#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_MISC_INIT_R
-#undef CONFIG_BOOTDELAY
+#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CFG_HZ 1000
+#define CFG_DAVINCI_PINMUX_0 0x00000c1f
+#define CFG_DAVINCI_WAITCFG 0x00000000
+#define CFG_DAVINCI_ACFG2 0x0432229c /* CE configs */
+#define CFG_DAVINCI_ACFG3 0x3ffffffd
+#define CFG_DAVINCI_ACFG4 0x3ffffffd
+#define CFG_DAVINCI_ACFG5 0x3ffffffd
+#define CFG_DAVINCI_NANDCE 2 /* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
+#define CFG_DAVINCI_SDREF 0x000005c3
+#define CFG_DAVINCI_SDCFG 0x00178622 /* 4 banks */
+#define CFG_DAVINCI_SDTIM0 0x28923211
+#define CFG_DAVINCI_SDTIM1 0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0 0x00444400
+/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL1_PLLM 0x15
+#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2 0x01
/*=============*/
/* Memory Info */
/*=============*/
#define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
-#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
/*====================*/
/* Serial Driver info */
/*====================*/
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CFG_HZ 1000
+#define CFG_DAVINCI_PINMUX_0 0x00000c1f
+#define CFG_DAVINCI_WAITCFG 0x00000000
+#define CFG_DAVINCI_ACFG2 0x3ffffffd /* CE configs */
+#define CFG_DAVINCI_ACFG3 0x3ffffffd
+#define CFG_DAVINCI_ACFG4 0x3ffffffd
+#define CFG_DAVINCI_ACFG5 0x3ffffffd
+#undef CFG_DAVINCI_NANDCE /* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
+#define CFG_DAVINCI_SDREF 0x000005c3
+#define CFG_DAVINCI_SDCFG 0x00178632 /* 8 banks */
+#define CFG_DAVINCI_SDTIM0 0x28923211
+#define CFG_DAVINCI_SDTIM1 0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0 0x00444400
+/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL1_PLLM 0x15
+#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2 0x01
/*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Texas Instruments.
+ *
+ * Configuration settings for the 242x TI H4 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
+#define CONFIG_MX31 1 /* in a mx31 */
+#define CONFIG_MX31_HCLK_FREQ 26000000
+#define CONFIG_MX31_CLK32 32000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Temporarily disabled */
+#if 0
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#endif
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE 128 /* num bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MX31_UART 1
+#define CFG_MX31_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.23.168
+#define CONFIG_SERVERIP 192.168.23.2
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
+ "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
+ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs), v3, tcp\0" \
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
+ "tftpboot 0x80000000 uImage-mx31; bootm\0" \
+ "prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; " \
+ "protect off all; erase 0xa00d0000 0xa01effff; " \
+ "cp.b 0x80000000 0xa00d0000 $(filesize)\0"
+
+#define CONFIG_DRIVER_SMC911X 1
+#define CONFIG_DRIVER_SMC911X_BASE 0xb4020000
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "uboot> "
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0 /* memtest works on */
+#define CFG_MEMTEST_END 0x10000
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0 /* default load address */
+
+#define CFG_HZ 32000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_FLASH_BASE 0xa0000000
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+
+#define CFG_ENV_ADDR 0xa01f0000
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SECT_SIZE (64 * 1024)
+#define CFG_ENV_SIZE (64 * 1024)
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
+#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */
+
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Texas Instruments.
+ *
+ * Configuration settings for the 242x TI H4 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
+#define CONFIG_MX31 1 /* in a mx31 */
+#define CONFIG_MX31_HCLK_FREQ 26000000
+#define CONFIG_MX31_CLK32 32000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Temporarily disabled */
+#if 0
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#endif
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE 128 /* num bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CFG_I2C_MX31_PORT2 1
+#define CFG_I2C_SPEED 100000
+#define CFG_I2C_SLAVE 0xfe
+
+#define CONFIG_MX31_UART 1
+#define CFG_MX31_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+
+#define CONFIG_BOOTDELAY 3
+
+#define MTDPARTS_DEFAULT \
+ "mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)"
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.23.168
+#define CONFIG_SERVERIP 192.168.23.2
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
+ "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
+ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
+ "bootargs_flash=setenv bootargs $(bootargs) " \
+ "root=/dev/mtdblock2 rootfstype=jffs2\0" \
+ "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
+ "tftpboot 0x80000000 $(uimage); bootm\0" \
+ "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash; " \
+ "bootm 0x80000000\0" \
+ "unlock=yes\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "prg_uboot=tftpboot 0x80000000 $(uboot); " \
+ "protect off 0xa0000000 +0x20000; " \
+ "erase 0xa0000000 +0x20000; " \
+ "cp.b 0x80000000 0xa0000000 $(filesize)\0" \
+ "prg_kernel=tftpboot 0x80000000 $(uimage); " \
+ "erase 0xa0040000 +0x180000; " \
+ "cp.b 0x80000000 0xa0040000 $(filesize)\0" \
+ "prg_jffs2=tftpboot 0x80000000 $(jffs2); " \
+ "erase 0xa01c0000 0xa1ffffff; " \
+ "cp.b 0x80000000 0xa01c0000 $(filesize)\0"
+
+#define CONFIG_DRIVER_SMC911X 1
+#define CONFIG_DRIVER_SMC911X_BASE 0xa8000000
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "uboot> "
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0 /* memtest works on */
+#define CFG_MEMTEST_END 0x10000
+
+#define CFG_LOAD_ADDR 0 /* default load address */
+
+#define CFG_HZ 32000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_FLASH_BASE 0xa0000000
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 259 /* max number of sectors on one chip */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
+
+#define CFG_ENV_IS_IN_EEPROM 1
+#define CFG_ENV_OFFSET 0x00 /* environment starts here */
+#define CFG_ENV_SIZE 4096
+#define CFG_I2C_EEPROM_ADDR 0x52
+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of byte address */
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
+#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */
+
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ *
+ * Configuration settings for the MX31ADS Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx31-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
+#define CONFIG_MX31 1 /* in a mx31 */
+#define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */
+#define CONFIG_MX31_CLK32 32000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/*
+ * Disabled for now due to build problems under Debian and
+ * a significant increase in the final file size: 144260 vs. 109536 Bytes
+ */
+#if 0
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#endif
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE 128 /* num bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MX31_UART 1
+#define CFG_MX31_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.23.168
+#define CONFIG_SERVERIP 192.168.23.2
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
+ "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
+ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
+ "tftpboot 0x80000000 uImage-mx31; bootm\0" \
+ "prg_uboot=tftpboot 0x80000000 u-boot-mx31ads.bin; " \
+ "protect off 0xa0000000 0xa001ffff; " \
+ "erase 0xa0000000 0xa001ffff; " \
+ "cp.b 0x80000000 0xa0000000 $(filesize)\0"
+
+#define CONFIG_DRIVER_CS8900 1
+#define CS8900_BASE 0xb4020300
+#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> "
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0 /* memtest works on */
+#define CFG_MEMTEST_END 0x10000
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR CSD0_BASE /* default load address */
+
+#define CFG_HZ 32000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_FLASH_BASE CS0_BASE
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 262 /* max number of sectors on one chip */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
+#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128KiB */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SECT_SIZE (32 * 1024)
+#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+/* S29WS256N NOR flash has 4 32KiB small sectors at beginning and end.
+ * The rest of 32MiB is in 128KiB big sectors.
+ * U-Boot occupies the low 4 sectors,
+ * if we put environment next to it, we will have to occupy 128KiB for it.
+ * Putting it at the top of flash we use only 32KiB. */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 32 * 1024 * 1024 - CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#if 0 /* Doesn't work yet, work in progress */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes(~10x faster)*/
+#endif
+#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
+
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ *
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*=======*/
+/* Board */
+/*=======*/
+#define CFG_PMDRA
+#define CFG_NAND_LARGEPAGE
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SYS_CLK_FREQ ((CFG_HZ_CLOCK * (CFG_DAVINCI_PLL1_PLLM + 1))/2)
+#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
+#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
+#define CFG_HZ 1000
+#define CFG_DAVINCI_PINMUX_0 0x00000c1f
+#define CFG_DAVINCI_WAITCFG 0x10000000
+#define CFG_DAVINCI_ACFG2 0x00460385 /* NOR CE Config */
+#define CFG_DAVINCI_ACFG3 0x0822218c /* NAND CE Config */
+#define CFG_DAVINCI_ACFG4 0x3ffffffd
+#define CFG_DAVINCI_ACFG5 0x3ffffffd
+#define CFG_DAVINCI_NANDCE 3 /* Use CE3 for NAND */
+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
+#define CFG_DAVINCI_SDREF 0x000005c3
+#define CFG_DAVINCI_SDCFG 0x00178832 /* 8 banks , CAS = 4*/
+#define CFG_DAVINCI_SDTIM0 0x28923211
+#define CFG_DAVINCI_SDTIM1 0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0 0x00444400
+/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL1_PLLM 0x12
+#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2 0x01
+/*====================================================*/
+/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
+/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
+/*====================================================*/
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_EEPROM_PAGE_WRITE_BITS 6
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+/*=============*/
+/* Memory Info */
+/*=============*/
+#define CFG_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
+#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */
+#define CFG_MEMTEST_START 0x80000000 /* memtest start address */
+#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
+#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */
+#define DDR_8BANKS /* 8-bank DDR2 (256MB) */
+/*====================*/
+/* Serial Driver info */
+/*====================*/
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */
+#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */
+#define CFG_NS16550_COM2 0x01c20800 /* Base address of UART2 */
+#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/*===================*/
+/* I2C Configuration */
+/*===================*/
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CFG_I2C_SPEED 50000 /* 100Kbps won't work, silicon bug */
+#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+/*==================================*/
+/* Network & Ethernet Configuration */
+/*==================================*/
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#define CFG_USE_NAND
+#define CFG_NAND_BASE 0x04000000
+#undef CFG_NAND_HW_ECC
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#define DEF_BOOTM ""
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR)
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster)*/
+#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
+#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
+#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
+#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
+#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
+#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size INTEL Flash */
+#define CFG_FLASH_PROTECTION 1
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CFG_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_ENV_OVERWRITE
+/*===================*/
+/* Linux Information */
+/*===================*/
+#define LINUX_BOOT_PARAM_ADDR 0x80000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_BOOTARGS \
+ "mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND "run nand"
+#define CONFIG_EXTRA_ENV_SETTINGS "ethaddr=00:11:22:33:44:55\n"
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+/*=======================*/
+/* KGDB support (if any) */
+/*=======================*/
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
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