pinctrl: renesas: pfc-r8a77990: Sync PFC tables with Linux 5.11

Sync the R8A77990 SoC PFC tables with Linux 5.11 , commit f40ddce88593.

Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>

diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c
index b13fc0ba632943c3c15d9ab687019adc0420bb10..572b041b83e62fa3cf8f7e251387c96c8f50f3e4 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -1603,6 +1603,7 @@ static const unsigned int canfd1_data_mux[] = {
        CANFD1_TX_MARK, CANFD1_RX_MARK,
 };
 
        CANFD1_TX_MARK, CANFD1_RX_MARK,
 };
 

+#ifdef CONFIG_PINCTRL_PFC_R8A77990

 /* - DRIF0 --------------------------------------------------------------- */
 static const unsigned int drif0_ctrl_a_pins[] = {
        /* CLK, SYNC */
 /* - DRIF0 --------------------------------------------------------------- */
 static const unsigned int drif0_ctrl_a_pins[] = {
        /* CLK, SYNC */


@@ -1795,6 +1796,7 @@ static const unsigned int drif3_data1_b_pins[] = {
 static const unsigned int drif3_data1_b_mux[] = {
        RIF3_D1_B_MARK,
 };
 static const unsigned int drif3_data1_b_mux[] = {
        RIF3_D1_B_MARK,
 };

+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */

 
 /* - DU --------------------------------------------------------------------- */
 static const unsigned int du_rgb666_pins[] = {
 
 /* - DU --------------------------------------------------------------------- */
 static const unsigned int du_rgb666_pins[] = {


@@ -2818,6 +2820,57 @@ static const unsigned int pwm6_b_mux[] = {
        PWM6_B_MARK,
 };
 
        PWM6_B_MARK,
 };
 

+/* - QSPI0 ------------------------------------------------------------------ */
+static const unsigned int qspi0_ctrl_pins[] = {
+       /* QSPI0_SPCLK, QSPI0_SSL */
+       RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 5),
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+       QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data2_pins[] = {
+       /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+       RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+};
+static const unsigned int qspi0_data2_mux[] = {
+       QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+};
+static const unsigned int qspi0_data4_pins[] = {
+       /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+       RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+       /* QSPI0_IO2, QSPI0_IO3 */
+       RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+};
+static const unsigned int qspi0_data4_mux[] = {
+       QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+       QSPI0_IO2_MARK, QSPI0_IO3_MARK,
+};
+/* - QSPI1 ------------------------------------------------------------------ */
+static const unsigned int qspi1_ctrl_pins[] = {
+       /* QSPI1_SPCLK, QSPI1_SSL */
+       RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 11),
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+       QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data2_pins[] = {
+       /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+       RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+};
+static const unsigned int qspi1_data2_mux[] = {
+       QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+};
+static const unsigned int qspi1_data4_pins[] = {
+       /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+       RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+       /* QSPI1_IO2, QSPI1_IO3 */
+       RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+};
+static const unsigned int qspi1_data4_mux[] = {
+       QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+       QSPI1_IO2_MARK, QSPI1_IO3_MARK,
+};
+

 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_a_pins[] = {
        /* RX, TX */
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_a_pins[] = {
        /* RX, TX */


@@ -3770,8 +3823,10 @@ static const unsigned int vin5_clk_b_mux[] = {
 };
 
 static const struct {
 };
 
 static const struct {

-       struct sh_pfc_pin_group common[247];
+       struct sh_pfc_pin_group common[253];
+#ifdef CONFIG_PINCTRL_PFC_R8A77990

        struct sh_pfc_pin_group automotive[21];
        struct sh_pfc_pin_group automotive[21];

+#endif

 } pinmux_groups = {
        .common = {
                SH_PFC_PIN_GROUP(audio_clk_a),
 } pinmux_groups = {
        .common = {
                SH_PFC_PIN_GROUP(audio_clk_a),


@@ -3916,6 +3971,12 @@ static const struct {
                SH_PFC_PIN_GROUP(pwm5_b),
                SH_PFC_PIN_GROUP(pwm6_a),
                SH_PFC_PIN_GROUP(pwm6_b),
                SH_PFC_PIN_GROUP(pwm5_b),
                SH_PFC_PIN_GROUP(pwm6_a),
                SH_PFC_PIN_GROUP(pwm6_b),

+               SH_PFC_PIN_GROUP(qspi0_ctrl),
+               SH_PFC_PIN_GROUP(qspi0_data2),
+               SH_PFC_PIN_GROUP(qspi0_data4),
+               SH_PFC_PIN_GROUP(qspi1_ctrl),
+               SH_PFC_PIN_GROUP(qspi1_data2),
+               SH_PFC_PIN_GROUP(qspi1_data4),

                SH_PFC_PIN_GROUP(scif0_data_a),
                SH_PFC_PIN_GROUP(scif0_clk_a),
                SH_PFC_PIN_GROUP(scif0_ctrl_a),
                SH_PFC_PIN_GROUP(scif0_data_a),
                SH_PFC_PIN_GROUP(scif0_clk_a),
                SH_PFC_PIN_GROUP(scif0_ctrl_a),


@@ -4022,6 +4083,7 @@ static const struct {
                SH_PFC_PIN_GROUP(vin5_clk_a),
                SH_PFC_PIN_GROUP(vin5_clk_b),
        },
                SH_PFC_PIN_GROUP(vin5_clk_a),
                SH_PFC_PIN_GROUP(vin5_clk_b),
        },

+#ifdef CONFIG_PINCTRL_PFC_R8A77990

        .automotive = {
                SH_PFC_PIN_GROUP(drif0_ctrl_a),
                SH_PFC_PIN_GROUP(drif0_data0_a),
        .automotive = {
                SH_PFC_PIN_GROUP(drif0_ctrl_a),
                SH_PFC_PIN_GROUP(drif0_data0_a),


@@ -4045,6 +4107,7 @@ static const struct {
                SH_PFC_PIN_GROUP(drif3_data0_b),
                SH_PFC_PIN_GROUP(drif3_data1_b),
        }
                SH_PFC_PIN_GROUP(drif3_data0_b),
                SH_PFC_PIN_GROUP(drif3_data1_b),
        }

+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */

 };
 
 static const char * const audio_clk_groups[] = {
 };
 
 static const char * const audio_clk_groups[] = {


@@ -4098,6 +4161,7 @@ static const char * const canfd1_groups[] = {
        "canfd1_data",
 };
 
        "canfd1_data",
 };
 

+#ifdef CONFIG_PINCTRL_PFC_R8A77990

 static const char * const drif0_groups[] = {
        "drif0_ctrl_a",
        "drif0_data0_a",
 static const char * const drif0_groups[] = {
        "drif0_ctrl_a",
        "drif0_data0_a",


@@ -4130,6 +4194,7 @@ static const char * const drif3_groups[] = {
        "drif3_data0_b",
        "drif3_data1_b",
 };
        "drif3_data0_b",
        "drif3_data1_b",
 };

+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */

 
 static const char * const du_groups[] = {
        "du_rgb666",
 
 static const char * const du_groups[] = {
        "du_rgb666",


@@ -4315,6 +4380,18 @@ static const char * const pwm6_groups[] = {
        "pwm6_b",
 };
 
        "pwm6_b",
 };
 

+static const char * const qspi0_groups[] = {
+       "qspi0_ctrl",
+       "qspi0_data2",
+       "qspi0_data4",
+};
+
+static const char * const qspi1_groups[] = {
+       "qspi1_ctrl",
+       "qspi1_data2",
+       "qspi1_data4",
+};
+

 static const char * const scif0_groups[] = {
        "scif0_data_a",
        "scif0_clk_a",
 static const char * const scif0_groups[] = {
        "scif0_data_a",
        "scif0_clk_a",


@@ -4469,8 +4546,10 @@ static const char * const vin5_groups[] = {
 };
 
 static const struct {
 };
 
 static const struct {

-       struct sh_pfc_function common[47];
+       struct sh_pfc_function common[49];
+#ifdef CONFIG_PINCTRL_PFC_R8A77990

        struct sh_pfc_function automotive[4];
        struct sh_pfc_function automotive[4];

+#endif

 } pinmux_functions = {
        .common = {
                SH_PFC_FUNCTION(audio_clk),
 } pinmux_functions = {
        .common = {
                SH_PFC_FUNCTION(audio_clk),


@@ -4504,6 +4583,8 @@ static const struct {
                SH_PFC_FUNCTION(pwm4),
                SH_PFC_FUNCTION(pwm5),
                SH_PFC_FUNCTION(pwm6),
                SH_PFC_FUNCTION(pwm4),
                SH_PFC_FUNCTION(pwm5),
                SH_PFC_FUNCTION(pwm6),

+               SH_PFC_FUNCTION(qspi0),
+               SH_PFC_FUNCTION(qspi1),

                SH_PFC_FUNCTION(scif0),
                SH_PFC_FUNCTION(scif1),
                SH_PFC_FUNCTION(scif2),
                SH_PFC_FUNCTION(scif0),
                SH_PFC_FUNCTION(scif1),
                SH_PFC_FUNCTION(scif2),


@@ -4521,12 +4602,14 @@ static const struct {
                SH_PFC_FUNCTION(vin4),
                SH_PFC_FUNCTION(vin5),
        },
                SH_PFC_FUNCTION(vin4),
                SH_PFC_FUNCTION(vin5),
        },

+#ifdef CONFIG_PINCTRL_PFC_R8A77990

        .automotive = {
                SH_PFC_FUNCTION(drif0),
                SH_PFC_FUNCTION(drif1),
                SH_PFC_FUNCTION(drif2),
                SH_PFC_FUNCTION(drif3),
        }
        .automotive = {
                SH_PFC_FUNCTION(drif0),
                SH_PFC_FUNCTION(drif1),
                SH_PFC_FUNCTION(drif2),
                SH_PFC_FUNCTION(drif3),
        }

+#endif /* CONFIG_PINCTRL_PFC_R8A77990 */

 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {