+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for AM6 SoC Family Main Domain peripherals
- *
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
- */
-#include <dt-bindings/phy/phy-am654-serdes.h>
-
-&cbass_main {
- msmc_ram: sram@70000000 {
- compatible = "mmio-sram";
- reg = <0x0 0x70000000 0x0 0x200000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x70000000 0x200000>;
-
- atf-sram@0 {
- reg = <0x0 0x20000>;
- };
-
- sysfw-sram@f0000 {
- reg = <0xf0000 0x10000>;
- };
-
- l3cache-sram@100000 {
- reg = <0x100000 0x100000>;
- };
- };
-
- gic500: interrupt-controller@1800000 {
- compatible = "arm,gic-v3";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01880000 0x00 0x90000>, /* GICR */
- <0x00 0x6f000000 0x00 0x2000>, /* GICC */
- <0x00 0x6f010000 0x00 0x1000>, /* GICH */
- <0x00 0x6f020000 0x00 0x2000>; /* GICV */
- /*
- * vcpumntirq:
- * virtual CPU interface maintenance interrupt
- */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-
- gic_its: msi-controller@1820000 {
- compatible = "arm,gic-v3-its";
- reg = <0x00 0x01820000 0x00 0x10000>;
- socionext,synquacer-pre-its = <0x1000000 0x400000>;
- msi-controller;
- #msi-cells = <1>;
- };
- };
-
- serdes0: serdes@900000 {
- compatible = "ti,phy-am654-serdes";
- reg = <0x0 0x900000 0x0 0x2000>;
- reg-names = "serdes";
- #phy-cells = <2>;
- power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
- clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
- assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
- assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
- ti,serdes-clk = <&serdes0_clk>;
- #clock-cells = <1>;
- mux-controls = <&serdes_mux 0>;
- };
-
- serdes1: serdes@910000 {
- compatible = "ti,phy-am654-serdes";
- reg = <0x0 0x910000 0x0 0x2000>;
- reg-names = "serdes";
- #phy-cells = <2>;
- power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
- clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
- assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
- assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
- ti,serdes-clk = <&serdes1_clk>;
- #clock-cells = <1>;
- mux-controls = <&serdes_mux 1>;
- };
-
- main_uart0: serial@2800000 {
- compatible = "ti,am654-uart";
- reg = <0x00 0x02800000 0x00 0x100>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_uart1: serial@2810000 {
- compatible = "ti,am654-uart";
- reg = <0x00 0x02810000 0x00 0x100>;
- interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_uart2: serial@2820000 {
- compatible = "ti,am654-uart";
- reg = <0x00 0x02820000 0x00 0x100>;
- interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- crypto: crypto@4e00000 {
- compatible = "ti,am654-sa2ul";
- reg = <0x0 0x4e00000 0x0 0x1200>;
- power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
-
- dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
- <&main_udmap 0x4003>;
- dma-names = "tx", "rx1", "rx2";
-
- rng: rng@4e10000 {
- compatible = "inside-secure,safexcel-eip76";
- reg = <0x0 0x4e10000 0x0 0x7d>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled"; /* Used by OP-TEE */
- };
- };
-
- /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
- main_timerio_input: pinctrl@104200 {
- compatible = "pinctrl-single";
- reg = <0x0 0x104200 0x0 0x30>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000001ff>;
- };
-
- /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
- main_timerio_output: pinctrl@104280 {
- compatible = "pinctrl-single";
- reg = <0x0 0x104280 0x0 0x20>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000000f>;
- };
-
- main_pmx0: pinctrl@11c000 {
- compatible = "pinctrl-single";
- reg = <0x0 0x11c000 0x0 0x2e4>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- main_pmx1: pinctrl@11c2e8 {
- compatible = "pinctrl-single";
- reg = <0x0 0x11c2e8 0x0 0x24>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- main_i2c0: i2c@2000000 {
- compatible = "ti,am654-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2000000 0x0 0x100>;
- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 110 1>;
- power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c1: i2c@2010000 {
- compatible = "ti,am654-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2010000 0x0 0x100>;
- interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 111 1>;
- power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c2: i2c@2020000 {
- compatible = "ti,am654-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2020000 0x0 0x100>;
- interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 112 1>;
- power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c3: i2c@2030000 {
- compatible = "ti,am654-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2030000 0x0 0x100>;
- interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 113 1>;
- power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- ecap0: pwm@3100000 {
- compatible = "ti,am654-ecap", "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x0 0x03100000 0x0 0x60>;
- power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 39 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_spi0: spi@2100000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x0 0x2100000 0x0 0x400>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 137 1>;
- power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
- dma-names = "tx0", "rx0";
- status = "disabled";
- };
-
- main_spi1: spi@2110000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x0 0x2110000 0x0 0x400>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 138 1>;
- power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- assigned-clocks = <&k3_clks 137 1>;
- assigned-clock-rates = <48000000>;
- status = "disabled";
- };
-
- main_spi2: spi@2120000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x0 0x2120000 0x0 0x400>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 139 1>;
- power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- main_spi3: spi@2130000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x0 0x2130000 0x0 0x400>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 140 1>;
- power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- main_spi4: spi@2140000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x0 0x2140000 0x0 0x400>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 141 1>;
- power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- main_timer0: timer@2400000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2400000 0x00 0x400>;
- interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 23 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 23 0>;
- assigned-clock-parents = <&k3_clks 23 1>;
- power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer1: timer@2410000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2410000 0x00 0x400>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 24 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 24 0>;
- assigned-clock-parents = <&k3_clks 24 1>;
- power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer2: timer@2420000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2420000 0x00 0x400>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 27 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 27 0>;
- assigned-clock-parents = <&k3_clks 27 1>;
- power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer3: timer@2430000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2430000 0x00 0x400>;
- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 28 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 28 0>;
- assigned-clock-parents = <&k3_clks 28 1>;
- power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer4: timer@2440000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2440000 0x00 0x400>;
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 29 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 29 0>;
- assigned-clock-parents = <&k3_clks 29 1>;
- power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer5: timer@2450000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2450000 0x00 0x400>;
- interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 30 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 30 0>;
- assigned-clock-parents = <&k3_clks 30 1>;
- power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer6: timer@2460000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2460000 0x00 0x400>;
- interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 31 0>;
- assigned-clocks = <&k3_clks 31 0>;
- assigned-clock-parents = <&k3_clks 31 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer7: timer@2470000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2470000 0x00 0x400>;
- interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 32 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 32 0>;
- assigned-clock-parents = <&k3_clks 32 1>;
- power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer8: timer@2480000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2480000 0x00 0x400>;
- interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 33 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 33 0>;
- assigned-clock-parents = <&k3_clks 33 1>;
- power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer9: timer@2490000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2490000 0x00 0x400>;
- interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 34 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 34 0>;
- assigned-clock-parents = <&k3_clks 34 1>;
- power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer10: timer@24a0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24a0000 0x00 0x400>;
- interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 25 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 25 0>;
- assigned-clock-parents = <&k3_clks 25 1>;
- power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer11: timer@24b0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24b0000 0x00 0x400>;
- interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 26 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 26 0>;
- assigned-clock-parents = <&k3_clks 26 1>;
- power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- sdhci0: mmc@4f80000 {
- compatible = "ti,am654-sdhci-5.1";
- reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
- power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
- clock-names = "clk_ahb", "clk_xin";
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0x0>;
- ti,otap-del-sel-sdr25 = <0x0>;
- ti,otap-del-sel-sdr50 = <0x8>;
- ti,otap-del-sel-sdr104 = <0x7>;
- ti,otap-del-sel-ddr50 = <0x5>;
- ti,otap-del-sel-ddr52 = <0x5>;
- ti,otap-del-sel-hs200 = <0x5>;
- ti,otap-del-sel-hs400 = <0x0>;
- ti,trm-icp = <0x8>;
- dma-coherent;
- };
-
- sdhci1: mmc@4fa0000 {
- compatible = "ti,am654-sdhci-5.1";
- reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
- power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
- clock-names = "clk_ahb", "clk_xin";
- interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0x0>;
- ti,otap-del-sel-sdr25 = <0x0>;
- ti,otap-del-sel-sdr50 = <0x8>;
- ti,otap-del-sel-sdr104 = <0x7>;
- ti,otap-del-sel-ddr50 = <0x4>;
- ti,otap-del-sel-ddr52 = <0x4>;
- ti,otap-del-sel-hs200 = <0x7>;
- ti,clkbuf-sel = <0x7>;
- ti,trm-icp = <0x8>;
- dma-coherent;
- };
-
- scm_conf: scm-conf@100000 {
- compatible = "syscon", "simple-mfd";
- reg = <0 0x00100000 0 0x1c000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x00100000 0x1c000>;
-
- serdes0_clk: clock@4080 {
- compatible = "syscon";
- reg = <0x00004080 0x4>;
- };
-
- serdes1_clk: clock@4090 {
- compatible = "syscon";
- reg = <0x00004090 0x4>;
- };
-
- serdes_mux: mux-controller {
- compatible = "mmio-mux";
- #mux-control-cells = <1>;
- mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
- <0x4090 0x3>; /* SERDES1 lane select */
- };
-
- dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
- compatible = "syscon";
- reg = <0x000041e0 0x14>;
- };
-
- ehrpwm_tbclk: clock-controller@4140 {
- compatible = "ti,am654-ehrpwm-tbclk";
- reg = <0x4140 0x18>;
- #clock-cells = <1>;
- };
- };
-
- dwc3_0: dwc3@4000000 {
- compatible = "ti,am654-dwc3";
- reg = <0x0 0x4000000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x4000000 0x20000>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- dma-coherent;
- power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
- assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
- assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
- <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
-
- usb0: usb@10000 {
- compatible = "snps,dwc3";
- reg = <0x10000 0x10000>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "peripheral",
- "host",
- "otg";
- maximum-speed = "high-speed";
- dr_mode = "otg";
- phys = <&usb0_phy>;
- phy-names = "usb2-phy";
- snps,dis_u3_susphy_quirk;
- };
- };
-
- usb0_phy: phy@4100000 {
- compatible = "ti,am654-usb2", "ti,omap-usb2";
- reg = <0x0 0x4100000 0x0 0x54>;
- syscon-phy-power = <&scm_conf 0x4000>;
- clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
- clock-names = "wkupclk", "refclk";
- #phy-cells = <0>;
- };
-
- dwc3_1: dwc3@4020000 {
- compatible = "ti,am654-dwc3";
- reg = <0x0 0x4020000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x4020000 0x20000>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- dma-coherent;
- power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 152 2>;
- assigned-clocks = <&k3_clks 152 2>;
- assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
-
- usb1: usb@10000 {
- compatible = "snps,dwc3";
- reg = <0x10000 0x10000>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "peripheral",
- "host",
- "otg";
- maximum-speed = "high-speed";
- dr_mode = "otg";
- phys = <&usb1_phy>;
- phy-names = "usb2-phy";
- };
- };
-
- usb1_phy: phy@4110000 {
- compatible = "ti,am654-usb2", "ti,omap-usb2";
- reg = <0x0 0x4110000 0x0 0x54>;
- syscon-phy-power = <&scm_conf 0x4020>;
- clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
- clock-names = "wkupclk", "refclk";
- #phy-cells = <0>;
- };
-
- intr_main_gpio: interrupt-controller@a00000 {
- compatible = "ti,sci-intr";
- reg = <0x0 0x00a00000 0x0 0x400>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <100>;
- ti,interrupt-ranges = <0 392 32>;
- };
-
- main_navss: bus@30800000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
- dma-coherent;
- dma-ranges;
-
- ti,sci-dev-id = <118>;
-
- intr_main_navss: interrupt-controller@310e0000 {
- compatible = "ti,sci-intr";
- reg = <0x0 0x310e0000 0x0 0x2000>;
- ti,intr-trigger-type = <4>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <182>;
- ti,interrupt-ranges = <0 64 64>,
- <64 448 64>;
- };
-
- inta_main_udmass: interrupt-controller@33d00000 {
- compatible = "ti,sci-inta";
- reg = <0x0 0x33d00000 0x0 0x100000>;
- interrupt-controller;
- interrupt-parent = <&intr_main_navss>;
- msi-controller;
- #interrupt-cells = <0>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <179>;
- ti,interrupt-ranges = <0 0 256>;
- };
-
- secure_proxy_main: mailbox@32c00000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x00 0x32c00000 0x00 0x100000>,
- <0x00 0x32400000 0x00 0x100000>,
- <0x00 0x32800000 0x00 0x100000>;
- interrupt-names = "rx_011";
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- hwspinlock: spinlock@30e00000 {
- compatible = "ti,am654-hwspinlock";
- reg = <0x00 0x30e00000 0x00 0x1000>;
- #hwlock-cells = <1>;
- };
-
- mailbox0_cluster0: mailbox@31f80000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f80000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster1: mailbox@31f81000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f81000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster2: mailbox@31f82000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f82000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster3: mailbox@31f83000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f83000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster4: mailbox@31f84000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f84000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster5: mailbox@31f85000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f85000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster6: mailbox@31f86000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f86000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster7: mailbox@31f87000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f87000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster8: mailbox@31f88000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f88000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster9: mailbox@31f89000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f89000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster10: mailbox@31f8a000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f8a000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster11: mailbox@31f8b000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f8b000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- ringacc: ringacc@3c000000 {
- compatible = "ti,am654-navss-ringacc";
- reg = <0x0 0x3c000000 0x0 0x400000>,
- <0x0 0x38000000 0x0 0x400000>,
- <0x0 0x31120000 0x0 0x100>,
- <0x0 0x33000000 0x0 0x40000>,
- <0x0 0x31080000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- ti,num-rings = <818>;
- ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <187>;
- msi-parent = <&inta_main_udmass>;
- };
-
- main_udmap: dma-controller@31150000 {
- compatible = "ti,am654-navss-main-udmap";
- reg = <0x0 0x31150000 0x0 0x100>,
- <0x0 0x34000000 0x0 0x100000>,
- <0x0 0x35000000 0x0 0x100000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
- msi-parent = <&inta_main_udmass>;
- #dma-cells = <1>;
-
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <188>;
- ti,ringacc = <&ringacc>;
-
- ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
- <0xd>; /* TX_CHAN */
- ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
- <0xa>; /* RX_CHAN */
- ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
- };
-
- cpts@310d0000 {
- compatible = "ti,am65-cpts";
- reg = <0x0 0x310d0000 0x0 0x400>;
- reg-names = "cpts";
- clocks = <&main_cpts_mux>;
- clock-names = "cpts";
- interrupts-extended = <&intr_main_navss 391>;
- interrupt-names = "cpts";
- ti,cpts-periodic-outputs = <6>;
- ti,cpts-ext-ts-inputs = <8>;
-
- main_cpts_mux: refclk-mux {
- #clock-cells = <0>;
- clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
- <&k3_clks 118 6>, <&k3_clks 118 3>,
- <&k3_clks 118 8>, <&k3_clks 118 14>,
- <&k3_clks 120 3>, <&k3_clks 121 3>;
- assigned-clocks = <&main_cpts_mux>;
- assigned-clock-parents = <&k3_clks 118 5>;
- };
- };
- };
-
- main_gpio0: gpio@600000 {
- compatible = "ti,am654-gpio", "ti,keystone-gpio";
- reg = <0x0 0x600000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&intr_main_gpio>;
- interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <96>;
- ti,davinci-gpio-unbanked = <0>;
- clocks = <&k3_clks 57 0>;
- clock-names = "gpio";
- };
-
- main_gpio1: gpio@601000 {
- compatible = "ti,am654-gpio", "ti,keystone-gpio";
- reg = <0x0 0x601000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&intr_main_gpio>;
- interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <90>;
- ti,davinci-gpio-unbanked = <0>;
- clocks = <&k3_clks 58 0>;
- clock-names = "gpio";
- };
-
- pcie0_rc: pcie@5500000 {
- compatible = "ti,am654-pcie-rc";
- reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
- reg-names = "app", "dbics", "config", "atu";
- power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
- <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
- ti,syscon-pcie-id = <&scm_conf 0x210>;
- ti,syscon-pcie-mode = <&scm_conf 0x4060>;
- bus-range = <0x0 0xff>;
- num-viewport = <16>;
- max-link-speed = <2>;
- dma-coherent;
- interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
- msi-map = <0x0 &gic_its 0x0 0x10000>;
- device_type = "pci";
- status = "disabled";
- };
-
- pcie0_ep: pcie-ep@5500000 {
- compatible = "ti,am654-pcie-ep";
- reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
- reg-names = "app", "dbics", "addr_space", "atu";
- power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
- ti,syscon-pcie-mode = <&scm_conf 0x4060>;
- num-ib-windows = <16>;
- num-ob-windows = <16>;
- max-link-speed = <2>;
- dma-coherent;
- interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- };
-
- pcie1_rc: pcie@5600000 {
- compatible = "ti,am654-pcie-rc";
- reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
- reg-names = "app", "dbics", "config", "atu";
- power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
- <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
- ti,syscon-pcie-id = <&scm_conf 0x210>;
- ti,syscon-pcie-mode = <&scm_conf 0x4070>;
- bus-range = <0x0 0xff>;
- num-viewport = <16>;
- max-link-speed = <2>;
- dma-coherent;
- interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
- msi-map = <0x0 &gic_its 0x10000 0x10000>;
- device_type = "pci";
- status = "disabled";
- };
-
- pcie1_ep: pcie-ep@5600000 {
- compatible = "ti,am654-pcie-ep";
- reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
- reg-names = "app", "dbics", "addr_space", "atu";
- power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
- ti,syscon-pcie-mode = <&scm_conf 0x4070>;
- num-ib-windows = <16>;
- num-ob-windows = <16>;
- max-link-speed = <2>;
- dma-coherent;
- interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- };
-
- mcasp0: mcasp@2b00000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x0 0x02b00000 0x0 0x2000>,
- <0x0 0x02b08000 0x0 0x1000>;
- reg-names = "mpu","dat";
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 104 0>;
- clock-names = "fck";
- power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp1: mcasp@2b10000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x0 0x02b10000 0x0 0x2000>,
- <0x0 0x02b18000 0x0 0x1000>;
- reg-names = "mpu","dat";
- interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 105 0>;
- clock-names = "fck";
- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp2: mcasp@2b20000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x0 0x02b20000 0x0 0x2000>,
- <0x0 0x02b28000 0x0 0x1000>;
- reg-names = "mpu","dat";
- interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 106 0>;
- clock-names = "fck";
- power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- cal: cal@6f03000 {
- compatible = "ti,am654-cal";
- reg = <0x0 0x06f03000 0x0 0x400>,
- <0x0 0x06f03800 0x0 0x40>;
- reg-names = "cal_top",
- "cal_rx_core0";
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- ti,camerrx-control = <&scm_conf 0x40c0>;
- clock-names = "fck";
- clocks = <&k3_clks 2 0>;
- power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- csi2_0: port@0 {
- reg = <0>;
- };
- };
- };
-
- dss: dss@4a00000 {
- compatible = "ti,am65x-dss";
- reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
- <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
- <0x0 0x04a06000 0x0 0x1000>, /* vid */
- <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
- <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
- <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
- <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
- reg-names = "common", "vidl1", "vid",
- "ovr1", "ovr2", "vp1", "vp2";
-
- ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
-
- power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
-
- clocks = <&k3_clks 67 1>,
- <&k3_clks 216 1>,
- <&k3_clks 67 2>;
- clock-names = "fck", "vp1", "vp2";
-
- /*
- * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
- * DIV1. See "Figure 12-3365. DSS Integration"
- * in AM65x TRM for details.
- */
- assigned-clocks = <&k3_clks 67 2>;
- assigned-clock-parents = <&k3_clks 67 5>;
-
- interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
-
- dma-coherent;
-
- dss_ports: ports {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- ehrpwm0: pwm@3000000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x3000000 0x0 0x100>;
- power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- ehrpwm1: pwm@3010000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x3010000 0x0 0x100>;
- power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- ehrpwm2: pwm@3020000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x3020000 0x0 0x100>;
- power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- ehrpwm3: pwm@3030000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x3030000 0x0 0x100>;
- power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- ehrpwm4: pwm@3040000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x3040000 0x0 0x100>;
- power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- ehrpwm5: pwm@3050000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x3050000 0x0 0x100>;
- power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- icssg0: icssg@b000000 {
- compatible = "ti,am654-icssg";
- reg = <0x00 0xb000000 0x00 0x80000>;
- power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0xb000000 0x80000>;
-
- icssg0_mem: memories@0 {
- reg = <0x0 0x2000>,
- <0x2000 0x2000>,
- <0x10000 0x10000>;
- reg-names = "dram0", "dram1",
- "shrdram2";
- };
-
- icssg0_cfg: cfg@26000 {
- compatible = "ti,pruss-cfg", "syscon";
- reg = <0x26000 0x200>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x26000 0x2000>;
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- icssg0_coreclk_mux: coreclk-mux@3c {
- reg = <0x3c>;
- #clock-cells = <0>;
- clocks = <&k3_clks 62 19>, /* icssg0_core_clk */
- <&k3_clks 62 3>; /* icssg0_iclk */
- assigned-clocks = <&icssg0_coreclk_mux>;
- assigned-clock-parents = <&k3_clks 62 3>;
- };
-
- icssg0_iepclk_mux: iepclk-mux@30 {
- reg = <0x30>;
- #clock-cells = <0>;
- clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */
- <&icssg0_coreclk_mux>; /* core_clk */
- assigned-clocks = <&icssg0_iepclk_mux>;
- assigned-clock-parents = <&icssg0_coreclk_mux>;
- };
- };
- };
-
- icssg0_iep0: iep@2e000 {
- compatible = "ti,am654-icss-iep";
- reg = <0x2e000 0x1000>;
- clocks = <&icssg0_iepclk_mux>;
- };
-
- icssg0_iep1: iep@2f000 {
- compatible = "ti,am654-icss-iep";
- reg = <0x2f000 0x1000>;
- clocks = <&icssg0_iepclk_mux>;
- };
-
- icssg0_mii_rt: mii-rt@32000 {
- compatible = "ti,pruss-mii", "syscon";
- reg = <0x32000 0x100>;
- };
-
- icssg0_mii_g_rt: mii-g-rt@33000 {
- compatible = "ti,pruss-mii-g", "syscon";
- reg = <0x33000 0x1000>;
- };
-
- icssg0_intc: interrupt-controller@20000 {
- compatible = "ti,icssg-intc";
- reg = <0x20000 0x2000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host_intr0", "host_intr1",
- "host_intr2", "host_intr3",
- "host_intr4", "host_intr5",
- "host_intr6", "host_intr7";
- };
-
- pru0_0: pru@34000 {
- compatible = "ti,am654-pru";
- reg = <0x34000 0x4000>,
- <0x22000 0x100>,
- <0x22400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-pru0_0-fw";
- };
-
- rtu0_0: rtu@4000 {
- compatible = "ti,am654-rtu";
- reg = <0x4000 0x2000>,
- <0x23000 0x100>,
- <0x23400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-rtu0_0-fw";
- };
-
- tx_pru0_0: txpru@a000 {
- compatible = "ti,am654-tx-pru";
- reg = <0xa000 0x1800>,
- <0x25000 0x100>,
- <0x25400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-txpru0_0-fw";
- };
-
- pru0_1: pru@38000 {
- compatible = "ti,am654-pru";
- reg = <0x38000 0x4000>,
- <0x24000 0x100>,
- <0x24400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-pru0_1-fw";
- };
-
- rtu0_1: rtu@6000 {
- compatible = "ti,am654-rtu";
- reg = <0x6000 0x2000>,
- <0x23800 0x100>,
- <0x23c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-rtu0_1-fw";
- };
-
- tx_pru0_1: txpru@c000 {
- compatible = "ti,am654-tx-pru";
- reg = <0xc000 0x1800>,
- <0x25800 0x100>,
- <0x25c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-txpru0_1-fw";
- };
-
- icssg0_mdio: mdio@32400 {
- compatible = "ti,davinci_mdio";
- reg = <0x32400 0x100>;
- clocks = <&k3_clks 62 3>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <0>;
- bus_freq = <1000000>;
- status = "disabled";
- };
- };
-
- icssg1: icssg@b100000 {
- compatible = "ti,am654-icssg";
- reg = <0x00 0xb100000 0x00 0x80000>;
- power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0xb100000 0x80000>;
-
- icssg1_mem: memories@0 {
- reg = <0x0 0x2000>,
- <0x2000 0x2000>,
- <0x10000 0x10000>;
- reg-names = "dram0", "dram1",
- "shrdram2";
- };
-
- icssg1_cfg: cfg@26000 {
- compatible = "ti,pruss-cfg", "syscon";
- reg = <0x26000 0x200>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x26000 0x2000>;
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- icssg1_coreclk_mux: coreclk-mux@3c {
- reg = <0x3c>;
- #clock-cells = <0>;
- clocks = <&k3_clks 63 19>, /* icssg1_core_clk */
- <&k3_clks 63 3>; /* icssg1_iclk */
- assigned-clocks = <&icssg1_coreclk_mux>;
- assigned-clock-parents = <&k3_clks 63 3>;
- };
-
- icssg1_iepclk_mux: iepclk-mux@30 {
- reg = <0x30>;
- #clock-cells = <0>;
- clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */
- <&icssg1_coreclk_mux>; /* core_clk */
- assigned-clocks = <&icssg1_iepclk_mux>;
- assigned-clock-parents = <&icssg1_coreclk_mux>;
- };
- };
- };
-
- icssg1_iep0: iep@2e000 {
- compatible = "ti,am654-icss-iep";
- reg = <0x2e000 0x1000>;
- clocks = <&icssg1_iepclk_mux>;
- };
-
- icssg1_iep1: iep@2f000 {
- compatible = "ti,am654-icss-iep";
- reg = <0x2f000 0x1000>;
- clocks = <&icssg1_iepclk_mux>;
- };
-
- icssg1_mii_rt: mii-rt@32000 {
- compatible = "ti,pruss-mii", "syscon";
- reg = <0x32000 0x100>;
- };
-
- icssg1_mii_g_rt: mii-g-rt@33000 {
- compatible = "ti,pruss-mii-g", "syscon";
- reg = <0x33000 0x1000>;
- };
-
- icssg1_intc: interrupt-controller@20000 {
- compatible = "ti,icssg-intc";
- reg = <0x20000 0x2000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host_intr0", "host_intr1",
- "host_intr2", "host_intr3",
- "host_intr4", "host_intr5",
- "host_intr6", "host_intr7";
- };
-
- pru1_0: pru@34000 {
- compatible = "ti,am654-pru";
- reg = <0x34000 0x4000>,
- <0x22000 0x100>,
- <0x22400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-pru1_0-fw";
- };
-
- rtu1_0: rtu@4000 {
- compatible = "ti,am654-rtu";
- reg = <0x4000 0x2000>,
- <0x23000 0x100>,
- <0x23400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-rtu1_0-fw";
- };
-
- tx_pru1_0: txpru@a000 {
- compatible = "ti,am654-tx-pru";
- reg = <0xa000 0x1800>,
- <0x25000 0x100>,
- <0x25400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-txpru1_0-fw";
- };
-
- pru1_1: pru@38000 {
- compatible = "ti,am654-pru";
- reg = <0x38000 0x4000>,
- <0x24000 0x100>,
- <0x24400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-pru1_1-fw";
- };
-
- rtu1_1: rtu@6000 {
- compatible = "ti,am654-rtu";
- reg = <0x6000 0x2000>,
- <0x23800 0x100>,
- <0x23c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-rtu1_1-fw";
- };
-
- tx_pru1_1: txpru@c000 {
- compatible = "ti,am654-tx-pru";
- reg = <0xc000 0x1800>,
- <0x25800 0x100>,
- <0x25c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-txpru1_1-fw";
- };
-
- icssg1_mdio: mdio@32400 {
- compatible = "ti,davinci_mdio";
- reg = <0x32400 0x100>;
- clocks = <&k3_clks 63 3>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <0>;
- bus_freq = <1000000>;
- status = "disabled";
- };
- };
-
- icssg2: icssg@b200000 {
- compatible = "ti,am654-icssg";
- reg = <0x00 0xb200000 0x00 0x80000>;
- power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0xb200000 0x80000>;
-
- icssg2_mem: memories@0 {
- reg = <0x0 0x2000>,
- <0x2000 0x2000>,
- <0x10000 0x10000>;
- reg-names = "dram0", "dram1",
- "shrdram2";
- };
-
- icssg2_cfg: cfg@26000 {
- compatible = "ti,pruss-cfg", "syscon";
- reg = <0x26000 0x200>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x26000 0x2000>;
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- icssg2_coreclk_mux: coreclk-mux@3c {
- reg = <0x3c>;
- #clock-cells = <0>;
- clocks = <&k3_clks 64 19>, /* icssg1_core_clk */
- <&k3_clks 64 3>; /* icssg1_iclk */
- assigned-clocks = <&icssg2_coreclk_mux>;
- assigned-clock-parents = <&k3_clks 64 3>;
- };
-
- icssg2_iepclk_mux: iepclk-mux@30 {
- reg = <0x30>;
- #clock-cells = <0>;
- clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */
- <&icssg2_coreclk_mux>; /* core_clk */
- assigned-clocks = <&icssg2_iepclk_mux>;
- assigned-clock-parents = <&icssg2_coreclk_mux>;
- };
- };
- };
-
- icssg2_iep0: iep@2e000 {
- compatible = "ti,am654-icss-iep";
- reg = <0x2e000 0x1000>;
- clocks = <&icssg2_iepclk_mux>;
- };
-
- icssg2_iep1: iep@2f000 {
- compatible = "ti,am654-icss-iep";
- reg = <0x2f000 0x1000>;
- clocks = <&icssg2_iepclk_mux>;
- };
-
- icssg2_mii_rt: mii-rt@32000 {
- compatible = "ti,pruss-mii", "syscon";
- reg = <0x32000 0x100>;
- };
-
- icssg2_mii_g_rt: mii-g-rt@33000 {
- compatible = "ti,pruss-mii-g", "syscon";
- reg = <0x33000 0x1000>;
- };
-
- icssg2_intc: interrupt-controller@20000 {
- compatible = "ti,icssg-intc";
- reg = <0x20000 0x2000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host_intr0", "host_intr1",
- "host_intr2", "host_intr3",
- "host_intr4", "host_intr5",
- "host_intr6", "host_intr7";
- };
-
- pru2_0: pru@34000 {
- compatible = "ti,am654-pru";
- reg = <0x34000 0x4000>,
- <0x22000 0x100>,
- <0x22400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-pru2_0-fw";
- };
-
- rtu2_0: rtu@4000 {
- compatible = "ti,am654-rtu";
- reg = <0x4000 0x2000>,
- <0x23000 0x100>,
- <0x23400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-rtu2_0-fw";
- };
-
- tx_pru2_0: txpru@a000 {
- compatible = "ti,am654-tx-pru";
- reg = <0xa000 0x1800>,
- <0x25000 0x100>,
- <0x25400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-txpru2_0-fw";
- };
-
- pru2_1: pru@38000 {
- compatible = "ti,am654-pru";
- reg = <0x38000 0x4000>,
- <0x24000 0x100>,
- <0x24400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-pru2_1-fw";
- };
-
- rtu2_1: rtu@6000 {
- compatible = "ti,am654-rtu";
- reg = <0x6000 0x2000>,
- <0x23800 0x100>,
- <0x23c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-rtu2_1-fw";
- };
-
- tx_pru2_1: txpru@c000 {
- compatible = "ti,am654-tx-pru";
- reg = <0xc000 0x1800>,
- <0x25800 0x100>,
- <0x25c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-txpru2_1-fw";
- };
-
- icssg2_mdio: mdio@32400 {
- compatible = "ti,davinci_mdio";
- reg = <0x32400 0x100>;
- clocks = <&k3_clks 64 3>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <0>;
- bus_freq = <1000000>;
- status = "disabled";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for AM6 SoC Family MCU Domain peripherals
- *
- * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_mcu {
- mcu_conf: scm-conf@40f00000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x0 0x40f00000 0x0 0x20000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x40f00000 0x20000>;
-
- phy_gmii_sel: phy@4040 {
- compatible = "ti,am654-phy-gmii-sel";
- reg = <0x4040 0x4>;
- #phy-cells = <1>;
- };
- };
-
- /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
- mcu_timerio_input: pinctrl@40f04200 {
- compatible = "pinctrl-single";
- reg = <0x0 0x40f04200 0x0 0x10>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x00000101>;
- };
-
- /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
- mcu_timerio_output: pinctrl@40f04280 {
- compatible = "pinctrl-single";
- reg = <0x0 0x40f04280 0x0 0x8>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x00000003>;
- };
-
- mcu_uart0: serial@40a00000 {
- compatible = "ti,am654-uart";
- reg = <0x00 0x40a00000 0x00 0x100>;
- interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <96000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcu_ram: sram@41c00000 {
- compatible = "mmio-sram";
- reg = <0x00 0x41c00000 0x00 0x80000>;
- ranges = <0x0 0x00 0x41c00000 0x80000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- mcu_i2c0: i2c@40b00000 {
- compatible = "ti,am654-i2c", "ti,omap4-i2c";
- reg = <0x0 0x40b00000 0x0 0x100>;
- interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 114 1>;
- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcu_spi0: spi@40300000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x0 0x40300000 0x0 0x400>;
- interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 142 1>;
- power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- mcu_spi1: spi@40310000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x0 0x40310000 0x0 0x400>;
- interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 143 1>;
- power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- mcu_spi2: spi@40320000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x0 0x40320000 0x0 0x400>;
- interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 144 1>;
- power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- tscadc0: tscadc@40200000 {
- compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
- reg = <0x0 0x40200000 0x0 0x1000>;
- interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 0 2>;
- assigned-clocks = <&k3_clks 0 2>;
- assigned-clock-rates = <60000000>;
- clock-names = "fck";
- dmas = <&mcu_udmap 0x7100>,
- <&mcu_udmap 0x7101 >;
- dma-names = "fifo0", "fifo1";
- status = "disabled";
-
- adc {
- #io-channel-cells = <1>;
- compatible = "ti,am654-adc", "ti,am3359-adc";
- };
- };
-
- tscadc1: tscadc@40210000 {
- compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
- reg = <0x0 0x40210000 0x0 0x1000>;
- interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 1 2>;
- assigned-clocks = <&k3_clks 1 2>;
- assigned-clock-rates = <60000000>;
- clock-names = "fck";
- dmas = <&mcu_udmap 0x7102>,
- <&mcu_udmap 0x7103>;
- dma-names = "fifo0", "fifo1";
- status = "disabled";
-
- adc {
- #io-channel-cells = <1>;
- compatible = "ti,am654-adc", "ti,am3359-adc";
- };
- };
-
- /*
- * The MCU domain timer interrupts are routed only to the ESM module,
- * and not currently available for Linux. The MCU domain timers are
- * of limited use without interrupts, and likely reserved by the ESM.
- */
- mcu_timer0: timer@40400000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40400000 0x00 0x400>;
- clocks = <&k3_clks 35 0>;
- clock-names = "fck";
- power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer1: timer@40410000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40410000 0x00 0x400>;
- clocks = <&k3_clks 36 0>;
- clock-names = "fck";
- power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer2: timer@40420000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40420000 0x00 0x400>;
- clocks = <&k3_clks 37 0>;
- clock-names = "fck";
- power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer3: timer@40430000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40430000 0x00 0x400>;
- clocks = <&k3_clks 38 0>;
- clock-names = "fck";
- power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_navss: bus@28380000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
- dma-coherent;
- dma-ranges;
-
- ti,sci-dev-id = <119>;
-
- mcu_ringacc: ringacc@2b800000 {
- compatible = "ti,am654-navss-ringacc";
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>,
- <0x0 0x28440000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg",
- "proxy_target", "cfg";
- ti,num-rings = <286>;
- ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <195>;
- msi-parent = <&inta_main_udmass>;
- };
-
- mcu_udmap: dma-controller@285c0000 {
- compatible = "ti,am654-navss-mcu-udmap";
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x2aa00000 0x0 0x40000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
- msi-parent = <&inta_main_udmass>;
- #dma-cells = <1>;
-
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <194>;
- ti,ringacc = <&mcu_ringacc>;
-
- ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
- <0xd>; /* TX_CHAN */
- ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
- <0xa>; /* RX_CHAN */
- ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
- };
- };
-
- secure_proxy_mcu: mailbox@2a480000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x0 0x2a480000 0x0 0x80000>,
- <0x0 0x2a380000 0x0 0x80000>,
- <0x0 0x2a400000 0x0 0x80000>;
- /*
- * Marked Disabled:
- * Node is incomplete as it is meant for bootloaders and
- * firmware on non-MPU processors
- */
- status = "disabled";
- };
-
- m_can0: can@40528000 {
- compatible = "bosch,m_can";
- reg = <0x0 0x40528000 0x0 0x400>,
- <0x0 0x40500000 0x0 0x4400>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 102 5>, <&k3_clks 102 0>;
- clock-names = "hclk", "cclk";
- interrupt-parent = <&gic500>;
- interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- m_can1: can@40568000 {
- compatible = "bosch,m_can";
- reg = <0x0 0x40568000 0x0 0x400>,
- <0x0 0x40540000 0x0 0x4400>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 103 5>, <&k3_clks 103 0>;
- clock-names = "hclk", "cclk";
- interrupt-parent = <&gic500>;
- interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- fss: bus@47000000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- ospi0: spi@47040000 {
- compatible = "ti,am654-ospi", "cdns,qspi-nor";
- reg = <0x0 0x47040000 0x0 0x100>,
- <0x5 0x00000000 0x1 0x0000000>;
- interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- clocks = <&k3_clks 248 0>;
- assigned-clocks = <&k3_clks 248 0>;
- assigned-clock-parents = <&k3_clks 248 2>;
- assigned-clock-rates = <166666666>;
- power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- ospi1: spi@47050000 {
- compatible = "ti,am654-ospi", "cdns,qspi-nor";
- reg = <0x0 0x47050000 0x0 0x100>,
- <0x7 0x00000000 0x1 0x00000000>;
- interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- clocks = <&k3_clks 249 6>;
- power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- };
-
- mcu_cpsw: ethernet@46000000 {
- compatible = "ti,am654-cpsw-nuss";
- #address-cells = <2>;
- #size-cells = <2>;
- reg = <0x0 0x46000000 0x0 0x200000>;
- reg-names = "cpsw_nuss";
- ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
- dma-coherent;
- clocks = <&k3_clks 5 10>;
- clock-names = "fck";
- power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
-
- dmas = <&mcu_udmap 0xf000>,
- <&mcu_udmap 0xf001>,
- <&mcu_udmap 0xf002>,
- <&mcu_udmap 0xf003>,
- <&mcu_udmap 0xf004>,
- <&mcu_udmap 0xf005>,
- <&mcu_udmap 0xf006>,
- <&mcu_udmap 0xf007>,
- <&mcu_udmap 0x7000>;
- dma-names = "tx0", "tx1", "tx2", "tx3",
- "tx4", "tx5", "tx6", "tx7",
- "rx";
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpsw_port1: port@1 {
- reg = <1>;
- ti,mac-only;
- label = "port1";
- ti,syscon-efuse = <&mcu_conf 0x200>;
- phys = <&phy_gmii_sel 1>;
- };
- };
-
- davinci_mdio: mdio@f00 {
- compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- reg = <0x0 0xf00 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 5 10>;
- clock-names = "fck";
- bus_freq = <1000000>;
- status = "disabled";
- };
-
- cpts@3d000 {
- compatible = "ti,am65-cpts";
- reg = <0x0 0x3d000 0x0 0x400>;
- clocks = <&mcu_cpsw_cpts_mux>;
- clock-names = "cpts";
- interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cpts";
- ti,cpts-ext-ts-inputs = <4>;
- ti,cpts-periodic-outputs = <2>;
-
- mcu_cpsw_cpts_mux: refclk-mux {
- #clock-cells = <0>;
- clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
- <&k3_clks 118 6>, <&k3_clks 118 3>,
- <&k3_clks 118 8>, <&k3_clks 118 14>,
- <&k3_clks 120 3>, <&k3_clks 121 3>;
- assigned-clocks = <&mcu_cpsw_cpts_mux>;
- assigned-clock-parents = <&k3_clks 118 5>;
- };
- };
- };
-
- mcu_r5fss0: r5fss@41000000 {
- compatible = "ti,am654-r5fss";
- ti,cluster-mode = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x41000000 0x00 0x41000000 0x20000>,
- <0x41400000 0x00 0x41400000 0x20000>;
- power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
-
- mcu_r5fss0_core0: r5f@41000000 {
- compatible = "ti,am654-r5f";
- reg = <0x41000000 0x00008000>,
- <0x41010000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <159>;
- ti,sci-proc-ids = <0x01 0xff>;
- resets = <&k3_reset 159 1>;
- firmware-name = "am65x-mcu-r5f0_0-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
-
- mcu_r5fss0_core1: r5f@41400000 {
- compatible = "ti,am654-r5f";
- reg = <0x41400000 0x00008000>,
- <0x41410000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <245>;
- ti,sci-proc-ids = <0x02 0xff>;
- resets = <&k3_reset 245 1>;
- firmware-name = "am65x-mcu-r5f0_1-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
- };
-
- mcu_rti1: watchdog@40610000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x0 0x40610000 0x0 0x100>;
- clocks = <&k3_clks 135 0>;
- power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
- assigned-clocks = <&k3_clks 135 0>;
- assigned-clock-parents = <&k3_clks 135 4>;
- };
-};
projects / J-u-boot.git / commitdiff