Merge tag 'v2023.10-rc4' into next

[J-u-boot.git] / arch / riscv / cpu / cpu.c

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index ecfb1fb08c4b15099211774314a7f890ef41289f..d64aa330f206531f57ce527b76f325752cbb3241 100644 (file)
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -66,7 +66,7 @@ static inline bool supports_extension(char ext)
 #endif /* CONFIG_CPU */
 }
 
-static int riscv_cpu_probe(void)
+static int riscv_cpu_probe(void *ctx, struct event *event)
 {
 #ifdef CONFIG_CPU
        int ret;
@@ -79,6 +79,7 @@ static int riscv_cpu_probe(void)
 
        return 0;
 }
+EVENT_SPY(EVT_DM_POST_INIT_R, riscv_cpu_probe);
 
 /*
  * This is called on secondary harts just after the IPI is init'd. Currently
@@ -91,11 +92,11 @@ static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1)
 }
 #endif
 
-int riscv_cpu_setup(void *ctx, struct event *event)
+int riscv_cpu_setup(void)
 {
        int ret;
 
-       ret = riscv_cpu_probe();
+       ret = riscv_cpu_probe(ctx, event);
        if (ret)
                return ret;
 
@@ -145,16 +146,10 @@ int riscv_cpu_setup(void *ctx, struct event *event)
 
        return 0;
 }
-EVENT_SPY(EVT_DM_POST_INIT_F, riscv_cpu_setup);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, riscv_cpu_setup);
 
 int arch_early_init_r(void)
 {
-       int ret;
-
-       ret = riscv_cpu_probe();
-       if (ret)
-               return ret;
-
        if (IS_ENABLED(CONFIG_SYSRESET_SBI))
                device_bind_driver(gd->dm_root, "sbi-sysreset",
                                   "sbi-sysreset", NULL);