spl: move SPL_OS_BOOT to Kconfig

[J-u-boot.git] / include / configs / cm_t335.h

diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index fbdead27946809cbf4b60869c1ced8a98bf53a12..7eed776f62faebf1b975f3698bfd4b0dfdc19c4c 100644 (file)
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -19,17 +19,12 @@
 #undef CONFIG_BOARD_LATE_INIT
 #undef CONFIG_SPI
 #undef CONFIG_OMAP3_SPI
-#undef CONFIG_CMD_SPI
-#undef CONFIG_SPL_OS_BOOT
 #undef CONFIG_BOOTCOUNT_LIMIT
 #undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
 
 #undef CONFIG_MAX_RAM_BANK_SIZE
 #define CONFIG_MAX_RAM_BANK_SIZE       (512 << 20)     /* 512MB */
 
-#undef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT              "CM-T335 # "
-
 #define CONFIG_OMAP_COMMON
 
 #define MACH_TYPE_CM_T335              4586    /* Until the next sync */
@@ -67,7 +62,6 @@
                "nboot ${loadaddr} nand0 900000; " \
                "bootm ${loadaddr}\0"
 
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "loadaddr=82000000\0" \
        "console=ttyO0,115200n8\0" \
@@ -107,6 +101,7 @@
 /* I2C Configuration */
 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x50    /* Main EEPROM */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_BUS      0
 
 /* SPL */
 #define CONFIG_SPL_LDSCRIPT            "$(CPUDIR)/am33xx/u-boot-spl.lds"
@@ -114,7 +109,6 @@
 /* Network. */
 #define CONFIG_PHY_GIGE
 #define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR                        0
 #define CONFIG_PHY_ATHEROS
 
 /* NAND support */
@@ -142,7 +136,6 @@
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    0x200000
 
 #define CONFIG_CMD_NAND
-#define GPMC_NAND_ECC_LP_x8_LAYOUT
 #define MTDIDS_DEFAULT                 "nand0=nand"
 #define MTDPARTS_DEFAULT               "mtdparts=nand:2m(spl)," \
                                        "1m(u-boot),1m(u-boot-env)," \
@@ -152,6 +145,11 @@
 #define CONFIG_ENV_OFFSET              0x300000 /* environment starts here */
 #define CONFIG_SYS_ENV_SECT_SIZE       (128 << 10)     /* 128 KiB */
 #define CONFIG_SYS_NAND_ONFI_DETECTION
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS                0x400000 /* un-assigned: (using dtb) */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS        0x500000
+#define CONFIG_CMD_SPL_WRITE_SIZE      0x2000
+#endif
 
 /* GPIO pin + bank to pin ID mapping */
 #define GPIO_PIN(_bank, _pin)          ((_bank << 5) + _pin)
@@ -166,5 +164,28 @@
 #define STATUS_LED_PERIOD              (CONFIG_SYS_HZ / 2)
 #define STATUS_LED_BOOT                        0
 
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN         1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  5
+#define CONFIG_SYS_EEPROM_SIZE                 256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * Enable PCA9555 at I2C0-0x26.
+ * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command.
+ */
+#define CONFIG_PCA953X
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_SYS_I2C_PCA953X_ADDR    0x26
+#define CONFIG_SYS_I2C_PCA953X_WIDTH   { {0x26, 16} }
+#endif /* CONFIG_SPL_BUILD */
+
 #endif /* __CONFIG_CM_T335_H */