board: puma: Use rockchip_* helpers to setup cpuid and macaddr

[J-u-boot.git] / include / spartan2.h

diff --git a/include/spartan2.h b/include/spartan2.h
index e257a6760db9d222b69926512124787e46a923e6..618eddd8384a47a3161970d5ef152669bd0da961 100644 (file)
--- a/include/spartan2.h
+++ b/include/spartan2.h
@@ -1,25 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2002
  * Rich Ireland, Enterasys Networks, [email protected].
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
  */
 
 #ifndef _SPARTAN2_H_
@@ -27,37 +9,40 @@
 
 #include <xilinx.h>
 
-extern int Spartan2_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int Spartan2_info(Xilinx_desc *desc);
-
 /* Slave Parallel Implementation function table */
 typedef struct {
-       Xilinx_pre_fn   pre;
-       Xilinx_pgm_fn   pgm;
-       Xilinx_init_fn  init;
-       Xilinx_err_fn   err;
-       Xilinx_done_fn  done;
-       Xilinx_clk_fn   clk;
-       Xilinx_cs_fn    cs;
-       Xilinx_wr_fn    wr;
-       Xilinx_rdata_fn rdata;
-       Xilinx_wdata_fn wdata;
-       Xilinx_busy_fn  busy;
-       Xilinx_abort_fn abort;
-       Xilinx_post_fn  post;
-} Xilinx_Spartan2_Slave_Parallel_fns;
+       xilinx_pre_fn   pre;
+       xilinx_pgm_fn   pgm;
+       xilinx_init_fn  init;
+       xilinx_err_fn   err;
+       xilinx_done_fn  done;
+       xilinx_clk_fn   clk;
+       xilinx_cs_fn    cs;
+       xilinx_wr_fn    wr;
+       xilinx_rdata_fn rdata;
+       xilinx_wdata_fn wdata;
+       xilinx_busy_fn  busy;
+       xilinx_abort_fn abort;
+       xilinx_post_fn  post;
+} xilinx_spartan2_slave_parallel_fns;
 
 /* Slave Serial Implementation function table */
 typedef struct {
-       Xilinx_pre_fn   pre;
-       Xilinx_pgm_fn   pgm;
-       Xilinx_clk_fn   clk;
-       Xilinx_init_fn  init;
-       Xilinx_done_fn  done;
-       Xilinx_wr_fn    wr;
-       Xilinx_post_fn  post;
-} Xilinx_Spartan2_Slave_Serial_fns;
+       xilinx_pre_fn   pre;
+       xilinx_pgm_fn   pgm;
+       xilinx_clk_fn   clk;
+       xilinx_init_fn  init;
+       xilinx_done_fn  done;
+       xilinx_wr_fn    wr;
+       xilinx_post_fn  post;
+} xilinx_spartan2_slave_serial_fns;
+
+#if defined(CONFIG_FPGA_SPARTAN2)
+extern struct xilinx_fpga_op spartan2_op;
+# define FPGA_SPARTAN2_OPS     &spartan2_op
+#else
+# define FPGA_SPARTAN2_OPS     NULL
+#endif
 
 /* Device Image Sizes
  *********************************************************************/
@@ -80,36 +65,47 @@ typedef struct {
  *********************************************************************/
 /* Spartan-II devices */
 #define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, \
+       FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, \
+       FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, \
+       FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, \
+       FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, \
+       FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, \
+       FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, \
+       FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, \
+       FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, \
+       FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, \
+       FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie }
+{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, \
+       FPGA_SPARTAN2_OPS }
 
 #endif /* _SPARTAN2_H_ */