#define CONFIG_SYS_BOOTM_LEN SZ_64M
-#define CONFIG_SPL_MAX_SIZE (152 * SZ_1K)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_STACK 0x960000
#define CONFIG_SPL_BSS_START_ADDR 0x98FC00
-#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000
/* UART */
-#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
-
-/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE SZ_2K
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
#endif /* __PHYCORE_IMX8MP_H */