Convert CONFIG_SYS_FLASH_EMPTY_INFO to Kconfig

[J-u-boot.git] / include / configs / corenet_ds.h

diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 6d272c6d880392e0e415c91a1f6a5db00701675b..7d666e553b0bee526eb38a811c30b9521fbe95b8 100644 (file)
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -15,17 +15,8 @@
 #include "../board/freescale/common/ics307_clk.h"
 
 #ifdef CONFIG_RAMBOOT_PBL
-#ifdef CONFIG_NXP_ESBC
 #define CONFIG_RAMBOOT_TEXT_BASE       CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS    0xfffffffc
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_RAMBOOT_NAND
-#endif
-#define CONFIG_BOOTSCRIPT_COPY_RAM
-#else
-#define CONFIG_RAMBOOT_TEXT_BASE       CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS    0xfffffffc
-#endif
 #endif
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
@@ -37,35 +28,21 @@
 #endif
 
 /* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV           /* Category E.HV supported */
 
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
 #endif
 
-#define CONFIG_SYS_FSL_CPC             /* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC             CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1                   /* PCIE controller 1 */
-#define CONFIG_PCIE2                   /* PCIE controller 2 */
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#endif
 
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
 #define CONFIG_SYS_INIT_L2CSR0         L2CSR0_L2E
-#define CONFIG_BTB                     /* toggle branch predition */
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #endif
 
-#define CONFIG_ENABLE_36BIT_PHYS
-
 #define CONFIG_POST CONFIG_SYS_POST_MEMORY     /* test POST memory test */
 
 /*
@@ -96,10 +73,6 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define CONFIG_SYS_SPD_BUS_NUM 1
 #define SPD_EEPROM_ADDRESS1    0x51
 #define SPD_EEPROM_ADDRESS2    0x52
 #define SPD_EEPROM_ADDRESS     SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
@@ -144,12 +117,6 @@
 #define CONFIG_SYS_FLASH_ERASE_TOUT    60000           /* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT    500             /* Flash Write Timeout (ms) */
 
-#define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE    /* start of monitor */
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
 /* Nand Flash */
 #ifdef CONFIG_NAND_FSL_ELBC
 #define CONFIG_SYS_NAND_BASE           0xffa00000
@@ -178,7 +145,6 @@
                               | OR_FCM_EHTR)
 #endif /* CONFIG_NAND_FSL_ELBC */
 
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 
 #define CONFIG_HWCONFIG
@@ -201,8 +167,7 @@
 #endif
 #define CONFIG_SYS_INIT_RAM_SIZE               0x00004000      /* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_SP_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 #define CONFIG_SYS_MONITOR_LEN         (768 * 1024)
 
@@ -341,23 +306,6 @@
 #define CONFIG_SYS_DPAA_PME
 #define CONFIG_SYS_FDT_PAD             (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-/* SATA */
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE     2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1               CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS         FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2               CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS         FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif
-
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
@@ -372,7 +320,6 @@
 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
 
 #define CONFIG_SYS_TBIPA_VALUE 8
-#define CONFIG_ETHPRIME                "FM1@DTSEC1"
 #endif
 
 /*
@@ -381,16 +328,6 @@
 #define CONFIG_LOADS_ECHO              /* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE   /* allow baudrate change */
 
-/*
-* USB
-*/
-#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_HAS_FSL_MPH_USB
-
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-
 #ifdef CONFIG_MMC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
@@ -406,13 +343,11 @@
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ   (64 << 20)      /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 
 /*
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH                "/opt/nfsroot"
-#define CONFIG_BOOTFILE                "uImage"
 #define CONFIG_UBOOTPATH       u-boot.bin      /* U-Boot image on TFTP server */
 
 #ifdef CONFIG_TARGET_P4080DS