Merge branch 'master' of git://www.denx.de/git/u-boot-sh

[J-u-boot.git] / include / asm-ppc / immap_86xx.h

diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index 685fcafdf2f30ba3fa91309d00c8c1e4ac6d87d6..7526061d5ab7c11240561785701b489523198142 100644 (file)
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -10,6 +10,8 @@
 #ifndef __IMMAP_86xx__
 #define __IMMAP_86xx__
 
+#include <asm/types.h>
+#include <asm/fsl_i2c.h>
 
 /* Local-Access Registers and MCM Registers(0x0000-0x2000) */
 typedef struct ccsr_local_mcm {
@@ -155,52 +157,9 @@ typedef struct ccsr_ddr {
 
 
 /* Daul I2C Registers(0x3000-0x4000) */
-
 typedef struct ccsr_i2c {
-       u_char  i2cadr1;        /* 0x3000 - I2C 1 Address Register */
-#define MPC86xx_I2CADR_MASK    0xFE
-       char    res1[3];
-       u_char  i2cfdr1;        /* 0x3004 - I2C 1 Frequency Divider Register */
-#define MPC86xx_I2CFDR_MASK    0x3F
-       char    res2[3];
-       u_char  i2ccr1;         /* 0x3008 - I2C 1 Control Register */
-#define MPC86xx_I2CCR_MEN      0x80
-#define MPC86xx_I2CCR_MIEN     0x40
-#define MPC86xx_I2CCR_MSTA      0x20
-#define MPC86xx_I2CCR_MTX       0x10
-#define MPC86xx_I2CCR_TXAK      0x08
-#define MPC86xx_I2CCR_RSTA      0x04
-#define MPC86xx_I2CCR_BCST      0x01
-       char    res3[3];
-       u_char  i2csr1;         /* 0x300c - I2C 1 Status Register */
-#define MPC86xx_I2CSR_MCF      0x80
-#define MPC86xx_I2CSR_MAAS      0x40
-#define MPC86xx_I2CSR_MBB       0x20
-#define MPC86xx_I2CSR_MAL       0x10
-#define MPC86xx_I2CSR_BCSTM     0x08
-#define MPC86xx_I2CSR_SRW       0x04
-#define MPC86xx_I2CSR_MIF       0x02
-#define MPC86xx_I2CSR_RXAK      0x01
-       char    res4[3];
-       u_char  i2cdr1;         /* 0x3010 - I2C 1 Data Register */
-#define MPC86xx_I2CDR_DATA     0xFF
-       char    res5[3];
-       u_char  i2cdfsrr1;      /* 0x3014 - I2C 1 Digital Filtering Sampling Rate Register */
-#define MPC86xx_I2CDFSRR       0x3F
-       char    res6[235];
-
-       u_char  i2cadr2;        /* 0x3100 - I2C 2 Address Register */
-       char    res7[3];
-       u_char  i2cfdr2;        /* 0x3104 - I2C 2 Frequency Divider Register */
-       char    res8[3];
-       u_char  i2ccr2;         /* 0x3108 - I2C 2 Control Register */
-       char    res9[3];
-       u_char  i2csr2;         /* 0x310c - I2C 2 Status Register */
-       char    res10[3];
-       u_char  i2cdr2;         /* 0x3110 - I2C 2 Data Register */
-       char    res11[3];
-       u_char  i2cdfsrr2;      /* 0x3114 - I2C 2 Digital Filtering Sampling Rate Register */
-       char    res12[3819];
+       struct fsl_i2c  i2c[2];
+       u8      res[4096 - 2 * sizeof(struct fsl_i2c)];
 } ccsr_i2c_t;
 
 /* DUART Registers(0x4000-0x5000) */
@@ -762,6 +721,8 @@ typedef struct ccsr_pic {
        uint    frr;            /* 0x41000 - Feature Reporting Register */
        char    res10[28];
        uint    gcr;            /* 0x41020 - Global Configuration Register */
+#define MPC86xx_PICGCR_RST     0x80000000
+#define MPC86xx_PICGCR_MODE    0x20000000
        char    res11[92];
        uint    vir;            /* 0x41080 - Vendor Identification Register */
        char    res12[12];
@@ -1295,10 +1256,17 @@ typedef struct ccsr_rio {
 typedef struct ccsr_gur {
        uint    porpllsr;       /* 0xe0000 - POR PLL ratio status register */
        uint    porbmsr;        /* 0xe0004 - POR boot mode status register */
-#define MPC86xx_PORBMSR_HA      0x00060000
+#define MPC8610_PORBMSR_HA      0x00070000
+#define MPC8610_PORBMSR_HA_SHIFT       16
+#define MPC8641_PORBMSR_HA      0x00060000
+#define MPC8641_PORBMSR_HA_SHIFT       17
        uint    porimpscr;      /* 0xe0008 - POR I/O impedance status and control register */
        uint    pordevsr;       /* 0xe000c - POR I/O device status regsiter */
-#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
+#define MPC8610_PORDEVSR_IO_SEL                0x00380000
+#define MPC8610_PORDEVSR_IO_SEL_SHIFT          19
+#define MPC8641_PORDEVSR_IO_SEL                0x000F0000
+#define MPC8641_PORDEVSR_IO_SEL_SHIFT          16
+#define MPC86xx_PORDEVSR_CORE1TE       0x00000080 /* ASMP (Core1 addr trans) */
        uint    pordbgmsr;      /* 0xe0010 - POR debug mode status register */
        char    res1[12];
        uint    gpporcr;        /* 0xe0020 - General-purpose POR configuration register */
@@ -1312,8 +1280,11 @@ typedef struct ccsr_gur {
        uint    pmuxcr;         /* 0xe0060 - Alternate function signal multiplex control */
        char    res6[12];
        uint    devdisr;        /* 0xe0070 - Device disable control */
-#define MPC86xx_DEVDISR_PCIEX1  0x80000000
-#define MPC86xx_DEVDISR_PCIEX2  0x40000000
+#define MPC86xx_DEVDISR_PCIEX1 0x80000000
+#define MPC86xx_DEVDISR_PCIEX2 0x40000000
+#define MPC86xx_DEVDISR_PCI1   0x80000000
+#define MPC86xx_DEVDISR_PCIE1  0x40000000
+#define MPC86xx_DEVDISR_PCIE2  0x20000000
        char    res7[12];
        uint    powmgtcsr;      /* 0xe0080 - Power management status and control register */
        char    res8[12];
@@ -1321,7 +1292,9 @@ typedef struct ccsr_gur {
        char    res9[12];
        uint    pvr;            /* 0xe00a0 - Processor version register */
        uint    svr;            /* 0xe00a4 - System version register */
-       char    res10[3416];
+       char    res10a[1880];
+       uint    clkdvdr;        /* 0xe0800 - Clock Divide register */
+       char    res10b[1532];
        uint    clkocr;         /* 0xe0e00 - Clock out select register */
        char    res11[12];
        uint    ddrdllcr;       /* 0xe0e10 - DDR DLL control register */
@@ -1361,4 +1334,9 @@ typedef struct immap {
 
 extern immap_t  *immr;
 
+#define CFG_MPC86xx_DDR_OFFSET (0x2000)
+#define CFG_MPC86xx_DDR_ADDR   (CFG_IMMR + CFG_MPC86xx_DDR_OFFSET)
+#define CFG_MPC86xx_DDR2_OFFSET        (0x6000)
+#define CFG_MPC86xx_DDR2_ADDR  (CFG_IMMR + CFG_MPC86xx_DDR2_OFFSET)
+
 #endif /*__IMMAP_86xx__*/