+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2000-2002
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
*/
+#ifndef CONFIG_CLK_MPC83XX
+
#include <common.h>
+#include <clock_legacy.h>
#include <mpc83xx.h>
#include <command.h>
+#include <vsprintf.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
mult_t vco_divider;
} corecnf_t;
-corecnf_t corecnf_tab[] = {
+static corecnf_t corecnf_tab[] = {
{_byp, _byp}, /* 0x00 */
{_byp, _byp}, /* 0x01 */
{_byp, _byp}, /* 0x02 */
u32 lcrr;
u32 csb_clk;
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
+#elif defined(CONFIG_ARCH_MPC8309)
+ u32 usbdr_clk;
#endif
-#ifdef CONFIG_MPC834x
+#ifdef CONFIG_ARCH_MPC834X
u32 usbmph_clk;
#endif
u32 core_clk;
u32 i2c1_clk;
-#if !defined(CONFIG_MPC832x)
+#if !defined(CONFIG_ARCH_MPC832X)
u32 i2c2_clk;
#endif
-#if defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC8315)
u32 tdm_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
#endif
+#if !defined(CONFIG_ARCH_MPC8309)
u32 enc_clk;
+#endif
u32 lbiu_clk;
u32 lclk_clk;
u32 mem_clk;
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
u32 mem_sec_clk;
#endif
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_QE)
u32 qepmf;
u32 qepdf;
u32 qe_clk;
u32 brg_clk;
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
u32 pciexp1_clk;
u32 pciexp2_clk;
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
u32 sata_clk;
#endif
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
if (im->reset.rcwh & HRCWH_PCI_HOST) {
-#if defined(CONFIG_83XX_CLKIN)
- pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
+#if defined(CONFIG_SYS_CLK_FREQ)
+ pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
#else
pci_sync_in = 0xDEADBEEF;
#endif
#endif
}
- spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT);
+ spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
sccr = im->clk.sccr;
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
case 0:
tsec1_clk = 0;
tsec1_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_TSEC1CM value */
+ /* unknown SCCR_TSEC1CM value */
return -2;
}
+#endif
+#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
case 0:
usbdr_clk = 0;
usbdr_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_USBDRCM value */
+ /* unknown SCCR_USBDRCM value */
return -3;
}
#endif
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
case 0:
tsec2_clk = 0;
tsec2_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_TSEC2CM value */
+ /* unknown SCCR_TSEC2CM value */
return -4;
}
-#elif defined(CONFIG_MPC8313)
+#elif defined(CONFIG_ARCH_MPC8313)
tsec2_clk = tsec1_clk;
if (!(sccr & SCCR_TSEC1ON))
tsec2_clk = 0;
#endif
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
case 0:
usbmph_clk = 0;
usbmph_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_USBMPHCM value */
+ /* unknown SCCR_USBMPHCM value */
return -5;
}
return -6;
}
#endif
+#if !defined(CONFIG_ARCH_MPC8309)
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
case 0:
enc_clk = 0;
enc_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_ENCCM value */
+ /* unknown SCCR_ENCCM value */
return -7;
}
+#endif
#if defined(CONFIG_FSL_ESDHC)
switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
sdhc_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_SDHCCM value */
+ /* unknown SCCR_SDHCCM value */
return -8;
}
#endif
-#if defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC8315)
switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
case 0:
tdm_clk = 0;
tdm_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_TDMCM value */
+ /* unknown SCCR_TDMCM value */
return -8;
}
#endif
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
i2c1_clk = tsec2_clk;
-#elif defined(CONFIG_MPC8360)
+#elif defined(CONFIG_ARCH_MPC8360)
i2c1_clk = csb_clk;
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_ARCH_MPC832X)
i2c1_clk = enc_clk;
-#elif defined(CONFIG_MPC831x)
+#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
i2c1_clk = enc_clk;
#elif defined(CONFIG_FSL_ESDHC)
i2c1_clk = sdhc_clk;
+#elif defined(CONFIG_ARCH_MPC837X)
+ i2c1_clk = enc_clk;
+#elif defined(CONFIG_ARCH_MPC8309)
+ i2c1_clk = csb_clk;
#endif
-#if !defined(CONFIG_MPC832x)
+#if !defined(CONFIG_ARCH_MPC832X)
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
case 0:
pciexp1_clk = 0;
pciexp1_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_PCIEXP1CM value */
+ /* unknown SCCR_PCIEXP1CM value */
return -9;
}
pciexp2_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_PCIEXP2CM value */
+ /* unknown SCCR_PCIEXP2CM value */
return -10;
}
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
case 0:
sata_clk = 0;
sata_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_SATACM value */
+ /* unknown SCCR_SATA1CM value */
return -11;
}
#endif
lbiu_clk = csb_clk *
- (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
- lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
+ (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
+ lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
switch (lcrr) {
case 2:
case 4:
}
mem_clk = csb_clk *
- (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
- corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
-#if defined(CONFIG_MPC8360)
+ (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
+ corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
+
+#if defined(CONFIG_ARCH_MPC8360)
mem_sec_clk = csb_clk * (1 +
- ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
+ ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
#endif
corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
- if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
- /* corecnf_tab_index is too high, possibly worng value */
+ if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
+ /* corecnf_tab_index is too high, possibly wrong value */
return -11;
}
switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
core_clk = 3 * csb_clk;
break;
default:
- /* unkown core to csb ratio */
+ /* unknown core to csb ratio */
return -13;
}
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
- qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
- qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
+#if defined(CONFIG_QE)
+ qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
+ qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
brg_clk = qe_clk / 2;
#endif
- gd->csb_clk = csb_clk;
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
- gd->tsec1_clk = tsec1_clk;
- gd->tsec2_clk = tsec2_clk;
- gd->usbdr_clk = usbdr_clk;
+ gd->arch.csb_clk = csb_clk;
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+ gd->arch.tsec1_clk = tsec1_clk;
+ gd->arch.tsec2_clk = tsec2_clk;
+ gd->arch.usbdr_clk = usbdr_clk;
+#elif defined(CONFIG_ARCH_MPC8309)
+ gd->arch.usbdr_clk = usbdr_clk;
#endif
-#if defined(CONFIG_MPC834x)
- gd->usbmph_clk = usbmph_clk;
+#if defined(CONFIG_ARCH_MPC834X)
+ gd->arch.usbmph_clk = usbmph_clk;
#endif
-#if defined(CONFIG_MPC8315)
- gd->tdm_clk = tdm_clk;
+#if defined(CONFIG_ARCH_MPC8315)
+ gd->arch.tdm_clk = tdm_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
- gd->sdhc_clk = sdhc_clk;
+ gd->arch.sdhc_clk = sdhc_clk;
+#endif
+ gd->arch.core_clk = core_clk;
+ gd->arch.i2c1_clk = i2c1_clk;
+#if !defined(CONFIG_ARCH_MPC832X)
+ gd->arch.i2c2_clk = i2c2_clk;
#endif
- gd->core_clk = core_clk;
- gd->i2c1_clk = i2c1_clk;
-#if !defined(CONFIG_MPC832x)
- gd->i2c2_clk = i2c2_clk;
+#if !defined(CONFIG_ARCH_MPC8309)
+ gd->arch.enc_clk = enc_clk;
#endif
- gd->enc_clk = enc_clk;
- gd->lbiu_clk = lbiu_clk;
- gd->lclk_clk = lclk_clk;
+ gd->arch.lbiu_clk = lbiu_clk;
+ gd->arch.lclk_clk = lclk_clk;
gd->mem_clk = mem_clk;
-#if defined(CONFIG_MPC8360)
- gd->mem_sec_clk = mem_sec_clk;
+#if defined(CONFIG_ARCH_MPC8360)
+ gd->arch.mem_sec_clk = mem_sec_clk;
#endif
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
- gd->qe_clk = qe_clk;
- gd->brg_clk = brg_clk;
+#if defined(CONFIG_QE)
+ gd->arch.qe_clk = qe_clk;
+ gd->arch.brg_clk = brg_clk;
#endif
-#if defined(CONFIG_MPC837x)
- gd->pciexp1_clk = pciexp1_clk;
- gd->pciexp2_clk = pciexp2_clk;
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
+ gd->arch.pciexp1_clk = pciexp1_clk;
+ gd->arch.pciexp2_clk = pciexp2_clk;
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
- gd->sata_clk = sata_clk;
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
+ gd->arch.sata_clk = sata_clk;
#endif
gd->pci_clk = pci_sync_in;
- gd->cpu_clk = gd->core_clk;
- gd->bus_clk = gd->csb_clk;
+ gd->cpu_clk = gd->arch.core_clk;
+ gd->bus_clk = gd->arch.csb_clk;
return 0;
}
*********************************************/
ulong get_bus_freq(ulong dummy)
{
- return gd->csb_clk;
+ return gd->arch.csb_clk;
+}
+
+/********************************************
+ * get_ddr_freq
+ * return ddr bus freq in Hz
+ *********************************************/
+ulong get_ddr_freq(ulong dummy)
+{
+ return gd->mem_clk;
+}
+
+int get_serial_clock(void)
+{
+ return get_bus_freq(0);
}
-int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
{
char buf[32];
printf("Clock configuration:\n");
- printf(" Core: %-4s MHz\n", strmhz(buf, gd->core_clk));
- printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
- printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk));
- printf(" BRG: %-4s MHz\n", strmhz(buf, gd->brg_clk));
-#endif
- printf(" Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk));
- printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->lclk_clk));
+ printf(" Core: %-4s MHz\n",
+ strmhz(buf, gd->arch.core_clk));
+ printf(" Coherent System Bus: %-4s MHz\n",
+ strmhz(buf, gd->arch.csb_clk));
+#if defined(CONFIG_QE)
+ printf(" QE: %-4s MHz\n",
+ strmhz(buf, gd->arch.qe_clk));
+ printf(" BRG: %-4s MHz\n",
+ strmhz(buf, gd->arch.brg_clk));
+#endif
+ printf(" Local Bus Controller:%-4s MHz\n",
+ strmhz(buf, gd->arch.lbiu_clk));
+ printf(" Local Bus: %-4s MHz\n",
+ strmhz(buf, gd->arch.lclk_clk));
printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
-#if defined(CONFIG_MPC8360)
- printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
+#if defined(CONFIG_ARCH_MPC8360)
+ printf(" DDR Secondary: %-4s MHz\n",
+ strmhz(buf, gd->arch.mem_sec_clk));
#endif
- printf(" SEC: %-4s MHz\n", strmhz(buf, gd->enc_clk));
- printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
-#if !defined(CONFIG_MPC832x)
- printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
+#if !defined(CONFIG_ARCH_MPC8309)
+ printf(" SEC: %-4s MHz\n",
+ strmhz(buf, gd->arch.enc_clk));
#endif
-#if defined(CONFIG_MPC8315)
- printf(" TDM: %-4s MHz\n", strmhz(buf, gd->tdm_clk));
+ printf(" I2C1: %-4s MHz\n",
+ strmhz(buf, gd->arch.i2c1_clk));
+#if !defined(CONFIG_ARCH_MPC832X)
+ printf(" I2C2: %-4s MHz\n",
+ strmhz(buf, gd->arch.i2c2_clk));
#endif
-#if defined(CONFIG_FSL_ESDHC)
- printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
-#endif
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
- printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
- printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
- printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
-#endif
-#if defined(CONFIG_MPC834x)
- printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
-#endif
-#if defined(CONFIG_MPC837x)
- printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->pciexp1_clk));
- printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->pciexp2_clk));
+#if defined(CONFIG_ARCH_MPC8315)
+ printf(" TDM: %-4s MHz\n",
+ strmhz(buf, gd->arch.tdm_clk));
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
- printf(" SATA: %-4s MHz\n", strmhz(buf, gd->sata_clk));
+#if defined(CONFIG_FSL_ESDHC)
+ printf(" SDHC: %-4s MHz\n",
+ strmhz(buf, gd->arch.sdhc_clk));
+#endif
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+ printf(" TSEC1: %-4s MHz\n",
+ strmhz(buf, gd->arch.tsec1_clk));
+ printf(" TSEC2: %-4s MHz\n",
+ strmhz(buf, gd->arch.tsec2_clk));
+ printf(" USB DR: %-4s MHz\n",
+ strmhz(buf, gd->arch.usbdr_clk));
+#elif defined(CONFIG_ARCH_MPC8309)
+ printf(" USB DR: %-4s MHz\n",
+ strmhz(buf, gd->arch.usbdr_clk));
+#endif
+#if defined(CONFIG_ARCH_MPC834X)
+ printf(" USB MPH: %-4s MHz\n",
+ strmhz(buf, gd->arch.usbmph_clk));
+#endif
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
+ printf(" PCIEXP1: %-4s MHz\n",
+ strmhz(buf, gd->arch.pciexp1_clk));
+ printf(" PCIEXP2: %-4s MHz\n",
+ strmhz(buf, gd->arch.pciexp2_clk));
+#endif
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
+ printf(" SATA: %-4s MHz\n",
+ strmhz(buf, gd->arch.sata_clk));
#endif
return 0;
}
"print clock configuration",
" clocks"
);
+
+#endif
projects / J-u-boot.git / blobdiff