+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2012 SAMSUNG Electronics
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <bouncebuf.h>
#include <common.h>
+#include <cpu_func.h>
#include <errno.h>
#include <malloc.h>
#include <memalign.h>
#include <mmc.h>
#include <dwmmc.h>
-#include <asm-generic/errno.h>
+#include <wait_bit.h>
+#include <asm/cache.h>
+#include <power/regulator.h>
#define PAGE_SIZE 4096
desc->flags = desc0;
desc->cnt = desc1;
desc->addr = desc2;
- desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac);
+ desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
}
static void dwmci_prepare_data(struct dwmci_host *host,
dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
+ /* Clear IDMAC interrupt */
+ dwmci_writel(host, DWMCI_IDSTS, 0xFFFFFFFF);
+
data_start = (ulong)cur_idmac;
- dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);
+ dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
do {
flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
cnt = data->blocksize * 8;
dwmci_set_idma_desc(cur_idmac, flags, cnt,
- (u32)bounce_buffer + (i * PAGE_SIZE));
+ (ulong)bounce_buffer + (i * PAGE_SIZE));
+ cur_idmac++;
if (blk_cnt <= 8)
break;
blk_cnt -= 8;
- cur_idmac++;
i++;
} while(1);
data_end = (ulong)cur_idmac;
- flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
+ flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN));
ctrl = dwmci_readl(host, DWMCI_CTRL);
ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
}
+static int dwmci_fifo_ready(struct dwmci_host *host, u32 bit, u32 *len)
+{
+ u32 timeout = 20000;
+
+ *len = dwmci_readl(host, DWMCI_STATUS);
+ while (--timeout && (*len & bit)) {
+ udelay(200);
+ *len = dwmci_readl(host, DWMCI_STATUS);
+ }
+
+ if (!timeout) {
+ debug("%s: FIFO underflow timeout\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size)
+{
+ unsigned int timeout;
+
+ timeout = size * 8; /* counting in bits */
+ timeout *= 10; /* wait 10 times as long */
+ timeout /= mmc->clock;
+ timeout /= mmc->bus_width;
+ timeout /= mmc->ddr_mode ? 2 : 1;
+ timeout *= 1000; /* counting in msec */
+ timeout = (timeout < 1000) ? 1000 : timeout;
+
+ return timeout;
+}
+
+static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
+{
+ struct mmc *mmc = host->mmc;
+ int ret = 0;
+ u32 timeout, mask, size, i, len = 0;
+ u32 *buf = NULL;
+ ulong start = get_timer(0);
+ u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
+ RX_WMARK_SHIFT) + 1) * 2;
+
+ size = data->blocksize * data->blocks;
+ if (data->flags == MMC_DATA_READ)
+ buf = (unsigned int *)data->dest;
+ else
+ buf = (unsigned int *)data->src;
+
+ timeout = dwmci_get_timeout(mmc, size);
+
+ size /= 4;
+
+ for (;;) {
+ mask = dwmci_readl(host, DWMCI_RINTSTS);
+ /* Error during data transfer. */
+ if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
+ debug("%s: DATA ERROR!\n", __func__);
+ ret = -EINVAL;
+ break;
+ }
+
+ if (host->fifo_mode && size) {
+ len = 0;
+ if (data->flags == MMC_DATA_READ &&
+ (mask & DWMCI_INTMSK_RXDR)) {
+ while (size) {
+ ret = dwmci_fifo_ready(host,
+ DWMCI_FIFO_EMPTY,
+ &len);
+ if (ret < 0)
+ break;
+
+ len = (len >> DWMCI_FIFO_SHIFT) &
+ DWMCI_FIFO_MASK;
+ len = min(size, len);
+ for (i = 0; i < len; i++)
+ *buf++ =
+ dwmci_readl(host, DWMCI_DATA);
+ size = size > len ? (size - len) : 0;
+ }
+ dwmci_writel(host, DWMCI_RINTSTS,
+ DWMCI_INTMSK_RXDR);
+ } else if (data->flags == MMC_DATA_WRITE &&
+ (mask & DWMCI_INTMSK_TXDR)) {
+ while (size) {
+ ret = dwmci_fifo_ready(host,
+ DWMCI_FIFO_FULL,
+ &len);
+ if (ret < 0)
+ break;
+
+ len = fifo_depth - ((len >>
+ DWMCI_FIFO_SHIFT) &
+ DWMCI_FIFO_MASK);
+ len = min(size, len);
+ for (i = 0; i < len; i++)
+ dwmci_writel(host, DWMCI_DATA,
+ *buf++);
+ size = size > len ? (size - len) : 0;
+ }
+ dwmci_writel(host, DWMCI_RINTSTS,
+ DWMCI_INTMSK_TXDR);
+ }
+ }
+
+ /* Data arrived correctly. */
+ if (mask & DWMCI_INTMSK_DTO) {
+ ret = 0;
+ break;
+ }
+
+ /* Check for timeout. */
+ if (get_timer(start) > timeout) {
+ debug("%s: Timeout waiting for data!\n",
+ __func__);
+ ret = -ETIMEDOUT;
+ break;
+ }
+ }
+
+ dwmci_writel(host, DWMCI_RINTSTS, mask);
+
+ return ret;
+}
+
static int dwmci_set_transfer_mode(struct dwmci_host *host,
struct mmc_data *data)
{
return mode;
}
+#ifdef CONFIG_DM_MMC
+static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
+#endif
struct dwmci_host *host = mmc->priv;
ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
data ? DIV_ROUND_UP(data->blocks, 8) : 0);
int ret = 0, flags = 0, i;
- unsigned int timeout = 100000;
- u32 retry = 10000;
+ unsigned int timeout = 500;
+ u32 retry = 100000;
u32 mask, ctrl;
ulong start = get_timer(0);
struct bounce_buffer bbstate;
while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
if (get_timer(start) > timeout) {
debug("%s: Timeout on data busy\n", __func__);
- return TIMEOUT;
+ return -ETIMEDOUT;
}
}
dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
if (data) {
- if (data->flags == MMC_DATA_READ) {
- bounce_buffer_start(&bbstate, (void*)data->dest,
- data->blocksize *
- data->blocks, GEN_BB_WRITE);
+ if (host->fifo_mode) {
+ dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
+ dwmci_writel(host, DWMCI_BYTCNT,
+ data->blocksize * data->blocks);
+ dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
} else {
- bounce_buffer_start(&bbstate, (void*)data->src,
- data->blocksize *
- data->blocks, GEN_BB_READ);
+ if (data->flags == MMC_DATA_READ) {
+ ret = bounce_buffer_start(&bbstate,
+ (void*)data->dest,
+ data->blocksize *
+ data->blocks, GEN_BB_WRITE);
+ } else {
+ ret = bounce_buffer_start(&bbstate,
+ (void*)data->src,
+ data->blocksize *
+ data->blocks, GEN_BB_READ);
+ }
+
+ if (ret)
+ return ret;
+
+ dwmci_prepare_data(host, data, cur_idmac,
+ bbstate.bounce_buffer);
}
- dwmci_prepare_data(host, data, cur_idmac,
- bbstate.bounce_buffer);
}
dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
if (i == retry) {
debug("%s: Timeout.\n", __func__);
- return TIMEOUT;
+ return -ETIMEDOUT;
}
if (mask & DWMCI_INTMSK_RTO) {
* CMD8, please keep that in mind.
*/
debug("%s: Response Timeout.\n", __func__);
- return TIMEOUT;
+ return -ETIMEDOUT;
} else if (mask & DWMCI_INTMSK_RE) {
debug("%s: Response Error.\n", __func__);
return -EIO;
+ } else if ((cmd->resp_type & MMC_RSP_CRC) &&
+ (mask & DWMCI_INTMSK_RCRC)) {
+ debug("%s: Response CRC Error.\n", __func__);
+ return -EIO;
}
}
if (data) {
- start = get_timer(0);
- timeout = 1000;
- for (;;) {
- mask = dwmci_readl(host, DWMCI_RINTSTS);
- /* Error during data transfer. */
- if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
- debug("%s: DATA ERROR!\n", __func__);
- ret = -EINVAL;
- break;
- }
-
- /* Data arrived correctly. */
- if (mask & DWMCI_INTMSK_DTO) {
- ret = 0;
- break;
- }
-
- /* Check for timeout. */
- if (get_timer(start) > timeout) {
- debug("%s: Timeout waiting for data!\n",
- __func__);
- ret = TIMEOUT;
- break;
- }
+ ret = dwmci_data_transfer(host, data);
+
+ /* only dma mode need it */
+ if (!host->fifo_mode) {
+ if (data->flags == MMC_DATA_READ)
+ mask = DWMCI_IDINTEN_RI;
+ else
+ mask = DWMCI_IDINTEN_TI;
+ ret = wait_for_bit_le32(host->ioaddr + DWMCI_IDSTS,
+ mask, true, 1000, false);
+ if (ret)
+ debug("%s: DWMCI_IDINTEN mask 0x%x timeout.\n",
+ __func__, mask);
+ /* clear interrupts */
+ dwmci_writel(host, DWMCI_IDSTS, DWMCI_IDINTEN_MASK);
+
+ ctrl = dwmci_readl(host, DWMCI_CTRL);
+ ctrl &= ~(DWMCI_DMA_EN);
+ dwmci_writel(host, DWMCI_CTRL, ctrl);
+ bounce_buffer_stop(&bbstate);
}
-
- dwmci_writel(host, DWMCI_RINTSTS, mask);
-
- ctrl = dwmci_readl(host, DWMCI_CTRL);
- ctrl &= ~(DWMCI_DMA_EN);
- dwmci_writel(host, DWMCI_CTRL, ctrl);
-
- bounce_buffer_stop(&bbstate);
}
udelay(100);
return 0;
}
-static void dwmci_set_ios(struct mmc *mmc)
+#ifdef CONFIG_DM_MMC
+static int dwmci_set_ios(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
+static int dwmci_set_ios(struct mmc *mmc)
{
+#endif
struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
u32 ctype, regs;
if (host->clksel)
host->clksel(host);
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (mmc->vqmmc_supply) {
+ int ret;
+
+ if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
+ regulator_set_value(mmc->vqmmc_supply, 1800000);
+ else
+ regulator_set_value(mmc->vqmmc_supply, 3300000);
+
+ ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
+ if (ret)
+ return ret;
+ }
+#endif
+
+ return 0;
}
static int dwmci_init(struct mmc *mmc)
dwmci_writel(host, DWMCI_CLKENA, 0);
dwmci_writel(host, DWMCI_CLKSRC, 0);
+ if (!host->fifo_mode)
+ dwmci_writel(host, DWMCI_IDINTEN, DWMCI_IDINTEN_MASK);
+
return 0;
}
+#ifdef CONFIG_DM_MMC
+int dwmci_probe(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+
+ return dwmci_init(mmc);
+}
+
+const struct dm_mmc_ops dm_dwmci_ops = {
+ .send_cmd = dwmci_send_cmd,
+ .set_ios = dwmci_set_ios,
+};
+
+#else
static const struct mmc_ops dwmci_ops = {
.send_cmd = dwmci_send_cmd,
.set_ios = dwmci_set_ios,
.init = dwmci_init,
};
+#endif
-int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
+void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
+ u32 max_clk, u32 min_clk)
{
- host->cfg.name = host->name;
- host->cfg.ops = &dwmci_ops;
- host->cfg.f_min = min_clk;
- host->cfg.f_max = max_clk;
+ cfg->name = host->name;
+#ifndef CONFIG_DM_MMC
+ cfg->ops = &dwmci_ops;
+#endif
+ cfg->f_min = min_clk;
+ cfg->f_max = max_clk;
- host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
- host->cfg.host_caps = host->caps;
+ cfg->host_caps = host->caps;
if (host->buswidth == 8) {
- host->cfg.host_caps |= MMC_MODE_8BIT;
- host->cfg.host_caps &= ~MMC_MODE_4BIT;
+ cfg->host_caps |= MMC_MODE_8BIT;
+ cfg->host_caps &= ~MMC_MODE_4BIT;
} else {
- host->cfg.host_caps |= MMC_MODE_4BIT;
- host->cfg.host_caps &= ~MMC_MODE_8BIT;
+ cfg->host_caps |= MMC_MODE_4BIT;
+ cfg->host_caps &= ~MMC_MODE_8BIT;
}
- host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
+ cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
+
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+}
- host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+#ifdef CONFIG_BLK
+int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
+{
+ return mmc_bind(dev, mmc, cfg);
+}
+#else
+int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
+{
+ dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
host->mmc = mmc_create(&host->cfg, host);
if (host->mmc == NULL)
return 0;
}
+#endif
projects / J-u-boot.git / blobdiff