Merge tag 'v2023.10-rc4' into next

[J-u-boot.git] / arch / riscv / cpu / cpu.c

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 0f323b26b3f896fad99fb1cf8ac3e937c2eeb9e4..d64aa330f206531f57ce527b76f325752cbb3241 100644 (file)
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -22,18 +22,23 @@
 #if !CONFIG_IS_ENABLED(XIP)
 u32 hart_lottery __section(".data") = 0;
 
+#ifdef CONFIG_AVAILABLE_HARTS
 /*
  * The main hart running U-Boot has acquired available_harts_lock until it has
  * finished initialization of global data.
  */
 u32 available_harts_lock = 1;
 #endif
+#endif
 
 static inline bool supports_extension(char ext)
 {
-#ifdef CONFIG_CPU
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+       return csr_read(CSR_MISA) & (1 << (ext - 'a'));
+#elif CONFIG_CPU
        struct udevice *dev;
        char desc[32];
+       int i;
 
        uclass_find_first_device(UCLASS_CPU, &dev);
        if (!dev) {
@@ -41,24 +46,27 @@ static inline bool supports_extension(char ext)
                return false;
        }
        if (!cpu_get_desc(dev, desc, sizeof(desc))) {
-               /* skip the first 4 characters (rv32|rv64) */
-               if (strchr(desc + 4, ext))
-                       return true;
+               /*
+                * skip the first 4 characters (rv32|rv64) and
+                * check until underscore
+                */
+               for (i = 4; i < sizeof(desc); i++) {
+                       if (desc[i] == '_' || desc[i] == '\0')
+                               break;
+                       if (desc[i] == ext)
+                               return true;
+               }
        }
 
        return false;
 #else  /* !CONFIG_CPU */
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-       return csr_read(CSR_MISA) & (1 << (ext - 'a'));
-#else  /* !CONFIG_IS_ENABLED(RISCV_MMODE) */
 #warning "There is no way to determine the available extensions in S-mode."
 #warning "Please convert your board to use the RISC-V CPU driver."
        return false;
-#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */
 #endif /* CONFIG_CPU */
 }
 
-static int riscv_cpu_probe(void)
+static int riscv_cpu_probe(void *ctx, struct event *event)
 {
 #ifdef CONFIG_CPU
        int ret;
@@ -71,6 +79,7 @@ static int riscv_cpu_probe(void)
 
        return 0;
 }
+EVENT_SPY(EVT_DM_POST_INIT_R, riscv_cpu_probe);
 
 /*
  * This is called on secondary harts just after the IPI is init'd. Currently
@@ -83,11 +92,11 @@ static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1)
 }
 #endif
 
-int riscv_cpu_setup(void *ctx, struct event *event)
+int riscv_cpu_setup(void)
 {
        int ret;
 
-       ret = riscv_cpu_probe();
+       ret = riscv_cpu_probe(ctx, event);
        if (ret)
                return ret;
 
@@ -102,12 +111,14 @@ int riscv_cpu_setup(void *ctx, struct event *event)
                 * Enable perf counters for cycle, time,
                 * and instret counters only
                 */
+               if (supports_extension('u')) {
 #ifdef CONFIG_RISCV_PRIV_1_9
-               csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
-               csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
+                       csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
+                       csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
 #else
-               csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
+                       csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
 #endif
+               }
 
                /* Disable paging */
                if (supports_extension('s'))
@@ -135,16 +146,10 @@ int riscv_cpu_setup(void *ctx, struct event *event)
 
        return 0;
 }
-EVENT_SPY(EVT_DM_POST_INIT, riscv_cpu_setup);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, riscv_cpu_setup);
 
 int arch_early_init_r(void)
 {
-       int ret;
-
-       ret = riscv_cpu_probe();
-       if (ret)
-               return ret;
-
        if (IS_ENABLED(CONFIG_SYSRESET_SBI))
                device_bind_driver(gd->dm_root, "sbi-sysreset",
                                   "sbi-sysreset", NULL);