#define MMC_STATUS_ERROR (1 << 19)
#define MMC_STATE_PRG (7 << 9)
+#define MMC_STATE_TRANS (4 << 9)
#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
#define MMC_NUM_BOOT_PARTITION 2
#define MMC_PART_RPMB 3 /* RPMB partition number */
+/* timing specification used */
+#define MMC_TIMING_LEGACY 0
+#define MMC_TIMING_MMC_HS 1
+#define MMC_TIMING_SD_HS 2
+#define MMC_TIMING_UHS_SDR12 3
+#define MMC_TIMING_UHS_SDR25 4
+#define MMC_TIMING_UHS_SDR50 5
+#define MMC_TIMING_UHS_SDR104 6
+#define MMC_TIMING_UHS_DDR50 7
+#define MMC_TIMING_MMC_DDR52 8
+#define MMC_TIMING_MMC_HS200 9
+#define MMC_TIMING_MMC_HS400 10
+
/* Driver model support */
/**
* @return 0 if Ok, -ve if error
*/
int (*deferred_probe)(struct udevice *dev);
+ /**
+ * reinit() - Re-initialization to clear old configuration for
+ * mmc rescan.
+ *
+ * @dev: Device to reinit
+ * @return 0 if Ok, -ve if error
+ */
+ int (*reinit)(struct udevice *dev);
/**
* send_cmd() - Send a command to the MMC device
*
* @return maximum number of blocks for this transfer
*/
int (*get_b_max)(struct udevice *dev, void *dst, lbaint_t blkcnt);
+
+ /**
+ * hs400_prepare_ddr - prepare to switch to DDR mode
+ *
+ * @dev: Device to check
+ * @return 0 if success, -ve on error
+ */
+ int (*hs400_prepare_ddr)(struct udevice *dev);
};
#define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout_us);
int dm_mmc_host_power_cycle(struct udevice *dev);
int dm_mmc_deferred_probe(struct udevice *dev);
+int dm_mmc_reinit(struct udevice *dev);
int dm_mmc_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt);
/* Transition functions for compatibility */
int mmc_set_enhanced_strobe(struct mmc *mmc);
int mmc_host_power_cycle(struct mmc *mmc);
int mmc_deferred_probe(struct mmc *mmc);
+int mmc_reinit(struct mmc *mmc);
int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt);
-
+int mmc_hs400_prepare_ddr(struct mmc *mmc);
#else
struct mmc_ops {
int (*send_cmd)(struct mmc *mmc,
int (*host_power_cycle)(struct mmc *mmc);
int (*get_b_max)(struct mmc *mmc, void *dst, lbaint_t blkcnt);
};
+
+static inline int mmc_hs400_prepare_ddr(struct mmc *mmc)
+{
+ return 0;
+}
#endif
struct mmc_config {
uint f_max;
uint b_max;
unsigned char part_type;
+#ifdef CONFIG_MMC_PWRSEQ
+ struct udevice *pwr_dev;
+#endif
};
struct sd_ssr {
* accessing the boot partitions
*/
u32 quirks;
+ u8 hs400_tuning;
};
+#if CONFIG_IS_ENABLED(DM_MMC)
+#define mmc_to_dev(_mmc) _mmc->dev
+#else
+#define mmc_to_dev(_mmc) NULL
+#endif
+
struct mmc_hwpart_conf {
struct {
uint enh_start; /* in 512-byte sectors */
*/
int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
+#ifdef CONFIG_MMC_PWRSEQ
+/**
+ * mmc_pwrseq_get_power() - get a power device from device tree
+ *
+ * @dev: MMC device
+ * @cfg: MMC configuration
+ * @return 0 if OK, -ve on error
+ */
+int mmc_pwrseq_get_power(struct udevice *dev, struct mmc_config *cfg);
+#endif
+
int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
/**
#define mmc_host_is_spi(mmc) 0
#endif
+#define mmc_dev(x) ((x)->dev)
+
void board_mmc_power_init(void);
int board_mmc_init(struct bd_info *bis);
int cpu_mmc_init(struct bd_info *bis);