// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/ls102xa_devdis.h>
+#include <asm/sections.h>
#include <hwconfig.h>
#include <mmc.h>
#include <fsl_csu.h>
#include <fsl_ifc.h>
-#include <fsl_sec.h>
#include <spl.h>
#include <fsl_devdis.h>
#include <fsl_validate.h>
#include <fsl_ddr.h>
+#include "../common/i2c_mux.h"
#include "../common/sleep.h"
#include "../common/qixis.h"
#include "ls1021aqds_qixis.h"
return 0;
}
+#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
}
return 66666666;
}
+#endif
+#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
}
return 66666666;
}
-
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
- int ret;
-#ifdef CONFIG_DM_I2C
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
- 1, &dev);
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return ret;
- }
- ret = dm_i2c_write(dev, 0, &ch, 1);
-#else
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#endif
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
int dram_init(void)
{
int board_early_init_f(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET
/* clear BD & FR bits for BE BD's and frame data */
void board_init_f(ulong dummy)
{
#ifdef CONFIG_NAND_BOOT
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 porsr1, pinctl;
/*
porsr1 = in_be32(&gur->porsr1);
pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
DCFG_CCSR_PORSR1_RCW_SRC_I2C);
- out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+ out_be32((unsigned int *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
pinctl);
#endif
preloader_console_init();
-#ifdef CONFIG_SPL_I2C_SUPPORT
+#ifdef CONFIG_SPL_I2C
i2c_init_all();
#endif
void config_etseccm_source(int etsec_gtx_125_mux)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
switch (etsec_gtx_125_mux) {
case GE0_CLK125:
int config_serdes_mux(void)
{
- struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur *gur = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR;
u32 cfg;
cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
#ifdef CONFIG_FSL_DEVICE_DISABLE
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
-#endif
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
#endif
return 0;
}
}
#endif
-int ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, struct bd_info *bd)
{
ft_cpu_setup(blob, bd);