#include <init.h>
#include <log.h>
#include <ns16550.h>
+#include <power/regulator.h>
#include <usb.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch-tegra/gpu.h>
#include <asm/arch-tegra/usb.h>
#include <asm/arch-tegra/xusb-padctl.h>
+#ifndef CONFIG_TEGRA186
+#include <asm/arch-tegra/fuse.h>
+#include <asm/arch/gp_padctrl.h>
+#endif
#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
#include <asm/arch/clock.h>
#endif
-#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
+#if CONFIG_IS_ENABLED(PINCTRL_TEGRA)
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
#endif
#ifdef CONFIG_SPL_BUILD
-U_BOOT_DEVICE(tegra_gpios) = {
+U_BOOT_DRVINFO(tegra_gpios) = {
"gpio_tegra"
};
#endif
__weak void pin_mux_display(void) {}
__weak void start_cpu_fan(void) {}
__weak void cboot_late_init(void) {}
+__weak void nvidia_board_late_init(void) {}
#if defined(CONFIG_TEGRA_NAND)
__weak void pin_mux_nand(void)
{
int board_id = tegra_board_id();
- printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
+ printf("Board: %s", CFG_TEGRA_BOARD_STRING);
if (board_id != -1)
printf(", ID: %d\n", board_id);
printf("\n");
#endif
/* Init is handled automatically in the driver-model case */
-#if defined(CONFIG_DM_VIDEO)
+#if defined(CONFIG_VIDEO)
pin_mux_display();
#endif
/* boot param addr */
pin_mux_usb();
#endif
-#if defined(CONFIG_DM_VIDEO)
+#if defined(CONFIG_VIDEO)
board_id = tegra_board_id();
err = tegra_lcd_pmic_init(board_id);
if (err) {
/* prepare the WB code to LP0 location */
warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
#endif
+
+ /* Set up boot-on regulators */
+ regulators_enable_boot_on(_DEBUG);
+
return nvidia_board_init();
}
}
#endif /* EARLY_INIT */
+#ifndef CONFIG_TEGRA186
+static void nvidia_board_late_init_generic(void)
+{
+ char serialno_str[17];
+
+ /* Set chip id as serialno */
+ sprintf(serialno_str, "%016llx", tegra_chip_uid());
+ env_set("serial#", serialno_str);
+
+ switch (tegra_get_chip()) {
+ case CHIPID_TEGRA20:
+ env_set("platform", "tegra20");
+ break;
+ case CHIPID_TEGRA30:
+ env_set("platform", "tegra30");
+ break;
+ case CHIPID_TEGRA114:
+ env_set("platform", "tegra114");
+ break;
+ case CHIPID_TEGRA124:
+ env_set("platform", "tegra124");
+ break;
+ case CHIPID_TEGRA210:
+ env_set("platform", "tegra210");
+ break;
+ default:
+ return;
+ }
+}
+#endif
+
int board_late_init(void)
{
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
start_cpu_fan();
cboot_late_init();
+ /*
+ * Perform generic env setup in case
+ * vendor does not provide it.
+ */
+#ifndef CONFIG_TEGRA186
+ nvidia_board_late_init_generic();
+#endif
+ nvidia_board_late_init();
+
return 0;
}
/* fall back to default DRAM bank size computation */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
#ifdef CONFIG_PCI
* This function is called before dram_init_banksize(), so we can't simply
* return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
*/
-ulong board_get_usable_ram_top(ulong total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
ulong ram_top;
/* fall back to default usable RAM computation */
- return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
+ return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
}