#define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30)
#define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31)
-/*
- * event types, cf.
- * "TCG Server Management Domain Firmware Profile Specification",
- * rev 1.00, 2020-05-01
- */
-#define EV_POST_CODE ((u32)0x00000001)
-#define EV_NO_ACTION ((u32)0x00000003)
-#define EV_SEPARATOR ((u32)0x00000004)
-#define EV_ACTION ((u32)0x00000005)
-#define EV_TAG ((u32)0x00000006)
-#define EV_S_CRTM_CONTENTS ((u32)0x00000007)
-#define EV_S_CRTM_VERSION ((u32)0x00000008)
-#define EV_CPU_MICROCODE ((u32)0x00000009)
-#define EV_PLATFORM_CONFIG_FLAGS ((u32)0x0000000A)
-#define EV_TABLE_OF_DEVICES ((u32)0x0000000B)
-#define EV_COMPACT_HASH ((u32)0x0000000C)
-
-/*
- * event types, cf.
- * "TCG PC Client Platform Firmware Profile Specification", Family "2.0"
- * rev 1.04, June 3, 2019
- */
-#define EV_EFI_EVENT_BASE ((u32)0x80000000)
-#define EV_EFI_VARIABLE_DRIVER_CONFIG ((u32)0x80000001)
-#define EV_EFI_VARIABLE_BOOT ((u32)0x80000002)
-#define EV_EFI_BOOT_SERVICES_APPLICATION ((u32)0x80000003)
-#define EV_EFI_BOOT_SERVICES_DRIVER ((u32)0x80000004)
-#define EV_EFI_RUNTIME_SERVICES_DRIVER ((u32)0x80000005)
-#define EV_EFI_GPT_EVENT ((u32)0x80000006)
-#define EV_EFI_ACTION ((u32)0x80000007)
-#define EV_EFI_PLATFORM_FIRMWARE_BLOB ((u32)0x80000008)
-#define EV_EFI_HANDOFF_TABLES ((u32)0x80000009)
-#define EV_EFI_HCRTM_EVENT ((u32)0x80000010)
-#define EV_EFI_VARIABLE_AUTHORITY ((u32)0x800000E0)
-
/* TPMS_TAGGED_PROPERTY Structure */
struct tpms_tagged_property {
u32 property;
union tpmu_capabilities data;
} __packed;
-/**
- * SHA1 Event Log Entry Format
- *
- * @pcr_index: PCRIndex event extended to
- * @event_type: Type of event (see EFI specs)
- * @digest: Value extended into PCR index
- * @event_size: Size of event
- * @event: Event data
- */
-struct tcg_pcr_event {
- u32 pcr_index;
- u32 event_type;
- u8 digest[TPM2_SHA1_DIGEST_SIZE];
- u32 event_size;
- u8 event[];
-} __packed;
-
/**
* Definition of TPMU_HA Union
*/
-union tmpu_ha {
+union tpmu_ha {
u8 sha1[TPM2_SHA1_DIGEST_SIZE];
u8 sha256[TPM2_SHA256_DIGEST_SIZE];
u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE];
*/
struct tpmt_ha {
u16 hash_alg;
- union tmpu_ha digest;
+ union tpmu_ha digest;
} __packed;
/**
struct tpmt_ha digests[TPM2_NUM_PCR_BANKS];
} __packed;
-/**
- * Crypto Agile Log Entry Format
- *
- * @pcr_index: PCRIndex event extended to
- * @event_type: Type of event
- * @digests: List of digestsextended to PCR index
- * @event_size: Size of the event data
- * @event: Event data
- */
-struct tcg_pcr_event2 {
- u32 pcr_index;
- u32 event_type;
- struct tpml_digest_values digests;
- u32 event_size;
- u8 event[];
-} __packed;
-
/**
* TPM2 Structure Tags for command/response buffers.
*
TPM2_ALG_SM3_256 = 0x12,
};
+/**
+ * struct digest_info - details of supported digests
+ *
+ * @hash_name: hash name
+ * @hash_alg: hash algorithm id
+ * @hash_mask: hash registry mask
+ * @hash_len: hash digest length
+ */
+struct digest_info {
+ const char *hash_name;
+ u16 hash_alg;
+ u32 hash_mask;
+ u16 hash_len;
+ bool supported;
+};
+
+/* Algorithm Registry */
+#define TCG2_BOOT_HASH_ALG_SHA1 0x00000001
+#define TCG2_BOOT_HASH_ALG_SHA256 0x00000002
+#define TCG2_BOOT_HASH_ALG_SHA384 0x00000004
+#define TCG2_BOOT_HASH_ALG_SHA512 0x00000008
+#define TCG2_BOOT_HASH_ALG_SM3_256 0x00000010
+
+static const struct digest_info hash_algo_list[] = {
+ {
+ "sha1",
+ TPM2_ALG_SHA1,
+ TCG2_BOOT_HASH_ALG_SHA1,
+ TPM2_SHA1_DIGEST_SIZE,
+#if IS_ENABLED(CONFIG_SHA1)
+ true,
+#else
+ false,
+#endif
+ },
+ {
+ "sha256",
+ TPM2_ALG_SHA256,
+ TCG2_BOOT_HASH_ALG_SHA256,
+ TPM2_SHA256_DIGEST_SIZE,
+#if IS_ENABLED(CONFIG_SHA256)
+ true,
+#else
+ false,
+#endif
+ },
+ {
+ "sha384",
+ TPM2_ALG_SHA384,
+ TCG2_BOOT_HASH_ALG_SHA384,
+ TPM2_SHA384_DIGEST_SIZE,
+#if IS_ENABLED(CONFIG_SHA384)
+ true,
+#else
+ false,
+#endif
+ },
+ {
+ "sha512",
+ TPM2_ALG_SHA512,
+ TCG2_BOOT_HASH_ALG_SHA512,
+ TPM2_SHA512_DIGEST_SIZE,
+#if IS_ENABLED(CONFIG_SHA512)
+ true,
+#else
+ false,
+#endif
+ },
+};
+
/* NV index attributes */
enum tpm_index_attrs {
TPMA_NV_PPWRITE = 1UL << 0,
TPM_STS_DATA_EXPECT = 1 << 3,
TPM_STS_SELF_TEST_DONE = 1 << 2,
TPM_STS_RESPONSE_RETRY = 1 << 1,
+ TPM_STS_READ_ZERO = 0x23
};
enum {
* @dev TPM device
* @mode TPM startup mode
*
- * @return code of the operation
+ * Return: code of the operation
*/
u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);
* @dev TPM device
* @full_test Asking to perform all tests or only the untested ones
*
- * @return code of the operation
+ * Return: code of the operation
*/
u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);
* @pw Password
* @pw_sz Length of the password
*
- * @return code of the operation
+ * Return: code of the operation
*/
u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw,
const ssize_t pw_sz);
* @nv_attributes TPM_NV_ATTRIBUTES of the area
* @nv_policy policy to use
* @nv_policy_size size of the policy
- * @return return code of the operation
+ * Return: return code of the operation
*/
u32 tpm2_nv_define_space(struct udevice *dev, u32 space_index,
size_t space_size, u32 nv_attributes,
* @digest Value representing the event to be recorded
* @digest_len len of the hash
*
- * @return code of the operation
+ * Return: code of the operation
*/
u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm,
const u8 *digest, u32 digest_len);
* @index Index of data to read
* @data Place to put data
* @count Number of bytes of data
- * @return code of the operation
+ * Return: code of the operation
*/
u32 tpm2_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count);
* @index Index of data to write
* @data Data to write
* @count Number of bytes of data
- * @return code of the operation
+ * Return: code of the operation
*/
u32 tpm2_nv_write_value(struct udevice *dev, u32 index, const void *data,
u32 count);
* @dev TPM device
* @idx Index of the PCR
* @idx_min_sz Minimum size in bytes of the pcrSelect array
+ * @algorithm Algorithm used, defined in 'enum tpm2_algorithms'
* @data Output buffer for contents of the named PCR
+ * @digest_len len of the data
* @updates Optional out parameter: number of updates for this PCR
*
- * @return code of the operation
+ * Return: code of the operation
*/
u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
- void *data, unsigned int *updates);
+ u16 algorithm, void *data, u32 digest_len,
+ unsigned int *updates);
/**
* Issue a TPM2_GetCapability command. This implementation is limited
* @buf Output buffer for capability information
* @prop_count Size of output buffer
*
- * @return code of the operation
+ * Return: code of the operation
*/
u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
void *buf, size_t prop_count);
+/**
+ * tpm2_get_pcr_info() - get the supported, active PCRs and number of banks
+ *
+ * @dev: TPM device
+ * @pcrs: struct tpml_pcr_selection of available PCRs
+ *
+ * @return 0 on success, code of operation or negative errno on failure
+ */
+int tpm2_get_pcr_info(struct udevice *dev, struct tpml_pcr_selection *pcrs);
+
/**
* Issue a TPM2_DictionaryAttackLockReset command.
*
* @pw Password
* @pw_sz Length of the password
*
- * @return code of the operation
+ * Return: code of the operation
*/
u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz);
* @recovery_time Time before decrementation of the failure count
* @lockout_recovery Time to wait after a lockout
*
- * @return code of the operation
+ * Return: code of the operation
*/
u32 tpm2_dam_parameters(struct udevice *dev, const char *pw,
const ssize_t pw_sz, unsigned int max_tries,
* @oldpw Old password
* @oldpw_sz Length of the old password
*
- * @return code of the operation
+ * Return: code of the operation
*/
int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw,
const ssize_t newpw_sz, const char *oldpw,
* @index Index of the PCR
* @digest New key to access the PCR
*
- * @return code of the operation
+ * Return: code of the operation
*/
u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw,
const ssize_t pw_sz, u32 index, const char *key);
* @digest New key to access the PCR
* @key_sz Length of the new key
*
- * @return code of the operation
+ * Return: code of the operation
*/
u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw,
const ssize_t pw_sz, u32 index, const char *key,
* @param data output buffer for the random bytes
* @param count size of output buffer
*
- * @return return code of the operation
+ * Return: return code of the operation
*/
u32 tpm2_get_random(struct udevice *dev, void *data, u32 count);
*
* @dev TPM device
* @index Index of data to lock
- * @return code of the operation
+ * Return: code of the operation
*/
u32 tpm2_write_lock(struct udevice *dev, u32 index);
* before calling the kernel.
*
* @dev TPM device
- * @return code of the operation
+ * Return: code of the operation
*/
u32 tpm2_disable_platform_hierarchy(struct udevice *dev);
+/**
+ * submit user specified data to the TPM and get response
+ *
+ * @dev TPM device
+ * @sendbuf: Buffer of the data to send
+ * @recvbuf: Buffer to save the response to
+ * @recv_size: Pointer to the size of the response buffer
+ *
+ * Return: code of the operation
+ */
+u32 tpm2_submit_command(struct udevice *dev, const u8 *sendbuf,
+ u8 *recvbuf, size_t *recv_size);
+
+/**
+ * tpm_cr50_report_state() - Report the Cr50 internal state
+ *
+ * @dev: TPM device
+ * @vendor_cmd: Vendor command number to send
+ * @vendor_subcmd: Vendor sub-command number to send
+ * @recvbuf: Buffer to save the response to
+ * @recv_size: Pointer to the size of the response buffer
+ * Return: result of the operation
+ */
+u32 tpm2_report_state(struct udevice *dev, uint vendor_cmd, uint vendor_subcmd,
+ u8 *recvbuf, size_t *recv_size);
+
+/**
+ * tpm2_enable_nvcommits() - Tell TPM to commit NV data immediately
+ *
+ * For Chromium OS verified boot, we may reboot or reset at different times,
+ * possibly leaving non-volatile data unwritten by the TPM.
+ *
+ * This vendor command is used to indicate that non-volatile data should be
+ * written to its store immediately.
+ *
+ * @dev TPM device
+ * @vendor_cmd: Vendor command number to send
+ * @vendor_subcmd: Vendor sub-command number to send
+ * Return: result of the operation
+ */
+u32 tpm2_enable_nvcommits(struct udevice *dev, uint vendor_cmd,
+ uint vendor_subcmd);
+
+/**
+ * tpm2_auto_start() - start up the TPM and perform selftests.
+ * If a testable function has not been tested and is
+ * requested the TPM2 will return TPM_RC_NEEDS_TEST.
+ *
+ * @param dev TPM device
+ * Return: TPM2_RC_TESTING, if TPM2 self-test is in progress.
+ * TPM2_RC_SUCCESS, if testing of all functions is complete without
+ * functional failures.
+ * TPM2_RC_FAILURE, if any test failed.
+ * TPM2_RC_INITIALIZE, if the TPM has not gone through the Startup
+ * sequence
+
+ */
+u32 tpm2_auto_start(struct udevice *dev);
+
+/**
+ * tpm2_name_to_algorithm() - Return an algorithm id given a supported
+ * algorithm name
+ *
+ * @name: algorithm name
+ * Return: enum tpm2_algorithms or -EINVAL
+ */
+enum tpm2_algorithms tpm2_name_to_algorithm(const char *name);
+
+/**
+ * tpm2_algorithm_name() - Return an algorithm name string for a
+ * supported algorithm id
+ *
+ * @algorithm_id: algorithm defined in enum tpm2_algorithms
+ * Return: algorithm name string or ""
+ */
+const char *tpm2_algorithm_name(enum tpm2_algorithms);
+
+/**
+ * tpm2_algorithm_supported() - Check if the algorithm supported by U-Boot
+ *
+ * @algorithm_id: algorithm defined in enum tpm2_algorithms
+ * Return: true if supported, otherwise false
+ */
+bool tpm2_algorithm_supported(enum tpm2_algorithms algo);
+
+/**
+ * tpm2_algorithm_to_len() - Return an algorithm length for supported algorithm id
+ *
+ * @algorithm_id: algorithm defined in enum tpm2_algorithms
+ * Return: len or 0 if not supported
+ */
+u16 tpm2_algorithm_to_len(enum tpm2_algorithms algo);
+
+/*
+ * When measured boot is enabled via EFI or bootX commands all the algorithms
+ * above are selected by our Kconfigs. Due to U-Boots nature of being small there
+ * are cases where we need some functionality from the TPM -- e.g storage or RNG
+ * but we don't want to support measurements.
+ *
+ * The choice of hash algorithms are determined by the platform and the TPM
+ * configuration. Failing to cap a PCR in a bank which the platform left
+ * active is a security vulnerability. It permits the unsealing of secrets
+ * if an attacker can replay a good set of measurements into an unused bank.
+ *
+ * On top of that a previous stage bootloader (e.g TF-A), migh pass an eventlog
+ * since it doesn't have a TPM driver, which U-Boot needs to replace. The algorit h
+ * choice is a compile time option in that case and we need to make sure we conform.
+ *
+ * Add a variable here that sums the supported algorithms U-Boot was compiled
+ * with so we can refuse to do measurements if we don't support all of them
+ */
+
+/**
+ * tpm2_check_active_banks() - Check if the active PCR banks are supported by
+ * our configuration
+ *
+ * @dev: TPM device
+ * Return: true if allowed
+ */
+bool tpm2_check_active_banks(struct udevice *dev);
+
+/**
+ * tpm2_is_active_bank() - check the pcr_select. If at least one of the PCRs
+ * supports the algorithm add it on the active ones
+ *
+ * @selection: PCR selection structure
+ * Return: True if the algorithm is active
+ */
+bool tpm2_is_active_bank(struct tpms_pcr_selection *selection);
+
#endif /* __TPM_V2_H */
projects / J-u-boot.git / blobdiff