+config ARCH_MAP_SYSMEM
+ depends on SANDBOX
+ def_bool y
+
config CREATE_ARCH_SYMLINK
bool
config HAVE_ARCH_IOREMAP
bool
-config NEEDS_MANUAL_RELOC
- bool
-
config SYS_CACHE_SHIFT_4
bool
select SUPPORT_OF_CONTROL
select SYS_CACHE_SHIFT_7
select TIMER
+ select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
+ select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
config ARM
bool "ARM architecture"
select ARCH_SUPPORTS_LTO
select CREATE_ARCH_SYMLINK
select HAVE_PRIVATE_LIBGCC if !ARM64
+ select SUPPORT_ACPI
select SUPPORT_OF_CONTROL
config M68K
config MICROBLAZE
bool "MicroBlaze architecture"
- select NEEDS_MANUAL_RELOC
select SUPPORT_OF_CONTROL
- imply CMD_IRQ
+ imply CMD_TIMER
+ imply SPL_REGMAP if SPL
+ imply SPL_TIMER if SPL
+ imply TIMER
+ imply XILINX_TIMER
config MIPS
bool "MIPS architecture"
select HAVE_ARCH_IOREMAP
select HAVE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL
-
-config NDS32
- bool "NDS32 architecture"
- select SUPPORT_OF_CONTROL
+ select SPL_SEPARATE_BSS if SPL
config NIOS2
bool "Nios II architecture"
select CPU
select DM
+ imply DM_EVENT
select OF_CONTROL
select SUPPORT_OF_CONTROL
imply CMD_DM
select SUPPORT_OF_CONTROL
select OF_CONTROL
select DM
+ select SPL_SEPARATE_BSS if SPL
imply DM_SERIAL
imply DM_ETH
+ imply DM_EVENT
imply DM_MMC
imply DM_SPI
imply DM_SPI_FLASH
imply SPL_OF_CONTROL
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
- imply SPL_SERIAL_SUPPORT
+ imply SPL_SERIAL
imply SPL_TIMER
config SANDBOX
select BZIP2
select CMD_POWEROFF
select DM
+ select DM_FUZZING_ENGINE
select DM_GPIO
select DM_I2C
select DM_KEYBOARD
select SYS_CACHE_SHIFT_4
select IRQ
select SUPPORT_EXTENSION_SCAN
+ select SUPPORT_ACPI
imply BITREVERSE
select BLOBLIST
imply LTO
imply CRC32_VERIFY
imply FAT_WRITE
imply FIRMWARE
+ imply FUZZING_ENGINE_SANDBOX
imply HASH_VERIFY
imply LZMA
- imply SCSI
imply TEE
imply AVB_VERIFY
imply LIBAVB
imply CMD_AVB
+ imply PARTITION_TYPE_GUID
imply SCP03
imply CMD_SCP03
imply UDP_FUNCTION_FASTBOOT
imply PHY_FIXED
imply DM_DSA
imply CMD_EXTENSION
+ imply KEYBOARD
+ imply PHYSMEM
+ imply GENERATE_ACPI_TABLE
+ imply BINMAN
config SH
bool "SuperH architecture"
select SUPPORT_TPL
select CREATE_ARCH_SYMLINK
select DM
- select DM_PCI
select HAVE_ARCH_IOMAP
select HAVE_PRIVATE_LIBGCC
select OF_CONTROL
select PCI
+ select SUPPORT_ACPI
select SUPPORT_OF_CONTROL
select SYS_CACHE_SHIFT_6
select TIMER
imply CMD_SF_TEST
imply CMD_ZBOOT
imply DM_ETH
+ imply DM_EVENT
imply DM_GPIO
imply DM_KEYBOARD
imply DM_MMC
imply USB_ETHER_SMSC95XX
imply USB_HOST_ETHER
imply PCH
+ imply PHYSMEM
imply RTC_MC146818
- imply ACPIGEN if !QEMU
+ imply ACPIGEN if !QEMU && !EFI_APP
imply SYSINFO if GENERATE_SMBIOS_TABLE
imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
+ imply TIMESTAMP
# Thing to enable for when SPL/TPL are enabled: SPL
imply SPL_DM
imply SPL_PINCTRL
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
- imply SPL_SERIAL_SUPPORT
+ imply SPL_SERIAL
imply SPL_SPI_FLASH_SUPPORT
- imply SPL_SPI_SUPPORT
+ imply SPL_SPI
imply SPL_OF_CONTROL
imply SPL_TIMER
imply SPL_REGMAP
imply TPL_PINCTRL
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
- imply TPL_SERIAL_SUPPORT
+ imply TPL_SERIAL
imply TPL_OF_CONTROL
imply TPL_TIMER
imply TPL_REGMAP
Note that, its up to the individual architectures to implement
this functionality.
+config SYS_IMMR
+ hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
+ depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
+ default 0xFF000000 if MPC8xx
+ default 0xF0000000 if ARCH_MPC8313
+ default 0xE0000000 if MPC83xx && !ARCH_MPC8313
+ default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
+ default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
+ ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
+ ARCH_P2020
+ default SYS_CCSRBAR_DEFAULT
+ help
+ Address for the Internal Memory-Mapped Registers (IMMR) window used
+ to configure the features of many Freescale / NXP SoCs.
+
+config SKIP_LOWLEVEL_INIT
+ bool "Skip the calls to certain low level initialization functions"
+ depends on ARM || MIPS || RISCV
+ help
+ If enabled, then certain low level initializations (like setting up
+ the memory controller) are omitted and/or U-Boot does not relocate
+ itself into RAM.
+ Normally this variable MUST NOT be defined. The only exception is
+ when U-Boot is loaded (to RAM) by some other boot loader or by a
+ debugger which performs these initializations itself.
+
+config SPL_SKIP_LOWLEVEL_INIT
+ bool "Skip the calls to certain low level initialization functions"
+ depends on SPL && (ARM || MIPS || RISCV)
+ help
+ If enabled, then certain low level initializations (like setting up
+ the memory controller) are omitted and/or U-Boot does not relocate
+ itself into RAM.
+ Normally this variable MUST NOT be defined. The only exception is
+ when U-Boot is loaded (to RAM) by some other boot loader or by a
+ debugger which performs these initializations itself.
+
+config TPL_SKIP_LOWLEVEL_INIT
+ bool "Skip the calls to certain low level initialization functions"
+ depends on SPL && ARM
+ help
+ If enabled, then certain low level initializations (like setting up
+ the memory controller) are omitted and/or U-Boot does not relocate
+ itself into RAM.
+ Normally this variable MUST NOT be defined. The only exception is
+ when U-Boot is loaded (to RAM) by some other boot loader or by a
+ debugger which performs these initializations itself.
+
+config SKIP_LOWLEVEL_INIT_ONLY
+ bool "Skip the call to lowlevel_init during early boot ONLY"
+ depends on ARM
+ help
+ This allows just the call to lowlevel_init() to be skipped. The
+ normal CP15 init (such as enabling the instruction cache) is still
+ performed.
+
+config SPL_SKIP_LOWLEVEL_INIT_ONLY
+ bool "Skip the call to lowlevel_init during early boot ONLY"
+ depends on SPL && ARM
+ help
+ This allows just the call to lowlevel_init() to be skipped. The
+ normal CP15 init (such as enabling the instruction cache) is still
+ performed.
+
+config TPL_SKIP_LOWLEVEL_INIT_ONLY
+ bool "Skip the call to lowlevel_init during early boot ONLY"
+ depends on TPL && ARM
+ help
+ This allows just the call to lowlevel_init() to be skipped. The
+ normal CP15 init (such as enabling the instruction cache) is still
+ performed.
+
source "arch/arc/Kconfig"
source "arch/arm/Kconfig"
source "arch/m68k/Kconfig"
source "arch/microblaze/Kconfig"
source "arch/mips/Kconfig"
-source "arch/nds32/Kconfig"
source "arch/nios2/Kconfig"
source "arch/powerpc/Kconfig"
source "arch/sandbox/Kconfig"
source "arch/x86/Kconfig"
source "arch/xtensa/Kconfig"
source "arch/riscv/Kconfig"
+
+if ARM || M68K || PPC
+
+source "arch/Kconfig.nxp"
+
+endif
+
+source "board/keymile/Kconfig"
+
+if MIPS || MICROBLAZE
+
+choice
+ prompt "Endianness selection"
+ help
+ Some MIPS boards can be configured for either little or big endian
+ byte order. These modes require different U-Boot images. In general there
+ is one preferred byteorder for a particular system but some systems are
+ just as commonly used in the one or the other endianness.
+
+config SYS_BIG_ENDIAN
+ bool "Big endian"
+ depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
+
+config SYS_LITTLE_ENDIAN
+ bool "Little endian"
+ depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE
+
+endchoice
+
+endif
projects / J-u-boot.git / blobdiff