+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2009 Freescale Semiconductor.
+ * Copyright 2009-2010 Freescale Semiconductor.
*
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
*/
#include <common.h>
+#include <console.h>
+#include <flash.h>
#include <hwconfig.h>
+#include <init.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
+#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <spd_sdram.h>
#include <i2c.h>
#include <ioports.h>
-#include <libfdt.h>
+#include <linux/libfdt.h>
#include <fdt_support.h>
#include <fsl_esdhc.h>
+#include <phy.h>
#include "bcsr.h"
-
-phys_size_t fixed_sdram(void);
+#if defined(CONFIG_PQ_MDS_PIB)
+#include "../common/pq-mds-pib.h"
+#endif
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* QE_MUX_MDC */
return 0;
}
-int checkboard (void)
-{
- printf ("Board: 8569 MDS\n");
-
- return 0;
-}
-
-phys_size_t
-initdram(int board_type)
+int board_early_init_r(void)
{
- long dram_size = 0;
-
- puts("Initializing\n");
+ const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
+ const u8 flash_esel = 0;
-#if defined(CONFIG_DDR_DLL)
/*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
+ * Remap Boot flash to caching-inhibited
+ * so that flash can be erased properly.
*/
- volatile ccsr_gur_t *gur =
- (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- out_be32(&gur->ddrdllcr, 0x81000000);
- udelay(200);
-#endif
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
-#ifdef CONFIG_SPD_EEPROM
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fixed_sdram();
-#endif
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
+ 0, flash_esel, /* ts, esel */
+ BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
+ return 0;
+}
- puts(" DDR: ");
- return dram_size;
+int checkboard (void)
+{
+ printf ("Board: 8569 MDS\n");
+
+ return 0;
}
#if !defined(CONFIG_SPD_EEPROM)
phys_size_t fixed_sdram(void)
{
- volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
uint d_init;
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
- uint lbc_hz;
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
out_be32(&gur->lbiuiplldcr1, 0x00078080);
if (clkdiv == 16)
clrbits_8(&bcsr[17], BCSR17_nUSBEN);
}
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif /* CONFIG_PCIE1 */
-
#ifdef CONFIG_PCI
void pci_init_board(void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct fsl_pci_info pci_info[1];
- u32 devdisr, pordevsr, io_sel;
- int first_free_busno = 0;
- int num = 0;
-
- int pcie_ep, pcie_configured;
-
- devdisr = in_be32(&gur->devdisr);
- pordevsr = in_be32(&gur->pordevsr);
- io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-
- debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
-
-#ifdef CONFIG_PCIE1
- pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- SET_STD_PCIE_INFO(pci_info[num], 1);
- pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
- printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
- } else {
- printf (" PCIE1: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
+#if defined(CONFIG_PQ_MDS_PIB)
+ pib_init();
#endif
+ fsl_pcie_init_board(0);
}
#endif /* CONFIG_PCI */
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_SYS_UCC_RMII_MODE)
int nodeoff, off, err;
break;
}
- err = fdt_setprop_string(blob, nodeoff, "phy-connection-type",
- "rmii");
+ err = fdt_fixup_phy_connection(blob, nodeoff,
+ PHY_INTERFACE_MODE_RMII);
+
if (err < 0) {
printf("WARNING: could not set phy-connection-type "
"%s.\n", fdt_strerror(err));
#endif
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
-#endif
+ FT_FSL_PCI_SETUP;
+
fdt_board_fixup_esdhc(blob, bd);
fdt_board_fixup_qe_uart(blob, bd);
fdt_board_fixup_qe_usb(blob, bd);
+
+ return 0;
}
#endif
projects / J-u-boot.git / blobdiff