imx: reorganize IMX code as other SOCs

[J-u-boot.git] / board / ge / bx50v3 / bx50v3.c

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index d45ed44c68435ecb93ad33a1c5fb846889ead7ce..b25c634bb5a072a1010496adbb62e38e7d1dcc0b 100644 (file)
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -10,12 +10,12 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
@@ -60,7 +60,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-       gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+       gd->ram_size = imx_ddr_size();
 
        return 0;
 }
@@ -103,8 +103,9 @@ static void setup_iomux_enet(void)
 
        /* Reset AR8033 PHY */
        gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
-       udelay(500);
+       mdelay(10);
        gpio_set_value(IMX_GPIO_NR(1, 28), 1);
+       mdelay(1);
 }
 
 static iomux_v3_cfg_t const usdhc2_pads[] = {
@@ -306,7 +307,8 @@ static int mx6_rgmii_rework(struct phy_device *phydev)
        /* set debug port address: SerDes Test and System Mode Control */
        phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
        /* enable rgmii tx clock delay */
-       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+       /* set the reserved bits to avoid board specific voltage peak issue*/
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 
        return 0;
 }
@@ -596,6 +598,57 @@ static const struct boot_mode board_boot_modes[] = {
 };
 #endif
 
+void pmic_init(void)
+{
+#define I2C_PMIC                0x2
+#define DA9063_I2C_ADDR         0x58
+#define DA9063_REG_BCORE2_CFG   0x9D
+#define DA9063_REG_BCORE1_CFG   0x9E
+#define DA9063_REG_BPRO_CFG     0x9F
+#define DA9063_REG_BIO_CFG      0xA0
+#define DA9063_REG_BMEM_CFG     0xA1
+#define DA9063_REG_BPERI_CFG    0xA2
+#define DA9063_BUCK_MODE_MASK   0xC0
+#define DA9063_BUCK_MODE_MANUAL 0x00
+#define DA9063_BUCK_MODE_SLEEP  0x40
+#define DA9063_BUCK_MODE_SYNC   0x80
+#define DA9063_BUCK_MODE_AUTO   0xC0
+
+       uchar val;
+
+       i2c_set_bus_num(I2C_PMIC);
+
+       i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
+       val &= ~DA9063_BUCK_MODE_MASK;
+       val |= DA9063_BUCK_MODE_SYNC;
+       i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
+
+       i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
+       val &= ~DA9063_BUCK_MODE_MASK;
+       val |= DA9063_BUCK_MODE_SYNC;
+       i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
+
+       i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
+       val &= ~DA9063_BUCK_MODE_MASK;
+       val |= DA9063_BUCK_MODE_SYNC;
+       i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
+
+       i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
+       val &= ~DA9063_BUCK_MODE_MASK;
+       val |= DA9063_BUCK_MODE_SYNC;
+       i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
+
+       i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
+       val &= ~DA9063_BUCK_MODE_MASK;
+       val |= DA9063_BUCK_MODE_SYNC;
+       i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
+
+       i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
+       val &= ~DA9063_BUCK_MODE_MASK;
+       val |= DA9063_BUCK_MODE_SYNC;
+       i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
+}
+
 int board_late_init(void)
 {
 #ifdef CONFIG_CMD_BMODE
@@ -619,6 +672,9 @@ int board_late_init(void)
        pwm_enable(0);
 #endif
 
+       /* board specific pmic init */
+       pmic_init();
+
        return 0;
 }