exynos5: add trace feature #ifdef in exynos5-common.h

[J-u-boot.git] / include / fsl_esdhc.h

diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index f9ae15ad42a91158034726b64539e826eca0e1e4..57295b4bc03496e596a3731e78aeae3dc936e314 100644 (file)
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -2,25 +2,9 @@
  * FSL SD/MMC Defines
  *-------------------------------------------------------------------
  *
- * Copyright 2007-2008,2010 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- *-------------------------------------------------------------------
+ * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
  *
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef  __FSL_ESDHC_H__
@@ -29,17 +13,21 @@
 #include <asm/errno.h>
 #include <asm/byteorder.h>
 
+/* needed for the mmc_cfg definition */
+#include <mmc.h>
+
 /* FSL eSDHC-specific constants */
 #define SYSCTL                 0x0002e02c
 #define SYSCTL_INITA           0x08000000
 #define SYSCTL_TIMEOUT_MASK    0x000f0000
 #define SYSCTL_CLOCK_MASK      0x0000fff0
-#define SYSCTL_RSTA            0x01000000
 #define SYSCTL_CKEN            0x00000008
 #define SYSCTL_PEREN           0x00000004
 #define SYSCTL_HCKEN           0x00000002
 #define SYSCTL_IPGEN           0x00000001
 #define SYSCTL_RSTA            0x01000000
+#define SYSCTL_RSTC            0x02000000
+#define SYSCTL_RSTD            0x04000000
 
 #define IRQSTAT                        0x0002e030
 #define IRQSTAT_DMAE           (0x10000000)
@@ -62,7 +50,9 @@
 #define IRQSTAT_CC             (0x00000001)
 
 #define CMD_ERR                (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
-#define DATA_ERR       (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE)
+#define DATA_ERR       (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
+                               IRQSTAT_DMAE)
+#define DATA_COMPLETE  (IRQSTAT_TC | IRQSTAT_DINT)
 
 #define IRQSTATEN              0x0002e034
 #define IRQSTATEN_DMAE         (0x10000000)
@@ -85,11 +75,13 @@
 #define IRQSTATEN_CC           (0x00000001)
 
 #define PRSSTAT                        0x0002e024
+#define PRSSTAT_DAT0           (0x01000000)
 #define PRSSTAT_CLSL           (0x00800000)
 #define PRSSTAT_WPSPL          (0x00080000)
 #define PRSSTAT_CDPL           (0x00040000)
 #define PRSSTAT_CINS           (0x00010000)
 #define PRSSTAT_BREN           (0x00000800)
+#define PRSSTAT_BWEN           (0x00000400)
 #define PRSSTAT_DLA            (0x00000004)
 #define PRSSTAT_CICHB          (0x00000002)
 #define PRSSTAT_CIDHB          (0x00000001)
@@ -116,11 +108,13 @@
 #define XFERTYP_RSPTYP_48_BUSY 0x00030000
 #define XFERTYP_MSBSEL         0x00000020
 #define XFERTYP_DTDSEL         0x00000010
+#define XFERTYP_DDREN          0x00000008
 #define XFERTYP_AC12EN         0x00000004
 #define XFERTYP_BCEN           0x00000002
 #define XFERTYP_DMAEN          0x00000001
 
 #define CINS_TIMEOUT           1000
+#define PIO_TIMEOUT            100000
 
 #define DSADDR         0x2e004
 
@@ -133,8 +127,21 @@
 
 #define WML            0x2e044
 #define WML_WRITE      0x00010000
+#ifdef CONFIG_FSL_SDHC_V2_3
+#define WML_RD_WML_MAX         0x80
+#define WML_WR_WML_MAX         0x80
+#define WML_RD_WML_MAX_VAL     0x0
+#define WML_WR_WML_MAX_VAL     0x0
+#define WML_RD_WML_MASK                0x7f
+#define WML_WR_WML_MASK                0x7f0000
+#else
+#define WML_RD_WML_MAX         0x10
+#define WML_WR_WML_MAX         0x80
+#define WML_RD_WML_MAX_VAL     0x10
+#define WML_WR_WML_MAX_VAL     0x80
 #define WML_RD_WML_MASK        0xff
 #define WML_WR_WML_MASK        0xff0000
+#endif
 
 #define BLKATTR                0x2e004
 #define BLKATTR_CNT(x) ((x & 0xffff) << 16)
@@ -148,13 +155,29 @@
 #define ESDHC_HOSTCAPBLT_DMAS  0x00400000
 #define ESDHC_HOSTCAPBLT_HSS   0x00200000
 
+#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
+
 struct fsl_esdhc_cfg {
        u32     esdhc_base;
-       u32     no_snoop;
+       u32     sdhc_clk;
+       u8      max_bus_width;
+       struct mmc_config cfg;
 };
 
 /* Select the correct accessors depending on endianess */
-#if __BYTE_ORDER == __LITTLE_ENDIAN
+#if defined CONFIG_SYS_FSL_ESDHC_LE
+#define esdhc_read32           in_le32
+#define esdhc_write32          out_le32
+#define esdhc_clrsetbits32     clrsetbits_le32
+#define esdhc_clrbits32                clrbits_le32
+#define esdhc_setbits32                setbits_le32
+#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
+#define esdhc_read32            in_be32
+#define esdhc_write32           out_be32
+#define esdhc_clrsetbits32      clrsetbits_be32
+#define esdhc_clrbits32         clrbits_be32
+#define esdhc_setbits32         setbits_be32
+#elif __BYTE_ORDER == __LITTLE_ENDIAN
 #define esdhc_read32           in_le32
 #define esdhc_write32          out_le32
 #define esdhc_clrsetbits32     clrsetbits_le32
@@ -178,5 +201,7 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd);
 static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
 static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
 #endif /* CONFIG_FSL_ESDHC */
+void __noreturn mmc_boot(void);
+void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
 
 #endif  /* __FSL_ESDHC_H__ */