+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2010-2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright 2010-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP Semiconductor
*/
/*
*/
#include <common.h>
+#include <cli.h>
+#include <command.h>
+#include <env.h>
#include <linux/ctype.h>
#include <asm/types.h>
#include <asm/io.h>
static const struct options_string options[] = {
COMMON_TIMING(tckmin_x_ps),
COMMON_TIMING(tckmax_ps),
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
COMMON_TIMING(taamin_ps),
+#endif
COMMON_TIMING(trcd_ps),
COMMON_TIMING(trp_ps),
COMMON_TIMING(tras_ps),
COMMON_TIMING(trrds_ps),
COMMON_TIMING(trrdl_ps),
COMMON_TIMING(tccdl_ps),
+ COMMON_TIMING(trfc_slr_ps),
#else
COMMON_TIMING(twtr_ps),
COMMON_TIMING(trfc_ps),
#define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
sizeof((dimm_params_t *)0)->x, 0}
+#define DIMM_PARM_HEX(x) {#x, offsetof(dimm_params_t, x), \
+ sizeof((dimm_params_t *)0)->x, 1}
static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
unsigned int ctrl_num,
DIMM_PARM(data_width),
DIMM_PARM(primary_sdram_width),
DIMM_PARM(ec_sdram_width),
+ DIMM_PARM(package_3ds),
DIMM_PARM(registered_dimm),
+ DIMM_PARM(mirrored_dimm),
DIMM_PARM(device_width),
DIMM_PARM(n_row_addr),
#ifdef CONFIG_SYS_FSL_DDR4
DIMM_PARM(bank_addr_bits),
DIMM_PARM(bank_group_bits),
+ DIMM_PARM_HEX(die_density),
#else
DIMM_PARM(n_banks_per_sdram_device),
#endif
DIMM_PARM(burst_lengths_bitmask),
- DIMM_PARM(row_density),
DIMM_PARM(tckmin_x_ps),
DIMM_PARM(tckmin_x_minus_1_ps),
DIMM_PARM(trrds_ps),
DIMM_PARM(trrdl_ps),
DIMM_PARM(tccdl_ps),
+ DIMM_PARM(trfc_slr_ps),
#else
DIMM_PARM(twr_ps),
DIMM_PARM(twtr_ps),
DIMM_PARM(tdqsq_max_ps),
DIMM_PARM(tqhs_ps),
#endif
-
+#ifdef CONFIG_SYS_FSL_DDR4
+ DIMM_PARM_HEX(dq_mapping[0]),
+ DIMM_PARM_HEX(dq_mapping[1]),
+ DIMM_PARM_HEX(dq_mapping[2]),
+ DIMM_PARM_HEX(dq_mapping[3]),
+ DIMM_PARM_HEX(dq_mapping[4]),
+ DIMM_PARM_HEX(dq_mapping[5]),
+ DIMM_PARM_HEX(dq_mapping[6]),
+ DIMM_PARM_HEX(dq_mapping[7]),
+ DIMM_PARM_HEX(dq_mapping[8]),
+ DIMM_PARM_HEX(dq_mapping[9]),
+ DIMM_PARM_HEX(dq_mapping[10]),
+ DIMM_PARM_HEX(dq_mapping[11]),
+ DIMM_PARM_HEX(dq_mapping[12]),
+ DIMM_PARM_HEX(dq_mapping[13]),
+ DIMM_PARM_HEX(dq_mapping[14]),
+ DIMM_PARM_HEX(dq_mapping[15]),
+ DIMM_PARM_HEX(dq_mapping[16]),
+ DIMM_PARM_HEX(dq_mapping[17]),
+ DIMM_PARM(dq_mapping_ors),
+#endif
DIMM_PARM(rank_density),
DIMM_PARM(capacity),
DIMM_PARM(base_address),
DIMM_PARM(data_width),
DIMM_PARM(primary_sdram_width),
DIMM_PARM(ec_sdram_width),
+ DIMM_PARM(package_3ds),
DIMM_PARM(registered_dimm),
+ DIMM_PARM(mirrored_dimm),
DIMM_PARM(device_width),
DIMM_PARM(n_row_addr),
#ifdef CONFIG_SYS_FSL_DDR4
DIMM_PARM(bank_addr_bits),
DIMM_PARM(bank_group_bits),
+ DIMM_PARM_HEX(die_density),
#else
DIMM_PARM(n_banks_per_sdram_device),
#endif
DIMM_PARM(tckmax_ps),
DIMM_PARM(caslat_x),
+ DIMM_PARM_HEX(caslat_x),
DIMM_PARM(taa_ps),
DIMM_PARM(caslat_x_minus_1),
DIMM_PARM(caslat_x_minus_2),
DIMM_PARM(trcd_ps),
DIMM_PARM(trp_ps),
DIMM_PARM(tras_ps),
+#if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
+ DIMM_PARM(tfaw_ps),
+#endif
#ifdef CONFIG_SYS_FSL_DDR4
DIMM_PARM(trfc1_ps),
DIMM_PARM(trfc2_ps),
DIMM_PARM(trrds_ps),
DIMM_PARM(trrdl_ps),
DIMM_PARM(tccdl_ps),
+ DIMM_PARM(trfc_slr_ps),
#else
DIMM_PARM(twr_ps),
DIMM_PARM(twtr_ps),
DIMM_PARM(tdh_ps),
DIMM_PARM(tdqsq_max_ps),
DIMM_PARM(tqhs_ps),
+#endif
+#ifdef CONFIG_SYS_FSL_DDR4
+ DIMM_PARM_HEX(dq_mapping[0]),
+ DIMM_PARM_HEX(dq_mapping[1]),
+ DIMM_PARM_HEX(dq_mapping[2]),
+ DIMM_PARM_HEX(dq_mapping[3]),
+ DIMM_PARM_HEX(dq_mapping[4]),
+ DIMM_PARM_HEX(dq_mapping[5]),
+ DIMM_PARM_HEX(dq_mapping[6]),
+ DIMM_PARM_HEX(dq_mapping[7]),
+ DIMM_PARM_HEX(dq_mapping[8]),
+ DIMM_PARM_HEX(dq_mapping[9]),
+ DIMM_PARM_HEX(dq_mapping[10]),
+ DIMM_PARM_HEX(dq_mapping[11]),
+ DIMM_PARM_HEX(dq_mapping[12]),
+ DIMM_PARM_HEX(dq_mapping[13]),
+ DIMM_PARM_HEX(dq_mapping[14]),
+ DIMM_PARM_HEX(dq_mapping[15]),
+ DIMM_PARM_HEX(dq_mapping[16]),
+ DIMM_PARM_HEX(dq_mapping[17]),
+ DIMM_PARM(dq_mapping_ors),
#endif
};
static const unsigned int n_opts = ARRAY_SIZE(options);
const common_timing_params_t *plcd_dimm_params)
{
static const struct options_string options[] = {
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
COMMON_TIMING(taamin_ps),
+#endif
COMMON_TIMING(trcd_ps),
COMMON_TIMING(trp_ps),
COMMON_TIMING(tras_ps),
COMMON_TIMING(trrds_ps),
COMMON_TIMING(trrdl_ps),
COMMON_TIMING(tccdl_ps),
+ COMMON_TIMING(trfc_slr_ps),
#else
COMMON_TIMING(twtr_ps),
COMMON_TIMING(trfc_ps),
CTRL_OPTIONS_CS(3, odt_rd_cfg),
CTRL_OPTIONS_CS(3, odt_wr_cfg),
#endif
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
CTRL_OPTIONS_CS(0, odt_rtt_norm),
CTRL_OPTIONS_CS(0, odt_rtt_wr),
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
*/
CTRL_OPTIONS(twot_en),
CTRL_OPTIONS(threet_en),
+ CTRL_OPTIONS(mirrored_dimm),
CTRL_OPTIONS(ap_en),
CTRL_OPTIONS(x4_en),
+ CTRL_OPTIONS(package_3ds),
CTRL_OPTIONS(bstopre),
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(wrlvl_start),
+ CTRL_OPTIONS(cswl_override),
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
+ CTRL_OPTIONS(rcw_3),
CTRL_OPTIONS(ddr_cdr1),
CTRL_OPTIONS(ddr_cdr2),
- CTRL_OPTIONS(tcke_clock_pulse_width_ps),
CTRL_OPTIONS(tfaw_window_four_activates_ps),
CTRL_OPTIONS(trwt_override),
CTRL_OPTIONS(trwt),
CFG_REGS(ddr_sr_cntr),
CFG_REGS(ddr_sdram_rcw_1),
CFG_REGS(ddr_sdram_rcw_2),
+ CFG_REGS(ddr_sdram_rcw_3),
CFG_REGS(ddr_cdr1),
CFG_REGS(ddr_cdr2),
CFG_REGS(dq_map_0),
print_option_table(options, n_opts, ddr);
- for (i = 0; i < 32; i++)
+ for (i = 0; i < 64; i++)
printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
}
CFG_REGS(ddr_sr_cntr),
CFG_REGS(ddr_sdram_rcw_1),
CFG_REGS(ddr_sdram_rcw_2),
+ CFG_REGS(ddr_sdram_rcw_3),
CFG_REGS(ddr_cdr1),
CFG_REGS(ddr_cdr2),
CFG_REGS(dq_map_0),
debug("fsl_ddr_regs_edit: ctrl_num = %u, "
"regname = %s, value = %s\n",
ctrl_num, regname, value_str);
- if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS)
+ if (ctrl_num > CONFIG_SYS_NUM_DDR_CTLRS)
return;
ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
if (handle_option_table(options, n_opts, ddr, regname, value_str))
return;
- for (i = 0; i < 32; i++) {
+ for (i = 0; i < 64; i++) {
unsigned int value = simple_strtoul(value_str, NULL, 0);
sprintf(buf, "debug_%u", i + 1);
if (strcmp(buf, regname) == 0) {
CTRL_OPTIONS_CS(3, odt_rd_cfg),
CTRL_OPTIONS_CS(3, odt_wr_cfg),
#endif
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
CTRL_OPTIONS_CS(0, odt_rtt_norm),
CTRL_OPTIONS_CS(0, odt_rtt_wr),
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
CTRL_OPTIONS(twot_en),
CTRL_OPTIONS(threet_en),
CTRL_OPTIONS(registered_dimm_en),
+ CTRL_OPTIONS(mirrored_dimm),
CTRL_OPTIONS(ap_en),
CTRL_OPTIONS(x4_en),
+ CTRL_OPTIONS(package_3ds),
CTRL_OPTIONS(bstopre),
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(wrlvl_start),
+ CTRL_OPTIONS_HEX(cswl_override),
CTRL_OPTIONS(rcw_override),
- CTRL_OPTIONS(rcw_1),
- CTRL_OPTIONS(rcw_2),
+ CTRL_OPTIONS_HEX(rcw_1),
+ CTRL_OPTIONS_HEX(rcw_2),
+ CTRL_OPTIONS_HEX(rcw_3),
CTRL_OPTIONS_HEX(ddr_cdr1),
CTRL_OPTIONS_HEX(ddr_cdr2),
- CTRL_OPTIONS(tcke_clock_pulse_width_ps),
CTRL_OPTIONS(tfaw_window_four_activates_ps),
CTRL_OPTIONS(trwt_override),
CTRL_OPTIONS(trwt),
printf("%-3d-%3d: ", 128, 255);
for (i = 128; i <= 255; i++)
- printf("%02x", spd->mod_section.uc[i - 60]);
+ printf("%02x", spd->mod_section.uc[i - 128]);
break;
}
/* STEP 1: DIMM SPD data */
if (do_mask & STEP_GET_SPD) {
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
/* STEP 2: DIMM Parameters */
if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
/* STEP 3: Common Parameters */
if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
printf("\"lowest common\" DIMM parameters: "
/* STEP 4: User Configuration Options */
if (do_mask & STEP_GATHER_OPTS) {
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
printf("User Config Options: Controller=%u\n", i);
/* STEP 5: Address assignment */
if (do_mask & STEP_ASSIGN_ADDRESSES) {
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
/* STEP 6: computed controller register values */
if (do_mask & STEP_COMPUTE_REGS) {
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
printf("Computed Register Values: Controller=%u\n", i);
{
char buffer[CONFIG_SYS_CBSIZE];
- if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
+ if (env_get_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
return 1;
return 0;
};
if (var_is_set) {
- if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) {
+ if (env_get_f("ddr_interactive", buffer2,
+ CONFIG_SYS_CBSIZE) > 0)
p = buffer2;
- } else {
+ else
var_is_set = 0;
- }
}
/*
} else {
/*
* No need to worry for buffer overflow here in
- * this function; readline() maxes out at CFG_CBSIZE
+ * this function; cli_readline() maxes out at
+ * CFG_CBSIZE
*/
- readline_into_buffer(prompt, buffer, 0);
+ cli_readline_into_buffer(prompt, buffer, 0);
}
- argc = parse_line(buffer, argv);
+ argc = cli_simple_parse_line(buffer, argv);
if (argc == 0)
continue;