common: Drop asm/global_data.h from common header

[J-u-boot.git] / drivers / clk / rockchip / clk_rk3399.c

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 22c373a623ca96d2bc36aa45a23d61626f31cb4c..f8cbda44551e0bbecdb6a886b0e3a4b5d32b88a6 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -18,11 +18,15 @@
 #include <asm/arch-rockchip/clock.h>
 #include <asm/arch-rockchip/cru.h>
 #include <asm/arch-rockchip/hardware.h>
+#include <asm/global_data.h>
+#include <dm/device-internal.h>
 #include <dm/lists.h>
 #include <dt-bindings/clock/rk3399-cru.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 struct rk3399_clk_plat {
        struct dtd_rockchip_rk3399_cru dtd;
@@ -50,10 +54,9 @@ struct pll_div {
        .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
        .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
 
-#if defined(CONFIG_SPL_BUILD)
 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
-#else
+#if !defined(CONFIG_SPL_BUILD)
 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
 #endif
 
@@ -233,6 +236,10 @@ enum {
        DCLK_VOP_DIV_CON_MASK           = 0xff,
        DCLK_VOP_DIV_CON_SHIFT          = 0,
 
+       /* CLKSEL_CON57 */
+       PCLK_ALIVE_DIV_CON_SHIFT        = 0,
+       PCLK_ALIVE_DIV_CON_MASK         = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT,
+
        /* CLKSEL_CON58 */
        CLK_SPI_PLL_SEL_WIDTH = 1,
        CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
@@ -867,6 +874,17 @@ static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
        return set_rate;
 }
 
+static ulong rk3399_alive_get_clk(struct rockchip_cru *cru)
+{
+        u32 div, val;
+
+        val = readl(&cru->clksel_con[57]);
+        div = (val & PCLK_ALIVE_DIV_CON_MASK) >>
+              PCLK_ALIVE_DIV_CON_SHIFT;
+
+        return DIV_TO_RATE(GPLL_HZ, div);
+}
+
 static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
 {
        u32 div, val;
@@ -936,6 +954,10 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
        case ACLK_GIC_PRE:
        case PCLK_DDR:
                break;
+       case PCLK_ALIVE:
+       case PCLK_WDT:
+               rate = rk3399_alive_get_clk(priv->cru);
+               break;
        default:
                log_debug("Unknown clock %lu\n", clk->id);
                return -ENOENT;
@@ -1274,7 +1296,6 @@ static struct clk_ops rk3399_clk_ops = {
        .disable = rk3399_clk_disable,
 };
 
-#ifdef CONFIG_SPL_BUILD
 static void rkclk_init(struct rockchip_cru *cru)
 {
        u32 aclk_div;
@@ -1352,24 +1373,34 @@ static void rkclk_init(struct rockchip_cru *cru)
                     hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
                     HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
 }
-#endif
 
 static int rk3399_clk_probe(struct udevice *dev)
 {
-#ifdef CONFIG_SPL_BUILD
        struct rk3399_clk_priv *priv = dev_get_priv(dev);
+       bool init_clocks = false;
 
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
-       struct rk3399_clk_plat *plat = dev_get_platdata(dev);
+       struct rk3399_clk_plat *plat = dev_get_plat(dev);
 
        priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
 #endif
-       rkclk_init(priv->cru);
+
+#if defined(CONFIG_SPL_BUILD)
+       init_clocks = true;
+#elif CONFIG_IS_ENABLED(HANDOFF)
+       if (!(gd->flags & GD_FLG_RELOC)) {
+               if (!(gd->spl_handoff))
+                       init_clocks = true;
+       }
 #endif
+
+       if (init_clocks)
+               rkclk_init(priv->cru);
+
        return 0;
 }
 
-static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk3399_clk_of_to_plat(struct udevice *dev)
 {
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
        struct rk3399_clk_priv *priv = dev_get_priv(dev);
@@ -1396,7 +1427,7 @@ static int rk3399_clk_bind(struct udevice *dev)
                                                    glb_srst_fst_value);
                priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
                                                    glb_srst_snd_value);
-               sys_child->priv = priv;
+               dev_set_priv(sys_child, priv);
        }
 
 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
@@ -1418,13 +1449,13 @@ U_BOOT_DRIVER(clk_rk3399) = {
        .name           = "rockchip_rk3399_cru",
        .id             = UCLASS_CLK,
        .of_match       = rk3399_clk_ids,
-       .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
-       .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata,
+       .priv_auto      = sizeof(struct rk3399_clk_priv),
+       .of_to_plat = rk3399_clk_of_to_plat,
        .ops            = &rk3399_clk_ops,
        .bind           = rk3399_clk_bind,
        .probe          = rk3399_clk_probe,
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
-       .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat),
+       .plat_auto      = sizeof(struct rk3399_clk_plat),
 #endif
 };
 
@@ -1502,6 +1533,7 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk)
        case PLL_PPLL:
                return PPLL_HZ;
        case PCLK_RKPWM_PMU:
+       case PCLK_WDT_M0_PMU:
                rate = rk3399_pwm_get_clk(priv->pmucru);
                break;
        case SCLK_I2C0_PMU:
@@ -1569,7 +1601,7 @@ static int rk3399_pmuclk_probe(struct udevice *dev)
 #endif
 
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
-       struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
+       struct rk3399_pmuclk_plat *plat = dev_get_plat(dev);
 
        priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
 #endif
@@ -1580,7 +1612,7 @@ static int rk3399_pmuclk_probe(struct udevice *dev)
        return 0;
 }
 
-static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
+static int rk3399_pmuclk_of_to_plat(struct udevice *dev)
 {
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
        struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
@@ -1592,7 +1624,7 @@ static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
 
 static int rk3399_pmuclk_bind(struct udevice *dev)
 {
-#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
        int ret;
 
        ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
@@ -1612,12 +1644,12 @@ U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
        .name           = "rockchip_rk3399_pmucru",
        .id             = UCLASS_CLK,
        .of_match       = rk3399_pmuclk_ids,
-       .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
-       .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
+       .priv_auto      = sizeof(struct rk3399_pmuclk_priv),
+       .of_to_plat = rk3399_pmuclk_of_to_plat,
        .ops            = &rk3399_pmuclk_ops,
        .probe          = rk3399_pmuclk_probe,
        .bind           = rk3399_pmuclk_bind,
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
-       .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
+       .plat_auto      = sizeof(struct rk3399_pmuclk_plat),
 #endif
 };