Enables a workaround for erratum A004510. If set,
then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
- CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
+ CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
See Freescale App Note 4493 for more information about
this erratum.
- CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+ CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
This is the value to write into CCSR offset 0x18600
according to the A004510 workaround.
Freescale DDR driver in use. This type of DDR controller is
found in mpc83xx, mpc85xx as well as some ARM core SoCs.
- CONFIG_SYS_FSL_DDR_ADDR
+ CFG_SYS_FSL_DDR_ADDR
Freescale DDR memory-mapped register base.
CONFIG_SYS_FSL_IFC_CLK_DIV
CONFIG_SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to eLBC controller).
- CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+ CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
Physical address from the view of DDR controllers. It is the
same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
it could be different for ARM SoCs.
Define this variable to enable hw flow control in serial driver.
Current user of this option is drivers/serial/nsl16550.c driver
-- Serial Download Echo Mode:
- CONFIG_LOADS_ECHO
- If defined to 1, all characters received during a
- serial download (using the "loads" command) are
- echoed back. This might be needed by some terminal
- emulations (like "cu"), but may as well just take
- time on others. This setting #define's the initial
- value of the "loads_echo" environment variable.
-
- Removal of commands
If no commands are needed to boot, you can disable
CONFIG_CMDLINE to remove them. In this case, the command line
entering dfuMANIFEST state. Host waits this timeout, before
sending again an USB request to the device.
-- Journaling Flash filesystem support:
- CONFIG_SYS_JFFS2_FIRST_SECTOR,
- CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
- Define these for a default partition on a NOR device
-
- Keyboard Support:
See Kconfig help for available keyboard drivers.
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
- CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
- CONFIG_SYS_NAND_ECCBYTES
+ CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE,
+ CFG_SYS_NAND_ECCBYTES
Defines the size and behavior of the NAND that SPL uses
to read U-Boot
- CONFIG_SYS_NAND_U_BOOT_DST
+ CFG_SYS_NAND_U_BOOT_DST
Location in memory to load U-Boot to
- CONFIG_SYS_NAND_U_BOOT_SIZE
+ CFG_SYS_NAND_U_BOOT_SIZE
Size of image to load
- CONFIG_SYS_NAND_U_BOOT_START
+ CFG_SYS_NAND_U_BOOT_START
Entry point in loaded image to jump to
- CONFIG_SYS_NAND_HW_ECC_OOBFIRST
- Define this if you need to first read the OOB and then the
- data. This is used, for example, on davinci platforms.
-
CONFIG_SPL_RAM_DEVICE
Support for running image already present in ram, in SPL binary
the RAM base is not zero, or RAM is divided into banks,
this variable needs to be recalcuated to get the address.
-- CONFIG_SYS_LOADS_BAUD_CHANGE:
- Enable temporary baudrate change while serial download
-
- CONFIG_SYS_SDRAM_BASE:
Physical start address of SDRAM. _Must_ be 0 here.
- CONFIG_SYS_FLASH_BASE:
Physical start address of Flash memory.
-- CONFIG_SYS_MONITOR_LEN:
- Size of memory reserved for monitor code, used to
- determine _at_compile_time_ (!) if the environment is
- embedded within the U-Boot image, or in a separate
- flash sector.
-
- CONFIG_SYS_MALLOC_LEN:
Size of DRAM reserved for malloc() use.
boards which do not use the full malloc in SPL (which is
enabled with CONFIG_SYS_SPL_MALLOC).
-- CONFIG_SYS_NONCACHED_MEMORY:
- Size of non-cached memory area. This area of memory will be
- typically located right below the malloc() area and mapped
- uncached in the MMU. This is useful for drivers that would
- otherwise require a lot of explicit cache maintenance. For
- some drivers it's also impossible to properly maintain the
- cache. For example if the regions that need to be flushed
- are not a multiple of the cache-line size, *and* padding
- cannot be allocated between the regions to align them (i.e.
- if the HW requires a contiguous array of regions, and the
- size of each region is not cache-aligned), then a flush of
- one region may result in overwriting data that hardware has
- written to another region in the same cache-line. This can
- happen for example in network drivers where descriptors for
- buffers are typically smaller than the CPU cache-line (e.g.
- 16 bytes vs. 32 or 64 bytes).
-
- Non-cached memory is only supported on 32-bit ARM at present.
-
- CONFIG_SYS_BOOTMAPSZ:
Maximum size of memory mapped by the startup code of
the Linux kernel; all data that must be processed by
- CONFIG_SYS_FAULT_MII_ADDR:
MII address of the PHY to check for the Ethernet link state.
-- CONFIG_NS16550_MIN_FUNCTIONS:
- Define this if you desire to only have use of the NS16550_init
- and NS16550_putc functions for the serial driver located at
- drivers/serial/ns16550.c. This option is useful for saving
- space for already greatly restricted images, including but not
- limited to NAND_SPL configurations.
-
- CONFIG_DISPLAY_BOARDINFO
Display information about the board that U-Boot is running on
when U-Boot starts up. The board function checkboard() is called
- CONFIG_SYS_OR_TIMING_SDRAM:
SDRAM timing
-- CONFIG_SYS_MAMR_PTA:
- periodic timer for refresh
-
- CONFIG_SYS_SRIO:
Chip has SRIO or not
If defined, the x86 reset vector code is included. This is not
needed when U-Boot is running from Coreboot.
-- CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
- Option to disable subpage write in NAND driver
- driver that uses this:
- drivers/mtd/nand/raw/davinci_nand.c
-
Freescale QE/FMAN Firmware Support:
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projects / J-u-boot.git / blobdiff