* (C) Copyright 2009, DAVE Srl <www.dave.eu>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
/*
#define __CONFIG_H
#define CONFIG_ARIA 1
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
+
/*
* Memory map for the ARIA board:
*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC512X 1 /* MPC512X family */
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
-#define CONFIG_FSL_DIU_LOGO_BMP 1 /* Don't include FSL DIU binary bmp */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
/* video */
#undef CONFIG_VIDEO
#define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_IMMR 0x80000000
*/
#define CONFIG_CMD_NAND /* enable NAND support */
#define CONFIG_JFFS2_NAND /* with JFFS2 on it */
-
-
#define CONFIG_NAND_MPC5121_NFC
#define CONFIG_SYS_NAND_BASE 0x40000000
-
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
/*
* Configuration parameters for MPC5121 NAND driver
#define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \
CONFIG_SYS_SRAM_SIZE)
#define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000 /* reserve 1MB-window */
+#define CONFIG_SYS_CS6_START CONFIG_SYS_ARIA_SRAM_BASE
+#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_ARIA_SRAM_SIZE
#define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \
CONFIG_SYS_ARIA_SRAM_SIZE)
#define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000 /* 128 KB */
+#define CONFIG_SYS_CS2_START CONFIG_SYS_ARIA_FPGA_BASE
+#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_ARIA_FPGA_SIZE
+
#define CONFIG_SYS_CS0_CFG 0x05059150
#define CONFIG_SYS_CS2_CFG ( (5 << 24) | \
(5 << 16) | \
/* Use SRAM for initial stack */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
#ifdef CONFIG_FSL_DIU_FB
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */
+#define CONFIG_SYS_PSC3
#if CONFIG_PSC_CONSOLE != 3
#error CONFIG_PSC_CONSOLE must be 3
#endif
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
/*
* PCI
*/
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
#define CONFIG_I2C_MULTI_BUS
/* I2C speed and slave address */
/*
* IIM - IC Identification Module
*/
-#undef CONFIG_IIM
+#undef CONFIG_FSL_IIM
/*
* EEPROM configuration for Atmel AT24C32A-10TQ-2.7:
* Ethernet configuration
*/
#define CONFIG_MPC512x_FEC 1
-#define CONFIG_NET_MULTI
#define CONFIG_PHY_ADDR 0x17
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_FEC_AN_TIMEOUT 1
#define CONFIG_LOADS_ECHO 1
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#undef CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#ifdef CONFIG_CMD_KGDB
# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ 1000
-
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
/* Cache Configuration */
#define CONFIG_SYS_DCACHE_SIZE 32768
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01
-#define BOOTFLAG_WARM 0x02
-
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
#define CONFIG_TIMESTAMP
#define CONFIG_HOSTNAME aria
-#define CONFIG_BOOTFILE aria/uImage
-#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
+#define CONFIG_BOOTFILE "aria/uImage"
+#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
#define CONFIG_LOADADDR 400000 /* default load addr */
#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
#define FSL_ATA_CTRL_IORDY_EN 0x01000000
+/* Clocks in use */
+#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
+ CLOCK_SCCR1_LPC_EN | \
+ CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
+ CLOCK_SCCR1_PSCFIFO_EN | \
+ CLOCK_SCCR1_DDR_EN | \
+ CLOCK_SCCR1_FEC_EN | \
+ CLOCK_SCCR1_NFC_EN | \
+ CLOCK_SCCR1_PATA_EN | \
+ CLOCK_SCCR1_PCI_EN | \
+ CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
+ CLOCK_SCCR2_SPDIF_EN | \
+ CLOCK_SCCR2_DIU_EN | \
+ CLOCK_SCCR2_I2C_EN)
+
#endif /* __CONFIG_H */
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