*/
+#define LOG_CATEGORY UCLASS_FPGA
+
#include <common.h>
#include <console.h>
+#include <log.h>
#include <virtex2.h>
#include <linux/delay.h>
-#if 0
-#define FPGA_DEBUG
-#endif
-
-#ifdef FPGA_DEBUG
-#define PRINTF(fmt, args...) printf(fmt, ##args)
-#else
-#define PRINTF(fmt, args...)
-#endif
-
/*
- * If the SelectMap interface can be overrun by the processor, define
- * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board
+ * If the SelectMap interface can be overrun by the processor, enable
+ * CONFIG_SYS_FPGA_CHECK_BUSY and/or define CFG_FPGA_DELAY in the board
* configuration file and add board-specific support for checking BUSY status.
* By default, assume that the SelectMap interface cannot be overrun.
*/
-#ifndef CONFIG_SYS_FPGA_CHECK_BUSY
-#undef CONFIG_SYS_FPGA_CHECK_BUSY
-#endif
-#ifndef CONFIG_FPGA_DELAY
-#define CONFIG_FPGA_DELAY()
+#ifndef CFG_FPGA_DELAY
+#define CFG_FPGA_DELAY()
#endif
/*
* Check for errors during configuration by default
*/
-#ifndef CONFIG_SYS_FPGA_CHECK_ERROR
-#define CONFIG_SYS_FPGA_CHECK_ERROR
+#ifndef CFG_SYS_FPGA_CHECK_ERROR
+#define CFG_SYS_FPGA_CHECK_ERROR
#endif
/*
* which yields 11.44 mS. So let's make it bigger in order to handle
* an XC2V1000, if anyone can ever get ahold of one.
*/
-#ifndef CONFIG_SYS_FPGA_WAIT_INIT
-#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */
+#ifndef CFG_SYS_FPGA_WAIT_INIT
+#define CFG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */
#endif
/*
* This is normally not necessary since for most reasonable configuration
* clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
*/
-#ifndef CONFIG_SYS_FPGA_WAIT_BUSY
-#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/
+#ifndef CFG_SYS_FPGA_WAIT_BUSY
+#define CFG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/
#endif
/* Default timeout for waiting for FPGA to enter operational mode after
* configuration data has been written.
*/
-#ifndef CONFIG_SYS_FPGA_WAIT_CONFIG
-#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */
+#ifndef CFG_SYS_FPGA_WAIT_CONFIG
+#define CFG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */
#endif
static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
switch (desc->iface) {
case slave_serial:
- PRINTF("%s: Launching Slave Serial Load\n", __func__);
+ log_debug("Launching Slave Serial Load\n");
ret_val = virtex2_ss_load(desc, buf, bsize);
break;
case slave_selectmap:
- PRINTF("%s: Launching Slave Parallel Load\n", __func__);
+ log_debug("Launching Slave Parallel Load\n");
ret_val = virtex2_ssm_load(desc, buf, bsize);
break;
switch (desc->iface) {
case slave_serial:
- PRINTF("%s: Launching Slave Serial Dump\n", __func__);
+ log_debug("Launching Slave Serial Dump\n");
ret_val = virtex2_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
- PRINTF("%s: Launching Slave Parallel Dump\n", __func__);
+ log_debug("Launching Slave Parallel Dump\n");
ret_val = virtex2_ssm_dump(desc, buf, bsize);
break;
{
unsigned long ts;
- PRINTF("%s:%d: Start with interface functions @ 0x%p\n",
- __func__, __LINE__, fn);
+ log_debug("Start with interface functions @ 0x%p\n", fn);
if (!fn) {
printf("%s:%d: NULL Interface function table!\n",
}
/* Gotta split this one up (so the stack won't blow??) */
- PRINTF("%s:%d: Function Table:\n"
- " base 0x%p\n"
- " struct 0x%p\n"
- " pre 0x%p\n"
- " prog 0x%p\n"
- " init 0x%p\n"
- " error 0x%p\n",
- __func__, __LINE__,
- &fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
- PRINTF(" clock 0x%p\n"
- " cs 0x%p\n"
- " write 0x%p\n"
- " rdata 0x%p\n"
- " wdata 0x%p\n"
- " busy 0x%p\n"
- " abort 0x%p\n"
- " post 0x%p\n\n",
- fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
- fn->busy, fn->abort, fn->post);
+ log_debug("Function Table:\n"
+ " base 0x%p\n"
+ " struct 0x%p\n"
+ " pre 0x%p\n"
+ " prog 0x%p\n"
+ " init 0x%p\n"
+ " error 0x%p\n",
+ &fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
+ log_debug(" clock 0x%p\n"
+ " cs 0x%p\n"
+ " write 0x%p\n"
+ " rdata 0x%p\n"
+ " wdata 0x%p\n"
+ " busy 0x%p\n"
+ " abort 0x%p\n"
+ " post 0x%p\n\n",
+ fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
+ fn->busy, fn->abort, fn->post);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf("Initializing FPGA Device %d...\n", cookie);
udelay(10);
ts = get_timer(0);
do {
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
- __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
+ __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
(*fn->abort)(cookie);
return FPGA_FAIL;
}
} while (!(*fn->init)(cookie));
(*fn->pgm)(false, true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
if (fn->clk)
(*fn->clk)(true, true, cookie);
*/
ts = get_timer(0);
do {
- CONFIG_FPGA_DELAY();
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
+ CFG_FPGA_DELAY();
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
- __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
+ __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
(*fn->abort)(cookie);
return FPGA_FAIL;
}
/*
* Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
*/
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
if (fn->cs)
(*fn->cs)(false, true, cookie);
if (fn->wr)
break;
}
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT_CONFIG) {
printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n",
- __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
+ __func__, __LINE__, CFG_SYS_FPGA_WAIT_CONFIG);
(*fn->abort)(cookie);
ret_val = FPGA_FAIL;
break;
(*fn->wbulkdata)(&dummy, 1, true, cookie);
} else {
(*fn->wdata)(0xff, true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
(*fn->clk)(false, true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
(*fn->clk)(true, true, cookie);
}
}
#endif
if ((*fn->done)(cookie) == FPGA_SUCCESS) {
- PRINTF("%s:%d:done went active early, bytecount = %d\n",
- __func__, __LINE__, bytecount);
+ log_debug("done went active early, bytecount = %zu\n",
+ bytecount);
break;
}
-#ifdef CONFIG_SYS_FPGA_CHECK_ERROR
+#ifdef CFG_SYS_FPGA_CHECK_ERROR
if ((*fn->init)(cookie)) {
printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
__func__, __LINE__);
#endif
(*fn->wdata)(data[bytecount++], true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
/*
* Cycle the clock pin
*/
(*fn->clk)(false, true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
(*fn->clk)(true, true, cookie);
#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
ts = get_timer(0);
while ((*fn->busy)(cookie)) {
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT_BUSY) {
printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
__func__, __LINE__,
- CONFIG_SYS_FPGA_WAIT_BUSY);
+ CFG_SYS_FPGA_WAIT_BUSY);
(*fn->abort)(cookie);
return FPGA_FAIL;
}
#endif
if ((*fn->done)(cookie) == FPGA_SUCCESS) {
- PRINTF("%s:%d:done went active early, bytecount = %d\n",
- __func__, __LINE__, bytecount);
+ log_debug("done went active early, bytecount = %zu\n",
+ bytecount);
break;
}
-#ifdef CONFIG_SYS_FPGA_CHECK_ERROR
+#ifdef CFG_SYS_FPGA_CHECK_ERROR
if ((*fn->init)(cookie)) {
printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
__func__, __LINE__);
for (bit = 7; bit >= 0; --bit) {
unsigned char curr_bit = (curr_data >> bit) & 1;
(*fn->wdata)(curr_bit, true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
(*fn->clk)(false, true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
(*fn->clk)(true, true, cookie);
}
projects / J-u-boot.git / blobdiff