]> Git Repo - J-u-boot.git/blobdiff - configs/socfpga_agilex_defconfig
board: phytec: am62a7: Add PHYTEC phyCORE-AM62A7 SoM
[J-u-boot.git] / configs / socfpga_agilex_defconfig
index 03d15efb52c0d5584c1c1ae63c88772933cd1eef..eaa2161a2f7759c73ee79789e5877564b9c210df 100644 (file)
@@ -11,21 +11,21 @@ CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x200
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
-CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_DM_RESET=y
 CONFIG_SPL_STACK=0xffe3f000
+CONFIG_SPL_TEXT_BASE=0xFFE00000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x3ff00000
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x02000000
 CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
 CONFIG_IDENT_STRING="socfpga_agilex"
 CONFIG_SPL_FS_FAT=y
 # CONFIG_PSCI_RESET is not set
-CONFIG_SYS_LOAD_ADDR=0x02000000
 CONFIG_SYS_MEMTEST_START=0x00000000
 CONFIG_SYS_MEMTEST_END=0x3fe00000
 CONFIG_REMAKE_ELF=y
-CONFIG_SYS_BOOTM_LEN=0x2000000
 CONFIG_BOOTDELAY=5
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="earlycon"
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