mpc83xx: Kconfig: Migrate HRCW to Kconfig

[J-u-boot.git] / include / configs / mpc8308_p1m.h

diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index e978734bab9b782a9097e6e0ef90b169615ff796..2822aa3b9da8a946fe66c8aa71a91a1a49ddebb7 100644 (file)
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -12,8 +12,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300            1 /* E300 family */
-#define CONFIG_MPC830x         1 /* MPC830x family */
-#define CONFIG_MPC8308         1 /* MPC8308 CPU specific */
 
 /*
  * On-board devices
@@ -23,44 +21,6 @@
 #define CONFIG_TSEC1
 #define CONFIG_TSEC2
 
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN      33333333 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ    CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_2X1 |\
-       HRCWL_SVCOD_DIV_2 |\
-       HRCWL_CSB_TO_CLKIN_4X1 |\
-       HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_RL_EXT_LEGACY |\
-       HRCWH_TSEC1M_IN_MII |\
-       HRCWH_TSEC2M_IN_MII |\
-       HRCWH_BIG_ENDIAN)
-
 /*
  * System IO Config
  */
@@ -214,13 +174,10 @@
 /*
  * FLASH on the Local Bus
  */
-#define CONFIG_SYS_FLASH_CFI           /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER                /* use the CFI driver */
 #define CONFIG_SYS_FLASH_CFI_WIDTH     FLASH_CFI_16BIT
 
 #define CONFIG_SYS_FLASH_BASE          0xFC000000 /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE          64 /* FLASH size is 64M */
-#define CONFIG_SYS_FLASH_PROTECTION    1 /* Use h/w Flash protection. */
 
 /* Window base at flash base */
 #define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
@@ -337,7 +294,6 @@
 /*
  * TSEC ethernet configuration
  */
-#define CONFIG_MII             1 /* MII PHY management */
 #define CONFIG_TSEC1_NAME      "eTSEC0"
 #define CONFIG_TSEC2_NAME      "eTSEC1"
 #define TSEC1_PHY_ADDR         1