Merge branch 'master' of git://git.denx.de/u-boot-imx

[J-u-boot.git] / include / configs / DP405.h

diff --git a/include/configs/DP405.h b/include/configs/DP405.h
index 4423f2ab62a0054d8758c22edff8758688856380..f6e265281e6e2e4ea6bb42991819d0d738e2f298 100644 (file)
--- a/include/configs/DP405.h
+++ b/include/configs/DP405.h
@@ -37,6 +37,8 @@
 #define CONFIG_4xx             1       /* ...member of PPC4xx family   */
 #define CONFIG_DP405           1       /* ...on a DP405 board          */
 
+#define        CONFIG_SYS_TEXT_BASE    0xFFFD0000
+
 #define CONFIG_BOARD_EARLY_INIT_F 1    /* call board_early_init_f()    */
 #define CONFIG_MISC_INIT_R     1       /* call misc_init_r()           */
 
@@ -63,6 +65,7 @@
 #define CONFIG_CMD_EEPROM
 
 #undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
 
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 
@@ -97,9 +100,14 @@
 #define CONFIG_SYS_MEMTEST_START       0x0400000       /* memtest works on     */
 #define CONFIG_SYS_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 
+#define CONFIG_CONS_INDEX      1       /* Use UART0                    */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK         get_serial_clock()
+
 #undef CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 #define CONFIG_SYS_BASE_BAUD       691200
-#undef CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
 
 /* The following table includes the supported baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE      \
@@ -152,8 +160,8 @@
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000
 #define CONFIG_SYS_FLASH_BASE          CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE                TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN         (~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN         (~(CONFIG_SYS_TEXT_BASE) + 1)
 #define CONFIG_SYS_MALLOC_LEN          (256 * 1024)
 
 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
@@ -221,10 +229,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR       0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE       0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
-#define CONFIG_SYS_INIT_RAM_END        CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM     */
+#define CONFIG_SYS_INIT_RAM_SIZE       CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -243,22 +250,14 @@
 /* GPIO Output:                OSR=00, ISR=00, TSR=00, TCR=1 */
 /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
-#define CONFIG_SYS_GPIO0_OSRH          0x40000540  /*  0 ... 15 */
-#define CONFIG_SYS_GPIO0_OSRL          0x00000110  /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_ISR1H         0x00000000  /*  0 ... 15 */
-#define CONFIG_SYS_GPIO0_ISR1L         0x14000045  /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_TSRH          0x00000000  /*  0 ... 15 */
-#define CONFIG_SYS_GPIO0_TSRL          0x00000000  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_OSRL          0x40000540  /*  0 ... 15 */
+#define CONFIG_SYS_GPIO0_OSRH          0x00000110  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_ISR1L         0x00000000  /*  0 ... 15 */
+#define CONFIG_SYS_GPIO0_ISR1H         0x14000045  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_TSRL          0x00000000  /*  0 ... 15 */
+#define CONFIG_SYS_GPIO0_TSRH          0x00000000  /* 16 ... 31 */
 #define CONFIG_SYS_GPIO0_TCR           0xB7FE0014  /*  0 ... 31 */
 
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD  0x01            /* Normal Power-On: Boot from FLASH     */
-#define BOOTFLAG_WARM  0x02            /* Software reboot                      */
-
 /*
  * Default speed selection (cpu_plb_opb_ebc) in mhz.
  * This value will be set if iic boot eprom is disabled.