mmc: msm_sdhci: use a more sensible default clock rate

[J-u-boot.git] / drivers / mmc / socfpga_dw_mmc.c

diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index dc008c5e2f0e2305652572657a23c99b8526a761..387cb8b6b50a1cbac0b0bfe29d8c601a75af032c 100644 (file)
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -6,13 +6,16 @@
 #include <common.h>
 #include <log.h>
 #include <asm/arch/clock_manager.h>
+#include <asm/arch/secure_reg_helper.h>
 #include <asm/arch/system_manager.h>
 #include <clk.h>
 #include <dm.h>
 #include <dwmmc.h>
 #include <errno.h>
 #include <fdtdec.h>
+#include <asm/global_data.h>
 #include <dm/device_compat.h>
+#include <linux/intel-smc.h>
 #include <linux/libfdt.h>
 #include <linux/err.h>
 #include <malloc.h>
@@ -46,7 +49,7 @@ static void socfpga_dwmci_reset(struct udevice *dev)
        reset_deassert_bulk(&reset_bulk);
 }
 
-static void socfpga_dwmci_clksel(struct dwmci_host *host)
+static int socfpga_dwmci_clksel(struct dwmci_host *host)
 {
        struct dwmci_socfpga_priv_data *priv = host->priv;
        u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
@@ -58,14 +61,28 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
 
        debug("%s: drvsel %d smplsel %d\n", __func__,
              priv->drvsel, priv->smplsel);
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+       int ret;
+
+       ret = socfpga_secure_reg_write32(SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC,
+                                        sdmmc_mask);
+       if (ret) {
+               printf("DWMMC: Failed to set clksel via SMC call");
+               return ret;
+       }
+#else
        writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
 
        debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
                readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
+#endif
 
        /* Enable SDMMC clock */
        setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
                     CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+
+       return 0;
 }
 
 static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
@@ -82,7 +99,6 @@ static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
 
        host->bus_hz = clk_get_rate(&clk);
 
-       clk_free(&clk);
 #else
        /* Fixed clock divide by 4 which due to the SDMMC wrapper */
        host->bus_hz = cm_get_mmc_controller_clk_hz();
@@ -127,6 +143,8 @@ static int socfpga_dwmmc_of_to_plat(struct udevice *dev)
                                        "smplsel", 0);
        host->priv = priv;
 
+       host->fifo_mode = dev_read_bool(dev, "fifo-mode");
+
        return 0;
 }